WO2021120712A8 - Instruction generation method and apparatus, instruction execution method, processor, electronic device, and storage medium - Google Patents

Instruction generation method and apparatus, instruction execution method, processor, electronic device, and storage medium Download PDF

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Publication number
WO2021120712A8
WO2021120712A8 PCT/CN2020/114002 CN2020114002W WO2021120712A8 WO 2021120712 A8 WO2021120712 A8 WO 2021120712A8 CN 2020114002 W CN2020114002 W CN 2020114002W WO 2021120712 A8 WO2021120712 A8 WO 2021120712A8
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WO
WIPO (PCT)
Prior art keywords
instruction
forwarding path
instruction execution
identifier
ith
Prior art date
Application number
PCT/CN2020/114002
Other languages
French (fr)
Chinese (zh)
Other versions
WO2021120712A1 (en
Inventor
蒋宇翔
王晓阳
Original Assignee
成都海光微电子技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 成都海光微电子技术有限公司 filed Critical 成都海光微电子技术有限公司
Publication of WO2021120712A1 publication Critical patent/WO2021120712A1/en
Publication of WO2021120712A8 publication Critical patent/WO2021120712A8/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30094—Condition code generation, e.g. Carry, Zero flag
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30196—Instruction operation extension or modification using decoder, e.g. decoder per instruction set, adaptable or programmable decoders

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)

Abstract

An instruction generation method and apparatus, an instruction execution method, a processor, an electronic device, and a storage medium. Said method comprises: determining that an instruction execution unit supports data forwarding (S101); when instructions are generated, setting, in an ith instruction, a first identifier configured to instruct to write destination data of the ith instruction into a forwarding path, and setting, in an (i+j)th instruction, a second identifier configured to instruct to acquire a source operand from the forwarding path (S102); and sending the ith instruction and the (i+j)th instruction to the instruction execution unit, so that when executing the instructions, the instruction execution unit writes the result of the ith instruction into the forwarding path according to the first identifier, and acquires the required source operand from the forwarding path according to the second identifier (S103). By means of setting, in the instructions, a first identifier configured to instruct to write the destination data into the forwarding path and a second identifier configured to indicate that a source operand is derived from the forwarding path, explicit data forwarding of hardware is realized forcibly by means of software, and the number of times of access of a memory is reduced.
PCT/CN2020/114002 2019-12-16 2020-09-08 Instruction generation method and apparatus, instruction execution method, processor, electronic device, and storage medium WO2021120712A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201911300243.6A CN111124492B (en) 2019-12-16 2019-12-16 Instruction generation method and device, instruction execution method, processor and electronic equipment
CN201911300243.6 2019-12-16

Publications (2)

Publication Number Publication Date
WO2021120712A1 WO2021120712A1 (en) 2021-06-24
WO2021120712A8 true WO2021120712A8 (en) 2021-08-05

Family

ID=70498193

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/114002 WO2021120712A1 (en) 2019-12-16 2020-09-08 Instruction generation method and apparatus, instruction execution method, processor, electronic device, and storage medium

Country Status (2)

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CN (1) CN111124492B (en)
WO (1) WO2021120712A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111124492B (en) * 2019-12-16 2022-09-20 成都海光微电子技术有限公司 Instruction generation method and device, instruction execution method, processor and electronic equipment
CN112182496B (en) * 2020-09-24 2022-09-16 成都海光集成电路设计有限公司 Data processing method and device for matrix multiplication
CN114968358A (en) * 2020-10-21 2022-08-30 上海壁仞智能科技有限公司 Apparatus and method for configuring cooperative thread bundle in vector computing system
CN112199119B (en) * 2020-10-21 2022-02-01 上海壁仞智能科技有限公司 Vector operation device
CN112506567B (en) * 2020-11-27 2022-11-04 海光信息技术股份有限公司 Data reading method and data reading circuit
CN112559045B (en) * 2020-12-23 2022-09-16 中国电子科技集团公司第五十八研究所 RISCV-based random instruction generation platform and method

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US5974538A (en) * 1997-02-21 1999-10-26 Wilmot, Ii; Richard Byron Method and apparatus for annotating operands in a computer system with source instruction identifiers
US6542982B2 (en) * 2000-02-24 2003-04-01 Hitachi, Ltd. Data processer and data processing system
US20080148020A1 (en) * 2006-12-13 2008-06-19 Luick David A Low Cost Persistent Instruction Predecoded Issue and Dispatcher
US7921279B2 (en) * 2008-03-19 2011-04-05 International Business Machines Corporation Operand and result forwarding between differently sized operands in a superscalar processor
CN101477456B (en) * 2009-01-14 2011-06-08 北京大学深圳研究生院 Self-correlated arithmetic unit and processor
US9424041B2 (en) * 2013-03-15 2016-08-23 Samsung Electronics Co., Ltd. Efficient way to cancel speculative ‘source ready’ in scheduler for direct and nested dependent instructions
CN104216681B (en) * 2013-05-31 2018-02-13 华为技术有限公司 A kind of cpu instruction processing method and processor
CN103455454B (en) * 2013-09-02 2016-09-07 华为技术有限公司 A kind of method and apparatus controlling memory startup
CN104516726B (en) * 2013-09-27 2018-08-07 联想(北京)有限公司 A kind of method and device of instruction processing
CN104536914B (en) * 2014-10-15 2017-08-11 中国航天科技集团公司第九研究院第七七一研究所 The associated processing device and method marked based on register access
US10108417B2 (en) * 2015-08-14 2018-10-23 Qualcomm Incorporated Storing narrow produced values for instruction operands directly in a register map in an out-of-order processor
US11687345B2 (en) * 2016-04-28 2023-06-27 Microsoft Technology Licensing, Llc Out-of-order block-based processors and instruction schedulers using ready state data indexed by instruction position identifiers
CN110058884B (en) * 2019-03-15 2021-06-01 佛山市顺德区中山大学研究院 Optimization method, system and storage medium for computational storage instruction set operation
CN111124492B (en) * 2019-12-16 2022-09-20 成都海光微电子技术有限公司 Instruction generation method and device, instruction execution method, processor and electronic equipment

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Publication number Publication date
CN111124492B (en) 2022-09-20
CN111124492A (en) 2020-05-08
WO2021120712A1 (en) 2021-06-24

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