WO2021120015A1 - 一种确定功耗限制的方法和装置 - Google Patents

一种确定功耗限制的方法和装置 Download PDF

Info

Publication number
WO2021120015A1
WO2021120015A1 PCT/CN2019/126086 CN2019126086W WO2021120015A1 WO 2021120015 A1 WO2021120015 A1 WO 2021120015A1 CN 2019126086 W CN2019126086 W CN 2019126086W WO 2021120015 A1 WO2021120015 A1 WO 2021120015A1
Authority
WO
WIPO (PCT)
Prior art keywords
power consumption
processor
cycle
period
consumption information
Prior art date
Application number
PCT/CN2019/126086
Other languages
English (en)
French (fr)
Inventor
胡荻
刘臻
王哲
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201980102242.2A priority Critical patent/CN114730207A/zh
Priority to PCT/CN2019/126086 priority patent/WO2021120015A1/zh
Publication of WO2021120015A1 publication Critical patent/WO2021120015A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power

Definitions

  • This application relates to the field of chip technology, and in particular to a method and device for determining power consumption limits.
  • TDP thermal design power
  • PL power limit
  • the short-term average power consumption of the processor will drop from the value of PL2 to and stabilize at the value of TDP. That is, the value of PL2 is less than the power consumption limit of the maximum power supply current of the system, which can prevent the occurrence of over-current situations, thereby avoiding situations such as power-off or hang-up of the processor.
  • the value of PL at all levels is statically configured and needs to be configured according to the worst case of the processor to ensure that the processor is also safe to run in worst case. Therefore, the default value of PL is usually set Lower. When the value of PL is low, the frequency of the processor running is also low, that is, the performance of the processor will be correspondingly low.
  • the embodiments of the present application provide a method and device for determining power consumption limits, which can flexibly configure power consumption limits PL according to different power consumption scenarios, and improve processor performance.
  • a method for determining a power consumption limit including: obtaining power consumption information of a processor during at least one first cycle running; and determining that the processor is running in a second cycle according to the power consumption information of at least one first cycle
  • the power consumption at the time limit PL, the first period is the period before the second period.
  • the power consumption information of at least one first cycle can be understood as historical power consumption information, and the historical power consumption information can reflect the power consumption changes of the processor in the past period of time. In this way, it can be based on the historical power consumption information.
  • the power consumption information judges the power consumption change of the current program, so that the instantaneous power consumption of the current program can be determined according to the power consumption change of the current program to reach the over-current power consumption limit, and the value of PL can be adjusted according to the level of risk. Flexible configuration of power consumption limit PL in the power consumption scenarios to improve processor performance.
  • the power consumption information of at least one first cycle is used to indicate the amount of power consumption change of the processor when the processor is running in the at least one first cycle.
  • the change in power consumption of the processor during at least one first cycle is relatively high, it means that the power consumption of the processor during at least one first cycle has high volatility; when the processor is operating during at least one first cycle
  • the amount of change in power consumption during internal operation is low, it indicates that the power consumption fluctuation of the processor during operation in at least one first cycle is low.
  • each first cycle includes multiple time points; acquiring the power consumption information of the processor during at least one first cycle includes: acquiring all adjacent points of the processor during at least one first cycle The accumulated value of the power consumption variation at two time points; and the power consumption variation of the processor when the processor is running in the at least one first cycle is obtained according to the accumulated value and the duration of the at least one first cycle.
  • the amount of change in power consumption at two adjacent time points is the absolute value of the difference between the power consumption at the two adjacent time points, that is, the absolute value of the difference between the instantaneous power consumption at the two adjacent time points.
  • obtaining the power consumption information of the processor during at least one first cycle includes: weighting the power consumption information of the processor during each first cycle to obtain the processor in the at least one first cycle. Power consumption information during one cycle of operation. The reason why the weighted calculation method is used here is that it takes into account that the power consumption information of the most recent first cycle can better reflect the volatility of the current power consumption.
  • the weighting method is exponentially weighted moving average EWMA. Taking into account that the instantaneous power consumption of the processor is constantly changing, the instantaneous power consumption at a close time point can better reflect the power consumption volatility of the current program. Therefore, when the EWMA calculation method is used, the weight of the close time point Larger.
  • the first cycle includes multiple time points, and the power consumption information corresponding to the first cycle is used to indicate the power consumption changes at all two adjacent time points when the processor is running in the first cycle The cumulative value of the amount.
  • determining the power consumption limit PL of the processor during operation in the second cycle according to the power consumption information of the at least one first cycle includes: PL setting processing corresponding to the power consumption information of the at least one first cycle PL when the device is running in the second cycle.
  • the PL of the second cycle can be determined according to the correspondence between the historical power consumption information and the PL.
  • the method further includes: acquiring at least one PL corresponding to the power consumption information of the first period.
  • obtaining the PL corresponding to the power consumption information of the at least one first cycle includes: determining the level of the power consumption information of the at least one first cycle; taking the PL corresponding to the determined level as the at least The PL corresponding to the power consumption information of a first cycle. That is to say, the present application may preset the correspondence between the level of power consumption information and the PL, so as to determine the PL of the second period according to the correspondence, so as to achieve the purpose of adjusting the PL according to the historical power consumption information.
  • the method further includes: determining the operating frequency of the processor when the processor is running in the second cycle according to the PL of the second cycle.
  • PL can be used as a reference factor when the processor is running in the second cycle.
  • the possibility of the processor running at a high operating frequency increases, which can improve the performance of the processor.
  • the at least one first cycle includes the current cycle and at least one cycle before the current cycle, and the second cycle is the next cycle of the current cycle.
  • a device for determining power consumption limits including: a power consumption monitor, configured to obtain power consumption information when a processor is running in at least one first cycle; and a power consumption predictor, configured according to at least one The power consumption information of the first cycle determines the power consumption limit PL when the processor is running in the second cycle, and the first cycle is the cycle before the second cycle.
  • the power consumption information of at least one first cycle is used to indicate the amount of power consumption change of the processor when the processor is running in the at least one first cycle.
  • each first cycle includes multiple time points; a power consumption monitor is used to obtain the cumulative amount of power consumption changes of the processor at all two adjacent time points in at least one first cycle Value; According to the accumulated value and the duration of at least one first cycle, obtain the power consumption change amount of the processor during at least one first cycle.
  • the power consumption monitor is configured to: weight the power consumption information of the processor during each first cycle to obtain the power consumption information of the processor during at least one first cycle.
  • the weighting method is exponentially weighted moving average EWMA.
  • the first cycle includes multiple time points, and the power consumption information corresponding to the first cycle is used to indicate the power consumption changes at all two adjacent time points when the processor is running in the first cycle The cumulative value of the amount.
  • the power consumption predictor is used to set the PL of the processor when the processor is running in the second cycle according to the PL corresponding to the power consumption information of the at least one first cycle.
  • the power consumption predictor is further used to obtain the PL corresponding to the power consumption information of at least one first cycle.
  • the power consumption predictor is used to: determine the level of at least one first cycle of power consumption information; use the PL corresponding to the determined level as the PL corresponding to the at least one first cycle of power consumption information .
  • the frequency controller is used to determine the operating frequency of the processor during the second cycle according to the PL of the second cycle.
  • the at least one first cycle includes the current cycle and at least one cycle before the current cycle, and the second cycle is the next cycle of the current cycle.
  • a computer-readable storage medium including a program or instruction.
  • the program or instruction is executed by a processor, the method described in the first aspect and any one of the possible designs of the first aspect is carried out.
  • a computer program product is provided.
  • the electronic device executes the method described in the first aspect and any one of the possible designs of the first aspect.
  • a communication device in a fifth aspect, includes the second aspect or a device corresponding to any possible design of the second aspect.
  • a chip in a sixth aspect, includes the second aspect or a device corresponding to any possible design of the second aspect.
  • FIG. 1 is a schematic diagram of an application scenario provided by an embodiment of the application
  • FIG. 2 is a schematic structural diagram of a multi-core processor provided by an embodiment of the application.
  • FIG. 3 is a schematic structural diagram of a multi-core processor provided by an embodiment of the application.
  • FIG. 4 is a schematic flowchart of a method for determining power consumption limit provided by an embodiment of the application
  • FIG. 5 is a schematic flowchart of a method for determining a power consumption limit provided by an embodiment of the application
  • FIG. 6 is a schematic structural diagram of a frequency controller provided by an embodiment of the application.
  • FIG. 7 is a schematic diagram of a curve of instantaneous power consumption provided by an embodiment of the application.
  • FIG. 8 is a schematic diagram of a curve of instantaneous power consumption provided by an embodiment of this application.
  • FIG. 9 is a schematic flowchart of a method for determining a power consumption limit provided by an embodiment of the application.
  • FIG. 10 is a schematic structural diagram of a computing system provided by an embodiment of this application.
  • Desktop processor refers to the processor used as a desktop computer, can be understood as a desktop computer or server processor. Desktop processors usually support overclocking features, with higher power consumption and temperature.
  • Mobile processor A processor designed for mobile terminals, such as laptops, smart phones, or tablets.
  • Server processor A processor designed for servers.
  • TDP It is an indicator that reflects the heat release of a processor, and its meaning is the highest heat dissipation heat that may be released when the processor reaches the maximum load, in watts (W).
  • W watts
  • the heat sink must ensure that when the processor's heat dissipation reaches the TDP, the processor's temperature is still within the design range, that is, the TDP is the highest heat dissipation limit for the processor to run stably for a long time.
  • the actual power consumption of the processor is generally greater than TDP, especially for processors that support overclocking, TDP can only represent the heat released under the default frequency state.
  • Processor power consumption The product of the current value flowing through the processor core and the core voltage value on the processor, in W.
  • the value of the TDP of the processor is less than the power consumption of the processor.
  • Instantaneous power consumption The power consumption of the processor at each point in time.
  • the embodiments of the present application may be applied to a terminal device or a network device.
  • the terminal device may be a desktop computer, a notebook computer, a mobile terminal, or a large computer.
  • the network device may be a server, etc., and its processor may be a server processor. If the terminal device is a desktop computer, its processor may be a desktop processor. If the terminal device is a mobile terminal, its processor may be a mobile-end processor, for example, it may specifically be a system-on-chip (SoC).
  • SoC system-on-chip
  • the processor of the terminal device or network device may be a single-core processor or a multi-core processor.
  • the processor 20 may include multiple processor cores 21, processor non-core circuits 22, and multiple power consumptions. Monitor 23 and frequency controller 24.
  • Each processor core 21 may correspond to a power consumption monitor 23 for monitoring the power consumption of the processor core 21.
  • the processor non-core circuit 22 also corresponds to a power consumption monitor 23 for monitoring the power consumption of the processor non-core circuit 22.
  • the processor non-core circuit 22 may include an external cache, an internal memory, a general-purpose unit, an accelerator, an input/output control unit (or interface unit), and the like.
  • Each power consumption monitor 23 can send the power consumption of the corresponding monitored processor core 21 or processor non-core circuit 22 to the frequency controller 24, and the frequency controller 24 can be used to summarize the power consumption sent by each power consumption monitor 23 , And finally determine the total power consumption of the processor 20 during operation.
  • the frequency controller 24 can control the operating frequency of the processor 20 according to the value of PL higher than the TDP to control the processing The power consumption of the device 20 does not exceed the value of PL to prevent the occurrence of overcurrent.
  • the frequency controller 24 may be a general-purpose processor.
  • the structure of the multi-core processor shown in FIG. 2 is only an exemplary structure, and is not limited to the structure shown in FIG. 2.
  • the multi-core processor may have only one power consumption monitor, and the power consumption monitor may monitor the power consumption of multiple processor cores 21 and processor non-core circuits 22.
  • the values of power consumption limits such as TDP and PL2 are statically configured.
  • the value of PL2 is usually set to a low value, which makes the processor's The instantaneous power consumption is low, which in turn makes the frequency of the processor work also low, resulting in low performance of the processor.
  • this application proposes a method for determining the power consumption limit, the basic principle of which can be: according to the historical power consumption of the processor, the change in the power consumption of the processor during operation can be determined, and the value of PL can be adjusted according to the change in power consumption. .
  • the value of PL can be adjusted up or down appropriately according to changes in power consumption.
  • a power consumption predictor 25 may be added to the above-mentioned processor of FIG. 2. As shown in FIG. 3, the power consumption predictor 25 may exist alone in the processor 20 or may be added to the frequency controller 24. When the power consumption predictor 25 exists alone, the power consumption predictor 25 may be implemented by hardware. When the power consumption predictor 25 is in the frequency controller 24, the power consumption predictor 25 may be implemented by hardware or firmware. In some embodiments, when the frequency controller 24 is a general-purpose processor, the present application may add firmware used to implement the embodiments of the present application in the processor to implement the method for determining the power consumption limit of the present application. .
  • this application provides a method for determining power consumption limits. As shown in FIG. 4, taking a terminal device as an example, the method includes:
  • a terminal device acquires power consumption information of a processor when at least one first cycle is running.
  • the first cycle may be one of a plurality of configured clock cycles. Since the load of the processor at different time points changes instantaneously, the operating voltage and operating current of the processor also change instantaneously, so the power consumption of the processor 20 at different time points also changes instantaneously. It can also be said that the power consumption of the processor when running a program is fluctuating.
  • the power consumption change of the processor 20 during operation in the first cycle can be known according to the power consumption information of the first cycle.
  • Step 301 may be performed by the power consumption monitor 23 described above.
  • the terminal device determines the PL when the processor is running in the second cycle according to at least one power consumption information of the first cycle, where the first cycle is a cycle before the second cycle.
  • the duration of the first period and the duration of the second period may be the same.
  • the current power consumption changes of the program can be known based on the power consumption information of at least one first cycle, that is, the power consumption changes of the processor 20 during at least one first cycle are known, and then the power consumption can be determined according to the power consumption. Change and adjust the value of PL in the second cycle.
  • the value of PL can be appropriately reduced to avoid the instantaneous power consumption at a certain point in time reaching the overcurrent power consumption limit, and to prevent overcurrent Circumstances occur; when at least one power consumption change in the first cycle reflects low power consumption volatility, then it is considered that the instantaneous power consumption of the current program has a low risk of reaching the overcurrent power consumption limit, and the value of PL can be appropriately increased At the same time as the value of PL is increased, the operating frequency of the processor is also increased correspondingly, and the performance of the processor is also optimized.
  • Step 302 may be executed by the power consumption predictor 25 described above.
  • the present application further describes the method for determining the power consumption limit.
  • the embodiment of the present application provides a method for determining power consumption limit, as shown in FIG. 5, including:
  • the terminal device obtains the cumulative value of the power consumption variation of the processor at all two adjacent time points in at least one first cycle.
  • the power consumption volatility may be reflected by the amount of power consumption change of the processor during at least one first cycle.
  • the change in power consumption may be an average value of the change in power consumption when the processor is running in one cycle.
  • To obtain the average value of the power consumption variation first obtain the cumulative value of the power consumption variation of the processor at all two adjacent time points in at least one first cycle.
  • each first cycle may include multiple time points, and the power consumption variation of the two time points may be the instantaneous power consumption of the processor at a previous time point and the instantaneous power consumption of the processor at a later time point.
  • the sum of the power consumption changes at all two adjacent time points in the first cycle is the cumulative value of the power consumption changes at all adjacent time points in the first cycle, and then multiple first cycles can be obtained.
  • the accumulated value P of the power consumption changes at all two adjacent time points.
  • the change in power consumption, the change in instantaneous power consumption, and the change in total power consumption mentioned in the embodiments of the present application are all positive values or absolute values.
  • the instantaneous power consumption of the processor core 21 or the processor non-core circuit 22 can be monitored through the power consumption monitor 23, namely Obtain the power consumption of the processor core 21 at each time point and the power consumption of the non-processor core circuit 22 at each time point.
  • the power consumption predictor 25 can be processed according to the power consumption monitored by each power consumption monitor 23 The total power consumption of the device 20 at each time point, and then according to the total power consumption at the previous time point and the total power consumption at the next time point, the amount of change in the total power consumption at two adjacent time points can be obtained, In this way, the power consumption predictor 25 can obtain the accumulated value P of the power consumption changes at all two adjacent time points in at least one first period.
  • the power consumption monitor 23 when the power consumption monitor 23 monitors the instantaneous power consumption of the processor core 21 or the processor non-core circuit 22 at each time point, the power consumption monitor 23 may be based on the integrated voltage regulator (integrated voltage regulator). , IVR) Read the real-time current and voltage values, and calculate the power consumption at each time point.
  • the implementation manner for the power consumption predictor 25 to obtain the accumulated value P of the power consumption variation at all adjacent time points in at least one first period may be a hardware implementation or a firmware implementation.
  • the power consumption predictor 25 may be a program executable by the frequency controller 24.
  • the power consumption predictor 25 can be based on the power consumption at each time point sent by each power consumption monitor 23.
  • the total power consumption of the processor 20 at each time point is calculated by calculation, and then the total power consumption of the two time points can be obtained according to the total power consumption at the previous time point and the total power consumption at the next time point.
  • the power consumption predictor 25 can then obtain the accumulated value P of the power consumption change amount at all two adjacent time points in at least one first period.
  • the power consumption predictor 25 obtains the cumulative value P of the power consumption changes at all two adjacent time points in at least one first period.
  • the hardware structure can be as shown in FIG. 6, the power consumption prediction
  • the device 25 may include a power consumption module, a register, a comparator, and an accumulator.
  • the power consumption module can be used to summarize the total power consumption of the processor core 21 and the processor non-core circuit 22 at each time point;
  • the comparator is used to obtain the total power consumption of the processor 20 at the current time point input by the power consumption module and the total power consumption of the processor 20 at the last time point input by the register to obtain the total power consumption of two adjacent time points.
  • the amount of change in power consumption In the embodiments of the present application, the amount of change in the total power consumption at adjacent time points may also be referred to as the amplitude of the instantaneous power consumption.
  • the accumulator is used to accumulate the total power consumption changes at two adjacent time points output by the comparator, so as to obtain the cumulative value of the power consumption changes at all two adjacent time points in at least one first period.
  • the terminal device obtains the power consumption change amount of the processor during the operation of the processor in the at least one first cycle according to the accumulated value and the duration of the at least one first cycle.
  • the power consumption information in step 301 may be used to indicate the amount of power consumption change of the processor 20 during at least one first cycle.
  • the power consumption information in step 301 may be used to indicate the average value of the power consumption variation when the processor 20 is running in at least one first cycle.
  • the average value of the change in power consumption of the processor 20 during operation in at least one first period can be understood as the average value of the change in instantaneous power consumption at multiple time points in the at least one first period, or referred to as average power. Consumption volatility.
  • the power consumption predictor 25 obtains the average value Q of the power consumption variation during the operation of the processor 20 in at least one first cycle, which may be implemented in firmware or hardware.
  • the power consumption predictor 25 may also include a divider.
  • the divider is set with a period. When the divider determines that the time of at least one first period is reached, it can be obtained according to the accumulator.
  • the accumulated value P corresponding to a first period and the duration T of at least one first period are calculated to obtain the average value Q of the power consumption change when the processor 20 is running in the first period less than one period.
  • the terminal device determines the PL of the second cycle according to the amount of change in power consumption when the processor is running in at least one first cycle.
  • the amount of change in power consumption of the processor 20 during at least one first cycle is relatively high, it is considered that the volatility of the power consumption of the processor 20 running the current program is relatively high, and at least one first cycle can be appropriately reduced.
  • the value of PL in the second cycle afterwards to prevent the instantaneous power consumption from reaching the limit power consumption of the maximum power supply current of the system; if the power consumption change of the processor 20 during at least one first cycle is low, the processor 20 is considered The power consumption volatility of running the current program is relatively low, and the value of PL in the second cycle after at least one first cycle can be appropriately increased to give the processor 20 the possibility of working at a high frequency in the second cycle, thereby improving the processor 20 Performance.
  • the second cycle can be appropriately reduced.
  • the value of PL is to prevent the instantaneous power consumption from reaching the limit power consumption of the maximum power supply current of the system; if the average value of the power consumption variation of the processor 20 during at least one first cycle is low, it is considered that the processor 20 is running the current program The power consumption volatility of the current program is low. The risk of the instantaneous power consumption of the current program reaching the limit of the maximum power supply current of the system is low.
  • the value of PL in the second cycle can be appropriately increased, so that the processor 20 can be given to work in the next cycle The possibility of high frequency, thereby enhancing the performance of the processor 20.
  • the terminal device determining the PL of the processor when the processor is running in the second cycle according to the power consumption information of the at least one first cycle may include:
  • the PL when the processor 20 is running in the second cycle is set according to the PL corresponding to the power consumption information of the at least one first cycle.
  • the present application may establish a correspondence between power consumption information and PL, so as to set the PL according to the correspondence.
  • the method may further include: acquiring the PL corresponding to the power consumption information of the at least one first period.
  • obtaining the PL corresponding to the power consumption information of at least one first period may include:
  • the level of at least one first cycle of power consumption information is determined; the PL corresponding to the determined level is taken as the PL corresponding to the at least one first cycle of power consumption information.
  • determining the level of the power consumption information of the at least one first cycle may be determined by comparing the power consumption information of the at least one first cycle with at least one preset threshold, that is, the power consumption determined according to the comparison result. The level of information.
  • the power consumption information AT corresponding to at least one first cycle is less than the first preset threshold (M)
  • the level of the power consumption information of the at least one first cycle is the first level
  • the PL corresponding to the first level is the first PL (X+Y);
  • the power consumption information AT corresponding to at least one first cycle is greater than or equal to the first preset threshold (M) and less than the second preset threshold (V), determine the level of the power consumption information of the at least one first cycle It is the second level, and the PL corresponding to the second level is the second PL(X);
  • the second preset threshold (N) If the historical power consumption information AT corresponding to at least one first cycle is greater than the second preset threshold (N), it is determined that the level of the power consumption information of the at least one first cycle is the third level, and the PL corresponding to the third level Is the third PL(XY);
  • the first PL (X+Y) is greater than the second PL (X), and the second PL (X) is greater than the third PL (XY).
  • X, Y, and AT are all positive values.
  • Historical power consumption information AT PL (Unit: W) A T ⁇ M X+Y M ⁇ A T ⁇ N X A T >N X-Y
  • the frequency controller 24 may send an update instruction to at least one processor core 21 and the processor non-core circuit 22, and the update instruction includes the value of the PL in the second cycle so that at least one
  • the processor core 21 or the processor non-core circuit 22 may control the operating load of the processor 20 according to the updated PL value. For example, when the value of PL is increased relative to the value of PL in the period before the second period, the processor core 21 may work at a higher frequency, which can improve the performance of the processor 20. When the value of PL is reduced relative to the value of PL in the period before the second period, the processor core 21 can appropriately reduce the operating frequency of the processor core 21 to prevent the occurrence of overcurrent.
  • FIG. 7 and FIG. 8 are schematic diagrams of the instantaneous power consumption of the processor 20.
  • PL1 can be considered as the power consumption limit corresponding to TDP
  • PL2 is the power consumption limit to prevent overcurrent.
  • the method for determining the power consumption limit in this application It can be an adjustment to PL2. It can be seen from FIGS. 7 and 8 that before time T, the average instantaneous power consumption of the processor 20 represented by the two instantaneous power consumption curves is the same, but the amount of change in the instantaneous power consumption is different. Among them, the amount of change in the instantaneous power consumption in FIG. 7 is smaller than the amount of change in the instantaneous power consumption in FIG. 8.
  • the embodiment of the present application can flexibly configure the value of PL according to different power consumption scenarios of the processor, improve the ability of the overclocking feature to cope with different power consumption scenarios, and improve the performance of the processor.
  • the following embodiments of the present application also provide a method for determining power consumption limits, as shown in FIG. 9, including:
  • the terminal device acquires power consumption information of the processor when the processor is running in each first cycle of at least one first cycle.
  • the first period may include multiple time points.
  • the power consumption information corresponding to the first cycle is used to indicate the cumulative value of the power consumption changes at all two adjacent time points when the processor is running in the first cycle.
  • the power consumption information corresponding to the first cycle may also be used to indicate the average value of the power consumption changes at all two adjacent time points when the processor is running in the first cycle.
  • the manner of acquiring the power consumption information corresponding to each first cycle in step 801 may refer to the manner of acquiring the power consumption information corresponding to the first cycle in step 401 above, which will not be repeated here.
  • the terminal device weights the power consumption information when the processor is running in each first cycle to obtain power consumption information when the processor is running in at least one first cycle.
  • the weighting method may be an exponentially weighted moving-average (EWMA) method. That is, the power consumption information corresponding to at least one first cycle is obtained by performing EWMA calculation on the power consumption information corresponding to at least one first cycle.
  • EWMA exponentially weighted moving-average
  • a t is assumed to be understood that the amount of change in the average power consumption of time on a small particle size, for example, the change amount A t is the average power consumption amount of change corresponding to the first period, the first period corresponding
  • the average value of is the average value of power consumption changes at all two adjacent time points in the first period; AT is understood as the average value of power consumption changes in a long-term granularity, for example, AT is at least
  • a T EWMA(A t ), that is, A T is the average value of the power consumption change in the long-term granularity obtained through EWMA.
  • a T EWMA(A t ) can be expanded and explained.
  • a T ⁇ A(t)+(1- ⁇ ) ⁇ A(t-1)+(1- ⁇ ) 2 ⁇ A(t-2)+(1- ⁇ ) 3 ⁇ A(t-3)
  • ⁇ can be understood as the weight corresponding to the most recent first cycle in at least one first cycle
  • A(t) can be understood as the average value of the power consumption change corresponding to the most recent first cycle. It can be seen that in at least one first cycle, the closer the time, the greater the weight of the average power consumption change corresponding to the first cycle, and the farther the time, the average power consumption change corresponding to the first cycle The smaller the weight.
  • the terminal device sets the PL when the processor is running in the second cycle according to the PL corresponding to the power consumption information when the processor is running in the at least one first cycle.
  • the terminal device may decide how to dynamically set the value of PL according to the value of AT. For specific implementation, see step 403 and Table 1.
  • the embodiment of the present application can flexibly configure the value of PL according to different power consumption scenarios of the processor, improve the ability of the overclocking feature to cope with different power consumption scenarios, and improve the performance of the processor.
  • FIG. 10 illustrates a block diagram of a computing system 100 according to an embodiment of the present application.
  • the computing system 100 may include one or more central processing units (CPU) or processors 102-1 to 102-P (herein may be referred to as "multiple processors 102" or “processors 102").
  • the processor 102 can communicate via a bus (or interconnection network) 104.
  • the processor 102 may include a general-purpose processor, a network processor (processing data transmitted on the computer network 103) or other types of processors (including reduced instruction set computing (RISC) processors or complex instruction set computers (complex instruction set computer, CISC)).
  • RISC reduced instruction set computing
  • CISC complex instruction set computers
  • multiple processors 102 may have a single or multiple core design.
  • the processor 102 with a multi-core design can integrate different types of processor cores on the same integrated circuit (IC) die.
  • the processor 102 with a multi-core design may be implemented as a symmetric or asymmetric multi-processor.
  • the one or more processors 102 may be the same as or similar to the processor
  • the computing system 100 of the present application may also include a chipset 106.
  • the chipset 106 can also communicate with the bus 104.
  • the chipset 106 may include a graphics memory controller hub (GMCH) 108.
  • the GMCH 108 may include a memory controller 110 that communicates with the memory 112.
  • the memory 112 may store data, which includes a sequence of instructions executed by the processor 102 or any other device included in the computing system 100.
  • the memory 112 may include one or more volatile storage (or memory) devices, such as random access memory (RAM), dynamic RAM (DRAM), and synchronous DRAM (synchronous dynamic RAM, SDRAM), static RAM (static RAM, SRAM) or other types of storage devices. It is also possible to use non-volatile memory, such as a hard disk. Other devices may communicate via the bus 104, such as multiple CPUs and/or multiple system memories.
  • the GMCH 108 may also include a graphics interface 114 for communicating with a graphics accelerator 116 and a display (not shown in the figure).
  • the display for example, a flat panel display, a cathode-ray-tube (CRT), a projection screen, etc.
  • the graphics interface 114 may communicate with the graphics interface 114 through, for example, a signal converter, wherein the signal conversion The converter converts the digital representation of the image stored in a storage device (for example, video memory or system memory) into a display signal that is interpreted and displayed by the display.
  • the display signal generated by the display device can pass through various control devices before being interpreted by the display and then displayed thereon.
  • the computing system 100 of the present application may further include an input/output control center (input/output controller hub, ICH) 120, and the ICH 120 may provide an interface for I/O devices that communicate with the computing system 100.
  • the ICH 120 can pass through a peripheral device bridge (or controller) 124 (for example, a Peripheral Component Interconnect (PCI) bridge, a universal serial bus (USB) controller, or other types of peripheral device bridges). Or the controller) communicates with the bus 122.
  • the peripheral device bridge 124 may provide a data path between the processor 102 and peripheral devices.
  • multiple buses 122 can communicate with the ICH 120.
  • bus 122 may also communicate with an audio device 126, one or more hard disk drives 128, and one or more network interface devices 130 (which communicate with the computer network 103).
  • the disclosed device and method may be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods, for example, multiple units or components may be divided. It can be combined or integrated into another device, or some features can be omitted or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate parts may or may not be physically separate.
  • the parts displayed as units may be one physical unit or multiple physical units, that is, they may be located in one place, or they may be distributed to multiple different places. . Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • the functional units in the various embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated unit can be implemented in the form of hardware or software functional unit.
  • the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium.
  • the technical solutions of the embodiments of the present application are essentially or the part that contributes to the prior art, or all or part of the technical solutions can be embodied in the form of a software product, and the software product is stored in a storage medium. It includes several instructions to make a device (which may be a single-chip microcomputer, a chip, etc.) or a processor (processor) execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read only memory (read only memory, ROM), random access memory (random access memory, RAM), magnetic disk or optical disk and other media that can store program codes.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)

Abstract

一种确定功耗限制的方法和装置，涉及芯片技术领域，可根据不同的功耗场景灵活配置功耗限制PL，提升处理器性能。其方法为：终端设备获取处理器在至少一个第一周期运行时的功耗信息（301）；终端设备根据至少一个第一周期的功耗信息确定处理器在第二周期运行时的功耗限制PL，第一周期为第二周期之前的周期（302）。该方法用于根据历史的功耗信息动态调整PL的值，进而提升处理器功耗。

Description

一种确定功耗限制的方法和装置 技术领域
本申请涉及芯片技术领域，尤其涉及一种确定功耗限制的方法和装置。
背景技术
目前，中高端处理器具备了超频特性。超频，是允许处理器在短时间内可以运行在较高的频率上，处理器的功耗在该短时间内可以超过热设计功耗(thermal design power，TDP)，TDP通常被认为是第一级功耗限制PL(power limit)，即PL1。为了防止超频状态的处理器功耗在突破TDP以后无限制的增长，进而引发过流等负面状态，还需要设置一个高于TDP的功耗限制PL2。通常的，当处理器在短时间内处于超频场景时，其长期平均功耗不可以超过TDP，而短期平均功耗不可以超过PL2。若系统功耗余量耗尽(即TDP或PL2的限制被突破)，处理器的短期平均功耗会从PL2的值下降至并稳定在TDP的值。即PL2的值小于系统最大供电电流的功耗限制，可防止过流的情况发生，进而避免发生例如处理器下电或挂死等情况。
通常，各级PL的值是静态配置的，且需按照处理器的最坏情况(worst case)进行配置，以保证处理器在worst case下也是安全运行的，因此，PL的默认值通常设置的较低。当PL的值较低时，导致处理器运行时的频率也较低，即处理器的性能也会相应的比较低。
发明内容
本申请实施例提供一种确定功耗限制的方法和装置，可根据不同的功耗场景灵活配置功耗限制PL，提升处理器性能。
为达到上述目的，本申请实施例采用如下技术方案：
第一方面，提供一种确定功耗限制的方法，包括:获取处理器在至少一个第一周期运行时的功耗信息；根据至少一个第一周期的功耗信息确定处理器在第二周期运行时的功耗限制PL，第一周期为所述第二周期之前的周期。
本申请实施例中，至少一个第一周期的功耗信息可以理解为历史的功耗信息，历史的功耗信息可以反映出处理器在过去一段时间的功耗变化情况，这样，可以根据历史的功耗信息判断目前程序的功耗变化，以便可以根据目前程序的功耗变化确定当前程序的瞬时功耗达到过流的功耗限制的风险，以根据风险高低调整PL的值，可以实现根据不同的功耗场景灵活配置功耗限制PL，提升处理器性能。
在一种可能的设计中，至少一个第一周期的功耗信息用于指示处理器在至少一个第一周期内运行时的功耗变化量。当处理器在至少一个第一周期内运行时的功耗变化量较高时，说明处理器在至少一个第一周期内运行时的功耗波动性较高；当处理器在至少一个第一周期内运行时的功耗变化量较低时，说明处理器在至少一个第一周期内运行时的功耗波动性较低。
在一种可能的设计中，每个第一周期包括多个时间点；获取处理器在至少一个第 一周期运行时的功耗信息包括：获取处理器在至少一个第一周期内所有相邻的两个时间点的功耗变化量的累加值；根据累加值与至少一个第一周期的时长，获取处理器在至少一个第一周期内运行时的功耗变化量。相邻的两个时间点的功耗变化量为相邻的两个时间点的功耗差值的绝对值，即前后两个时间点的瞬时功耗的差值的绝对值。
在一种可能的设计中，获取处理器在至少一个第一周期运行时的功耗信息包括:对处理器在每个第一周期运行时的功耗信息进行加权以获得处理器在至少一个第一周期运行时的功耗信息。这里之所以用到加权的计算方式，是考虑到时间最近的第一周期的功耗信息更能反映出当前功耗的波动性。
在一种可能的设计中，加权方式为指数加权移动平均EWMA。考虑到处理器的瞬时功耗是不断变化的，距离近的时间点的瞬时功耗更能够反映出当前程序的功耗波动性，因此，采用EWMA的计算方式时，距离近的时间点的权重较大。
在一种可能的设计中，第一周期包括多个时间点，第一周期对应的功耗信息用于指示处理器在第一周期内运行时，所有相邻的两个时间点的功耗变化量的累加值。
在一种可能的设计中，根据至少一个第一周期的功耗信息确定处理器在第二周期运行时的功耗限制PL包括：根据至少一个第一周期的功耗信息所对应的PL设置处理器在第二周期运行时的PL。也就是说，可以根据历史的功耗信息与PL的对应关系确定第二周期的PL。
在一种可能的设计中，还包括：获取至少一个第一周期的功耗信息所对应的PL。
在一种可能的设计中，获取所述至少一个第一周期的功耗信息所对应的PL包括：确定至少一个第一周期的功耗信息所在的级别；将确定的级别所对应的PL作为至少一个第一周期的功耗信息所对应的PL。也就是说，本申请可以预置有功耗信息的级别与PL的对应关系，以便根据该对应关系确定第二周期的PL，以实现根据历史的功耗信息调整PL的目的。
在一种可能的设计中，还包括：根据第二周期的PL确定处理器在第二周期运行时的工作频率。PL可以作为处理器在第二周期内运行时的一个参考因素。当PL较高时，处理器在高工作频率运行的可能性增加，可提升处理器的性能。
在一种可能的设计中，至少一个第一周期包括当前周期和当前周期之前的至少一个周期，第二周期为当前周期的下一个周期。
第二方面，提供一种确定功耗限制的装置，包括：功耗监测器，用于获取处理器在至少一个第一周期内运行时的功耗信息；功耗预测器，用于根据至少一个第一周期的功耗信息确定处理器在第二周期运行时的功耗限制PL，第一周期为第二周期之前的周期。
在一种可能的设计中，至少一个第一周期的功耗信息用于指示处理器在至少一个第一周期内运行时的功耗变化量。
在一种可能的设计中，每个第一周期包括多个时间点；功耗监测器，用于获取处理器在至少一个第一周期所有相邻的两个时间点的功耗变化量的累加值；根据累加值与至少一个第一周期的时长，获取处理器在至少一个第一周期内运行时的功耗变化量。
在一种可能的设计中，功耗监测器，用于：对处理器在每个第一周期运行时的功耗信息进行加权以获得处理器在至少一个第一周期运行时的功耗信息。
在一种可能的设计中，加权方式为指数加权移动平均EWMA。
在一种可能的设计中，第一周期包括多个时间点，第一周期对应的功耗信息用于指示处理器在第一周期内运行时，所有相邻的两个时间点的功耗变化量的累加值。
在一种可能的设计中，功耗预测器，用于：根据至少一个第一周期的功耗信息所对应的PL设置处理器在第二周期运行时的PL。
在一种可能的设计中，功耗预测器还用于：获取至少一个第一周期的功耗信息所对应的PL。
在一种可能的设计中，功耗预测器用于：确定至少一个第一周期的功耗信息所在的级别；将确定的级别所对应的PL作为至少一个第一周期的功耗信息所对应的PL。
在一种可能的设计中，还包括频率控制器；频率控制器，用于根据第二周期的PL确定处理器在第二周期运行时的工作频率。
在一种可能的设计中，至少一个第一周期包括当前周期和当前周期之前的至少一个周期，第二周期为当前周期的下一个周期。
第三方面，提供一种计算机可读存储介质，包括程序或指令，当所述程序或指令被处理器运行时，如第一方面以及第一方面的任一种可能的设计所述的方法被执行。
第四方面，提供一种计算机程序产品，当计算机程序产品在计算机上运行时，使得电子设备执行如第一方面以及第一方面的任一种可能的设计所述的方法。
第五方面，提供一种通信装置，该通信装置包括第二方面或第二方面的任一种可能的设计对应的装置。
第六方面，提供一种芯片，该芯片包括第二方面或第二方面的任一种可能的设计对应的装置。
附图说明
图1为本申请实施例提供的一种应用场景的示意图；
图2为本申请实施例提供的一种多核处理器的结构示意图；
图3为本申请实施例提供的一种多核处理器的结构示意图；
图4为本申请实施例提供的一种确定功耗限制的方法的流程示意图；
图5为本申请实施例提供的一种确定功耗限制的方法的流程示意图；
图6为本申请实施例提供的一种频率控制器的结构示意图；
图7为本申请实施例提供的一种瞬时功耗的曲线示意图；
图8为本申请实施例提供的一种瞬时功耗的曲线示意图；
图9为本申请实施例提供的一种确定功耗限制的方法的流程示意图；
图10为本申请实施例提供的一种计算系统的结构示意图。
具体实施方式
为了便于理解，示例的给出了部分与本申请实施例相关概念的说明以供参考。如下所示：
桌面级处理器：是指用作桌面型电脑使用的处理器，可以理解为台式电脑或服务器的处理器。桌面级处理器通常支持超频特性，功耗和温度较高。
移动端处理器：针对移动终端，如笔记本电脑、智能手机或平板电脑等而设计的处理器。
服务器处理器：针对服务器设计的处理器。
TDP：是反应一颗处理器热量释放的指标，其含义是当处理器达到负荷最大的时候，可能会释放出的最高散热热量，单位为瓦(W)。散热器必须保证在处理器的散热热量达到TDP时，处理器的温度仍然在设计范围之内，即TDP为处理器能够长期稳定运行的最高散热热量限制。处理器的实际功耗一般会大于TDP，尤其对于支持超频的处理器来说，TDP仅能代表其在默认频率状态下释放的热量。
处理器的功耗(功率)：流经处理器核心的电流值与该处理器上的核心电压值的乘积，单位为W。处理器的TDP的值小于处理器的功耗。
瞬时功耗：处理器运行在每个时间点时的功耗。
本申请可以应用于处理器处于超频场景下对功耗限制的调整。本申请实施例可以应用于终端设备或网络设备，如图1所示，该终端设备可以为台式电脑、笔记本电脑、移动终端或大型电脑等。网络设备可以为服务器等，其处理器可以为服务器处理器。若终端设备为台式电脑，其处理器可以为桌面级处理器。若终端设备为移动终端，其处理器可以为移动端处理器，例如具体可以为系统级芯片(system on chip，SoC)。
该终端设备或网络设备的处理器可以为单核处理器，也可以为多核处理器。
以处理器为多核处理器为例，本申请实施例中，如图2所示为一个多核处理器，处理器20可以包括多个处理器核心21、处理器非核心电路22、多个功耗监测器23以及频率控制器24。每个处理器核心21可以对应一个功耗监测器23，用于监测处理器核心21的功耗。处理器非核心电路22也对应一个功耗监测器23，用于监测处理器非核心电路22的功耗。处理器非核心电路22可以包括外部缓存、内部存储器、通用单元、加速器以及输入/输出控制单元(或接口单元)等。每个功耗监测器23可以将对应监测的处理器核心21或处理器非核心电路22的功耗发送给频率控制器24，频率控制器24可用于汇总各个功耗监测器23发送的功耗，最终确定处理器20运行时总的功耗。当处理器20处于超频场景时，即当处理器20的功耗在短时间内超越TDP时，频率控制器24可根据高于TDP的PL的值，控制处理器20的工作频率，以控制处理器20的功耗不超越PL的值，防止过流的情况发生。在一些情况下，频率控制器24可以是一个通用的处理器。
需要说明的是，图2示出的多核处理器的结构仅为一种示例性的结构，并不限于图2示出的结构。例如，该多核处理器可以仅有一个功耗监测器，该功耗监测器可以监测多个处理器核心21和处理器非核心电路22的功耗。
目前，TDP和PL2等功耗限制的值为静态配置，为了防止过流的情况发生，以及使得处理器可以在worst case下安全运行，因此PL2的值通常设置的较低，这使得处理器的瞬时功耗较低，进而使得处理器工作时的频率也较低，导致处理器的性能低。为此，本申请提出一种确定功耗限制的方法，其基本原理可以为：根据处理器的历史功耗可以确定处理器运行时其功耗的变化，可以根据功耗的变化调整PL的值。例如可以根据功耗的变化适当调高或调低PL的值。当PL的值被调高时，处理器在高频率工作的可能性增加，即给了处理器可以工作在高频率的机会，从而可提升处理器的性能。
本申请可以通过硬件或固件，或硬件和固件结合的方式实现上述原理。具体可以是对上述图2的处理器增设一个功耗预测器25，如图3所示，该功耗预测器25可以 在处理器20中单独存在，也可以增设在频率控制器24中。该功耗预测器25单独存在时，功耗预测器25可以是硬件实现。当功耗预测器25在频率控制器24中时，该功耗预测器25可以是硬件实现，还可以是固件实现。在一些实施例中，频率控制器24是一个通用的处理器时，本申请可以通过在该处理器中添加用于实现本申请实施例的固件，以实现本申请用于确定功耗限制的方法。
基于以上原理，本申请提供一种确定功耗限制的方法，如图4所示，以终端设备为例，该方法包括：
301、终端设备获取处理器在至少一个第一周期运行时的功耗信息。
在一些实施例中，第一周期可以是配置的多个时钟周期中的一个周期。由于处理器在不同时间点运行时的负载是瞬时变化的，导致处理器的工作电压和工作电流也是瞬时变化的，因此处理器20在不同时间点下的功耗也是瞬时变化的。也可以说，处理器运行程序时的功耗具有波动性。
在一些实施例中，可以根据第一周期的功耗信息知道处理器20在第一周期内运行时的功耗变化情况。
步骤301可以是上述功耗监测器23执行。
302、终端设备根据至少一个第一周期的功耗信息确定处理器在第二周期运行时的PL，第一周期为第二周期之前的周期。
在一些实施例中，第一周期的时长和第二周期的时长可以相同。
在一些实施例中，可以根据至少一个第一周期的功耗信息知道目前程序的功耗变化情况，即知道处理器20在至少一个第一周期内运行时的功耗变化，进而可以根据功耗变化调整第二周期的PL的值。例如当至少一个第一周期的功耗变化反映出功耗波动性较高时，可以适当降低PL的值，以避免某个时间点的瞬时功耗达到过流的功耗限制，防止过流的情况发生；当至少一个第一周期的功耗变化反映出功耗波动性较低时，这时认为目前程序的瞬时功耗达到过流的功耗限制的风险较低，可以适当提升PL的值，提升PL的值的同时，处理器的工作频率也相应得到提升的可能性增加，处理器的性能也得到优化。
步骤302可以是上述功耗预测器25执行。
基于上述图3对应的方法实施例，本申请对确定功耗限制的方法进一步进行说明。
本申请实施例提供一种确定功耗限制的方法，如图5所示，包括：
401、终端设备获取处理器在至少一个第一周期内所有相邻的两个时间点的功耗变化量的累加值。
在一些实施例中，功耗波动性可以通过处理器在至少一个第一周期内运行时的功耗变化量来反映。例如，该功耗变化量可以是处理器在一个周期内运行时的功耗变化量的平均值。要获得功耗变化量的平均值，可以先获取处理器在至少一个第一周期内所有相邻的两个时间点的功耗变化量的累加值。
示例性的，每个第一周期可以包括多个时间点，两个时间点的功耗变化量可以是处理器前一个时间点的瞬时功耗和后一个时间点的瞬时功耗的变化量。这样，第一周期内所有相邻的两个时间点的功耗变化量的和即为第一周期内所有相邻的时间点的功耗变化量的累加值，进而可以得到多个第一周期的所有相邻的两个时间点的功耗变化量的累加值P。
需要说明的是，本申请实施例中提到的功耗变化量、瞬时功耗的变化量、以及总功耗的变化量等均为正值，或者为绝对值。
在一些实施例中，应用图3的处理器20结构，如果该处理器20为多核处理器，可以通过功耗监测器23监测处理器核心21或者处理器非核心电路22的瞬时功耗，即获取每个时间点下处理器核心21的功耗，以及每个时间点下非处理器核心电路22的功耗，功耗预测器25可根据各个功耗监测器23监测到的功耗得到处理器20在每个时间点下的总功耗，进而根据前一个时间点下的总功耗和后一个时间点下的总功耗可以得到两个相邻时间点的总功耗的变化量，这样功耗预测器25就可以得到至少一个第一周期内所有相邻的两个时间点的功耗变化量的累加值P。
在一些实施例中，功耗监测器23监测每个时间点下处理器核心21或处理器非核心电路22的瞬时功耗时，该功耗监测器23可以根据集成稳压器(integrated voltage regulator，IVR)读取的实时的电流和电压的值，计算得到每个时间点的功耗。在一些实施例中，功耗预测器25得到至少一个第一周期内所有相邻时间点的功耗变化量的累加值P的实现方式可以是硬件的实现方式，也可以是固件的实现方式。
若是固件的实现方式实现，功耗预测器25可以为频率控制器24可执行的一段程序。当功耗预测器25得到每个功耗监测器23发送的每个时间点下的功耗时，该功耗预测器25可以根据每个功耗监测器23发送的每个时间点下的功耗计算得到处理器20在每个时间点下的总功耗，进而可以根据前一个时间点下的总功耗和后一个时间点下的总功耗可以得到两个时间点的总功耗的变化量，功耗预测器25进而可以得到至少一个第一周期内所有相邻的两个时间点的功耗变化量的累加值P。
若是以硬件的实现方式实现，功耗预测器25得到至少一个第一周期内所有相邻的两个时间点的功耗变化量的累加值P的硬件结构可以如图6所示，功耗预测器25可以包括功耗模块、寄存器、比较器以及累加器。
其中，功耗模块可以用于汇总每个时间点下处理器核心21以及处理器非核心电路22的总功耗；
寄存器，用于存储上个时间点下处理器20的总功耗；
比较器，用于根据功耗模块输入的当前时间点下处理器20的总功耗，和寄存器输入的上个时间点下处理器20的总功耗，得到相邻的两个时间点的总功耗的变化量。本申请实施例中，相邻时间点的总功耗的变化量也可以称为瞬时功耗的波幅。
累加器，用于累加比较器输出的相邻的两个时间点的总功耗的变化量，从而得到至少一个第一周期内所有相邻的两个时间点的功耗变化量的累加值。
402、终端设备根据累加值与至少一个第一周期的时长，获取处理器在至少一个第一周期内运行时的功耗变化量。
也就是说，步骤301中的功耗信息可以用于指示处理器20在至少一个第一周期内运行时的功耗变化量。
在一些实施例中，步骤301中的功耗信息可以用于指示处理器20在至少一个第一周期内运行时的功耗变化量的平均值。
处理器20在至少一个第一周期内运行时的功耗变化量的平均值可以理解为至少一个第一周期内的多个时间点的瞬时功耗的变化量的平均值，或者称为平均功耗波幅。
在一些实施例中，可以根据至少一个第一周期对应的累加值P与至少一个第一周期的时长T的比值得到处理器20在至少一个第一周期内运行时的功耗变化量的平均值Q。即，Q＝P/T。
在一些实施例中，功耗预测器25得到处理器20在至少一个第一周期内运行时的功耗变化量的平均值Q可以是通过固件的方式实现，也可以是硬件的方式实现。
若是以硬件的方式实现，参考图6，功耗预测器25还可以包括除法器，除法器中设置有周期，当除法器确定至少一个第一周期的时间到达时，可以根据累加器得到的少一个第一周期对应的累加值P和至少一个第一周期的时长T计算得到处理器20在少一个第一周期内运行时的功耗变化量的平均值Q。
403、终端设备根据处理器在至少一个第一周期内运行时的功耗变化量，确定第二周期的PL。
在一些实施例中，如果处理器20在至少一个第一周期内运行时的功耗变化量较高，认为处理器20运行目前程序的功耗波动性较高，可以适当降低至少一个第一周期之后的第二周期的PL的值，以防止瞬时功耗达到系统最大供电电流的限制功耗；如果处理器20在至少一个第一周期内运行时的功耗变化量较低，认为处理器20运行目前程序的功耗波动性较低，可以适当提升至少一个第一周期之后的第二周期的PL的值，给予处理器20在第二周期工作在高频率的可能性，从而提升处理器20的性能。
类似的，如果处理器20在至少一个第一周期内运行时的功耗变化量的平均值Q较高，认为处理器20运行目前程序的功耗波动性较高，可以适当降低第二周期的PL的值，以防止瞬时功耗达到系统最大供电电流的限制功耗；如果处理器20在至少一个第一周期内运行时的功耗变化量的平均值较低，认为处理器20运行目前程序的功耗波动性较低，目前程序的瞬时功耗达到系统最大供电电流的限制功耗的风险较低，可以适当提升第二周期的PL的值，这样，可以给予处理器20在下一个周期工作在高频率的可能性，从而提升处理器20的性能。
在一些实施例中，终端设备根据至少一个第一周期的功耗信息确定处理器在第二周期运行时的PL可以包括：
根据至少一个第一周期的功耗信息所对应的PL设置处理器20在第二周期运行时的PL。例如，本申请可以建立功耗信息与PL的对应关系，以根据该对应关系设置PL。
在一些实施例中，在设置PL之前，该方法还可以包括：获取至少一个第一周期的功耗信息所对应的PL。
在一些实施例中，获取至少一个第一周期的功耗信息所对应的PL可以包括：
确定至少一个第一周期的功耗信息所在的级别；将确定的级别所对应的PL作为至少一个第一周期的功耗信息所对应的PL。
在一些实施例中，确定至少一个第一周期的功耗信息所在的级别可以是通过至少一个第一周期的功耗信息与至少一个预设阈值进行比较确定的，即根据比较结果确定的功耗信息的级别。
示例性的，参考表1，若至少一个第一周期对应的功耗信息A T小于第一预设阈值(M)，则确定至少一个第一周期的功耗信息所在的级别为第一级别，第一级别对应的PL为第一PL(X+Y)；
若至少一个第一周期对应的功耗信息A T大于或等于第一预设阈值(M)，且小于第二预设阈值(V)，则确定至少一个第一周期的功耗信息所在的级别为第二级别，第二级别对应的PL为第二PL(X)；
若至少一个第一周期对应的历史功耗的信息A T大于第二预设阈值(N)，则确定至少一个第一周期的功耗信息所在的级别为第三级别，第三级别对应的PL为第三PL(X-Y)；
其中，所述第一PL(X+Y)大于所述第二PL(X)，所述第二PL(X)大于所述第三PL(X-Y)。X、Y和A T均为正值。
表1
历史功耗的信息A T PL(单位：W)
A T<M X+Y
M<A T<N X
A T>N X-Y
当频率控制器24确定了第二周期的PL的值时，可以向至少一个处理器核心21以及处理器非核心电路22发送更新指示，更新指示中包括第二周期的PL的值，以便至少一个处理器核心21或者处理器非核心电路22可以根据更新后的PL的值控制处理器20运行的负载。例如，当PL的值相对于第二周期之前的周期的PL的值提高了，处理器核心21有可能在更高的频率工作，可提升处理器20性能。当PL的值相对于第二周期之前的周期的PL的值降低了，处理器核心21可以适当降低处理器核心21的工作频率，以防止过流的情况发生。
示例性的，图7和图8为处理器20的瞬时功耗的曲线示意图，PL1可以认为是TDP对应的功耗限制，PL2是防止过流的功耗限制，本申请确定功耗限制的方法可以为对PL2的调整。从图7和图8可以看出，在T时刻之前，两条瞬时功耗的曲线表征出来的处理器20的平均瞬时功耗相同，但是瞬时功耗的变化量不同。其中，图7的瞬时功耗的变化量小于图8的瞬时功耗的变化量。因此，可以看出，虽然图7和图8表征出来的T时刻之前的平均瞬时功耗相同，但是由于图8的瞬时功耗的变化量较大，因此，图8中，在T时刻达到了最大电流限制ICCMax的功耗水线，并因随之引发的过流机制迅速降低了功耗，此时，处理器20的工作在高频率的可能性降低，处理器20的性能表现不佳。而图7中，由于瞬时功耗的变化量不大，因此没有引发大幅度的功耗降低。由此可见，当瞬时功耗的变化量较大时，也就是说，处理器20的功耗变化量较大时，或者说功耗的波动性较大时，可以设置一个较低的PL2值，有助于防止过流的情况发生，对系统的性能表现以及安全性都有所助益。
由此，本申请实施例可以根据处理器的不同的功耗场景，灵活配置PL的值，提升超频特性应对不同功耗场景的能力，提升处理器性能表现。
下面本申请实施例还提供一种确定功耗限制的方法，如图9所示，包括：
801、终端设备获取处理器在至少一个第一周期中的每个第一周期运行时的功耗信息。
在一些实施例中，第一周期可以包括多个时间点。第一周期对应的功耗信息用于指示处理器在第一周期内运行时，所有相邻的两个时间点的功耗变化量的累加值。
在一些实施例中，第一周期对应的功耗信息还可以是用于指示处理器在第一周期内运行时，所有相邻的两个时间点的功耗变化量的平均值。
在一些实施例中，步骤801中每个第一周期对应的功耗信息的获取方式可以参见上述步骤401对于第一周期对应的功耗信息的获取方式，此处不再赘述。
802、终端设备对处理器在每个第一周期运行时的功耗信息进行加权以获得处理器在至少一个第一周期内运行时的功耗信息。
在一些实施例中，加权方式可以为指数加权移动平均(exponentially weighted moving-average，EWMA)方式。即至少一个第一周期对应的功耗信息是通过对至少一个第一周期对应的功耗信息进行EWMA计算得到的。
这样是考虑到：处理器的瞬时功耗是不断变化的，距离近的时间点的瞬时功耗更能够反映出当前程序的功耗波动性，因此，采用EWMA的计算方式时，距离近的时间点的权重较大。
示例性的，假设A t理解为一个小时间粒度上的功耗变化量的平均值，例如A t为上述第一周期对应的功耗变化量的平均值，第一周期对应的功耗变化量的平均值即为第一周期内所有的相邻两个时间点的功耗变化量的平均值；A T理解为一个长时间粒度上的功耗变化量的平均值，例如A T为至少一个第一周期对应的功耗变化量的平均值时，可以有A T＝EWMA(A t)，即A T为通过EWMA获得的长时间粒度上的功耗变化量的平均值。
例如可以将A T＝EWMA(A t)展开说明下。
A T＝μA(t)+(1-μ)μA(t-1)+(1-μ) 2μA(t-2)+(1-μ) 3μA(t-3)
+(1-μ) 4μA(t-4)+…
其中，μ可以理解为至少一个第一周期内时间最近的第一周期对应的权重，A(t)可以理解为最近的第一周期对应的功耗变化量的平均值。可以看出，至少一个第一周期内，时间越近，其第一周期对应的功耗变化量的平均值的权重越大，时间越远，其第一周期对应的功耗变化量的平均值的权重越小。
803、终端设备根据处理器在至少一个第一周期内运行时的功耗信息所对应的PL设置处理器在第二周期运行时的PL。
步骤803中，终端设备可以根据A T的值决定如何动态设置PL的值。具体实现可以参见步骤403以及表1。
由此，本申请实施例可以根据处理器的不同的功耗场景，灵活配置PL的值，提升超频特性应对不同功耗场景的能力，提升处理器性能表现。
以上结合图4、图5以及图9详细说明了本申请实施例的方法。以下结合图10说明本申请实施例的计算系统的框图。图10说明了根据本申请的实施例的计算系统100的框图。
计算系统100可以包括一个或多个中央处理器单元(central processing unit，CPU)或处理器102-1到102-P(本文可以称为“多个处理器102”或“处理器102”)。处理器102可以经由总线(或互连网络)104进行通信。处理器102可以包括通用处理器、网络处理器(处理在计算机网络103上传送的数据)或其它类型的处理器(包括精简指令集计算机(reduced instruction set computing，RISC)处理器或复杂指令集计 算机(complex instruction set computer，CISC))。此外，多个处理器102可以具有单个或多个核心的设计。具有多核心设计的处理器102可以将不同类型的处理器核心集成到相同的集成电路(integrated circuit，IC)管芯上。此外，具有多核心设计的处理器102可以实现为对称的或不对称的多处理器。在实施例中，一个或多个处理器102可以与图2或图3的处理器相同或相似。
本申请的计算系统100还可以包括芯片组106。芯片组106还可以与总线104进行通信。芯片组106可以包括图形和存储控制集线器(graphics memory controller hub，GMCH)108。GMCH 108可以包括与存储器112进行通信的存储器控制器110。存储器112可以存储数据，其包括由处理器102或计算系统100中包括的任何其它设备执行的指令的序列。在本申请的一个实施例中，存储器112可以包括一个或多个易失性存储(或存储器)设备，例如随机存取存储器(random access memory，RAM)、动态RAM(dynamic RAM，DRAM)、同步DRAM(synchronous dynamic RAM，SDRAM)、静态RAM(static RAM，SRAM)或其它类型的存储设备。还可以使用非易失性存储器，例如硬盘。其它设备可以经由总线104进行通信，例如多个CPU和/或多个系统存储器。
GMCH 108还可以包括与图形加速器116进行通信的图形接口114以及显示器(图中未示出)。在本申请的实施例中，显示器(例如，平板显示器、阴极射线管(cathode-ray-tube，CRT)、投影屏幕等)可以通过例如信号转换器与图形接口114进行通信，其中所述信号转换器将在存储设备(例如，视频存储器或系统存储器)中存储的图像的数字表示转换为由显示器解释并显示的显示器信号。在由显示器解释并随后在其上显示之前，由显示设备产生的显示器信号可以通过各种控制设备。
本申请的计算系统100还可以包括输入/输出控制中心(input/output controller hub，ICH)120，ICH 120可以向与计算系统100进行通信的I/O设备提供接口。ICH 120可以通过外围设备桥(或控制器)124(例如，外围设备部件互连(Peripheral Component Interconnect，PCI)桥、通用串行总线(universal serial bus，USB)控制器或其它类型的外围设备桥或控制器)与总线122进行通信。外围设备桥124可以在处理器102与外围设备之间提供数据路径。此外，多个总线122可以与ICH 120进行通信。
此外，总线122还可以与音频设备126、一个或多个硬盘驱动器128以及一个或多个网络接口设备130(其与计算机网络103进行通信)进行通信。
通过以上实施方式的描述，所属领域的技术人员可以了解到，为描述的方便和简洁，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将装置的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个装置，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是一个物理单元或多个物理单元，即可以位于一个地方，或者也可以分布到多个不同地方。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个可读取存储介质中。基于这样的理解，本申请实施例的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该软件产品存储在一个存储介质中，包括若干指令用以使得一个设备(可以是单片机，芯片等)或处理器(processor)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(read only memory，ROM)、随机存取存储器(random access memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上内容，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (24)

  1. 一种确定功耗限制的方法，其特征在于，包括:
    获取处理器在至少一个第一周期运行时的功耗信息；
    根据所述至少一个第一周期的功耗信息确定所述处理器在第二周期运行时的功耗限制PL，所述第一周期为所述第二周期之前的周期。
  2. 根据权利要求1所述的方法，其特征在于，所述至少一个第一周期的功耗信息用于指示所述处理器在所述至少一个第一周期内运行时的功耗变化量。
  3. 根据权利要求2所述方法，其特征在于，每个第一周期包括多个时间点，所述获取处理器在至少一个第一周期运行时的功耗信息包括：
    获取所述处理器在所述至少一个第一周期内所有相邻的两个时间点的功耗变化量的累加值；
    根据所述累加值与所述至少一个第一周期的时长，获取所述处理器在所述至少一个第一周期内运行时的功耗变化量。
  4. 根据权利要求2所述的方法，其特征在于，所述获取处理器在至少一个第一周期运行时的功耗信息包括:
    对所述处理器在每个第一周期运行时的功耗信息进行加权以获得所述处理器在所述至少一个第一周期运行时的功耗信息。
  5. 根据权利要求4所述的方法，其特征在于，加权方式为指数加权移动平均。
  6. 根据权利要求4或5所述的方法，其特征在于，所述第一周期包括多个时间点，所述第一周期对应的功耗信息用于指示所述处理器在所述第一周期内运行时，所有相邻的两个时间点的功耗变化量的累加值。
  7. 根据权利要求1-6任一项所述的方法，其特征在于，所述根据所述至少一个第一周期的功耗信息确定所述处理器在第二周期运行时的功耗限制PL包括：
    根据所述至少一个第一周期的功耗信息所对应的PL设置所述处理器在第二周期运行时的PL。
  8. 根据权利要求7所述的方法，其特征在于，还包括：
    获取所述至少一个第一周期的功耗信息所对应的PL。
  9. 根据权利要求8所述的方法，其特征在于，所述获取所述至少一个第一周期的功耗信息所对应的PL包括：
    确定所述至少一个第一周期的功耗信息所在的级别；
    将确定的级别所对应的PL作为所述至少一个第一周期的功耗信息所对应的PL。
  10. 根据权利要求1-6任一所述的方法，其特征在于，还包括：
    根据所述第二周期的PL确定所述处理器在所述第二周期运行时的工作频率。
  11. 根据权利要求1-10任一所述的方法，其特征在于，所述至少一个第一周期包括当前周期和所述当前周期之前的至少一个周期，所述第二周期为所述当前周期的下一个周期。
  12. 一种确定功耗限制的装置，其特征在于，包括：
    功耗监测器，用于获取处理器在至少一个第一周期运行时的功耗信息；
    功耗预测器，用于根据至少一个第一周期的功耗信息确定所述处理器在第二周期 运行时的功耗限制PL，所述第一周期为所述第二周期之前的周期。
  13. 根据权利要求12所述的装置，其特征在于，所述至少一个第一周期的功耗信息用于指示所述处理器在所述至少一个第一周期内运行时的功耗变化量。
  14. 根据权利要求13所述的装置，其特征在于，每个第一周期包括多个时间点；
    所述功耗监测器，用于获取所述处理器在所述至少一个第一周期内所有相邻的两个时间点的功耗变化量的累加值；
    根据所述累加值与所述至少一个第一周期的时长，获取所述处理器在所述至少一个第一周期内运行时的功耗变化量。
  15. 根据权利要求13所述的装置，其特征在于，
    所述功耗监测器，用于对所述处理器在每个第一周期运行时的功耗信息进行加权以获得所述处理器在所述至少一个第一周期运行时的功耗信息。
  16. 根据权利要求15所述的装置，其特征在于，加权方式为指数加权移动平均。
  17. 根据权利要求15或16所述的装置，其特征在于，所述第一周期包括多个时间点，所述第一周期对应的功耗信息用于指示所述处理器在所述第一周期内运行时，所有相邻的两个时间点的功耗变化量的累加值。
  18. 根据权利要求12-17任一项所述的装置，其特征在于，所述功耗预测器，用于：根据所述至少一个第一周期的功耗信息所对应的PL设置所述处理器在第二周期运行时的PL。
  19. 根据权利要求18所述的装置，其特征在于，所述功耗预测器还用于：
    获取所述至少一个第一周期的功耗信息所对应的PL。
  20. 根据权利要求19所述的装置，其特征在于，所述功耗预测器用于：
    确定所述至少一个第一周期的功耗信息所在的级别；
    将确定的级别所对应的PL作为所述至少一个第一周期的功耗信息所对应的PL。
  21. 根据权利要求12-17任一项所述的装置，其特征在于，还包括频率控制器；
    所述频率控制器，用于根据所述第二周期的PL确定所述处理器在所述第二周期运行时的工作频率。
  22. 根据权利要求12-21任一项所述的装置，其特征在于，所述至少一个第一周期包括当前周期和所述当前周期之前的至少一个周期，所述第二周期为所述当前周期的下一个周期。
  23. 一种计算机可读存储介质，其特征在于，包括程序或指令，当所述程序或指令被处理器运行时，如权利要求1至11中任意一项所述的方法被执行。
  24. 一种计算机程序产品，其特征在于，当计算机程序产品在计算机上运行时，使得电子设备执行如权利要求1至11中任意一项所述的方法。
PCT/CN2019/126086 2019-12-17 2019-12-17 一种确定功耗限制的方法和装置 WO2021120015A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201980102242.2A CN114730207A (zh) 2019-12-17 2019-12-17 一种确定功耗限制的方法和装置
PCT/CN2019/126086 WO2021120015A1 (zh) 2019-12-17 2019-12-17 一种确定功耗限制的方法和装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2019/126086 WO2021120015A1 (zh) 2019-12-17 2019-12-17 一种确定功耗限制的方法和装置

Publications (1)

Publication Number Publication Date
WO2021120015A1 true WO2021120015A1 (zh) 2021-06-24

Family

ID=76476982

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/126086 WO2021120015A1 (zh) 2019-12-17 2019-12-17 一种确定功耗限制的方法和装置

Country Status (2)

Country Link
CN (1) CN114730207A (zh)
WO (1) WO2021120015A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6564332B1 (en) * 1998-12-23 2003-05-13 Intel Corporation Method and apparatus for managing power consumption in a computer system responsive to the power delivery specifications of a power outlet
CN101030095A (zh) * 2006-03-02 2007-09-05 联想（新加坡）私人有限公司 发热量的控制方法以及计算机
CN103116526A (zh) * 2013-02-22 2013-05-22 中国人民解放军国防科学技术大学 高性能异构并行计算机的最大功耗控制方法
CN105786152A (zh) * 2014-12-26 2016-07-20 联想(北京)有限公司 一种控制方法及电子设备
CN107239133A (zh) * 2017-06-01 2017-10-10 合肥联宝信息技术有限公司 一种智能设备的控制方法及装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6564332B1 (en) * 1998-12-23 2003-05-13 Intel Corporation Method and apparatus for managing power consumption in a computer system responsive to the power delivery specifications of a power outlet
CN101030095A (zh) * 2006-03-02 2007-09-05 联想（新加坡）私人有限公司 发热量的控制方法以及计算机
CN103116526A (zh) * 2013-02-22 2013-05-22 中国人民解放军国防科学技术大学 高性能异构并行计算机的最大功耗控制方法
CN105786152A (zh) * 2014-12-26 2016-07-20 联想(北京)有限公司 一种控制方法及电子设备
CN107239133A (zh) * 2017-06-01 2017-10-10 合肥联宝信息技术有限公司 一种智能设备的控制方法及装置

Also Published As

Publication number Publication date
CN114730207A (zh) 2022-07-08

Similar Documents

Publication Publication Date Title
US10331186B2 (en) Adaptive algorithm for thermal throttling of multi-core processors with non-homogeneous performance states
US10860082B2 (en) Dynamic power budget allocation
US10108240B2 (en) Power excursion warning system
US9563254B2 (en) System, method and apparatus for energy efficiency and energy conservation by configuring power management parameters during run time
US8595520B2 (en) System and method for determining thermal management policy from leakage current measurement
US9552034B2 (en) Systems and methods for providing local hardware limit management and enforcement
US9335803B2 (en) Calculating a dynamically changeable maximum operating voltage value for a processor based on a different polynomial equation using a set of coefficient values and a number of current active cores
KR101707096B1 (ko) 일반 호스트 기반 제어기 레이턴시 방법 및 장치
US8862918B2 (en) Efficient frequency boost operation
US20120221873A1 (en) Method, Apparatus, and System for Energy Efficiency and Energy Conservation by Mitigating Performance Variations Between Integrated Circuit Devices
WO2022052626A1 (zh) 功耗管理的方法和相关设备
US20180253236A1 (en) System and method for dynamic control of shared memory management resources
WO2022099477A1 (zh) 一种功耗控制方法及装置
US9268393B2 (en) Enforcing a power consumption duty cycle in a processor
US20150363212A1 (en) Minimizing performance loss on workloads that exhibit frequent core wake-up activity
US20220179706A1 (en) Adaptive resource allocation system and method for a target application executed in an information handling system (ihs)
KR101672357B1 (ko) 응답 타이밍 최적화에 기초하는 멀티프로세서 시스템에서의 주파수 조정 수행
WO2021120015A1 (zh) 一种确定功耗限制的方法和装置
US8539132B2 (en) Method and system for dynamically managing a bus of a portable computing device
CN115390609B (zh) 一种电压调整方法、装置、电子设备及可读存储介质
US20240004448A1 (en) Platform efficiency tracker

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19956623

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19956623

Country of ref document: EP

Kind code of ref document: A1