WO2022052626A1 - 功耗管理的方法和相关设备 - Google Patents

功耗管理的方法和相关设备 Download PDF

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Publication number
WO2022052626A1
WO2022052626A1 PCT/CN2021/106819 CN2021106819W WO2022052626A1 WO 2022052626 A1 WO2022052626 A1 WO 2022052626A1 CN 2021106819 W CN2021106819 W CN 2021106819W WO 2022052626 A1 WO2022052626 A1 WO 2022052626A1
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voltage domain
voltage
load
domain
power consumption
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PCT/CN2021/106819
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English (en)
French (fr)
Inventor
周罗青
姜炜祥
王俊捷
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华为技术有限公司
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Priority to EP21865682.5A priority Critical patent/EP4206863A4/en
Publication of WO2022052626A1 publication Critical patent/WO2022052626A1/zh
Priority to US18/181,688 priority patent/US20230214002A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G06F9/4893—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues taking into account power or heat criteria
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3293—Power saving characterised by the action undertaken by switching to a less power-consuming processor, e.g. sub-CPU
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3228—Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3243—Power saving in microcontroller unit
    • G—PHYSICS
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    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
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    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/329—Power saving characterised by the action undertaken by task scheduling
    • G—PHYSICS
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    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/485—Task life-cycle, e.g. stopping, restarting, resuming execution
    • G06F9/4856—Task life-cycle, e.g. stopping, restarting, resuming execution resumption being on a different machine, e.g. task migration, virtual machine migration
    • G06F9/4862—Task life-cycle, e.g. stopping, restarting, resuming execution resumption being on a different machine, e.g. task migration, virtual machine migration the task being a mobile agent, i.e. specifically designed to migrate
    • G06F9/4875—Task life-cycle, e.g. stopping, restarting, resuming execution resumption being on a different machine, e.g. task migration, virtual machine migration the task being a mobile agent, i.e. specifically designed to migrate with migration policy, e.g. auction, contract negotiation
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/505—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the load
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the technical field of energy consumption, and in particular, to a method, apparatus, scheduler, device, and computer-readable storage medium for power consumption management.
  • the energy consumption of equipment is closely related to the operating cost of the equipment. Therefore, how to manage the power consumption of the equipment is always an important issue affecting the operating cost of the equipment.
  • the traditional method is mainly aimed at devices with few processor cores and large differences between processor cores (for example, mobile terminals), and evaluates and adjusts based on the current utilization rate of the processor. Type handler requirements. Therefore, how to provide a more applicable power consumption management method has become an urgent technical problem to be solved.
  • the present application provides a method, apparatus, scheduler, device, and computer-readable storage medium for power consumption management, so as to provide a power consumption management method with wider applicability.
  • a method for power consumption management is provided, and the method can be applied to a device including multiple voltage domains, wherein each voltage domain includes at least one processor core.
  • the device can identify the first voltage domain that satisfies the preset condition.
  • the first voltage domain is any voltage domain in the device, and then the device can migrate the tasks to be executed by the processor core of the first voltage domain to the second voltage domain, and the second voltage domain is the device except the first voltage domain. other voltage domains than a voltage domain.
  • the device may set the operation mode of the device in the first voltage domain to the first mode, where the device in the first voltage domain includes a processor core.
  • the power consumption management of a device with multiple processor cores can be realized, and the above power consumption management method for a device can not only be applied to a device with few processor cores and a large difference between the processor cores, but also can be applied to For devices with many processor cores and small differences between processor cores (such as SMP devices, etc.), the above-mentioned power consumption management method has wider applicability than traditional methods for device power consumption management.
  • the device since the operating modes of the devices in the migrated first voltage domain are all set to the first mode, and when the first mode is a mode with lower or lowest operating power consumption, the device performs power consumption management in this way, Although the power consumption of the processor cores in the second voltage domain is increased, not only can the power consumption of all processor cores be reduced in the first voltage domain, but also the power consumption in the first voltage domain such as the QPI bus, L1 cache, L2 The power consumption of devices such as caches will also be reduced, which allows the overall power consumption of the device to be reduced.
  • the device can reduce the migration of tasks executed on processor cores in multiple voltage domains to one or more second voltage domains, and set the operating mode of the devices in multiple first voltage domains to power consumption.
  • the lower first mode thus, can effectively reduce the power consumption of the device.
  • the device can migrate tasks in multiple voltage domains to the second voltage domain, and the specific implementation of the identification, task migration, and operation mode setting of each first voltage domain can be performed as described above for a first voltage domain. processing process.
  • the device when it identifies the first voltage domain that satisfies the preset condition, it may specifically identify the first voltage domain according to the load conditions of multiple voltage domains in the device, and the identified first voltage domain A load in a voltage domain satisfies the preset condition. For example, a voltage domain with a smaller load among the multiple voltage domains may be identified as the first voltage domain, or, when the total load of the multiple voltage domains is less than a preset threshold, the device may identify any voltage domain as the first voltage domain domain, identify any other voltage domain as the second voltage domain, etc.
  • the device when identifying the first voltage domain according to the load conditions of multiple voltage domains in the device, the device may specifically select a load in the multiple voltage domains that is less than or equal to the load order of the multiple voltage domains.
  • the voltage domain of the first load threshold is used as the first voltage domain.
  • the load of a voltage domain is small, the number of tasks on the processor cores in this voltage domain is usually small. Therefore, when migrating tasks on the first voltage domain with a small load to other voltage domains, it is necessary to The amount of migration tasks can be as small as possible.
  • the above-mentioned first load threshold may be a load value of a voltage domain with the smallest load among the multiple voltage domains.
  • the first load threshold value may also be a preset fixed value or the like.
  • the device when it identifies the first voltage domain that satisfies the preset condition, it may specifically identify the first voltage domain according to a preset load balancing strategy, for example, when the load balancing strategy indicates a certain voltage domain When the load of a voltage domain is small or minimum, the device may identify the voltage domain as the first voltage domain.
  • the device may also identify the second voltage domain, wherein the load of the first voltage domain is relatively small, specifically less than the first load threshold, and the The load of the second voltage domain is greater than the second load threshold, and the second voltage domain is a voltage domain whose load condition is less than or equal to the third load threshold.
  • the second load threshold may be greater than or equal to the first load threshold.
  • the device may also identify any other voltage domain except the first voltage domain as the second voltage domain, and so on.
  • the device migrates the tasks performed by the processor cores in the first voltage domain to the second voltage domain, the load distribution of the processor cores in the second voltage domain satisfies the load balancing policy, and the load
  • the balancing strategy is used to balance the load of the processor cores in the second voltage domain.
  • the device can balance and migrate multiple tasks in the first voltage domain to the processor cores in the second voltage domain according to the load balancing strategy. In the case where the tasks of some processor cores in the voltage domain are too high and the load is too large, while the load of other processor cores in the second voltage domain is relatively small, it is possible to avoid task migration as much as possible and reduce the performance of the device.
  • the device may also migrate tasks to the second voltage domain, and then perform load balancing processing on multiple processor cores in the second voltage domain.
  • the device may, according to the load conditions of the multiple voltage domains, The voltage domain performs load balancing.
  • load balancing can be performed on all voltage domains in the device, so as to avoid as much as possible the overload of some voltage domains in the device. The performance of the entire device is reduced.
  • the device may perform load balancing in part of the voltage domains , of course, this part of the voltage domain includes a voltage domain with a load greater than the second complex threshold.
  • the device may identify the first voltage domain and perform task migration when it is in a low load scenario. Specifically, the device can calculate the total load of the multiple voltage domains, and, when the total load of the multiple voltage domains is less than the fourth load threshold, identify the first voltage domain that satisfies the preset condition, so as to further determine the first voltage
  • the tasks performed by the processor cores in the domain migrate to the second voltage domain.
  • the task migration may not be performed, or part of the task migration may be performed, so as to avoid excessive load on the second voltage domain after the task migration is completed, thereby reducing the overall performance of the device.
  • the device before identifying the first voltage domain that satisfies the preset condition, the device first identifies the corresponding relationship between the voltage domain and the processor core in the device, so as to determine which processor cores in the device are divided is a voltage domain.
  • the BIOS system in the device may record the voltage domain division in the ACPI table by reading the device register, and then report the information to the device through an interrupt.
  • the device when the device sets the operating mode of the device in the first voltage domain to the first mode, it may specifically predict the idle duration of the processor core in the first voltage domain, and then, according to the The idle time period is reduced, and the operation mode of the device in the first voltage domain is set to the first mode.
  • the device in the first voltage domain can have multiple operation modes, and when the device in the first voltage domain enters each operation mode, there are certain requirements for the duration of entering the operation mode. Therefore, the device Which operation mode to set the operation mode of the device in the first voltage domain to may be determined by predicting the idle time period of the device in the first voltage domain.
  • the load of the second voltage domain is not greater than the fifth load threshold.
  • the device can first predict the tasks performed by the processor core in the first voltage domain to be migrated, how much load will be added to the second voltage domain after the migration to the second voltage domain, and Calculate the sum of the predicted increased load and the current existing load in the second voltage domain, and then determine whether the sum of the loads exceeds a fourth load threshold. If it does not exceed, the device can migrate the tasks performed by the processor cores in the first voltage domain to the second voltage domain, and after the task migration is completed, the load of the second voltage domain is usually smaller than the fourth load threshold.
  • the characterization device migrates the tasks in the first voltage domain to the second voltage domain, the load in the second voltage domain may exceed the fourth load threshold, which may cause Because the load of the second voltage domain is too large to affect the performance of the device, at this time, the device may migrate the tasks in the first voltage domain to the second voltage domain without reducing it, or only migrate a part of the tasks to the second voltage domain, and so on.
  • the device may also present the power consumption management results on a preset display interface for users (eg, operation and maintenance personnel) to view.
  • the presented power consumption management results may include, for example, the identification and power consumption of each voltage domain in the multiple voltage domains, and the identification, operating mode, power consumption, operating frequency, voltage, utilization rate, and status of the processor core. Any one or more of the duration ratio of the first mode and the temperature of the device.
  • the interface presents the power consumption information in the dimension of the voltage domain, which allows maintenance personnel to understand the power consumption of the device more intuitively.
  • the voltages of the processor cores in the voltage domain are uniformly regulated, specifically, an independent power supply or a module may be used to uniformly control the voltages of all the processor cores in the voltage domain.
  • the present application provides an apparatus for power consumption management, where the apparatus for power consumption management includes various modules for executing the power consumption management method in the first aspect or any possible implementation manner of the first aspect.
  • the present application provides a scheduler, including a processor and a memory; the memory is used to store computer instructions; the processor is used to execute any one of the first aspect or the first aspect according to the computer instructions. Operation steps of a power consumption management method in one possible implementation.
  • the present application provides a device, which may include the above scheduler, configured to perform the operation steps of the power consumption management method in the above first aspect or any implementation manner of the first aspect.
  • the present application provides a computer-readable storage medium, where instructions are stored in the computer-readable storage medium to enable the computer to execute the first aspect or any one of the first aspects when it runs on a computer. Operation steps of the method described in the implementation manner.
  • the present application provides a computer program product comprising instructions that, when run on a computer, cause the computer to perform the operations of the method described in the first aspect or any possible implementation manner of the first aspect. step.
  • the present application may further combine to provide more implementation manners.
  • FIG. 2 is a schematic diagram of a voltage domain division provided by the present application.
  • FIG. 3 is a schematic flowchart of a power consumption management method provided by the present application.
  • FIG. 4 is a schematic diagram of the load of each processor core in voltage domain 1 and voltage domain 2 before and after a task migration provided by the present application;
  • FIG. 5 is a schematic diagram of a display interface provided by the present application.
  • FIG. 6 is a schematic structural diagram of a power consumption management apparatus provided by the present application.
  • FIG. 7 is a schematic structural diagram of a scheduler provided by the present application.
  • An Energy Aware Scheduler can be configured in the device.
  • the EAS is a module that arranges processes to perform tasks for the processor core.
  • the scheduling of tasks on the processor cores is managed to maximize the performance-to-power ratio, ie MAX (performance/power).
  • the performance of the device includes, but is not limited to, the computing efficiency and computing power of the device.
  • the power consumption of the device can be reduced as much as possible to reduce the operating cost of the device, so that the above-mentioned maximum performance and power consumption ratio can be achieved.
  • the power consumption refers to the power loss, specifically the difference between the input power and the output power of the device or a device on the device.
  • the management of the power consumption of the device may specifically be to manage the power consumption of each processor core in the device and the power consumption of other devices related to the processor core.
  • the current method of managing power consumption of a device in combination with the current utilization rate of the processor is usually only suitable for devices with few processor cores and large differences between processor cores, and has little benefit on other devices.
  • the embodiments of the present application provide a power consumption management method, so as to implement effective power consumption management for a device, and make the power consumption management method more adaptable.
  • the power consumption management method can be applied to a device including multiple voltage domains (voltage domains, VDs), and each voltage domain includes at least one processor core, and the voltage of the processor cores in the same voltage domain can be Unified control.
  • the device may identify a first voltage domain that satisfies a preset condition among multiple voltage domains, and migrate tasks performed by all processor cores in the first voltage domain to the second voltage domain,
  • the first voltage domain is any one of a plurality of voltage domains
  • the second voltage domain is other voltage domains in the device except the first voltage domain; after the task migration is completed, the first voltage domain There may be no tasks running on the processor core, and the device may set the operation modes of the devices in the first voltage domain to the first mode.
  • the first voltage domain includes a device with adjustable power consumption
  • the device includes a processor core, and also includes other electronic components associated with the processor core, such as Quick Path Interconnect (QPI) bus, cache , On-chip memory controller and other devices.
  • QPI Quick Path Interconnect
  • the power consumption management of the device is realized, and the power consumption management method is implemented by means of task migration and setting the operation mode of the device to realize the management of the power consumption of the device, which makes the power consumption management method not only applicable It is suitable for devices with few processor cores and large differences between processor cores, or for devices with many processor cores and small differences between processor cores, such as symmetrical multi-processor (SMP) devices.
  • SMP symmetrical multi-processor
  • the operation modes of all devices in the migrated first voltage domain will be set to the first mode
  • the first mode is the mode with lower or lowest running power consumption
  • the power consumption of the processor core can also be reduced, and the power consumption of other related devices other than the processor core in the first voltage domain can also be reduced.
  • the power consumption of the QPI bus and other devices can be reduced.
  • the calculation process required by the task scheduling process is relatively simple, which makes the computing resources consumed by the task scheduling lower and the task scheduling delay smaller.
  • the device to which the above-mentioned power consumption management method is applied may be, for example, a computing device, a network device, or a storage device in specific multiple voltage domains.
  • the computing device can be, for example, a server that provides computing services, an intelligent terminal, etc.
  • the network device can be a device that accesses the network and provides network services
  • the storage device can be, for example, a storage server.
  • the device to which the above power consumption management method is applied may include the system architecture shown in FIG. 1 , and specifically, the above power consumption management process may be performed by the scheduler 102 shown in FIG. 1 .
  • the system architecture shown in FIG. 1 may include an operating system 200 and a processor 300 including multiple processor cores, and may communicate and interact with the front-end application 100 .
  • the system architecture shown in FIG. 1 is illustrated by including one processor 300 as an example, and in practical applications, it may include multiple processors.
  • the processor 300 shown in FIG. 1 may include four processor cores, namely processor core 1, processor core 2, processor core 3, and processor core 4, and these four processor cores may be
  • the hardware structure is divided into two voltage domains, and the voltage of the processor core in each voltage domain can be controlled uniformly.
  • the processor core 1 and the processor core 2 can be classified into the voltage domain 1, and the processor core 3 and the processor core 4 can be classified into the voltage domain 2.
  • other devices that are logically or physically associated with the processor core 1 and the processor core 2 may also be included, that is, the associated device 1 shown in FIG. 1, and the associated device may be used to support the processor The operation of core 1 and processor core 2, such as QPI bus, L3 cache, on-die memory controller, snoop agent pipeline, thunderbolt controller ) and other devices.
  • the voltage domain 2 may also include other devices that are logically or physically associated with the processor core 3 and the processor core 4 , that is, the associated device 2 .
  • the voltage domain can be understood as an area in a chip (for example, a processor chip) that allows unified voltage control, and an independent voltage power supply and module can be used in the same area to uniformly control the voltage of the processor core.
  • One or more voltage domains can be included within the same chip.
  • the same processor includes two voltage domains, and each voltage domain may include several processor cores.
  • the voltage control module 1 can be used to perform unified voltage control
  • the voltage control module 2 can perform unified voltage control.
  • Multiple processor cores in a processor may be divided into different voltage domains, that is, a processor may include multiple voltage domains.
  • the processor 300 may include two distinct voltage domains.
  • the voltage control module 1 and the voltage control module 2 may be devices or logic circuits in the processor 300 in FIG. 1 , or may be software logic functions implemented by the above-mentioned devices or logic circuits, which are used to control the processor core in the voltage domain. and associated devices for power control.
  • the voltage control module 1 and the voltage control module 2 may also be combined, and one voltage control module controls the two voltage domains respectively.
  • the scheduler 201 may be implemented by software, for example, the scheduler 201 may be a computer program running in the operating system 200 for task scheduling. Specifically, the front-end application 100 may generate one or more tasks. In FIG. 1 , four tasks (task 1 to task 4) are generated as an example for illustration; the scheduler 201 may schedule these tasks to processors 1 to 4. One or more of the processor cores 4 to perform the task by the processor cores. During the scheduling process, the scheduler 201 can use the above power consumption management method to migrate all tasks to be executed on the processor core in the voltage domain 1 to the processor core in the voltage domain 2, and then control the power consumption in the voltage domain 1. The processor core 1, the processor core 2, and the associated device 1 enter a low-power operating mode. Thus, the scheduler 201 completes the power consumption management of the device.
  • the scheduler 201 may be integrated with a system scheduling unit 2011 , an idle duration prediction unit 2012 , a voltage domain identification unit 2013 and an operating frequency adjustment unit 2014 .
  • the system scheduling unit 2011 is configured to perform load balancing for all voltage domains in the device when the number of voltage domains with excessive load in the device exceeds a preset threshold, such as a Linux scheduler.
  • the voltage domain identification unit 2012 is used to identify the voltage domain distribution of the processor cores in the device, that is, to identify that the processor core 1 and the processor core 2 in the device belong to the voltage domain 1, and the processor core 3 and the processor core 4 belong to the voltage domain 2.
  • the idle duration prediction unit 2013 is used to predict the idle duration of the processor core in the voltage domain, so as to set the running mode of the processor core to a corresponding mode according to the idle duration of the processor core, such as the idle mode of Linux (CPUidle). ).
  • the working frequency adjustment unit 2014 is configured to adjust the working frequency of the processor core according to the load of the processor core, including increasing or decreasing the working frequency of the processor core, such as the working frequency of Linux (CPUfreq).
  • the system scheduling unit 2011 may be configured with other strategies, such as a load balancing strategy applied in one voltage domain, in addition to the above-mentioned strategy for performing load balancing on all voltage domains.
  • the scheduler 201 may During the process of migrating the task in the first voltage domain to the second voltage domain, load balancing is performed on the processor cores in the second voltage domain based on the load balancing strategy.
  • the policies in the scheduler 201 are not limited to the above examples.
  • the function of the above-mentioned scheduler may also be implemented by using separate hardware, for example, by using an application-specific integrated circuit (application-specific integrated circuit, ASIC), or a programmable logic device (programmable logic device).
  • ASIC application-specific integrated circuit
  • programmable logic device programmable logic device
  • device, PLD programmable logic device
  • the above-mentioned PLD can be a complex program logic device (complex programmable logical device, CPLD), field-programmable gate array (field-programmable gate array, FPGA), general array logic (generic array logic, GAL) or its Any combination realizes the functions of the above scheduler.
  • FIG. 1 is only used as an exemplary description, and is not used to limit the system architecture to which this embodiment applies.
  • some devices or functional modules and units in the system architecture can be adaptively added, deleted and replaced, for example, the front-end application shown in Figure 1 can also be located on the device, or, in Figure 1
  • the processor 300 of the device may include a larger number of processor cores, or the device may include other processors while including the processor 300 . This embodiment does not limit this.
  • FIG. 3 is a schematic flowchart of a power consumption management method in an embodiment of the present application.
  • the method may be applied to a device including the system architecture shown in FIG. 1 , or to other devices including multiple voltage domains. In the device, this embodiment does not limit this.
  • the power consumption management method can be specifically executed by the scheduler 201 in FIG. 1 , and the specific method includes:
  • S301 Identify a first voltage domain that satisfies a preset condition, where the first voltage domain is any voltage domain in the device.
  • the scheduler may first identify the correspondence between each processor core in the device and the voltage domain, that is, identify which processor cores in the device are divided into the same voltage domain, From this, each voltage domain in the device and the processor core contained in each voltage domain can be determined.
  • the identified correspondence between the processor core and the voltage domain can be stored in a storage area of the device, such as a memory.
  • the basic input output system (BIOS) system in the device can record the voltage domain partitioning in the device's Advanced Configuration and Power Interface (Advanced Configuration and Power Interface) by reading hardware registers , ACPI) table, and then report the voltage domain division in the power management interface table to the device through an interrupt.
  • BIOS basic input output system
  • a voltage domain satisfying a preset condition among the multiple voltage domains can be identified.
  • the voltage domain meeting the preset condition is hereinafter referred to as a first voltage domain.
  • the first voltage domain satisfies a preset condition, specifically, the load of the first voltage domain satisfies the preset condition.
  • the load of the voltage domain is the sum of the loads of all processor cores in the voltage domain, which may be through a per-entity load tracking (PELT) module in the device.
  • PELT per-entity load tracking
  • the processor load can be described by the utilization rate of the processor core, for example, the value used to describe the processor core load can be the value of the utilization rate of the processor core.
  • the load of the first voltage domain may be smaller than the load of other voltage domains in the plurality of voltage domains.
  • the multiple voltage domains may be sorted according to the load size, and according to the sorting result, the first voltage domain with the smallest load is selected from the multiple voltage domains.
  • the first voltage domain may also be a voltage domain where the load is not greater than the first load threshold.
  • the first load threshold may be a minimum value among loads in multiple voltage domains, and correspondingly, the first voltage domain is a voltage domain with the smallest load among the multiple voltage domains.
  • a value obtained from experience or statistical data can also be used as a preset value to define the first load threshold, such as 10%.
  • first voltage domain the above-mentioned implementation manner of determining the first voltage domain is only an example, and this embodiment does not refer to the specific implementation of how to determine the first voltage domain with a relatively small load from multiple voltage domains in practical applications. be limited.
  • the first voltage domain may also be determined according to other methods, such as comparing the number of tasks in multiple voltage domains. A small voltage domain as the first voltage domain, etc.
  • the number of tasks in the voltage domain is the sum of the number of tasks executed on all processor cores in the voltage domain.
  • the load of the first voltage domain may also be higher than the load of other voltage domains in the multiple voltage domains, and the specific implementation of how to determine the first voltage domain is not limited in this embodiment.
  • S402 Migrate the identified tasks to be executed by the processor core of the first voltage domain to a second voltage domain, where the second voltage domain is a voltage domain other than the first voltage domain in the device.
  • the device also includes a second voltage domain that does not meet the above preset conditions, for example, the load of the second voltage domain is greater than the load of the first voltage domain, and the like.
  • the device may also identify the second voltage domain.
  • the device may identify a voltage domain whose load is greater than the second load threshold and less than or equal to the third load threshold in the plurality of voltage domains as the second voltage domain.
  • the second voltage domain may also be determined in other manners, such as determining based on the number of tasks to be executed on the processor core in the voltage domain.
  • the device can migrate them to the second voltage domain, specifically to the processor cores in the second voltage domain, so that the processor in the second voltage domain can perform tasks
  • the core completes the processing of the above-mentioned migrated tasks.
  • the processor core in the first voltage domain can be configured with at least two queues, including queue 1 and queue 2, where queue 1 can be used to store tasks being executed by the processor core, and queue 2 can be used to store tasks being executed by the processor core. for storing tasks to be executed by the processor core.
  • the processor core in the second voltage domain may also be configured with two queues, which are respectively a queue 3 for storing tasks being executed by the processor core and a queue 4 for tasks to be executed.
  • the scheduler in the device migrates the tasks, it may specifically migrate the tasks to be executed in the queue 2 to the queue 4, so that the tasks in the queue 4 can be executed by the processor core in the second voltage domain.
  • the tasks to be executed by the processor core include the tasks being executed by the processor core and the tasks to be executed by the processor core.
  • the device may The balancing strategy evenly distributes the tasks of the first voltage domain to one or more processor cores in the second voltage domain.
  • the device can determine to assign each task according to the load situation of each processor core in the second voltage domain. Which processor core in the second voltage domain is migrated to, respectively, and then, according to the determined migration strategy, the task is respectively migrated to the corresponding processor core for execution.
  • the load distribution of the processor cores in the second voltage domain can be made to satisfy the load balancing strategy, so as to avoid as much as possible after the task migration, the load of one processor core is too large and the load of other processor cores is too large in the second voltage domain. smaller issues.
  • the device may also perform load balancing on each processor core in the second voltage domain after migrating all tasks in the first voltage domain to the second voltage domain.
  • the specific implementation that the load of each processor core in the second voltage domain is in a balanced state is not limited.
  • the device includes 8 processor cores, and the 8 processor cores are divided into two voltage domains (respectively, voltage domain 1 and voltage domain 2 ) for illustration.
  • the loads of the four processor cores in the voltage domain 1 are 5%, 1%, 0%, and 4%, respectively, and the loads of the four processor cores in the voltage domain 2 are 2%, 1%, and 0%, respectively.
  • 4% all tasks in voltage domain 2 can be migrated to voltage domain 1, and during or after task migration, load balancing can be performed on each processor core in voltage domain 1. After the task is migrated, the load of each processor core in voltage domain 1 and voltage domain 2 is shown in the lower left of Figure 4.
  • all tasks in voltage domain 1 can also be migrated to voltage domain 2, and the load of each processor core in voltage domain 2 satisfies the load balancing policy. Then, after the tasks are migrated, voltage domain 1 and The load of each processor core in the second voltage domain 2 is shown in the lower right corner of FIG. 4 .
  • the total load of the 4 processor cores in the voltage domain 1 is 10% (ie 5%+1%+0%+4%), which is greater than that of the 4 processor cores in the voltage domain 2
  • the total load is 7% (ie, 2%+1%+0%+4%). Therefore, migrating tasks from voltage domain 2 to voltage domain 1 can usually reduce the number of tasks that need to be migrated as much as possible.
  • the load balancing among the processor cores may mean that the load difference between different processor cores is within a preset range. For example, as shown in FIG. 4 , after the voltage domain 1 or the voltage domain 2 performs load balancing, the difference between the loads of the respective processor cores in the voltage domain 1 or the voltage domain 2 does not exceed 1%.
  • the device will Before the tasks executed by all the processor cores in the first voltage domain are migrated to the second voltage domain, it is also possible to determine whether the first voltage Tasks performed by all processor cores in the domain migrate to the second voltage domain. Specifically, the device may first calculate the sum of the load in the first voltage domain and the load in the second voltage domain, and determine whether the sum of the loads is greater than the fifth load threshold corresponding to the second voltage domain.
  • the device migrates the tasks executed by all processor cores in the first voltage domain to the second voltage domain; and when the load sum is greater than the fifth load threshold, the device may not Perform task migration, or migrate some tasks in the first voltage domain to the second voltage domain, or migrate all tasks to a voltage domain with a smaller load, otherwise the tasks of the first voltage source are migrated to the second voltage domain, which will cause The load of the second voltage domain is too large, thereby affecting the task processing performance of the device, for example, the processing delay of the task is too high.
  • the device migrates all tasks in the first voltage domain to the second voltage domain, that is, when the loads of all voltage domains of the device are lower than the predetermined voltage domain.
  • the task migration of the processor core in the first voltage domain is performed again.
  • the device can calculate the load of each voltage domain, and the load of each voltage domain is the sum of the loads of each processor core in the voltage domain.
  • the device can further calculate the sum of the loads of all voltage domains, and, When the total load of all voltage domains is less than the fourth load threshold, the device is in a low load scenario, and the device can identify the first voltage domain from the multiple voltage domains and migrate the tasks in the first voltage domain; When the total load of all voltage domains is not less than the fourth load threshold, and the device is not in a low-load scenario, the device may not perform the above task migration process.
  • the fourth load threshold for example, may be the maximum load allowed by one voltage domain, or may be the sum of the maximum loads allowed by multiple voltage domains.
  • the device when the device is an SMP device, it can be determined whether the device is in a low load scenario based on the following formula:
  • total_until_avg refers to the sum of the loads of all processor cores on the device
  • pd_capability is the computing capability of a single voltage domain
  • pd_capability*80% is the maximum load allowed by a single voltage domain
  • N is the number of voltage domains
  • pd_capability* 80%*N is the above-mentioned fourth load threshold, and when N is 1, the fourth load threshold is the maximum allowable load in a voltage domain, and when N is greater than 1, the fourth load
  • the threshold is the sum of the maximum loads allowed by multiple voltage domains.
  • the above formula is only used as an exemplary description, and is not used to limit the specific implementation for determining whether the device is in a low load scenario to be limited to this example.
  • S403 Set the operation mode of the device in the first voltage domain to the first mode, where the device includes a processor core.
  • the devices in the first voltage domain include devices that consume energy in the first voltage domain, including a processor core, and other devices used to support the operation of the processor core, such as a QPI bus, an on-chip memory controller, and the like.
  • a chip (also called a package) packaged in a chip or unit or logic circuit can include one or more voltage domains, for example, the processor chip is Intel(R) Xeon(R) Gold 6148 CPU@2.40GHz This kind of processing
  • a chip of a device core which can include two or more voltage domains.
  • the device migrates all the tasks to be executed by the processor core in the first voltage domain to the second voltage domain, the processor core in the first voltage domain may no longer have tasks to be executed, or have a smaller number of tasks to be executed , at this time, the device can set the operating mode of all devices (such as the entire package) in the first voltage domain to power consumption after completing the task migration and the processor core in the first voltage domain executing the currently executing task.
  • the relatively lower mode is hereinafter referred to as the first mode.
  • the operating modes of the processor core and the device associated with the processor core are the same.
  • the load and power consumption of the processor cores are usually approximately linear.
  • the reduction in power consumption of the processor core and the increase in power consumption of the processor core in the second voltage domain can be approximately offset, and the overall reduction in power consumption of the device generally lies in the reduced power consumption of other devices related to the processor core in the first voltage domain. Therefore, setting the operating modes of all processor cores and non-core devices in the first voltage domain to the first mode with low power consumption can effectively reduce the overall power consumption of the device.
  • the extra power consumption caused by task migration is usually much smaller than the power consumption reduced by other devices related to the processor core in the first voltage domain. Therefore, the additional power consumption caused by task migration can be ignored in this embodiment. .
  • a device may support processor cores in a number of different operating modes. Taking Intel(R) Xeon(R) Gold 6148 CPU@2.40GHz as an example, the device can support four different operating modes of the processor core: C0, C1, C1E, and C6. Among them, the C0 mode is the normal operation mode, the power consumption of the processor core in the C0 mode is usually higher than the power consumption of the processor core in other operating modes; C6 is the deep energy saving mode, the power consumption of the processor core in the C6 mode Usually lower than the power consumption of the processor core in other operating modes. Among them, the power consumption of the processor core in the four different operating modes of C0, C1, C1E and C6 is sequentially reduced. Of course, the device may also support other possible operation modes, which are not limited in this embodiment.
  • the operating mode of each processor core in the first voltage domain may be the second mode
  • the device may The operating mode of each processor core in the first voltage domain is set to the first mode, and the power consumption of the processor core in the first mode is smaller than the power consumption of the processor core in the second mode.
  • the second mode may be the C0 mode
  • the first mode may be the C1 mode, the C1E mode, or the C6 mode, or the like.
  • the residence time is the time required for the processor core to be in the operation mode, or the residence time can also be used for processing.
  • the operating frequency of the core under the operating model is characterized.
  • the processor core has extra power consumption when entering and exiting the operating mode, and when the processor core can stay in the operating mode for as long as the residence time (or frequency), the device can save power
  • the power consumption can offset the extra power consumption caused by the processor core entering and exiting the operating mode, and at the same time, it can also prevent the processor core from frequently switching the operating mode of the processor core due to entering an inappropriate operating mode.
  • each operation mode has a corresponding dwell time.
  • the device when the device sets the operating modes of all devices in the first voltage domain, the device can predict the idle duration of the processor core in the first voltage domain, and the idle duration is when the processor core does not execute The duration of the task, and then, the device can compare the idle duration with the residence duration corresponding to each operating mode, and determine the maximum dwell duration that is less than the idle duration, and the operation mode corresponding to the maximum dwell duration is the first mode. , and the device may set the operating mode of all processor cores and non-core devices in the first voltage domain to the first mode.
  • the dwell time corresponding to C1, C1E, and C6 operating modes are 2us (microseconds), 10us, and 50us. If the device predicts that the idle time of the processor core in the first voltage domain is 55us, since 55us is greater than 50us, the device will You can choose to use the C6 operating mode as the first mode, and set the operating mode of the processor core in the first voltage domain to the C6 mode; and if the device predicts that the idle duration of the processor core in the first voltage domain is 30s, because 10us ⁇ 30us ⁇ 50us, therefore, the device may choose to use the C1E operating mode as the first mode, and set the operating modes of the processor core and non-core devices in the first voltage domain to the C1E mode.
  • the device when the device predicts the idle duration of the processor core, it may specifically calculate the predicted idle duration in each time period according to the predicted idle duration and the actual idle duration of the processor core in multiple different time periods in the past. The ratio between the idle time and the actual idle time, so that the ratio values corresponding to multiple different time periods can be obtained. Then, the device can use a dynamic average algorithm to adjust the currently predicted initial idle duration according to the ratio values corresponding to multiple time periods to obtain the final predicted idle duration. For example, the device can calculate the average of multiple ratio values, And take the product of the average value and the initial idle time as the idle time of the processor core predicted by the device in the current time period.
  • the device may also use other methods to predict the idle duration of the processor core, or use a more complex/simplified calculation process than the above example, or use other methods to determine the first mode, which is not limited in this embodiment. .
  • the device can also adjust the operating frequency of the processor core according to the load of the processor core, for example, increase the operating frequency of the processor core, so that the processing The core can perform more tasks per unit time, thereby ensuring that the performance of the device is not degraded as much as possible.
  • the load of some voltage domains may be too high.
  • the load of some voltage domains may have exceeded the second load threshold allowed by the voltage domain. Load balancing is performed for this part of the voltage domain.
  • the device may determine whether to perform local load balancing or global load balancing according to the number of loads exceeding the second load threshold. Specifically, the device may determine the number of voltage domains whose loads are greater than the second load threshold in the multiple voltage domains according to the loads in each voltage domain. When the number is greater than the preset number, the device may determine the number of voltage domains with loads greater than the second load threshold in the multiple voltage domains.
  • Load balancing is performed on multiple voltage domains, and when the number is less than the preset number, the device can perform load balancing on part of the voltage domains according to the load conditions of the partial voltage domains in the multiple voltage domains.
  • the device includes 80 processor cores, and the 80 processor cores can be divided into 20 voltage domains
  • 10 when the number of voltage domains with a load greater than the second load threshold does not exceed 5, 10 can be selected.
  • the load is less than the second load threshold in the voltage domain, and the selected 10 voltage domains are used to load balance the voltage domain with the load greater than the second load threshold; and when the number of voltage domains with the load greater than the second load threshold exceeds 5 , the device can perform load balancing in 20 voltage domains.
  • the power consumption management result of the device may also be presented for the user to view.
  • the power consumption management result of the device may include information of multiple different dimensions such as processor, voltage domain, and processor core.
  • the power consumption management result may include the power consumption management result of each processor, the power consumption management result of each voltage domain in each processor, the power consumption management result of each processor core in each voltage domain, and the like.
  • the device may present the power consumption management result of the device through a preset display interface, the preset display interface may be located on the device, or the device may transmit the power consumption management result to other devices, and use the preset display interface to transmit the power consumption management result to other devices.
  • the display interface of other devices presents information.
  • the power consumption management results presented on the preset display interface may include information such as the power consumption, identification, and utilization rate of the processor, information such as the power consumption and identification of each voltage domain, and the processor in each voltage domain. Core identification, operating mode, power consumption, operating frequency, voltage, utilization, percentage of time spent in each operating mode, and device temperature (including the temperature of the processor core and the temperature of the device associated with the processor core) and other information any one or more of them. As shown in FIG. 5 , the utilization rate of the processor in the device, the dynamic change curve and value of the utilization rate, the number of running processes and threads, the normal running time, etc., can be presented on the interface.
  • the user can view the identification of different voltage domains in the processor, the identification of the processor core, the identification of the processor core, the identification of the processor core, and the identification of the processor core in the pop-up display interface by clicking "Details".
  • Information such as operating mode, power consumption of the processor core, and operating frequency.
  • the user can also click "Other Information" in the display interface to view other related information of the processor, such as the running time of the processor core, fault handling and other information; or, the user can click the "Other Information” in the display interface "Other Information” to view the information of other devices associated with the processor core in the voltage domain of the first point, such as the temperature, usage, load and other information of other devices (not shown in the figure).
  • a first voltage domain is used as an example for illustration.
  • the device can migrate tasks in multiple first voltage domains to other voltage domains.
  • the number of voltage domains is less than the total number of voltage domains in the device.
  • the specific implementation process of identification, task migration, and operation mode setting performed by the device can be referred to the relevant descriptions in the foregoing embodiments, and details are not repeated here.
  • the power consumption management method provided by the present application is described in detail above with reference to FIGS. 1 to 5 , and the power consumption management apparatus and device provided by the present application will be described below with reference to FIGS. 6 to 7 .
  • FIG. 6 is a power consumption management apparatus 600 provided by this application.
  • the power consumption management apparatus 600 can be applied to a device including multiple voltage domains, and each voltage domain includes at least one processor core.
  • the power consumption management Apparatus 600 may include:
  • An identification module 601 configured to identify a first voltage domain that satisfies a preset condition, where the first voltage domain is any voltage domain in the device;
  • a task migration module 602 configured to migrate tasks to be executed by the processor core of the first voltage domain to a second voltage domain, where the second voltage domain is the device in the device other than the first voltage domain voltage domain;
  • a setting module 603 is configured to set the operating mode of the device in the first voltage domain to the first mode, where the device includes the processor core.
  • the apparatus 600 in this embodiment of the present application may be implemented by an application-specific integrated circuit (ASIC), or a programmable logic device (programmable logic device, PLD), and the above-mentioned PLD may be a complex program logic device (complex programmable logical device, CPLD), field-programmable gate array (field-programmable gate array, FPGA), general array logic (generic array logic, GAL) or any combination thereof.
  • ASIC application-specific integrated circuit
  • PLD programmable logic device
  • PLD programmable logic device
  • the apparatus 600 and its respective modules can also be software modules.
  • the identifying module 601 is specifically used for:
  • the first voltage domain is identified according to load conditions of multiple voltage domains in the device, and the load of the first voltage domain satisfies the preset condition.
  • the identifying module 601 is specifically used for:
  • a voltage domain whose load is less than or equal to a first load threshold among the plurality of voltage domains is selected as the first voltage domain.
  • the first load threshold is a load value of a voltage domain with the smallest load among the plurality of voltage domains.
  • the identification module is specifically used for:
  • the first voltage domain is identified according to a preset load balancing strategy.
  • the identification module 601 is further configured to:
  • the second voltage domain is identified according to the load conditions of a plurality of voltage domains in the device, the load of the second voltage domain is greater than the second load threshold, and the second voltage domain is that the load condition is less than or equal to the third load threshold voltage domain.
  • the identifying module 601 is specifically used for:
  • the identifying module 601 is further configured to identify the corresponding relationship between the voltage domain and the processor core in the device before identifying the first voltage domain satisfying the preset condition.
  • the setting module is specifically used for:
  • the operation mode of the device in the first voltage domain is set to the first mode.
  • the power consumption management apparatus 600 further includes:
  • a presentation module 604 configured to present a power consumption management result on a preset display interface, where the power consumption management result includes the identification and power consumption of each voltage domain in the plurality of voltage domains, as well as the identification and operation mode of the processor core , any one or more of power consumption, operating frequency, voltage, utilization rate, the percentage of time in the first mode, and the temperature of the device
  • the load distribution of the processor cores in the first voltage domain satisfies a load balancing strategy, and the load balancing strategy is used to balance all load of the processor core in the first voltage domain.
  • the power consumption management apparatus 600 further includes:
  • the load balancing module 605 is configured to, when the number of voltage domains with a load greater than a second load threshold in the plurality of voltage domains is greater than a preset number, according to the load conditions of the plurality of voltage domains, for the plurality of voltage domains domain for load balancing.
  • the load of the second voltage domain is not greater than the fifth load threshold.
  • the voltages of the processor cores in the voltage domain can be uniformly adjusted.
  • the power consumption management apparatus 600 may correspond to executing the methods described in the embodiments of the present application, and the above-mentioned and other operations and/or functions of the units in the power consumption management apparatus 600 are respectively for realizing the functions shown in FIG. 3 .
  • the corresponding processes of each method are not repeated here.
  • FIG. 7 is a schematic diagram of a scheduler 700 provided by the present application.
  • the scheduler 700 includes a processor 701 , a storage medium 702 , a communication interface 703 and a memory unit 704 .
  • the processor 701 , the storage medium 702 , the communication interface 703 , and the memory unit 704 communicate through the bus 705 , and can also communicate through other means such as wireless transmission.
  • the memory 702 is used for storing instructions, and the processor 701 is used for executing the instructions stored in the memory 702 .
  • the memory 702 stores program codes, and the processor 701 can call the program codes stored in the memory 702 to perform the following operations:
  • the first voltage domain is any voltage domain in the device, the device includes multiple voltage domains, and each voltage domain includes at least one processor core;
  • An operating mode of a device in the first voltage domain is set to a first mode, the device including the processor core.
  • the processor 701 may be a CPU, and the processor 701 may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete device components, etc.
  • DSPs digital signal processors
  • ASICs application specific integrated circuits
  • FPGA field programmable gate arrays
  • a general purpose processor may be a microprocessor or any conventional processor or the like.
  • the memory 702 which may include read-only memory and random access memory, provides instructions and data to the processor 701 .
  • Memory 702 may also include non-volatile random access memory.
  • memory 702 may also store device type information.
  • the memory 702 may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (erasable PROM, EPROM), electrically programmable Erase programmable read-only memory (electrically EPROM, EEPROM) or flash memory.
  • Volatile memory may be random access memory (RAM), which acts as an external cache.
  • RAM static random access memory
  • DRAM dynamic random access memory
  • SDRAM synchronous dynamic random access memory
  • Double data rate synchronous dynamic random access memory double data date SDRAM, DDR SDRAM
  • enhanced synchronous dynamic random access memory enhanced SDRAM, ESDRAM
  • synchronous link dynamic random access memory direct rambus RAM, DR RAM
  • the scheduler 700 may correspond to the power consumption management apparatus 600 in the embodiment of the present application, and may correspond to the corresponding subject in executing the method shown in FIG. 3 according to the embodiment of the present application, and schedule The above and other operations and/or functions of each module in the device 700 are respectively to implement the corresponding flow of each method in FIG. 3 , and are not repeated here for brevity.
  • the present application also provides a device, the device may include the scheduler 700 shown in FIG. 7 , and the device may implement the corresponding processes of each method in FIG. 3 , which will not be repeated here for brevity.
  • the present application also provides a computer program product comprising one or more computer instructions.
  • the computer may be a general purpose computer, special purpose computer, computer network, or other programmable device.
  • the computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be retrieved from a website, computer, training device, or data
  • the center transmits to another website site, computer, training equipment or data center by wire (eg, coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (eg, infrared, wireless, microwave, etc.).
  • wire eg, coaxial cable, fiber optic, digital subscriber line (DSL)
  • wireless eg, infrared, wireless, microwave, etc.
  • the device embodiments described above are only schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be A physical unit, which can be located in one place or distributed over multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of the present application.
  • the connection relationship between the modules indicates that there is a communication connection between them, which may be specifically implemented as one or more communication buses or signal lines.

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Abstract

一种功耗管理的方法及相关设备，可以用于管理包括多个电压域的设备功耗，并且每个电压域包括至少一个处理器核。该方法包括：在功耗管理时，识别多个电压域中满足预设条件的第一电压域（S301），并将第一电压域中所有处理器核待执行的任务迁移至第二电压域（S302），然后将第一电压域中器件的运行模式均设置为第一模式（S303）。以此实现了对设备功耗的管理。

Description

功耗管理的方法和相关设备 技术领域
本申请涉及能耗技术领域，尤其涉及一种功耗管理的方法、装置、调度器、设备和计算机可读存储介质。
背景技术
设备的能耗，与设备的运营成本密切相关，因此，如何管理设备的功耗，始终是影响设备运营成本的重要问题。传统方法主要针对处理器中处理器核少、处理器核间差异大的设备(例如，移动终端)，结合处理器的当前使用率进行评估和调整，收益甚微，适用范围有限，无法满足所有类型处理器的需求。因此，如何提供一种适用性更广的功耗管理方法成为亟待解决的技术问题。
发明内容
本申请提供了一种功耗管理的方法、装置、调度器、设备和计算机可读存储介质，以提供一种适用性更广的功耗管理的方法。
第一方面，提供一种功耗管理的方法，该方法可以应用于包括多个电压域的设备上，其中，每个电压域中包括至少一个处理器核。在进行功耗管理的过程中，设备可以识别满足预设条件的第一电压域。该第一电压域为该设备中任意一个电压域，然后，该设备可以将第一电压域的处理器核待执行的任务迁移至第二电压域，而该第二电压域为设备中除第一电压域之外的其它电压域。在完成任务迁移后，设备可以将第一电压域中器件的运行模式设置为第一模式，该第一电压域中器件包括处理器核。如此，可以实现对多处理器核的设备功耗的管理，并且，上述对于设备的功耗管理方法不仅可以应用于处理器核少、处理器核间差异大的设备，而且，也可以应用于处理器核较多、处理器核间差异较小的设备(如SMP设备等)，从而相对于传统方法对于设备的功耗管理，上述功耗管理方法的适用性更广。
另外，由于迁移后的第一电压域中的器件的运行模式均会被设置为第一模式，而当该第一模式为运行功耗更低或者最低的模式时，设备如此进行功耗管理，虽然第二电压域中处理器核的功耗增加，但是第一电压域中不仅所有处理器核的功耗可以得到降低，而且，该第一电压域中诸如QPI总线、一级缓存、二级缓存等器件的功耗也会得到降低，这使得设备整体的功耗可以得到降低。
实际应用中，设备可以降低多个电压域中的处理器核上执行的任务迁移至一个或者多个第二电压域上，并将多个第一电压域中的器件的运行模式设置为功耗更低的第一模式，如此，可以有效降低设备的功耗。
并且，设备可以将多个电压域中的任务迁移至第二电压域中，而对于每个第一电压域的识别、任务迁移以及运行模式设置的具体实现，可以如同上述对一个第一电压域的处理过程。
在一种可能的实施方式中，设备在识别满足预设条件的第一电压域时，具体可以是根据该设备中多个电压域的负载情况识别第一电压域，并且，所识别出的第一电压域的负载满足该预设条件。比如，可以将多个电压域中负载较小的电压域识别为第一电压域，或者，当多 个电压域的总负载小于预设阈值时，设备可以将任意一个电压域识别为第一电压域，将其它任意一个电压域识别为第二电压域等。
在一种可能实施方式中，在根据设备中多个电压域的负载情况识别第一电压域时，设备具体可以是根据多个电压域的负载排序，选择该多个电压域中负载小于或者等于第一负载阈值的电压域作为第一电压域。通常情况下，电压域的负载较小时，该电压域中处理器核上的任务数量通常较少，因此，在将负载较小的第一电压域上的任务迁移至其它电压域时，所需迁移的任务量可以尽可能的较小。
在一种可能的实施方式中，上述第一负载阈值可以是多个电压域中负载最小的电压域的负载值。当然，在其它可能的实施方式中，该第一负载阈值也可以是预设的固定值等。
在一种可能的实施方式中，设备在识别满足预设条件的第一电压域时，具体可以是根据预设的负载均衡策略，识别第一电压域，比如，在该负载均衡策略指示出某个电压域的负载较小或者最小时，设备可以将该电压域识别为第一电压域。
在一种可能的实施方式中，设备在识别出第一电压域的同时，还可以识别出第二电压域，其中，第一电压域的负载较小，具体是小于第一负载阈值，而第二电压域的负载大于第二负载阈值，并且，该第二电压域为负载情况小于或者等于第三负载阈值的电压域。示例性的，该第二负载阈值可以大于或者等于第一负载阈值。当然，在其他可能的实施方式中，设备也可以是将任意一个除第一电压域之外的其它电压域识别为第二电压域等。
在一种可能的实施方式中，设备在将第一电压域中处理器核执行的任务迁移至第二电压域后，该第二电压域中处理器核的负载分布满足负载均衡策略，该负载均衡策略用于均衡第二电压域中处理器核的负载。具体实现时，设备可以根据该负载均衡策略，将第一电压域中的多个任务均衡迁移至第二电压域中的处理器核上，如此，可以尽可能避免在完成任务迁移后，第二电压域中部分处理器核的任务过高，负载过大，而该第二电压域中的其它处理器核的负载较小的情况，从而可以尽可能避免任务迁移而导致设备的性能降低。当然，在其它可能的实施方式中，设备也可以是将任务迁移至第二电压域中，然后再在第二电压域中对多个处理器核进行负载均衡处理。
在一种可能的实施方式中，当设备的多个电压域中存在负载大于第二负载阈值的电压域的数量大于预设数量时，设备可以根据该多个电压域的负载情况，对多个电压域进行负载均衡。在该实施方式中，当设备中存在较多数量的电压域的负载过大，则可以在设备中对所有电压域进行负载均衡，以尽可能避免设备中的部分电压域的负载过大而导致整个设备的性能被降低。而在其它可能的实施方式中，当设备的多个电压域中存在负载大于第二负载阈值的电压域，但是，该电压域的数量小于预设数量时，设备可以在部分电压域内进行负载均衡，当然，该部分电压域中包括负载大于第二复杂阈值的电压域。
在一种可能的实施方式中，设备可以是在处于低负载场景下时，识别第一电压域并进行任务迁移。具体的，设备可以计算多个电压域的总负载，并且，当多个电压域的总负载小于第四负载阈值时，识别出满足预设条件的第一电压域，以便进一步将该第一电压域中处理器核执行的任务迁移至第二电压域中。相应的，当设备的整体负载较高时，可以不进行任务迁移，或者进行部分任务迁移等，以避免完成任务迁移后，第二电压域的负载过大，从而降低设备的整体性能。
在一种可能的实施方式中，设备在识别满足预设条件的第一电压域之前，先识别出设备中电压域与处理器核的对应关系，以便于确定设备中的哪些处理器核被划分为一个电压域。实际应用中，可以是由设备中的BIOS系统通过读器件寄存器将电压域划分情况记录在ACPI 表，然后，通过中断向设备上报该信息。
在一种可能的实施方式中，设备在将第一电压域中器件的运行模式设置为第一模式时，具体可以是先预测该第一电压域的处理器核的空闲时长，然后，根据该空闲时长，降低第一电压域中器件的运行模式设置为第一模式。实际应用中，第一电压域中器件的运行模式可以包括多种，而第一电压域中器件在进入每种运行模式时，都需要对其进入该运行模式的时长存在一定要求，因此，设备可以是通过预测第一电压域中器件的空闲时长，来确定将第一电压域中的器件的运行模式设置为哪个运行模式。
在一种可能的实施方式中，设备在将第一电压域中处理器核执行的任务迁移至第二电压域后，该第二电压域的负载不大于第五负载阈值。具体实现时，设备在进行任务迁移之前，可以先预测待迁移的该第一电压域中处理器核所执行的任务，在迁移至第二电压域后会使得第二电压域增加多少负载，并计算该预测的增加负载与第二电压域当前已有负载之和，然后判断该负载之和是否超过第四负载阈值。若不超过，则设备可以将第一电压域中处理器核执行的任务迁移至第二电压域中，而在完成任务迁移后，第二电压域的负载通常也小于该第四负载阈值。而若负载之和超过第四负载阈值，表征设备若是将第一电压域中的任务迁移至第二电压域中，则可能会使得第二电压域的负载超过该第四负载阈值，从而可能会因为第二电压域的负载过大而影响设备的性能，此时，设备可以不降低第一电压域中的任务迁移至第二电压域，或者仅迁移一部分任务至第二电压域等。
在一种可能的实施方式中，设备还可以在预设显示界面上呈现功耗管理结果，以便用户(如运维人员)查看。其中，所呈现的功耗管理结果，例如可以包括多个电压域中每个电压域的标识、功耗，以及处理器核的标识、运行模式、功耗、工作频率、电压、利用率、处于所述第一模式的时长占比，以及器件的温度中的任意一种或多种。通过界面呈现以电压域维度的功耗信息，可以让维护人员更直观了解设备的功耗情况。
在一种可能的实施方式中，电压域中的处理器核的电压被统一调节，具体可以是采用独立电源或者模块对电压域内所有的处理器核的电压进行统一控制。
第二方面，本申请提供一种功耗管理装置，所述功耗管理装置包括用于执行第一方面或第一方面任一种可能实现方式中的功耗管理方法的各个模块。
第三方面，本申请提供一种调度器，包括处理器和存储器；所述存储器，用于存储计算机指令；所述处理器，用于根据所述计算机指令执行如第一方面或第一方面任一种可能实现方式中的功耗管理方法的操作步骤。
第四方面，本申请提供了一种设备，该设备可以包括上述调度器，用于执行上述第一方面或第一方面任一种实现方式中的功耗管理方法的操作步骤。
第五方面，本申请提供一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述第一方面或第一方面任一种可能实现方式中的所述的方法的操作步骤。
第六方面，本申请提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述第一方面或第一方面任一种可能实现方式中的所述的方法的操作步骤。
本申请在上述各方面提供的实现方式的基础上，还可以进行进一步组合以提供更多实现方式。
附图说明
图1为本申请提供一种系统架构的示意图；
图2为本申请提供的一种电压域划分示意图；
图3为本申请提供的一种功耗管理方法的流程示意图；
图4为本申请提供的一种任务迁移前后电压域1以及电压域2中各个处理器核的负载示意图；
图5为本申请提供的一种显示界面示意图；
图6为本申请提供的一种功耗管理装置的结构示意图；
图7为本申请提供的一种调度器的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请中的技术方案进行描述。
设备中可以配置有能耗感知调度器(Energy Aware Scheduler，EAS)，该EAS为处理器核(core)安排进程执行任务的模块，可以根据处理器核的功耗、性能、负载差异等信息对任务在处理器核上的调度进行管理，以期望达到最大化性能和功耗比，即MAX(performance/power)。其中，设备的性能，包括但不限于设备的计算效率、计算能力等。
在对设备功耗进行管理时，可以尽可能的降低设备的功耗，以降低设备的运营成本，从而可以达到上述最大化性能和功耗比。其中，功耗，是指功率损耗，具体为该设备或者该设备上的器件等输入功率与输出功率的差额。对于设备功耗的管理，具体可以是对设备中各个处理器核的功耗以及与该处理器核相关的其它器件的功耗进行管理。但是，目前结合处理器的当前使用率来对设备进行功耗管理的方式，通常仅适用于处理器核少、处理器核间差异大的设备，而在其它设备上收益甚微。
基于此，本申请实施例提供了一种功耗管理方法，以实现对设备进行有效的功耗管理，并使得功耗管理方法的适应性更广。具体的，该功耗管理方法可以应用于包括多个电压域(voltage domain，VD)的设备中，并且每个电压域包括至少一个处理器核，同一电压域中的处理器核的电压可以被统一控制。在进行功耗管理过程中，该设备可以识别多个电压域中满足预设条件的第一电压域，并将该第一电压域中所有处理器核执行的任务均迁移至第二电压域，该第一电压域为多个电压域中的任意一个电压域，而该第二电压域为该设备中除第一电压域之外的其它电压域；在完成任务迁移后，第一电压域的处理器核上可以没有运行有任务，则设备可以将该第一电压域中器件的运行模式均设置为第一模式。其中，该第一电压域中包括可调整功耗的器件，器件包括处理器核，还包括与该处理器核关联的其它电子元器件，如快速通道互联(Quick Path Interconnect，QPI)总线、缓存、片上存储器的控制器等器件。如此，实现了对设备功耗的管理，并且，该功耗管理方法是通过任务迁移以及设置器件的运行模式的方式来实现对设备的功耗进行管理，这使得该功耗管理方法不仅可以适用于处理器核少、处理器核间差异大的设备，也可以是适用于处理器核多、处理器核间差异小的设备，如对称多处理器(symmetrical multi-processor，SMP)设备等。
并且，由于迁移后的第一电压域中所有器件的运行模式均会被设置为第一模式，当该第一模式为运行功耗更低或者最低的模式时，不仅可以降低第一电压域中处理器核的功耗，而且，也可以降低了该第一电压域中除处理器核之外的其它相关器件的功耗，如降低了QPI总线等器件的功耗，在合理调度处理任务的处理器核所在电压域的情况下，可以从电压域的维度进行调度和控制，尽量减少正在工作的电压域的数量，由此可以有效降低设备的整体功耗。
同时，在对设备进行功耗管理的过程中，任务调度过程所需的计算过程较为简单，这使得任务调度所需消耗的计算资源较低，任务调度时延较小。
示例性的，上述功耗管理方法所应用的设备，例如可以是具体多个电压域的计算设备、网络设备或存储设备等。其中，计算设备，例如可以是提供计算服务的服务器、智能终端等；网络设备，可以是接入网络并提供网络服务的设备等；存储设备，例如可以是存储服务器等。
作为一种示例，上述功耗管理方法所应用的设备，可以包括如图1所示的系统架构，并且，具体可以是由图1中所示的调度器102执行上述功耗管理过程。图1所示的系统架构，可以包括操作系统200以及包括多个处理器核的处理器300，并可以与前端应用100存在通信交互等。图1所示的系统架构，是以包括一个处理器300为例进行说明，实际应用中，可以是包括多个处理器。图1所示的处理器300中可以包括4个处理器核，分别为处理器核1、处理器核2、处理器核3以及处理器核4，并且，这4个处理器核可以根据物理硬件结构划分为两个电压域，每个电压域中的处理器核的电压可以进行统一控制。其中，处理器核1和处理器核2可以划入电压域1中，处理器核3以及处理器核4可以划入电压域2中。并且，在电压域1中，可以还包括与处理器核1以及处理器核2存在逻辑或者物理关联的其它器件，即图1中所示的关联器件1，该关联器件可以用于支持处理器核1以及处理器核2的运行，例如可以是QPI总线、三级缓存(L3cache)、片上存储器控制器(on-die memory controller)、窥探代理管道(snoop agent pipeline)、雷电控制器(thunderbolt controller)等器件中的一种或多种。同样的，在电压域2中，也可以包括与处理器核3以及处理器核4存在逻辑或者物理关联的其它器件，即关联器件2。
其中，电压域，可以理解为芯片(例如，处理器芯片)中允许进行电压统一控制的区域，同一区域可以采用独立的电压电源以及模块对处理器核的电压进行统一控制。同一芯片内可以包括一个或多个电压域。例如图2所示的设备中，同一处理器中包括2个电压域，每个电压域中的可以包括若干个处理器核。对于电压域1中的多个处理器核，可以利用电压控制模块1进行统一的电压控制，而对于电压域2中的多个处理器核，可以由电压控制模块2进行统一的电压控制。一个处理器中的多个处理器核可以被划分为不同的电压域，即一个处理器中可以包括有多个电压域。如图1中，处理器300可以包括两个不同的电压域。其中，电压控制模块1和电压控制模块2可以是图1中处理器300中器件或逻辑电路或者，也可以是由上述器件或逻辑电路实现的软件逻辑功能，用于对电压域中处理器核和关联器件进行功耗控制。可选地，对于图1所示的设备，也可以将电压控制模块1和电压控制模块2进行合并，由一个电压控制模块分别对两个电压域进行控制。
调度器201可以由软件实现，例如，调度器201可以是运行在操作系统200中计算机程序，用于进行任务调度。具体的，前端应用100可以产生一个或者多个任务，图1中以产生4个任务(任务1至任务4)为例进行示例性说明；调度器201可以将该这些任务调度至处理器1至处理器核4中的一个或者多个处理器核，以便由处理器核执行该任务。在调度过程中，调度器201可以采用上述功耗管理方法，将电压域1中的处理器核上的所有待执行任务均迁移至电压域2中的处理器核上，然后控制电压域1中的处理器核1、处理器核2以及关联器件1进入低功耗的运行模式。由此，调度器201完成对设备的功耗管理。
具体地，调度器201可以整合有系统调度单元2011、空闲时长预测单元2012、电压域识别单元2013以及工作频率调整单元2014。其中，系统调度单元2011用于在设备中负载过大的电压域的数量超过预设阈值时，为该设备中的所有电压域进行负载均衡，如Linux调度器(scheduler)。电压域识别单元2012，用于识别设备中处理器核的电压域分布情况，即识别设 备中处理器核1以及处理器核2属于电压域1，处理器核3以及处理器核4属于电压域2。空闲时长预测单元2013，用于预测电压域中的处理器核的空闲时长，以便根据该处理器核的空闲时长将该处理器核的运行模式设置为相应的模式，如Linux的空闲模式(CPUidle)。工作频率调整单元2014，用于根据处理器核的负载对处理器核进行工作频率的调整，包括增加或者降低处理器核的工作频率等，如Linux的工作频率(CPUfreq)。
可选地，系统调度单元2011除了可以配置有上述对所有电压域进行负载均衡的策略以外，还可以配置有其它策略，如应用于在一个电压域中的负载均衡策略等，该调度器201可以在将第一电压域中的任务迁移至第二电压域的过程中，基于该负载均衡策略对第二电压域内的处理器核进行负载均衡。实际应用中，调度器201中的策略不局限于上述示例。
可选地，为了提升调度器的运算能力，也可以利用单独的硬件实现上述调度器的功能，例如，利用专用集成电路(application-specific integrated circuit，ASIC)实现，或可编程逻辑器件(programmable logic device，PLD)实现，上述PLD可以是复杂程序逻辑器件(complex programmable logical device，CPLD)，现场可编程门阵列(field-programmable gate array，FPGA)，通用阵列逻辑(generic array logic，GAL)或其任意组合实现上述调度器的功能。
应当理解，图1所示的系统架构仅作为一种示例性说明，并不用于对本实施例所适用的系统架构进行限定。实际应用中，可以对该系统架构中的部分器件或者功能模块、单元进行适应性增加、删减及替换等，比如，图1所示的前端应用也可以是位于设备上，或者，图1中的处理器300可以包括更多数量的处理器核，或者设备在包括处理器300的同时，还可以包括其它处理器。本实施例对此并不进行限定。
下面，参见图3所示，为本申请实施例中一种功耗管理方法的流程示意图，该方法可以应用于包括如图1所示的系统架构的设备，或者应用于其它包括多个电压域的设备中，本实施例对此并不进行限定。以应用于图1所示设备为例，如图3所示，功耗管理方法具体可以由图1中调度器201执行，具体方法包括：
S301：识别满足预设条件的第一电压域，其中，该第一电压域为该设备中的任意一个电压域。
示例性的，调度器在识别第一电压域之前，可以先识别出设备中各个处理器核与电压域之间的对应关系，即识别出该设备中哪些处理器核被划分为同一电压域，由此可以确定出设备中的各个电压域以及每个电压域中所包含的处理器核。所识别得到的处理器核与电压域之间的对应关系，可以保存在设备的存储区域，如内存等。在一些示例中，该设备中的基本输入输出系统(basic input output system，BIOS)系统可以通过读取硬件寄存器将电压域划分情况记录在设备中的高级配置和电源管理接口(Advanced Configuration and Power Interface，ACPI)表中，然后通过中断将电源管理接口表中的电压域划分情况上报给设备。
对于设备中的多个电压域，可以识别出该多个电压域中满足预设条件的电压域，为便于描述，以下将满足预设条件的电压域称之为第一电压域。
在一种可能的实施方式中，第一电压域满足预设条件，具体可以是第一电压域的负载满足预设条件，此时，在识别第一电压域时，可以是根据设备中多个电压域的负载情况选择第一电压域。其中，对于每个电压域，该电压域的负载，即为该电压域中所有处理器核的负载总和，其可以是通过设备中的任务负载跟踪(per-entity load tracking，PELT)模块。特别地，当处理器核的利用率超过80％时，可以利用处理器核的利用率描述处理器的负载，如用于描述处理器核负载的数值可以是处理器核的利用率的数值。
作为一种可能的实现方式，第一电压域的负载可以小于多个电压域中的其它电压域的负 载。例如，可以对多个电压域按照负载大小进行排序，并根据该排序结果，从多个电压域中选择负载最小的作为第一电压域。
作为另一种可能的实现方式，第一电压域也可以是负载不大于第一负载阈值的电压域。其中，第一负载阈值，可以是多个电压域的负载中的最小值，相应的，第一电压域为多个电压域中负载最小的电压域。可选地，也可以根据经验或统计数据获得的值作为预设值来限定第一负载阈值，如10％等，此时，可以将多个电压域中负载小于10％的电压域确定为上述第一电压域。当然，上述确定第一电压域的实现方式仅作为一种示例，对于实际应用中如何从多个电压域中确定出负载相对较小的第一电压域的具体实现，本实施例对此并不进行限定。
作为另一种可能的实现方式，除了根据电压域的负载确定第一电压域外，具体实施过程中，也可以是根据其它方式确定第一电压域，如可以是将多个电压域中任务数量较小的电压域作为第一电压域等。其中，电压域的任务数量，即为该电压域中所有处理器核上执行的任务数量总和。或者，实际应用中，第一电压域的负载也可以高于多个电压域中其它电压域的负载，本实施例中对于如何确定第一电压域的具体实现并不进行限定。
S402：将所识别的第一电压域的处理器核待执行的任务迁移至第二电压域，该第二电压域为该设备中除第一电压域之外的电压域。
设备除了包括第一电压域以外，还包括不满足上述预设条件的第二电压域，比如，该第二电压域的负载大于第一电压域的负载等。示例性的，设备在识别出满足预设条件的第一电压域的同时，还可以识别出第二电压域。作为一种示例，设备可以将多个电压域中负载大于第二负载阈值，并且小于或等于第三负载阈值的电压域，识别为第二电压域。当然，也可以是采用其它方式确定第二电压域，如基于电压域中处理器核上待执行的任务数量进行确定等。
对于第一电压域中所有处理器核待执行的任务，设备可以将其迁移至第二电压域，具体是迁移至第二电压域中的处理器核上，以便由第二电压域中处理器核完成上述迁移的任务的处理。实际应用中，第一电压域中的处理器核可以配置有至少两个队列，包括队列1以及队列2，其中，队列1可以用于存储该处理器核正在执行的任务，而队列2可以用于存储该处理器核待执行的任务。同样，第二电压域中的处理器核也可以配置有两个队列，分别为用于存储该处理器核正在执行任务的队列3以及待执行的任务的队列4。此时，设备中的调度器在进行任务迁移时，具体可以是将队列2中待执行的任务迁移至队列中4中，以便于由第二电压域中的处理器核执行队列4中的任务。也就是说，处理器核待执行的任务包括处理器核正在执行的任务，以及该处理器核待执行的任务。
为使得第二电压域中的处理器核的负载在第二电压域内相对均衡，在一种可能的实施方式中，在将第一电压域的任务迁移至第二电压域时，设备可以基于负载均衡策略将第一电压域的任务均衡分配至第二电压域中的一个或多个处理器核，具体实现时，设备可以根据第二电压域中各个处理器核的负载情况，确定将各个任务分别迁移至第二电压域中的哪个处理器核，然后，根据所确定出的迁移策略将任务分别迁移至相应的处理器核执行。如此，可以使得第二电压域中的处理器核的负载分布满足负载均衡策略，尽可能避免任务迁移后，第二电压域中出现某个处理器核的负载过大而其它处理器核的负载较小的问题。而在其它可能的实施方式中，设备也可以是先将第一电压域的所有任务全部迁移至第二电压域后，再对第二电压域中的各个处理器核进行负载均衡。本实施例中，对于第二电压域内各个处理器核的负载处于均衡状态的具体实现并不进行限定。
如图4所示，以设备包括8个处理器核，并将8个处理器核划分为两个电压域(分别为电压域1和电压域2)为例进行说明。其中，电压域1中的4个处理器核的负载分别为5％、 1％、0％、4％，电压域2中的4个处理器核的负载分别为2％、1％、0％、4％，则可以将电压域2中的全部任务迁移至电压域1中，并且，在任务迁移过程中或者任务迁移后，可以对电压域1中各个处理器核进行负载均衡。任务迁移后，电压域1以及电压域2中各个处理器核的负载如图4左下方所示。当然，实际应用中也可以是将电压域1中的全部任务迁移至电压域2中，并且电压域2中的各个处理器核的负载满足负载均衡策略，则，任务迁移后，电压域1以及第二电压域2中的各个处理器核的负载如图4右下方所示。特别的，由于在进行任务迁移之前，电压域1中4个处理器核的总负载为10％(即5％+1％+0％+4％)，大于电压域2中4个处理器核的总负载7％(即2％+1％+0％+4％)，因此，将电压域2中任务迁移至电压域1中，通常可以尽可能减少所需迁移的任务数量。
值得注意的是，本实施例中，处理器核之间的负载均衡，可以是指不同处理器核之间的负载差异处于预设范围内。比如，如图4所示，电压域1或者电压域2进行负载均衡后，电压域1或者电压域2中各个处理器核的负载之间的差异不超过1％。
实际应用中，基于设备的性能要求，可能要求第二电压域中各个处理器核的负载不能超过该第二电压域所允许承受的负载阈值，因此，在一些可能的实施方式中，设备在将第一电压域中所有处理器核执行的任务迁移至第二电压域之前，还可以根据执行待迁移的任务所需占用的负载和第二电压域可承担的负载情况，判断能够将第一电压域中所有处理器核执行的任务迁移至第二电压域。具体地，设备可以先计算第一电压域的负载以及第二电压域的负载之和，并判断该负载之和是否大于第二电压域对应的第五负载阈值。当该负载之和不大于第五负载阈值时，设备将第一电压域中所有处理器核执行的任务迁移至第二电压域；而当该负载之和大于第五负载阈值时，设备可以不进行任务迁移，或者将第一电压域中的部分任务迁移至第二电压域，或者将所有任务迁移至负载更小的电压域，否则第一电压源的任务迁移至第二电压域，会导致第二电压域的负载过大，从而影响设备的任务处理性能，如任务的处理时延过高等。
在另一些可能的实施方式中，当设备处于低负载场景时，设备才将第一电压域中的任务全部迁移至第二电压域，也就是说，当设备的所有电压域的负载低于预设值时，再执行第一电压域中处理器核的任务迁移。具体的，设备可以计算出各个电压域的负载，每个电压域的负载即为该电压域中各个处理器核的负载之和，然后，设备可以进一步计算出所有电压域的负载总和，并且，当所有电压域的总负载小于第四负载阈值时，设备处于低负载场景，并且，该设备可以从多个电压域中识别出第一电压域并将该第一电压域中的任务进行迁移；而当所有电压域的总负载不小于第四负载阈值时，设备不处于低负载场景，则设备可以不进行上述任务迁移过程。其中，第四负载阈值，例如可以是一个电压域所能允许的最大负载，或者，可以是多个电压域所能允许的最大负载之和。
示例性的，当设备为SMP设备时，可以基于下述公式确定该设备是否处于低负载场景：
total_until_avg<pd_capability*80％*N
其中，total_until_avg是指设备上所有处理器核的负载之和，pd_capability为单个电压域的计算能力，而pd_capability*80％为单独电压域所能允许的最大负载，N为电压域的数量，pd_capability*80％*N，即为上述第四负载阈值，并且，当N取值为1时，第四负载阈值为一个电压域所能允许的最大负载，而当N取值大于1时，第四负载阈值为多个电压域所能允许的最大负载之和。当然，上述公式仅作为一种示例性说明，并不用于限定用于确定设备是否处于低负载场景的具体实现局限于该示例。
S403：将第一电压域中器件的运行模式设置为第一模式，该器件包括处理器核。
本实施例中，第一电压域中器件包括第一电压域中消耗能源的器件，包括处理器核，以及用于支持处理器核的运行的其它器件，如QPI总线、片上存储器控制器等。封装在一个芯片或单元或逻辑电路的芯片(也可以称为package)可以包括一个或多个电压域，比如，处理器芯片是Intel(R)Xeon(R)Gold 6148 CPU@2.40GHz这种处理器核的芯片，其可以包括两个及两个以上的电压域。
设备在将第一电压域中处理器核待执行的任务全部迁移至第二电压域后，第一电压域中的处理器核可以不再有待执行的任务，或者具有更少数量的待执行任务，此时，设备可以在完成任务迁移以及第一电压域中的处理器核执行完当前正在执行的任务后，将第一电压域中的所有器件(如整个package)的运行模式设置为功耗相对较低的模式，以下称之为第一模式。此时，处理器核和与处理器核关联的器件的运行模式相同。
通常情况下，当第一电压域中的任意一个处理器核未进入第一模式，则该第一电压域中的其它器件也无法进入第一模式，上述package也就无法被设置为第一模式；而当该第一电压域中的所有处理器核的运行模式均设置为第一模式时，第一电压域中用于支持该处理器核运行的其它器件的运行模式才能被设置为第一模式。
虽然，第二电压域中的处理器核因为需要执行任务的增加而导致功耗增加，但是实际应用中，处理器核的负载和功耗通常近似呈线性关系，因此，第一电压域中处理器核的功耗降低与第二电压域中处理器核的功耗增加可以近似相抵，而设备整体降低的能耗通常在于第一电压域中与处理器核相关的其它器件降低的功耗。因此，将第一电压域中所有处理器核以及非核器件的运行模式设置为低功耗的第一模式，能够实现有效降低设备的整体功耗。其中，任务迁移所造成的额外功耗通常远小于第一电压域中与处理器核相关的其它器件降低的功耗，因此，对于任务迁移所造成的额外功耗，本实施例中可以忽略不计。
示例性的，设备可以支持处理器核处于多种不同的运行模式。以Intel(R)Xeon(R)Gold 6148 CPU@2.40GHz为例，设备可以支持处理器核处于C0、C1、C1E、C6这4种不同的运行模式。其中，C0模式为正常运行模式，处理器核在C0模式下的功耗通常高于处理器核在其它运行模式下的功耗；C6为深度节能模式，处理器核在C6模式下的功耗通常低于处理器核在其它运行模式下的功耗。其中，处理器核在C0、C1、C1E以及C6这4种不同的运行模式下的功耗依次降低。当然，设备还可以支持其它可能的运行模式，本实施例对此并不进行限定。
本实施例中，第一电压域的任务在迁移至第二电压域之前，第一电压域中的各个处理器核的运行模式可以是第二模式，而在设备完成任务迁移后，设备可以将第一电压域中各个处理器核的运行模式设置为第一模式，处理器核在该第一模式下的功耗小于处理器核在第二模式下的功耗。比如，第二模式可以是C0模式，而第一模式可以是C1模式、C1E模式或者C6模式等。
值得注意的是，不同运行模式可能对于处理器核具有不同的驻留时长要求，该驻留时长即为处理器核处于该运行模式时所要求达到的时长，或者该驻留时长也可以用处理器核在运行模型下的工作频率进行表征。通常情况下，处理器核在进入以及退出该运行模式时具有额外功耗，而处理器核进入该运行模式所能停留的时长达到该驻留时长(或频率)时，设备所能节省的功耗能够抵消该处理器核进入以及退出该运行模式时所造成的额外功耗，同时，也可以是避免处理器核因为进入不合适的运行模式而频繁切换处理器核的运行模式。在C1至C6的运行模式中，每种运行模式都有对应的驻留时长。
因此，在一些可能的实施方式中，设备在设置第一电压域中所有器件的运行模式时，可 以预测该第一电压域的处理器核的空闲时长，该空闲时长即为处理器核不执行任务的时长，然后，设备可以将该空闲时长与各个运行模式对应的驻留时长进行比较，确定出小于该空闲时长的最大驻留时长，该最大驻留时长对应的运行模式即为第一模式，而设备可以将第一电压域中的所有处理器核以及非核器件的运行模式设置为该第一模式。
例如，C1、C1E以及C6运行模式对应的驻留时长依次为2us(微秒)、10us、50us，若设备预测第一电压域中处理器核的空闲时长为55us，由于55us大于50us，则设备可以选择将C6运行模式作为第一模式，并将第一电压域的处理器核的运行模式设置为C6模式；而若设备预测第一电压域中处理器核的空闲时长为30s，由于10us<30us<50us，因此，设备可以选择将C1E运行模式作为第一模式，并将该第一电压域的处理器核以及非核器件的运行模式设置为C1E模式。
示例性的，设备在预测处理器核的空闲时长时，具体可以是根据处理器核在过去多个不同时间段内的预测出的空闲时长以及实际空闲时长，计算出每个时间段内预测出的空闲时长以及实际空闲时长之间的比率，以此可以得到多个不同时间段对应的比率值。然后，设备可以采用动态平均算法，根据多个时间段对应的比率值对当前预测出的初始空闲时长进行调整，得到最终预测出的空闲时长，比如，设备可以计算多个比率值的平均值，并将该平均值与初始空闲时长时间的乘积，作为设备在当前时间段预测出的处理器核的空闲时长。
当然，设备也可以是采用其它方式对处理器核的空闲时长进行预测，或者是采用比上述示例更加复杂/简化的计算过程或者采用其它方式确定第一模式，本实施例对此并不进行限定。
另外，第二电压域中处理器核所执行的任务增加后，设备还可以根据该处理器核的负载，调整处理器核的工作频率，例如增加该处理器核的工作频率，以使得该处理器核能够在单位时间内执行更多的任务，从而尽可能保证设备的性能不被降低。
实际应用的一些场景中，设备的多个电压域中，可能存在部分电压域的负载过高，比如，部分电压域的负载可能已经超出该电压域所能允许的第二负载阈值，则设备可以针对于该部分电压域进行负载均衡。其中，设备可以是根据负载超出第二负载阈值的数量确定进行局部负载均衡还是全局负载均衡。具体的，设备可以根据各个电压域的负载确定多个电压域中负载大于第二负载阈值的电压域的数量，当该数量大于预设数量时，设备可以根据多个电压域的负载情况，对多个电压域进行负载均衡，而当该数量小于预设数量时，设备可以根据多个电压域中的部分电压域的负载情况，对部分电压域进行负载均衡，该部分电压域中包括负载大于第二负载阈值的电压域以及负载小于第二负载阈值的电压域。
比如，假设设备包括80个处理器核，并且该80个处理器核可以被划分为20个电压域，则当负载大于第二负载阈值的电压域的数量不超过5个时，可以选取10个负载小于第二负载阈值的电压域，并利用所选取的10个电压域对负载大于第二负载阈值的电压域进行负载均衡；而当负载大于第二负载阈值的电压域的数量超过5个时，则设备可以在20个电压域内进行负载均衡。
进一步的，设备在进行功耗管理时，还可以呈现该设备的功耗管理结果，以便用户查看。示例性的，该设备的功耗管理结果，可以包括处理器、电压域、处理器核等多个不同维度的信息。比如，功耗管理结果可以包括各个处理器的功耗管理结果、每个处理器中各个电压域的功耗管理结果、每个电压域中各个处理器核的功耗管理结果等。在一种示例中设备可以通过预设显示界面呈现该设备的功耗管理结果，该预设显示界面可以位于该设备上，也可以是由设备将该功耗管理结果传输给其它设备，并通过其它设备的显示界面进行信息呈现。其中， 在预设显示界面上所呈现的功耗管理结果，可以包括处理器的功耗、标识、利用率等信息，各个电压域的功耗、标识等信息，每个电压域中的处理器核的标识、运行模式、功耗、工作频率、电压、利用率、处于各个运行模式的时长占比，以及器件温度(包括处理器核的温度以及与处理器核关联的器件的温度)等信息中的任意一种或者多种。如图5所示，可以在界面上呈现设备中处理器的利用率、利用率的动态变化曲线以及数值、运行进程以及线程数量、正常运行时间等。当用户期望进一步查看该处理器的相关信息，用户通过点击“具体详情”，可以在弹出的显示界面中查看到处理器中不同电压域的标识、处理器核的标识、处理器核所处的运行模式、处理器核的功耗以及工作频率等信息。进一步的，用户还可以点击该显示界面中的“其它信息”以查看该处理器的其它相关信息，如处理器核的运行时长、故障处理等信息；或者，用户通过点击该显示界面中的“其它信息”查看第一点电压域中与处理器核关联的其它器件的信息，如其它器件的温度、使用率、负载等信息(图中未示出)。
本实施例中，是以一个第一电压域为例进行示例性说明，实际应用中，设备可以将多个第一电压域中的任务迁移至其它电压域中，当然，进行任务迁移的第一电压域的数量小于设备中电压域的总数量。针对于每个第一电压域，设备所执行的识别、任务迁移以及运行模式设置的具体实现过程，可以参见上述实施例中的相关描述，在此不做赘述。
需要说明的是，对于上述方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本申请并不受所描述的动作顺序的限制。
本领域的技术人员根据以上描述的内容，能够想到的其他合理的步骤组合，也属于本申请的保护范围内。其次，本领域技术人员也应该熟悉，说明书中所描述的实施例均属于优选实施例，所涉及的动作并不一定是本申请所必须的。
上文中结合图1至图5，详细描述了本申请所提供的功耗管理方法，下面将结合图6至图7，描述根据本申请所提供的功耗管理装置和设备。
图6为本申请提供的一种功耗管理装置600，该功耗管理装置600可以应用于包括多个电压域的设备，并且，每个电压域中包括至少一个处理器核，该功耗管理装置600可以包括：
识别模块601，用于识别满足预设条件的第一电压域，所述第一电压域为所述设备中任意一个电压域；
任务迁移模块602，用于将所述第一电压域的处理器核待执行的任务迁移至第二电压域，所述第二电压域为所述设备中除所述第一电压域之外的电压域；
设置模块603，用于将所述第一电压域中器件的运行模式设置为第一模式，所述器件包括所述处理器核。
应理解的是，本申请实施例的装置600可以通过专用集成电路(application-specific integrated circuit，ASIC)实现，或可编程逻辑器件(programmable logic device，PLD)实现，上述PLD可以是复杂程序逻辑器件(complex programmable logical device，CPLD)，现场可编程门阵列(field-programmable gate array，FPGA)，通用阵列逻辑(generic array logic，GAL)或其任意组合。也可以通过软件实现图3所示的功耗管理方法时，装置600及其各个模块也可以为软件模块。
在一种可能的实施方式中，所述识别模块601，具体用于：
根据所述设备中多个电压域的负载情况识别所述第一电压域，所述第一电压域的负载满足所述预设条件。
在一种可能的实施方式中，所述识别模块601，具体用于：
根据所述多个电压域的负载排序，选择所述多个电压域中负载小于或等于第一负载阈值 的电压域为所述第一电压域。
在一种可能的实施方式中，所述第一负载阈值为所述多个电压域中负载最小的电压域的负载值。
在一种可能的实施方式中，所述识别模块，具体用于：
根据预设负载均衡策略，识别所述第一电压域。
在一种可能的实施方式中，所述识别模块601，还用于：
根据所述设备中多个电压域的负载情况识别所述第二电压域，所述第二电压域的负载大于第二负载阈值，所述第二电压域为负载情况小于或等于第三负载阈值的电压域。
在一种可能的实施方式中，所述识别模块601，具体用于：
当所述多个电压域的总负载小于第四负载阈值时，识别满足预设条件的第一电压域。
在一种可能的实施方式中，所述识别模块601，还用于在识别满足预设条件的第一电压域之前，识别所述设备中电压域和处理器核的对应关系。
在一种可能的实施方式中，所述设置模块，具体用于：
预测所述第一电压域的处理器核的空闲时长；
根据所述空闲时长，将所述第一电压域中器件的运行模式设置为所述第一模式。
在一种可能的实施方式中，所述功耗管理装置600，还包括：
呈现模块604，用于在预设显示界面呈现功耗管理结果，所述功耗管理结果包括所述多个电压域中每个电压域的标识、功耗，以及处理器核的标识、运行模式、功耗、工作频率、电压、利用率、处于所述第一模式的时长占比，以及所述器件的温度中的任意一种或多种
在一种可能的实施方式中，在所述任务迁移至所述第二电压域后，所述第一电压域中处理器核的负载分布满足负载均衡策略，所述负载均衡策略用于均衡所述第一电压域中处理器核的负载。
在一种可能的实施方式中，所述功耗管理装置600，还包括：
负载均衡模块605，用于当所述多个电压域中存在负载大于第二负载阈值的电压域的数量大于预设数量时，根据所述多个电压域的负载情况，对所述多个电压域进行负载均衡。
在一种可能的实施方式中，所述第二电压域的负载不大于第五负载阈值。
在一种可能的实施方式中，所述电压域中的处理器核的电压能够被统一调节。
根据本申请实施例的功耗管理装置600可对应于执行本申请实施例中描述的方法，并且功耗管理装置600中的各个单元的上述和其它操作和/或功能分别为了实现图3中的各个方法的相应流程，为了简洁，在此不再赘述。
图7为本申请提供的一种调度器700的示意图，如图所示，所述调度器700包括处理器701、存储介质702、通信接口703和内存单元704。其中，处理器701、存储介质702、通信接口703、内存单元704通过总线705进行通信，也可以通过无线传输等其他手段实现通信。该存储器702用于存储指令，该处理器701用于执行该存储器702存储的指令。该存储器702存储程序代码，且处理器701可以调用存储器702中存储的程序代码执行以下操作：
识别满足预设条件的第一电压域，所述第一电压域为设备中任意一个电压域，该设备包括多个电压域，并且，每个电压域中包括至少一个处理器核；
将所述第一电压域的处理器核执行的任务迁移至第二电压域，所述第二电压域为所述设备中除所述第一电压域之外的电压域；
将所述第一电压域中器件的运行模式设置为第一模式，所述器件包括所述处理器核。
应理解，在本申请实施例中，该处理器701可以是CPU，该处理器701还可以是其他通 用处理器、数字信号处理器(DSP)、专用集成电路(ASIC)、现场可编程门阵列(FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立器件组件等。通用处理器可以是微处理器或者是任何常规的处理器等。
该存储器702可以包括只读存储器和随机存取存储器，并向处理器701提供指令和数据。存储器702还可以包括非易失性随机存取存储器。例如，存储器702还可以存储设备类型的信息。
该存储器702可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(read-only memory,ROM)、可编程只读存储器(programmable ROM,PROM)、可擦除可编程只读存储器(erasable PROM,EPROM)、电可擦除可编程只读存储器(electrically EPROM,EEPROM)或闪存。易失性存储器可以是随机存取存储器(random access memory,RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(static RAM,SRAM)、动态随机存取存储器(DRAM)、同步动态随机存取存储器(synchronous DRAM,SDRAM)、双倍数据速率同步动态随机存取存储器(double data date SDRAM,DDR SDRAM)、增强型同步动态随机存取存储器(enhanced SDRAM,ESDRAM)、同步连接动态随机存取存储器(synchlink DRAM,SLDRAM)和直接内存总线随机存取存储器(direct rambus RAM,DR RAM)。
该通信接口703用于与调度器700连接的其它设备进行通信，如调度器700可以通过通信接口703获取该包括多个电压域的设备中电压域的划分情况等。该总线705除包括数据总线之外，还可以包括电源总线、控制总线和状态信号总线等。但是为了清楚说明起见，在图中将各种总线都标为总线705。
应理解，根据本申请实施例的调度器700可对应于本申请实施例中的功耗管理装置600，并可以对应于执行根据本申请实施例中图3所示方法中的相应主体，并且调度器700中的各个模块的上述和其它操作和/或功能分别为了实现图3中的各个方法的相应流程，为了简洁，在此不再赘述。
此外，本申请还提供了一种设备，该设备中可以包括上述图7所示的调度器700，该设备可以实现图3中的各个方法的相应流程，为了简洁，在此不再赘述。
此外，本申请还提供了一种计算机程序产品，所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、训练设备或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、训练设备或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存储的任何可用介质或者是包含一个或多个可用介质集成的训练设备、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘(solid state disk，SSD))等。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的术语在适当情况下可以互换，这仅仅是描述本申请的实施例中对相同属性的对象在描述时所采用的区分方式。
另外需说明的是，以上所描述的装置实施例仅是示意性的，其中所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本申请方案的目的。另外，本申请提供的装置附图中，模块之间的连接关系表示它们之间具有通信连接，具体可以实现为一条或多条通信总线或信号线。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (23)

  1. 一种功耗管理的方法，其特征在于，所述方法应用于设备，所述设备包括多个电压域，每个电压域中包括至少一个处理器核，所述方法包括：
    识别满足预设条件的第一电压域，所述第一电压域为所述设备中任意一个电压域；
    将所述第一电压域的处理器核待执行的任务迁移至第二电压域，所述第二电压域为所述设备中除所述第一电压域之外的电压域；
    将所述第一电压域中器件的运行模式设置为第一模式，所述器件包括所述处理器核。
  2. 根据权利要求1所述的方法，其特征在于，所述识别满足预设条件的第一电压域，包括：
    根据所述设备中多个电压域的负载情况识别所述第一电压域，所述第一电压域的负载满足所述预设条件。
  3. 根据权利要求2所述的方法，其特征在于，所述根据所述设备中多个电压域的负载情况识别所述第一电压域，包括：
    根据所述多个电压域的负载排序，选择所述多个电压域中负载小于或等于第一负载阈值的电压域为所述第一电压域。
  4. 根据权利要求3所述的方法，其特征在于，所述第一负载阈值为所述多个电压域中负载最小的电压域的负载值。
  5. 根据权利要求1所述的方法，其特征在于，所述识别满足预设条件的第一电压域，包括：
    根据预设负载均衡策略，识别所述第一电压域。
  6. 根据权利要求1至5任一项所述的方法，其特征在于，所述方法还包括：
    根据所述设备中多个电压域的负载情况识别所述第二电压域，所述第二电压域的负载大于第二负载阈值，所述第二电压域为负载情况小于或等于第三负载阈值的电压域。
  7. 根据权利要求1至6任一项所述的方法，其特征在于，所述识别满足预设条件的第一电压域，包括：
    当所述多个电压域的总负载小于第四负载阈值时，识别满足预设条件的第一电压域。
  8. 根据权利要求1所述的方法，其特征在于，在识别满足预设条件的第一电压域之前，所述方法还包括：
    识别所述设备中电压域和处理器核的对应关系。
  9. 根据权利要求1至8中任一项所述的方法，其特征在于，所述将所述第一电压域中器件的运行模式设置为第一模式，包括：
    预测所述第一电压域的处理器核的空闲时长；
    根据所述空闲时长，将所述第一电压域中器件的运行模式设置为所述第一模式。
  10. 根据权利要求1至9任一项所述的方法，其特征在于，所述方法还包括：
    在预设显示界面呈现功耗管理结果，所述功耗管理结果包括所述多个电压域中每个电压域的标识、功耗，以及处理器核的标识、运行模式、功耗、工作频率、电压、利用率、处于所述第一模式的时长占比，以及器件的温度中的任意一种或多种。
  11. 一种功耗管理的装置，其特征在于，所述装置应用于设备，所述设备包括多个电压域，每个电压域中包括至少一个处理器核，所述装置包括：
    识别模块，用于识别满足预设条件的第一电压域，所述第一电压域为所述设备中任意一个电压域；
    迁移模块，用于将所述第一电压域的处理器核待执行的任务迁移至第二电压域，所述第二电压域为所述设备中除所述第一电压域之外的电压域；
    设置模块，用于将所述第一电压域中器件的运行模式设置为第一模式，所述器件包括所述处理器核。
  12. 根据权利要求11所述的装置，其特征在于，所述识别模块，具体用于根据所述设备中多个电压域的负载情况识别所述第一电压域，所述第一电压域的负载满足所述预设条件。
  13. 根据权利要求12所述的装置，其特征在于，所述识别模块，具体用于根据所述多个电压域的负载排序，选择所述多个电压域中负载小于或等于第一负载阈值的电压域为所述第一电压域。
  14. 根据权利要求13所述的装置，其特征在于，所述第一负载阈值为所述多个电压域中负载最小的电压域的负载值。
  15. 根据权利要求11所述的装置，其特征在于，所述识别模块，具体用于根据预设负载均衡策略，识别所述第一电压域。
  16. 根据权利要求11至15任一项所述的装置，其特征在于，所述识别模块，还用于根据所述设备中多个电压域的负载情况识别所述第二电压域，所述第二电压域的负载大于第二负载阈值，所述第二电压域为负载情况小于或等于第三负载阈值的电压域。
  17. 根据权利要求11至16任一项所述的装置，其特征在于，所述识别模块，具体用于当所述多个电压域的总负载小于第四负载阈值时，识别满足预设条件的第一电压域。
  18. 根据权利要求11所述的装置，其特征在于，所述识别模块，还用于在识别满足预设条件的第一电压域之前，识别所述设备中电压域和处理器核的对应关系。
  19. 根据权利要求11至18中任一项所述的装置，其特征在于，所述设置模块，具体用于：
    预测所述第一电压域的处理器核的空闲时长；
    根据所述空闲时长，将所述第一电压域中器件的运行模式设置为所述第一模式。
  20. 根据权利要求11至19任一项所述的装置，其特征在于，所述装置还包括：
    呈现模块，用于在预设显示界面呈现功耗管理结果，所述功耗管理结果包括所述多个电压域中每个电压域的标识、功耗，以及处理器核的标识、运行模式、功耗、工作频率、电压、利用率、处于所述第一模式的时长占比，以及器件的温度中的任意一种或多种
  21. 一种调度器，其特征在于，包括处理器和存储器；
    所述存储器，用于存储计算机指令；
    所述处理器，用于根据所述计算机指令执行如权利要求1至10任一项所述方法的操作步骤。
  22. 一种设备，其特征在于，所述设备包括权利要求12所述调度器，用于实现如权利要求1至10任一项所述方法的操作步骤。
  23. 一种计算机可读存储介质，其特征在于，包括指令，所述指令用于实现如权利要求1至10中任一项所述方法的操作步骤。
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