WO2021114774A1

WO2021114774A1 - Method and device for processing aggregated link

Info

Publication number: WO2021114774A1
Application number: PCT/CN2020/114059
Authority: WO
Inventors: 何志川; 李磊; 赵子苍; 赵茂聪
Original assignee: 盛科网络（苏州）有限公司
Priority date: 2019-12-09
Filing date: 2020-09-08
Publication date: 2021-06-17
Also published as: CN111131024A

Abstract

The present invention provides a method and a device for processing an aggregated link. Said method comprises: detecting a link state of an aggregated link in an aggregated link group by means of a switching chip; and upon detection that the link state of the aggregated link is a failure state, the switching chip deleting, from the aggregated link group, a first port corresponding to the aggregated link. The present invention solves the problem in the related art of a long duration required for processing a failure in an aggregated link group, thereby shortening the duration for processing a failure in the aggregated link group, and further reducing the number of messages discarded in the aggregated link group.

Description

Method and device for processing aggregated links

Technical field

The present invention relates to the field of communications, and in particular, to a method and device for processing aggregated links.

Background technique

In related technologies, after the member link is found to be disconnected in the aggregated link group, the chip will first generate a LinkDown interrupt event (also known as Linkdown message, that is, link failure message) to inform the CPU that the CPU is learning the specific member port Then, delete the member port from the aggregation link.

It can be seen that in related technologies, after detecting a member link failure, the CPU needs to be notified for processing, and then the member port is deleted from the aggregated link. However, it takes a period of time to process from the detection of the link disconnection to the deletion of the member port. During this period of time, through aggregation link routing, the packets sent to the failed member link will be discarded, resulting in packets going out from the member port corresponding to the member link in the failed state. A lot of text is lost.

Regarding the problem of long time required for processing failures in the aggregated link group in related technologies, no technical solution has been proposed.

Summary of the invention

The embodiment of the present invention provides a method and device for processing an aggregated link, so as to at least solve the problem of a long time required for processing a fault in an aggregated link group in the related art.

According to an embodiment of the present invention, a method for processing aggregated links is provided, including:

Detect the link status of the aggregated links in the aggregated link group through the switch chip;

In the case of detecting that the link state of the aggregated link is a failure state, the switch chip deletes the first port corresponding to the aggregated link from the aggregated link group.

Optionally, the switch chip deleting the first port corresponding to the aggregated link from the aggregated link group includes: determining a target position of the first port in the aggregated link group; Deleting the first port corresponding to the target location from the aggregated link group.

Optionally, after the first port corresponding to the target location is deleted from the aggregated link group, the method further includes: updating the number of member ports in the aggregated link group.

Optionally, in the case that the first port is not the last port in the aggregated link group, after the first port corresponding to the target location is deleted from the aggregated link group, The method further includes: determining a second port corresponding to a second position in the aggregated link group, wherein the second port is located at the last position in the aggregated link group; writing the second port Enter the target location; delete the second location in the aggregated link group, and update the number of member ports in the aggregated link group.

Optionally, after the switch chip deletes the first port corresponding to the aggregate link from the aggregate link group, the method further includes: the switch chip sends an interrupt notification to the CPU, wherein: The interrupt notification is used to instruct the CPU to update the soft table.

According to an embodiment of the present invention, there is provided an apparatus for processing aggregated links, including:

The detection module is set to detect the link status of the aggregated link in the aggregated link group through the switch chip;

The deleting module is configured to delete the first port corresponding to the aggregated link from the aggregated link group when it is detected that the link state of the aggregated link is a fault state.

Optionally, the deletion module is further configured to: determine the target position of the first port in the aggregated link group; remove the first port corresponding to the target position from the aggregated link group Delete from the group.

Optionally, the device further includes: an update module configured to update the number of member ports in the aggregated link group.

Optionally, the device further includes: a determining module configured to determine the second position in the aggregated link group when the first port is not the last port in the aggregated link group Corresponding second port, wherein the second port is located at the last position in the aggregated link group; a writing module, configured to write the second port into the target position; a processing module, setting To delete the second position in the aggregated link group and update the number of member ports in the aggregated link group.

Optionally, the device further includes: a notification module configured to, after the switching chip deletes the first port corresponding to the aggregated link from the aggregated link group, the switching chip to the CPU Sending an interrupt notification, where the interrupt notification is used to instruct the CPU to update the soft table.

According to yet another embodiment of the present invention, there is also provided a computer-readable storage medium in which a computer program is stored, wherein the computer program is configured to execute any of the above methods when running Steps in the embodiment.

According to another embodiment of the present invention, there is also provided an electronic device, including a memory and a processor, the memory is stored with a computer program, and the processor is configured to run the computer program to execute any of the above Steps in the method embodiment.

Through the present invention, the link state of the aggregated link in the aggregated link group is detected by the switch chip; in the case that the link state of the aggregated link is detected as a failure state, the switch chip will communicate with the aggregated link. The first port corresponding to the link is deleted from the aggregated link group. Therefore, it can solve the problem of the long time required to process the failure of the aggregated link group in the related technology, and realize the shortening of the time for processing the failure of the aggregated link group, thereby reducing the number of discarded packets of the aggregated link group .

Description of the drawings

The drawings described here are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments and descriptions of the present invention are used to explain the present invention, and do not constitute an improper limitation of the present invention. In the attached picture:

Fig. 1 is a flowchart of a method for processing aggregated links according to an embodiment of the present invention;

Figure 2 is a schematic diagram of a processing method for aggregated links according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a method for processing aggregated links according to another embodiment of the present invention;

4 is a schematic diagram of a method for processing aggregated links according to another embodiment of the present invention;

Fig. 5 is a schematic diagram of a method for processing aggregated links according to another embodiment of the present invention;

Fig. 6 is a structural block diagram of an apparatus for processing aggregated links according to an embodiment of the present invention.

Detailed ways

Hereinafter, the present invention will be described in detail with reference to the drawings and in conjunction with the embodiments. It should be noted that the embodiments in the application and the features in the embodiments can be combined with each other if there is no conflict.

It should be noted that the terms "first" and "second" in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific sequence or sequence.

Example 1

The embodiment of the present invention provides a processing method for aggregated links. Fig. 1 is a flowchart of a method for processing aggregated links according to an embodiment of the present invention, as shown in Fig. 1, including:

Step S102: Detect the link state of the aggregated link in the aggregated link group through the switch chip;

Step S104: In a case where it is detected that the link state of the aggregated link is a failure state, the switch chip deletes the first port corresponding to the aggregated link from the aggregated link group.

Optionally, the fault state includes: a disconnected state.

Through the present invention, the link state of the aggregated link in the aggregated link group is detected by the switch chip; in the case that the link state of the aggregated link is detected as a failure state, the switch chip will communicate with the aggregated link. The first port corresponding to the link is deleted from the aggregated link group. Therefore, it can solve the problem of long time required to process the failure of the aggregated link group in the related technology, realize the shortening of the time for processing the failure of the aggregated link group, and thereby reduce the number of discarded packets of the aggregated link group .

As an optional implementation manner, the detecting that the link state of the aggregated link is a failure state includes: detecting a Linkdown event (that is, a Linkdown packet) of a member link in the aggregated link group . Figure 2 is a schematic diagram of a method for processing aggregated links according to an embodiment of the present invention. As shown in Figure 2, the aggregated link group consists of 8 members, namely port #1 to port #8. When port #3 corresponds to After the link is disconnected, the chip will detect the link Link Down event and immediately enter the aggregation link protection processing flow in the chip.

It should be noted that in the above-mentioned embodiment, because a switch chip detects that the link state of the aggregated link is a failure state, it directly removes the first port corresponding to the aggregated link from the aggregated link group. Delete, without notifying the central processing unit (CPU) of the fault status before deleting, which saves the processing time of the fault, speeds up the processing of the fault, and realizes the rapid aggregation of the link heal.

As an optional implementation manner, the switch chip deleting the first port corresponding to the aggregated link from the aggregated link group includes: determining that the first port is in the aggregated link group The target location in the; the first port corresponding to the target location is deleted from the aggregated link group. As shown in Figure 2, after the port #7 link is disconnected, the chip immediately enters the aggregation link protection processing flow in the chip. Since port #7 is the last member of the link group, it is only necessary to connect the aggregation chain The number of road group members minus 1 becomes 6. FIG. 3 is a schematic diagram of a method for processing an aggregated link according to another embodiment of the present invention. After the foregoing processing, the distribution of members of the aggregated link becomes the distribution as shown in FIG. 3.

As an optional implementation manner, after the first port corresponding to the target location is deleted from the aggregated link group, the method further includes: updating member ports in the aggregated link group Quantity.

As an optional implementation manner, in the case that the first port is not the last port in the aggregated link group, the first port corresponding to the target location is removed from the aggregated link group. After deleting from the group, the method further includes: determining a second port corresponding to a second position in the aggregated link group, wherein the second port is located at the last position in the aggregated link group; The second port is written into the target location; the second location is deleted in the aggregated link group, and the number of member ports in the aggregated link group is updated.

It should be noted that in the above embodiment, when the first port is not the last port in the aggregated link group, the last port in the aggregated link group is also written to the target where the first port is located. Position, and delete the last position in the aggregated link group, thereby realizing the update of the aggregated link group.

Fig. 4 is a schematic diagram of a method for processing aggregated links according to another embodiment of the present invention. As shown in Figure 4, the chip first finds the location of port #3, moves the last member port #8 of the aggregated link group to the location of port #3, and reduces the number of members of the aggregated link group by 1. When it becomes 7, the chip completes the process of removing port #3 from the aggregated link. FIG. 5 is a schematic diagram of a method for processing an aggregated link according to another embodiment of the present invention. After the foregoing processing, the distribution of members of the aggregated link becomes the distribution shown in FIG. 5. After the chip executes the above steps, it then informs the CPU through interruption, and then the CPU synchronizes the status of the soft table, for example, to update the status of the aggregated link maintained in the soft table.

As an optional implementation manner, after the switching chip deletes the first port corresponding to the aggregated link from the aggregated link group, the method further includes: the switching chip sends to the CPU An interrupt notification, where the interrupt notification is used to instruct the CPU to update the soft table.

It should be noted that the soft table is stored in the CPU and is used to record information related to the aggregated link group (for example, the status of the member links in the aggregated link group, and the members of the aggregated link group). The status of the port). As an optional implementation manner, the foregoing embodiment may be applied to an Ethernet environment that requires high real-time data transmission, such as a data center network and an industrial network. Through the above-mentioned embodiments, it is possible to realize rapid healing at the level of microseconds or even nanoseconds. After the member link in the aggregation link is disconnected (that is, the aggregation link in the failed state in the above-mentioned embodiment), it is sent to the member link. No packet loss or only a few packets are dropped on the traffic on the network.

Optionally, the aforementioned switching chip may be an Application Specific Integrated Circuit (ASIC for short) chip, or a Field Programmable Gate Array (FPGA for short) chip or a network processor ( neural-network process units (referred to as NPU) chip. As an optional implementation manner, the foregoing technical solution may be executed by an aggregated link protection processing module in the switch chip, and the aggregated link protection processing module is configured to execute the foregoing aggregated link processing method.

Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, of course, it can also be implemented by hardware, but in many cases the former is Better implementation. Based on this understanding, the technical solution of the present invention essentially or the part that contributes to the existing technology can be embodied in the form of a software product, and the computer software product is stored in a storage medium (such as ROM/RAM, magnetic disk, The optical disc) includes a number of instructions to enable a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the method described in each embodiment of the present invention.

Example 2

According to another embodiment of the present invention, an apparatus for processing aggregated links is provided, and the apparatus is used to implement the above-mentioned embodiments and preferred implementations, and what has been described will not be repeated. As used below, the term "module" can implement a combination of software and/or hardware with predetermined functions. Although the devices described in the following embodiments are preferably implemented by software, implementation by hardware or a combination of software and hardware is also possible and conceived.

Fig. 6 is a structural block diagram of an apparatus for processing aggregated links according to an embodiment of the present invention, and the apparatus includes:

The detecting module 62 is configured to detect the link state of the aggregated link in the aggregated link group through the switch chip;

The deleting module 64 is configured to remove the first port corresponding to the aggregated link from the aggregated link group when the link state of the aggregated link is detected as a failure state. delete.

As an optional implementation manner, the deletion module 64 is further configured to: determine the target position of the first port in the aggregated link group; and set the first port corresponding to the target position Delete from the aggregated link group.

Optionally, the device further includes: a determining module configured to determine the second position in the aggregated link group when the first port is not the last port in the aggregated link group Corresponding second port, wherein the second port is located at the last position in the aggregated link group; a writing module configured to write the second port into the target position; a processing module, setting To delete the second position in the aggregated link group and update the number of member ports in the aggregated link group.

It should be noted that each of the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following manner, but not limited to this: the above modules are all located in the same processor; or, the above modules can be combined in any combination. The forms are located in different processors.

The embodiment of the present invention also provides a computer-readable storage medium having a computer program stored in the computer-readable storage medium, wherein the computer program is configured to execute the steps in any one of the foregoing method embodiments when running.

Optionally, in this embodiment, the above-mentioned computer-readable storage medium may include, but is not limited to: U disk, Read-Only Memory (Read-Only Memory, ROM for short), Random Access Memory (Random Access Memory, for short) RAM), mobile hard disks, magnetic disks or optical disks and other media that can store computer programs.

An embodiment of the present invention also provides an electronic device, including a memory and a processor, the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the foregoing method embodiments.

Optionally, the aforementioned electronic device may further include a transmission device and an input-output device, wherein the transmission device is connected to the aforementioned processor, and the input-output device is connected to the aforementioned processor.

Optionally, for specific examples in this embodiment, reference may be made to the examples described in the above-mentioned embodiments and optional implementation manners, and details are not described herein again in this embodiment.

Obviously, those skilled in the art should understand that the above-mentioned modules or steps of the present invention can be implemented by a general computing device, and they can be concentrated on a single computing device or distributed in a network composed of multiple computing devices. Above, alternatively, they can be implemented with program codes executable by the computing device, so that they can be stored in the storage device for execution by the computing device, and in some cases, can be executed in a different order than here. Perform the steps shown or described, or fabricate them into individual integrated circuit modules respectively, or fabricate multiple modules or steps of them into a single integrated circuit module for implementation. In this way, the present invention is not limited to any specific combination of hardware and software.

The above descriptions are only preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various modifications and changes. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present invention should be included in the protection scope of the present invention.

Industrial applicability

Claims

A processing method for aggregated links includes:

Detect the link status of the aggregated links in the aggregated link group through the switch chip;

In the case of detecting that the link state of the aggregated link is a failure state, the switch chip deletes the first port corresponding to the aggregated link from the aggregated link group.
The method according to claim 1, wherein the removal of the first port corresponding to the aggregated link from the aggregated link group by the switching chip comprises:

Determine the target position of the first port in the aggregated link group;

Deleting the first port corresponding to the target location from the aggregated link group.
The method according to claim 2, wherein after deleting the first port corresponding to the target location from the aggregated link group, the method further comprises:

Update the number of member ports in the aggregation link group.
The method according to claim 2, wherein, in the case that the first port is not the last port in the aggregated link group, the first port corresponding to the target location is removed from the aggregated link group. After the link group is deleted, the method further includes:

Determine the second port corresponding to the second position in the aggregated link group, where the second port is located at the last position in the aggregated link group;

Write the second port into the target location;

Delete the second position in the aggregate link group, and update the number of member ports in the aggregate link group.
The method according to claim 1, wherein after the switching chip deletes the first port corresponding to the aggregated link from the aggregated link group, the method further comprises:

The switch chip sends an interrupt notification to the CPU, where the interrupt notification is used to instruct the CPU to update the soft table.
A processing device for aggregated links, including:

The detection module is set to detect the link status of the aggregated link in the aggregated link group through the switch chip;

The deleting module is configured to delete the first port corresponding to the aggregated link from the aggregated link group when it is detected that the link state of the aggregated link is a fault state.
The device according to claim 6, wherein the deleting module is further configured to:

Determine the target position of the first port in the aggregated link group;

Deleting the first port corresponding to the target location from the aggregated link group.
The device according to claim 7, wherein the device further comprises:

The update module is configured to update the number of member ports in the aggregation link group.
The device according to claim 7, wherein the device further comprises:

The determining module is configured to determine the second port corresponding to the second position in the aggregated link group in the case that the first port is not the last port in the aggregated link group, wherein the first port is The second port is located at the last position in the aggregated link group;

A writing module, configured to write the second port into the target location;

The processing module is configured to delete the second position in the aggregated link group and update the number of member ports in the aggregated link group.
The device according to claim 6, wherein the device further comprises:

A notification module, configured to send an interrupt notification to the CPU after the switching chip deletes the first port corresponding to the aggregate link from the aggregate link group, wherein the interrupt notification is used for To instruct the CPU to update the soft table.