CN111131024A - Processing method and device of aggregated link - Google Patents
Processing method and device of aggregated link Download PDFInfo
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- CN111131024A CN111131024A CN201911252252.2A CN201911252252A CN111131024A CN 111131024 A CN111131024 A CN 111131024A CN 201911252252 A CN201911252252 A CN 201911252252A CN 111131024 A CN111131024 A CN 111131024A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/24—Multipath
- H04L45/245—Link aggregation, e.g. trunking
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/28—Routing or path finding of packets in data switching networks using route fault recovery
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Abstract
The invention provides a processing method and a device of an aggregated link, wherein the method comprises the following steps: detecting link states of aggregation links in the aggregation link group through a switching chip; and under the condition that the link state of the aggregation link is detected to be a fault state, the switching chip deletes the first port corresponding to the aggregation link from the aggregation link group. The invention solves the problem of longer time for processing the fault in the aggregation link group in the related technology, realizes the shortening of the time for processing the fault of the aggregation link group and further reduces the number of discarded messages of the aggregation link group.
Description
Technical Field
The present invention relates to the field of communications, and in particular, to a method and an apparatus for processing an aggregated link.
Background
In the related art, after a member link is found to be disconnected in an aggregation link group, a chip first generates a LinkDown interrupt event (also called a LinkDown message, i.e. a link failure message) to notify a CPU, and after the CPU knows a specific member port, the CPU deletes the member port from the aggregation link.
It can be seen that, in the related art, after the failure of the member link is detected, the CPU needs to be informed to perform processing, and then the member port is deleted from the aggregated link. However, a period of time elapses from the detection of a link disconnection to the deletion of a member port. During this time, the packets sent to the failed member link are discarded by the aggregated link routing, resulting in a large loss of packets from the member port corresponding to the failed member link.
Aiming at the problem that the time for processing the fault in the aggregation link group is long in the related art, no technical scheme is provided.
Disclosure of Invention
The embodiment of the invention provides a method and a device for processing an aggregation link, which are used for at least solving the problem that the time for processing faults in an aggregation link group is long in the related art.
According to an embodiment of the present invention, a method for processing an aggregated link is provided, including:
detecting link states of aggregation links in the aggregation link group through a switching chip;
and under the condition that the link state of the aggregation link is detected to be a fault state, the switching chip deletes the first port corresponding to the aggregation link from the aggregation link group.
Optionally, the deleting, by the switch chip, the first port corresponding to the aggregation link from the aggregation link group includes: determining a target location of the first port in the aggregation link group; deleting the first port corresponding to the target location from the aggregated link group.
Optionally, after deleting the first port corresponding to the target location from the aggregation link group, the method further includes: and updating the number of member ports in the aggregation link group.
Optionally, in a case that the first port is not the last port in the aggregation link group, after the first port corresponding to the target location is deleted from the aggregation link group, the method further includes: determining a second port corresponding to a second position in the aggregation link group, wherein the second port is located at the last position in the aggregation link group; writing the second port into the target location; deleting the second location in the aggregated link group and updating the number of member ports in the aggregated link group.
Optionally, after the switch chip deletes the first port corresponding to the aggregated link from the aggregated link group, the method further includes: and the switching chip sends an interrupt notification to the CPU, wherein the interrupt notification is used for indicating the CPU to update the soft table.
According to an embodiment of the present invention, there is provided a processing apparatus for aggregating links, including:
the detection module is used for detecting the link state of the aggregation link in the aggregation link group through the exchange chip;
a deleting module, configured to delete, by the switch chip, the first port corresponding to the aggregated link from the aggregated link group when it is detected that the link status of the aggregated link is a failure status.
Optionally, the deleting module is further configured to: determining a target location of the first port in the aggregation link group; deleting the first port corresponding to the target location from the aggregated link group.
Optionally, the apparatus further includes: and the updating module is used for updating the number of the member ports in the aggregation link group.
Optionally, the apparatus further includes: a determining module, configured to determine, when the first port is not a last port in the aggregation link group, a second port corresponding to a second location in the aggregation link group, where the second port is located at the last location in the aggregation link group; a write module to write the second port into the target location; and the processing module is used for deleting the second position in the aggregation link group and updating the number of the member ports in the aggregation link group.
Optionally, the apparatus further includes: a notification module, configured to send, by the switch chip, an interrupt notification to a CPU after the switch chip deletes the first port corresponding to the aggregated link from the aggregated link group, where the interrupt notification is used to instruct the CPU to update a soft table.
According to a further embodiment of the present invention, there is also provided a computer-readable storage medium having a computer program stored thereon, wherein the computer program is arranged to perform the steps of any of the above method embodiments when executed.
According to yet another embodiment of the present invention, there is also provided an electronic device, including a memory in which a computer program is stored and a processor configured to execute the computer program to perform the steps in any of the above method embodiments.
According to the invention, the link state of the aggregation link in the aggregation link group is detected through the exchange chip; and under the condition that the link state of the aggregation link is detected to be a fault state, the switching chip deletes the first port corresponding to the aggregation link from the aggregation link group. Therefore, the problem that the time required for processing the fault in the aggregation link group is long in the related art can be solved, the time for processing the fault of the aggregation link group is shortened, and the number of discarded messages of the aggregation link group is reduced.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
fig. 1 is a flow chart of a method of processing an aggregated link according to an embodiment of the invention;
fig. 2 is a schematic diagram of a processing method of an aggregated link according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a processing method of an aggregated link according to another embodiment of the present invention;
fig. 4 is a schematic diagram of a processing method of an aggregated link according to yet another embodiment of the present invention;
fig. 5 is a schematic diagram of a processing method of an aggregated link according to yet another embodiment of the present invention;
fig. 6 is a block diagram of a processing apparatus for aggregating links according to an embodiment of the present invention.
Detailed Description
The invention will be described in detail hereinafter with reference to the accompanying drawings in conjunction with embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
Example 1
The embodiment of the invention provides a processing method of an aggregation link. Fig. 1 is a flowchart of a processing method of an aggregated link according to an embodiment of the present invention, as shown in fig. 1, including:
step S102, detecting the link state of the aggregation link in the aggregation link group through an exchange chip;
step S104, when detecting that the link status of the aggregated link is a failure status, the switch chip deletes the first port corresponding to the aggregated link from the aggregated link group.
Optionally, the fault condition includes: an off state.
According to the invention, the link state of the aggregation link in the aggregation link group is detected through the exchange chip; and under the condition that the link state of the aggregation link is detected to be a fault state, the switching chip deletes the first port corresponding to the aggregation link from the aggregation link group. Therefore, the problem that the time required for processing the fault in the aggregation link group is long in the related art can be solved, the time for processing the fault of the aggregation link group is shortened, and the number of discarded messages of the aggregation link group is reduced.
As an optional implementation manner, the detecting that the link status of the aggregated link is a failure status includes: detecting a Linkdown event (i.e. a Linkdown message) of a member link in the aggregation link group. Fig. 2 is a schematic diagram of a processing method of an aggregated Link according to an embodiment of the present invention, as shown in fig. 2, an aggregated Link group is composed of 8 members, which are respectively a port #1 to a port #8, and after a Link corresponding to the port #3 is disconnected, a chip detects a Link Down event and immediately enters an aggregated Link protection processing flow in the chip.
It should be noted that, in the above embodiment, when the switch chip detects that the link status of the aggregated link is the failure status, the switch chip directly deletes the first port corresponding to the aggregated link from the aggregated link group, and does not need to delete the failure status after notifying a Central Processing Unit (CPU), so that the processing time of the failure is saved, the processing of the failure is accelerated, and the fast healing of the aggregated link is realized.
As an optional implementation manner, the deleting, by the switch chip, the first port corresponding to the aggregated link from the aggregated link group includes: determining a target location of the first port in the aggregation link group; deleting the first port corresponding to the target location from the aggregated link group. As shown in fig. 2, after the port #7 link is disconnected, the chip immediately enters the protection processing flow of the aggregated link in the chip, and since the port #7 is the last member of the link group, it is only necessary to reduce the number of the members of the aggregated link group by 1 to 6. Fig. 3 is a schematic diagram of a processing method of an aggregated link according to another embodiment of the present invention, after the above processing, the member distribution of the aggregated link becomes the distribution shown in fig. 3.
As an optional implementation manner, after deleting the first port corresponding to the target location from the aggregation link group, the method further includes: and updating the number of member ports in the aggregation link group.
As an optional implementation, in a case that the first port is not the last port in the aggregation link group, after the first port corresponding to the target location is deleted from the aggregation link group, the method further includes: determining a second port corresponding to a second position in the aggregation link group, wherein the second port is located at the last position in the aggregation link group; writing the second port into the target location; deleting the second location in the aggregated link group and updating the number of member ports in the aggregated link group.
It should be noted that, in the above embodiment, when the first port is not the last port in the aggregation link group, the last port in the aggregation link group is further written to the target location where the first port is located, and the last location in the aggregation link group is deleted, so that the update of the aggregation link group is implemented.
Fig. 4 is a schematic diagram of a processing method of an aggregated link according to still another embodiment of the present invention. As shown in fig. 4, the chip first finds the location of port #3, moves the last port #8 of the aggregation link group to the location of port #3, and changes the number of the aggregation link group members from 1 to 7, and the chip completes the process of removing the aggregation link from port # 3. Fig. 5 is a schematic diagram of a processing method of an aggregated link according to another embodiment of the present invention, after the above processing, the member distribution of the aggregated link becomes the distribution shown in fig. 5. After the chip executes the above steps, the CPU is notified in an interrupt manner, and then the CPU synchronizes the state of the soft table, for example, updates the state of the aggregation link maintained in the soft table.
As an optional implementation manner, after the switch chip deletes the first port corresponding to the aggregated link from the aggregated link group, the method further includes: and the switching chip sends an interrupt notification to the CPU, wherein the interrupt notification is used for indicating the CPU to update the soft table.
Illustratively, the soft table is stored in the CPU and is used for recording information related to the aggregation link group (e.g., the status of the member links in the aggregation link group, and the status of the member ports in the aggregation link group). As an optional implementation manner, the foregoing embodiment may be applied to an ethernet environment with a high requirement on data transmission real-time performance, such as a data center network and an industrial network. By the embodiment, delicate or nanosecond-level rapid healing can be realized, and after a member link in an aggregated link is disconnected (i.e., the aggregated link in the failure state in the embodiment), traffic sent to the member link does not drop packets or only drops a few messages.
Optionally, the switch chip may be an Application Specific Integrated Circuit (ASIC) chip, and may also be a Field Programmable Gate Array (FPGA) chip or a Network Processor (NPU) chip. As an optional implementation manner, the foregoing technical solution may be executed by an aggregation link protection processing module in a switch chip, where the aggregation link protection processing module is configured to execute the processing method of the aggregation link.
Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but the former is a better implementation mode in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present invention.
Example 2
According to another embodiment of the present invention, a processing apparatus for aggregating links is provided, which is used to implement the foregoing embodiments and preferred embodiments, and the description of which is already given is omitted. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. Although the means described in the embodiments below are preferably implemented in software, an implementation in hardware, or a combination of software and hardware is also possible and contemplated.
Fig. 6 is a block diagram of a processing apparatus for aggregating links according to an embodiment of the present invention, the apparatus including:
a detecting module 62, configured to detect, by a switch chip, a link state of an aggregation link in an aggregation link group;
a deleting module 64, configured to, when it is detected that the link status of the aggregated link is a failure status, delete, by the switch chip, the first port corresponding to the aggregated link from the aggregated link group.
According to the invention, the link state of the aggregation link in the aggregation link group is detected through the exchange chip; and under the condition that the link state of the aggregation link is detected to be a fault state, the switching chip deletes the first port corresponding to the aggregation link from the aggregation link group. Therefore, the problem that the time required for processing the fault in the aggregation link group is long in the related art can be solved, the time for processing the fault of the aggregation link group is shortened, and the number of discarded messages of the aggregation link group is reduced.
As an optional implementation manner, the deleting module 64 is further configured to: determining a target location of the first port in the aggregation link group; deleting the first port corresponding to the target location from the aggregated link group.
Optionally, the apparatus further includes: and the updating module is used for updating the number of the member ports in the aggregation link group.
Optionally, the apparatus further includes: a determining module, configured to determine, when the first port is not a last port in the aggregation link group, a second port corresponding to a second location in the aggregation link group, where the second port is located at the last location in the aggregation link group; a write module to write the second port into the target location; and the processing module is used for deleting the second position in the aggregation link group and updating the number of the member ports in the aggregation link group.
Optionally, the apparatus further includes: a notification module, configured to send, by the switch chip, an interrupt notification to a CPU after the switch chip deletes the first port corresponding to the aggregated link from the aggregated link group, where the interrupt notification is used to instruct the CPU to update a soft table.
It should be noted that, the above modules may be implemented by software or hardware, and for the latter, the following may be implemented, but not limited to: the modules are all positioned in the same processor; alternatively, the modules are respectively located in different processors in any combination.
Embodiments of the present invention also provide a computer-readable storage medium having a computer program stored thereon, wherein the computer program is arranged to perform the steps of any of the above-mentioned method embodiments when executed.
Optionally, in this embodiment, the computer-readable storage medium may include, but is not limited to: various media capable of storing computer programs, such as a usb disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.
Embodiments of the present invention also provide an electronic device comprising a memory having a computer program stored therein and a processor arranged to run the computer program to perform the steps of any of the above method embodiments.
Optionally, the electronic apparatus may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.
Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments and optional implementation manners, and this embodiment is not described herein again.
It will be apparent to those skilled in the art that the modules or steps of the present invention described above may be implemented by a general purpose computing device, they may be centralized on a single computing device or distributed across a network of multiple computing devices, and alternatively, they may be implemented by program code executable by a computing device, such that they may be stored in a storage device and executed by a computing device, and in some cases, the steps shown or described may be performed in an order different than that described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A method for processing an aggregated link, comprising:
detecting link states of aggregation links in the aggregation link group through a switching chip;
and under the condition that the link state of the aggregation link is detected to be a fault state, the switching chip deletes the first port corresponding to the aggregation link from the aggregation link group.
2. The method of claim 1, wherein the switch chip removing the first port corresponding to the aggregated link from the aggregated link group comprises:
determining a target location of the first port in the aggregation link group;
deleting the first port corresponding to the target location from the aggregated link group.
3. The method of claim 2, wherein after removing the first port corresponding to the target location from the aggregated link group, the method further comprises:
and updating the number of member ports in the aggregation link group.
4. The method of claim 2, wherein after removing the first port corresponding to the target location from the aggregated link group if the first port is not the last port in the aggregated link group, the method further comprises:
determining a second port corresponding to a second position in the aggregation link group, wherein the second port is located at the last position in the aggregation link group;
writing the second port into the target location;
deleting the second location in the aggregated link group and updating the number of member ports in the aggregated link group.
5. The method of claim 1, wherein after the switch chip removes the first port corresponding to the aggregated link from the aggregated link group, the method further comprises:
and the switching chip sends an interrupt notification to the CPU, wherein the interrupt notification is used for indicating the CPU to update the soft table.
6. A processing apparatus for aggregating links, comprising:
the detection module is used for detecting the link state of the aggregation link in the aggregation link group through the exchange chip;
a deleting module, configured to delete, by the switch chip, the first port corresponding to the aggregated link from the aggregated link group when it is detected that the link status of the aggregated link is a failure status.
7. The apparatus of claim 6, wherein the deletion module is further configured to:
determining a target location of the first port in the aggregation link group;
deleting the first port corresponding to the target location from the aggregated link group.
8. The apparatus of claim 7, further comprising:
and the updating module is used for updating the number of the member ports in the aggregation link group.
9. The apparatus of claim 7, further comprising:
a determining module, configured to determine, when the first port is not a last port in the aggregation link group, a second port corresponding to a second location in the aggregation link group, where the second port is located at the last location in the aggregation link group;
a write module to write the second port into the target location;
and the processing module is used for deleting the second position in the aggregation link group and updating the number of the member ports in the aggregation link group.
10. The apparatus of claim 6, further comprising:
a notification module, configured to send, by the switch chip, an interrupt notification to a CPU after the switch chip deletes the first port corresponding to the aggregated link from the aggregated link group, where the interrupt notification is used to instruct the CPU to update a soft table.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911252252.2A CN111131024A (en) | 2019-12-09 | 2019-12-09 | Processing method and device of aggregated link |
| PCT/CN2020/114059 WO2021114774A1 (en) | 2019-12-09 | 2020-09-08 | Method and device for processing aggregated link |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911252252.2A CN111131024A (en) | 2019-12-09 | 2019-12-09 | Processing method and device of aggregated link |
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| CN111131024A true CN111131024A (en) | 2020-05-08 |
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| CN112737945A (en) * | 2020-12-30 | 2021-04-30 | 杭州迪普信息技术有限公司 | Server connection control method and device |
| WO2021114774A1 (en) * | 2019-12-09 | 2021-06-17 | 盛科网络（苏州）有限公司 | Method and device for processing aggregated link |
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| WO2021114774A1 (en) | 2021-06-17 |
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