WO2021111818A1 - Dispositif d'imagerie à semi-conducteur et son procédé de fabrication - Google Patents

Dispositif d'imagerie à semi-conducteur et son procédé de fabrication Download PDF

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WO2021111818A1
WO2021111818A1 PCT/JP2020/041861 JP2020041861W WO2021111818A1 WO 2021111818 A1 WO2021111818 A1 WO 2021111818A1 JP 2020041861 W JP2020041861 W JP 2020041861W WO 2021111818 A1 WO2021111818 A1 WO 2021111818A1
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light
shielding portion
solid
shielding
unit
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PCT/JP2020/041861
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English (en)
Japanese (ja)
Inventor
成拓 池原
健太郎 秋山
吉田　慎一
雄基 川原
由宇 椎原
奈緒 吉本
勇樹 宮波
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ソニーセミコンダクタソリューションズ株式会社
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Publication of WO2021111818A1 publication Critical patent/WO2021111818A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures

Definitions

  • the present disclosure relates to a solid-state image sensor and a method for manufacturing the same.
  • a global shutter type back-illuminated solid-state image sensor has been developed in which a memory unit that holds the electric charge transferred from the photoelectric conversion unit is provided in the pixel separately from the floating diffusion layer.
  • a solid-state image sensor it has been proposed to provide a light-shielding portion in the vicinity thereof so that light does not enter the memory portion, or to form an element separation portion between pixels.
  • the first surface is the surface of the semiconductor substrate in the plane orientation (111), and the second light-shielding portion extends in the crystal orientation ⁇ 110> and may be provided in the space having the plane in the plane orientation (111).
  • the sixth light-shielding portion may be provided at a position closer to the first surface than the third light-shielding portion.
  • a photoelectric conversion unit is formed on a semiconductor substrate including a first surface substantially orthogonal to the thickness direction, and a charge holding unit is provided in the thickness direction with respect to the photoelectric conversion unit.
  • a transfer transistor is formed on the first surface of the semiconductor substrate to transfer charges from the photoelectric conversion unit to the charge holding unit, and the first light-shielding portion provided along the first surface is photoelectric.
  • a second light-shielding portion formed between the conversion portion and the charge holding portion and extending from the first surface to the second surface in the thickness direction is formed between a plurality of adjacent transfer transistors. Equipped.
  • FIG. 6A is a plan view showing an example of a manufacturing method following FIG. 6A.
  • FIG. 6B is a cross-sectional view showing an example of a manufacturing method following FIG. 6B.
  • FIG. 7B is a cross-sectional view showing an example of a manufacturing method following FIG. 7B.
  • FIG. 7A is a plan view showing an example of a manufacturing method following FIG. 7A.
  • FIG. 7C is a cross-sectional view showing an example of a manufacturing method following FIG. 7C.
  • FIG. 8B is a cross-sectional view showing an example of a manufacturing method following FIG. 8B.
  • FIG. 8A is a plan view showing an example of a manufacturing method following FIG. 8A.
  • FIG. 12 is a cross-sectional view showing an example of a manufacturing method following FIG.
  • FIG. 13A is a plan view showing an example of a manufacturing method following FIG. 13A.
  • FIG. 13B is a cross-sectional view showing an example of a manufacturing method following FIG. 13B.
  • FIG. 14B is a cross-sectional view showing an example of a manufacturing method following FIG. 14B.
  • FIG. 3 is a cross-sectional view of a part of the pixel region in the pixel array portion according to the third embodiment. Top view showing the horizontal part and the vertical part extracted for convenience.
  • FIG. 5 is a cross-sectional view of a part of a pixel region in the pixel array portion according to the fourth embodiment.
  • FIG. 5 is a cross-sectional view of a part of a pixel region in the pixel array portion according to the fifth embodiment.
  • FIG. 6 is a cross-sectional view of a part of a pixel region in the pixel array portion according to the sixth embodiment.
  • FIG. 5 is a cross-sectional view of a part of a pixel region in the pixel array portion according to the seventh embodiment.
  • FIG. 5 is a cross-sectional view of a part of a pixel region in the pixel array portion according to the eighth embodiment.
  • 9 is a cross-sectional view of a part of a pixel region in the pixel array unit according to the ninth embodiment.
  • FIG. 5 is a cross-sectional view showing a configuration example of a solid-state image sensor according to a modified example.
  • FIG. 5 is a cross-sectional view showing a configuration example of a solid-state image sensor according to a modified example.
  • the figure which shows the specific example of the plane shape of the horizontal shading part The figure which shows the specific example of the plane shape of the horizontal shading part.
  • the figure which shows the specific example of the plane shape of the horizontal shading part The figure which shows the specific example of the plane shape of the horizontal shading part.
  • the figure which shows the specific example of the plane shape of the horizontal shading part The schematic diagram explaining the back bond in the crystal plane of the Si substrate of this disclosure.
  • FIG. 1 is a block diagram showing a configuration example of a function of the solid-state image sensor 101 according to the first embodiment of the present technology.
  • a photoelectric conversion unit such as a photodiode that receives light from a subject and converts it into an electric signal has a light receiving surface on which light from the subject is incident and wiring such as a transistor that drives each pixel.
  • wiring such as a transistor that drives each pixel.
  • the pixel array unit 111 has a plurality of pixels 121 including a photoelectric conversion element that generates and stores electric charges according to the amount of light incident from the subject. As shown in FIG. 1, the pixels 121 are arranged in the horizontal direction (row direction) and the vertical direction (column direction), respectively. In the pixel array unit 111, pixel drive lines 122 are wired along the row direction for each pixel row consisting of pixels 121 arranged in a row in the row direction. Further, a vertical signal line 123 is wired along the column direction for each pixel row consisting of pixels 121 arranged in a row in the row direction.
  • the lamp wave module 113 generates a lamp wave signal used for A / D (Analog / Digital) conversion of a pixel signal and supplies it to the column signal processing unit 114.
  • the column signal processing unit 114 is composed of, for example, a shift register, an address decoder, or the like, and performs noise removal processing, correlation double sampling processing, A / D conversion processing, and the like to generate a pixel signal.
  • the column signal processing unit 114 supplies the generated pixel signal to the signal processing unit 119.
  • the signal processing unit 119 performs signal processing such as arithmetic processing on the pixel signal supplied from the column signal processing unit 114 while temporarily storing data in the data storage unit 116 as necessary, and each pixel signal. Outputs an image signal consisting of.
  • FIG. 2 is an equivalent circuit diagram of the sensor pixel 121 and the readout circuit 120.
  • FIG. 3 is a plan layout view of a part of the pixel region in the pixel array unit 111.
  • FIG. 3 shows a planar layout of a pixel region having 2 pixels in the X direction and 4 pixels in the Y direction.
  • FIG. 4 is a cross-sectional view taken along the line AA of FIG.
  • the read circuit 120 has four transfer transistors TRZ, TRY, TRX, TRG, an emission transistor OFG, a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. These transistors are N-type MOS transistors. Since the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are formed and bonded to a semiconductor substrate different from the semiconductor substrate 11 on which the pixel array unit 111 is arranged, these transistors are clearly shown in the planar layout of FIG. It has not been.
  • the amplification transistor AMP has a gate electrode connected to a floating diffusion FD and a drain connected to a power supply line VDD, and serves as an input unit of a source follower circuit that reads out the electric charge obtained by photoelectric conversion in the photodiode PD. That is, the amplification transistor AMP constitutes a constant current source and a source follower circuit connected to one end of the vertical signal line VSL by connecting the source to the vertical signal line VSL via the selection transistor SEL.
  • the selection transistor SEL is connected between the source of the amplification transistor AMP and the vertical signal line VSL, and a control signal is supplied as a selection signal to the gate electrode of the selection transistor SEL.
  • the control signal is turned on, the selection transistor SEL is in a conductive state, and the sensor pixel 121 connected to the selection transistor SEL is in a selection state.
  • the sensor pixel 121 is in the selected state, the pixel signal output from the amplification transistor AMP is read out to the column signal processing circuit 22 via the vertical signal line VSL.
  • FIG. 4 is a cross-sectional view taken along the line AA of FIG.
  • the symbols "P" and “N” in the figure represent a P-type semiconductor region and an N-type semiconductor region, respectively. Further, “P ++", “P +”, “P -”, and “P -” at the end of the "+” or in the symbol “-” are all represent the impurity concentration of the P-type semiconductor region There is. Similarly, “N ++”, “N +", “N -”, and “N -” “+” at the end of each symbol or "-” are all represent the impurity concentration of the N-type semiconductor region ing. Here, the larger the number of "+”, the higher the impurity concentration, and the larger the number of "-”, the lower the impurity concentration. This also applies to the subsequent drawings.
  • a P + type semiconductor region having a higher P-type impurity concentration than the P-type semiconductor region 51C may be provided between the N-type semiconductor region and the P-type semiconductor region 51C.
  • the layer structure of the photoelectric conversion unit 51 formed in the semiconductor substrate 11 is not necessarily limited to that shown in FIG.
  • a fixed charge film 15 is provided between the photoelectric conversion unit 51 and the back surface 11B.
  • the fixed charge film 15 is provided along the back surface 11B of the semiconductor substrate 11.
  • the fixed charge film 15 has a negative fixed charge in order to suppress the generation of dark current due to the interface state of the back surface 11B, which is the light receiving surface of the semiconductor substrate 11.
  • the electric field induced by the fixed charge film 15 forms a hole storage layer in the vicinity of the back surface 11B of the semiconductor substrate 11.
  • the hole accumulation layer suppresses the generation of electrons from the back surface 11B.
  • the horizontal light-shielding portion 12H is provided between the photoelectric conversion unit 51 and the MEM 54 so as to spread along the surface 11A (XY surface) as the first surface.
  • the vertical light-shielding portion 12V is provided so as to spread along the YZ plane so as to be substantially orthogonal to the horizontal light-shielding portion 12H.
  • the light incident from the back surface 11B side and transmitted through the photoelectric conversion unit 51 without being absorbed by the photoelectric conversion unit 51 is reflected by the horizontal light-shielding portion 12H of the light-shielding portion 12 and is incident on the photoelectric conversion unit 51 again. .. That is, the horizontal light-shielding portion 12H of the light-shielding portion 12 functions as a reflector, and functions so as to suppress the light transmitted through the photoelectric conversion unit 51 from entering the MEM 54 and generating noise. As a result, the horizontal light-shielding portion 12H can suppress PLS (Parasitic Light Sensitivity). Further, the vertical light-shielding portion 12V of the light-shielding portion 12 can suppress noise such as color mixing (that is, crosstalk) by incident light leaked from the adjacent pixel 121 onto the photoelectric conversion unit 51.
  • PLS Physical Light Sensitivity
  • the inner layer portion 12A may be made of graphite or an organic material.
  • the outer layer portion 12B is made of an insulating material such as SiOx (silicon oxide). The outer layer portion 12B ensures electrical insulation between the inner layer portion 12A and the semiconductor substrate 11.
  • the etching stoppers 17 are provided at both ends of the horizontal light-shielding portions 12H and 13H in the X direction on the surface 11A. Further, the etching stopper 17 is provided on the surface 11A between the TRZ 52 and the horizontal light-shielding portions 12H and 13H.
  • the etching stopper 17 has a function of stopping the progress of etching when the lateral trenches (spaces 12Z and 13Z) of the horizontal light-shielding portions 12H and 13H are formed by wet etching.
  • the etching stopper 17 is made of a material having etching resistance to an etching solution of the semiconductor substrate 11, for example, an alkaline aqueous solution.
  • the transfer transistor TRZ has a horizontal gate electrode 52H arranged in the horizontal plane direction of the semiconductor substrate 11 and a vertical gate electrode 52V extending in the depth direction of the semiconductor substrate 11.
  • the deepest position of the vertical gate electrode 52V is, for example, in the N - type semiconductor region 52A.
  • each sensor pixel 121 has two vertical gate electrodes 52V, but the number of vertical gate electrodes 52V is not limited and may be one or a plurality.
  • the transfer transistor TRZ transfers the electric charge photoelectrically converted by the photoelectric conversion unit 51 to the transfer electrode TRY via the vertical gate electrode 52V.
  • each transistor in the readout circuit 120 is not necessarily limited to that shown in FIG. If the arrangement of each transistor in the readout circuit 120 is changed, the arrangement location of the photodiode PD and the charge holding unit (MEM) 54 arranged below the transistor is also changed.
  • MEM charge holding unit
  • trenches 12T and 13T are formed in the formation region of the vertical shading portions 12V and 13V by using the lithography technique and the etching technique.
  • a hard mask HM that opens the formation region of the vertical light-shielding portion 12V is formed, and the surface 11A of the semiconductor substrate 11 is etched by the RIE method using the hard mask HM as a mask.
  • trenches 12T and 13T can be formed.
  • the trenches 12T and 13T are alternately provided between the adjacent sensor pixels 121 and continuously extend in the Y direction.
  • the semiconductor substrate 11 is somewhat etched in the ⁇ 111> direction as well. Therefore, it is preferable that the depths of the trenches 12T and 13T are set in consideration of etching in the ⁇ 111> direction.
  • the etching rate of the semiconductor substrate 11 differs depending on the plane orientation (111) of the surface 11A, crystal anisotropic etching is performed.
  • the etching rate in the ⁇ 110> direction is sufficiently higher than the etching rate in the ⁇ 111> direction. Therefore, when wet etching is performed using an alkaline aqueous solution, the etching proceeds in the X direction, while the etching hardly proceeds in the Y direction and the Z direction.
  • FIG. 7D the spaces 12Z and 13Z communicating with the trenches 12T and 13T spread in the X direction inside the semiconductor substrate 11.
  • the outer layer portions 12B and 13B are deposited on the inner surfaces of the trenches 12T and 13T and the spaces 12Z and 13Z and on the surface 11A of the semiconductor substrate 11.
  • an insulating material such as a silicon oxide film is used.
  • the outer layer portions 12B and 13B do not completely embed the trenches 12T and 13T and the spaces 12Z and 13Z.
  • a vertical gate electrode 52V is formed in the region A52.
  • the horizontal light-shielding portions 12H and 13H are provided in, for example, a silicon substrate having a surface 11A having a plane orientation (111).
  • the horizontal light-shielding portions 12H and 13H can be easily formed by crystal anisotropic etching using an etching solution such as an alkaline aqueous solution.
  • the etching stopper 17 is provided between the TRZ 52 and the MEM 53 and between the adjacent vertical gate electrodes 52V, and the spaces 12Z and 13Z for forming the horizontal light-shielding portions 12H and 13H are formed up to the etching stopper 17. Will be done.
  • the horizontal light-shielding portions 12H and 13H can be easily formed with high dimensional accuracy.
  • each transistor for example, TRZ52
  • each sensor pixel 121 due to the presence of the horizontal light-shielding portion 12H, it is possible to prevent the influence of the electric field generated in each transistor (for example, TRZ52) in each sensor pixel 121 from affecting the photoelectric conversion unit 51. That is, it is possible to suppress the dark current generated by the electric field of each transistor from flowing into the photoelectric conversion unit 51, and to suppress the generation of noise.
  • the material of the inner layer portion 12A may be embedded in the trenches 12T, 13T and the spaces 12Z, 13Z following the formation of the outer layer portion 12B without using the sacrificial film SAC.
  • FIG. 11A is a plan layout view of a part of the pixel region in the pixel array unit 111 according to the second embodiment.
  • FIG. 11B is a cross-sectional view taken along the line AA of FIG. 11A.
  • the second embodiment is different from the first embodiment in that the element separating portion 13 includes the horizontal light-shielding portion 13Ha at a position different in height (depth) from the horizontal light-shielding portion 13H.
  • Other configurations of the second embodiment may be the same as the corresponding configurations of the first embodiment.
  • the gap 13G is provided between the vertical light-shielding portion 13Vt and the horizontal light-shielding portion 13Ha or the vertical light-shielding portion 13Vb.
  • the element separation portion 13 is provided so as to penetrate the semiconductor substrate 11 from the front surface 11A to the back surface 11B. Therefore, the element separation unit 13 can suppress crosstalk between adjacent pixels.
  • Other configurations of the third embodiment may be the same as the corresponding configurations of the first embodiment. Therefore, the third embodiment can also obtain the effects of the first and second embodiments.
  • the end portion of the horizontal portion 20H extends in the X direction so as to overlap the end portion of the horizontal light-shielding portion 13Ha. That is, although the horizontal portions 20H and 13Ha are not connected, they are provided alternately in the X direction. As a result, it is possible to prevent the incident light from directly entering the TRZ52 side while ensuring a charge passage between the horizontal light-shielding portion 13Ha and the horizontal portion 20H.
  • (Modification example) 28 to 33 are modified examples of the ninth to fourteenth embodiments, respectively.
  • the height relationship between the horizontal portion 13H and the horizontal portion 20H is opposite to that of the ninth embodiment. Therefore, the horizontal portion 13H is provided at a position closer to the surface 11A than the horizontal portion 20H.
  • the effect of the modified example shown in FIG. 28 is the same as the effect of the ninth embodiment.
  • the side surfaces of the light-shielding portion 12 and the vertical portions 12V, 13V, 20V of the element separation portions 13 and 20 may have a taper.
  • FIG. 34A is a plan view of a part of the pixel region in the pixel array unit 111 according to the fifteenth embodiment.
  • FIG. 34B is a cross-sectional view taken along the line BB of FIG. 34A.
  • FIG. 34C is a cross-sectional view taken along the line CC of FIG. 34A.
  • the two sensor pixels 121 adjacent to each other in the X direction and the Y direction are mirror-inverted, and the TRZ 52s of the four sensor pixels 121 sharing the cross point XP are unevenly distributed in the vicinity of the cross point XP. doing.
  • the charge transfer unit 50 of each sensor pixel 121 is arranged in the same planar layout as the photodiode PD, the element separation units 13d, 13d_1, and 13d_2 penetrating the semiconductor substrate 11 separate each sensor pixel 121. can do. As a result, crosstalk and blooming can be suppressed even better.
  • FIG. 36 is a plan view schematically showing the configuration of pixels 121A and 121B according to the 17th embodiment.
  • FIG. 37A is a cross-sectional view taken along the line AA of FIG. 36.
  • FIG. 37B is a cross-sectional view taken along the line BB of FIG. 36.
  • the configurations of the element separation units 13 and 20 will be described in more detail.
  • FIG. 36 shows the plane of the semiconductor substrate 11 as seen from the back surface 11B side.
  • the element separation units 13 and 20 are provided between a plurality of pixels and electrically or optically separate the plurality of pixels.
  • the element separating portion 13 is composed of a substantially rhombic horizontal portion 13H and a vertical portion 13V provided in the diagonal direction (Y direction) of the horizontal portion 13H, as in the above embodiment.
  • the element separating portion 20 as an isolation portion does not have a horizontal portion and is composed of only a vertical portion.
  • the transfer transistor TRZ52 is provided at each of the four corners of the cross point XP between the element separation portions 13 and 20, and is shielded from light by the horizontal portion 13H (see FIGS. 37A and 37B). ..
  • the element separation units 13 and 20 are separated without being overlapped or connected.
  • the vertical portion 13V is extended in the Y direction, is separated from the element separating portion 20 extending in the Y direction, and is also separated from the element separating portion 20 extending in the X direction. ..
  • the element separating portion 13 is composed of an inner layer portion 13A and an outer layer portion 13B.
  • the inner layer portion 13A is made of a light-shielding material, and may be at least one of a simple substance metal, a metal alloy, a metal nitride, and a metal silicide.
  • the constituent materials of the inner layer portion 13A include Al (aluminum), Ag (silver), Cu (copper), Co (cobalt), W (tungsten), Ti (titanium), Ta (tantalum), Ni (nickel), and Mo. Examples thereof include (molybdenum), Cr (chromium), Ir (iridium), platinum iridium, TiN (titanium nitride), and tungsten silicon compounds.
  • Al (aluminum) is the most optically preferable constituent material.
  • the inner layer portion 13A may be made of graphite or an organic material.
  • FIG. 38A is a graph showing the extinction coefficient of tungsten as an example of the material of the inner layer portion 13A.
  • FIG. 38B is a graph showing the extinction coefficient of the silicon oxide film as an example of the material of the outer layer portion 13B.
  • the extinction coefficient of the outer layer portion 13B is lower than that of the inner layer portion 13A. Therefore, the outer layer portion 13B does not absorb the incident light so much, but the inner layer portion 13A absorbs the incident light, so that the element separating portion 13 has a light-shielding property.
  • FIG. 39A is a graph showing the refractive index of a silicon single crystal as an example of the semiconductor substrate 11.
  • FIG. 39B is a graph showing the refractive index of the silicon oxide film as an example of the material of the outer layer portion 13B.
  • silicon is used as the semiconductor substrate 11 and a silicon oxide film is used as the outer layer portion 13B of the element separating portion 13 and the element separating portion 20, the semiconductor substrate is formed at the interface between the element separating portion 13 or the element separating portion 20 and the semiconductor substrate 11.
  • the incident light from 11 is easily reflected.
  • the refractive index of silicon is 3.9 and the refractive index of the silicon oxide film is 1.46 with respect to the incident light having a wavelength of 633 nm. In this case, the refraction angle of the incident light from the semiconductor substrate 11 to the element separation unit 13 or the element separation unit 20 becomes larger than the incident angle, and total reflection is likely to occur.
  • the element separation portion 13 By covering the inner layer portion 13A with the outer layer portion 13B, the electrical insulation between the inner layer portion 13A and the semiconductor substrate 11 is ensured. Further, since the outer layer portion 13B has a lower refractive index than the semiconductor substrate 11 and a light extinction coefficient K lower than that of the inner layer portion 13A, the element separation portion 13 emits incident light at the interface between the outer layer portion 13B and the semiconductor substrate 11. Can be reflected. Thereby, the photoelectric conversion efficiency QE can be improved. Further, since the inner layer portion 13A has a relatively high light extinction coefficient K and has a light-shielding property, the element separation portion 13 does not transmit the incident light even if the outer layer portion 13B is a transparent material. Therefore, the vertical portion 13V can suppress crosstalk between pixels, and the horizontal portion 13H can suppress the ingress of noise into the transfer transistor TRZ52.
  • the element separating portion 20 does not include the material of the inner layer portion 13A, but is composed only of the material of the outer layer portion 13B. That is, the element separating portion 20 is made of a material having a refractive index lower than that of the semiconductor substrate 11 and a light extinction coefficient K lower than that of the inner layer portion 13A.
  • the element separation unit 20 is made of a transparent insulating material, and reflects the incident light at the interface between the element separation unit 20 and the semiconductor substrate 11 without significantly extinguishing the incident light. As a result, the element separation unit 20 can further improve the photoelectric conversion efficiency QE while suppressing crosstalk between pixels.
  • the material of the element separating portion 20 may be the same material as the outer layer portion 13B, but may be another material different from the outer layer portion 13B as long as it has the above characteristics.
  • the first width W13 in the direction perpendicular to the stretching direction (that is, the Y direction) of the vertical portion 13V is the stretching direction (that is, Y) of the element separating portion 20. It is wider than the second width W20 in the direction perpendicular to the direction).
  • the element separating portion 20 is formed only of the material of the outer layer portion 13B, while the element separating portion 13 is formed by using both the outer layer portion 13B and the inner layer portion 13A. Therefore, when the film thickness of the outer layer portion 13B is x and the film thickness of the inner layer portion 13A is y, the first width W13 is preferably larger than 2x and smaller than 2x + 2y.
  • the second width W20 is preferably smaller than 2x.
  • the width (thickness) of the inner layer portion 13A in the Z direction may be larger than 2x + 2y.
  • the BB cross section of FIG. 37B includes a cross point XP.
  • the semiconductor substrate 11 remains between the element separating portion 20 and the vertical portion 13V, and the element separating portion 20 is separated from the vertical portion 13V of the element separating portion 13. .
  • the element separating portion 20 is in contact with the outer layer portion 13B of the horizontal portion 13H of the element separating portion 13. This is because the element separation unit 13 functions as an etching stopper for the element separation unit 20 in the manufacturing process of the element separation units 13 and 20.
  • FIGS. 41A and 41B the trench 20T is formed in the formation region of the element separation portion 20 by using the lithography technique and the etching technique.
  • FIG. 41A shows a cross section taken along line AA of FIG. 41C.
  • FIG. 41B shows a cross section taken along line BB of FIG. 41C.
  • the width W20 of the trench 20T is formed narrower than the width W13 of the trench 13T.
  • the trench 20T is formed between pixels other than the trench 13T.
  • the cross point XP is covered with the resist PR, and the sacrificial film 13S of the trench 13T is left behind.
  • the other region of the trench 20T is etched.
  • the sacrificial film 13S in the space 13Z functions as an etching stopper.
  • the sacrificial membrane 13S is removed after the resist PR is removed.
  • the material of the outer layer portion 13B is formed into the trenches 13T, 20T and the space 13Z.
  • the material of the outer layer portion 13B is deposited so as to fill the trench 20T without filling the trench 13T and the space 13Z.
  • the deposited film thickness x of the material of the outer layer portion 13B is less than half of the width W13 of FIG. 37A and more than half of the width W20.
  • the outer layer portion 13B is formed in the trench 13T and the space 13Z, and the trench 20T is filled with the material of the outer layer portion 13B to form the element separation portion 20.
  • FIG. 47 is a cross-sectional view showing a configuration example of a solid-state image sensor according to a modified example.
  • the N-type impurity concentration has a concentration gradient in the photoelectric conversion unit 51.
  • the concentration gradient of the N-type impurity is opposite between the lower side and the upper side of the horizontal portion 13H. That is, below the horizontal portion 13H, the N-type impurity concentration increases in the direction away from TRZ52 (+ X direction), and above the horizontal portion 13H, toward the direction approaching TRZ52 (-X direction). It's getting higher. This is because it is necessary to bypass the horizontal portion 13H in order for the electric charge to move to the TRZ 52.
  • the space 13Z in FIGS. 14A and 14B for forming the horizontal light-shielding portion 13Ha is used for crystal anisotropic etching utilizing the property that the etching rate differs depending on the plane orientation of Si ⁇ 111 ⁇ . It was explained that it is formed.
  • the Si ⁇ 111 ⁇ substrate in the present disclosure is a substrate or wafer made of a silicon single crystal and having a crystal plane represented by ⁇ 111 ⁇ in the notation of the Miller index.
  • the Si ⁇ 111 ⁇ substrate in the present disclosure also includes a substrate or wafer whose crystal orientation is deviated by several degrees, for example, a substrate or wafer deviated by several degrees from the ⁇ 111 ⁇ plane in the closest [110] direction. Further, it also includes a silicon single crystal grown on a part or the entire surface of these substrates or wafers by an epitaxial method or the like.
  • the ⁇ 110> direction in the description of the present invention is the [110] direction, the [101] direction, the [011] direction, the [-110] direction, and [1-10], which are crystal plane directions equivalent to each other in terms of symmetry.
  • Direction, [-101] direction, [10-1] direction, [0-11] direction, [01-1] direction, [-1-10] direction, [-10-1] direction and [0-1- 1] It is a general term for directions, and may be read as either.
  • etching is performed in a direction orthogonal to the element forming surface and a direction further orthogonal to the direction orthogonal to the element forming surface (that is, a direction parallel to the element forming surface).
  • the case where the etching proceeds in the X-axis direction but does not proceed in the Y-axis direction and the Z-axis direction is illustrated by using the Si ⁇ 111 ⁇ substrate.
  • the present disclosure is not limited to this, and it is sufficient that the etching progress direction is in both the X-axis direction and the Y-axis direction, or in either the X-axis direction or the Y-axis direction.
  • the horizontal shading portion has one or two Si backbonds, at least less than three, in a direction substantially horizontal to the substrate surface, whereas three Si backbonds are formed substantially perpendicular to the substrate surface.
  • the back bond represents a bond extending in the negative direction on the opposite side with respect to the normal of the Si ⁇ 111 ⁇ plane, where the Si unbonded hand side is the positive direction. ..
  • the in-vehicle information detection unit 12040 detects the in-vehicle information.
  • a driver state detection unit 12041 that detects the driver's state is connected to the in-vehicle information detection unit 12040.
  • the driver state detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 determines the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether the driver is dozing.
  • the audio image output unit 12052 transmits an output signal of at least one of audio and an image to an output device capable of visually or audibly notifying information to the passenger or the outside of the vehicle.
  • an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices.
  • the display unit 12062 may include, for example, at least one of an onboard display and a heads-up display.
  • the imaging units 12101, 12102, 12103, 12104, 12105 are provided at positions such as, for example, the front nose, side mirrors, rear bumpers, back doors, and the upper part of the windshield in the vehicle interior of the vehicle 12100.
  • the imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the upper part of the windshield in the vehicle interior mainly acquire an image in front of the vehicle 12100.
  • the imaging units 12102 and 12103 provided in the side mirrors mainly acquire images of the side of the vehicle 12100.
  • the imaging unit 12104 provided on the rear bumper or the back door mainly acquires an image of the rear of the vehicle 12100.
  • the imaging unit 12105 provided on the upper part of the windshield in the vehicle interior is mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.
  • the present technology may also have the following configurations.
  • a semiconductor substrate including a first surface that is substantially orthogonal to the thickness direction,
  • a photoelectric conversion unit provided on the semiconductor substrate and generating an electric charge according to the amount of incident light from the second surface of the semiconductor substrate on the side opposite to the first surface by photoelectric conversion.
  • a charge holding unit arranged in the thickness direction with respect to the photoelectric conversion unit and holding the charge transferred from the photoelectric conversion unit, and a charge holding unit.
  • a transfer transistor that transfers the electric charge generated by the photoelectric conversion unit from the photoelectric conversion unit to the charge holding unit, and A first light-shielding portion located between the photoelectric conversion unit and the charge holding unit and provided along the first surface
  • a solid-state image pickup device including a second light-shielding portion provided between a plurality of adjacent transfer transistors and extending from the first surface to the second surface in the thickness direction.
  • the solid-state image sensor according to any one of (1) 1 to (13), wherein the sixth light-shielding portion is provided at a position closer to the second surface than the third light-shielding portion.
  • a third light-shielding portion extending along the first surface between the photoelectric conversion unit and the transfer transistor and connected to the second light-shielding portion, An isolation portion extending from the second surface toward the first surface and provided at a position facing the first light-shielding portion is further provided. On the second surface, the first width in the direction perpendicular to the stretching direction of the second light-shielding portion is wider than the second width in the direction perpendicular to the stretching direction of the isolation portion, from (1).
  • the solid-state imaging device according to any one of (15).
  • the second and third light-shielding portions are an inner layer portion made of a light-shielding material and an outer layer portion made of a material that covers the inner layer portion and has a lower refractive index than the semiconductor substrate and a lower light extinction coefficient than the inner layer portion. Consists of The solid-state imaging device according to (16), wherein the isolation unit is composed of the outer layer portion without including the inner layer portion. (18) The solid-state image sensor according to (17), wherein the first width is larger than twice the film thickness of the outer layer portion, and the second width is smaller than twice the film thickness of the outer layer portion. (19) The solid-state image sensor according to any one of (1) 6 to (18), wherein the second light-shielding portion and the isolation portion are separated on the second surface.
  • a photoelectric conversion unit is formed on a semiconductor substrate including a first surface substantially orthogonal to the thickness direction, and a charge holding unit is provided in the thickness direction with respect to the photoelectric conversion unit.
  • a transfer transistor is formed on the first surface of the semiconductor substrate to transfer charges from the photoelectric conversion unit to the charge holding unit, and the first light-shielding portion provided along the first surface is photoelectric.
  • a second light-shielding portion formed between the conversion portion and the charge holding portion and extending from the first surface to the second surface in the thickness direction is formed between a plurality of adjacent transfer transistors. Equipped.
  • 101 solid-state imaging device 121A, 121B pixels, 11 semiconductor substrate, 51 photoelectric conversion unit, 52 TRZ, 54 MEM, 55 TRG, 57 OFG, 12 light-shielding part, 12H horizontal light-shielding part, 12V vertical light-shielding part, 13 element separation part, 14 P-type semiconductor region, 15 fixed charge film, 17 etching stopper

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

Le problème décrit par la présente invention est de fournir un dispositif d'imagerie à semi-conducteur capable de supprimer le bruit dû à l'incidence de la lumière sur une unité de mémoire, et une diaphonie entre des pixels adjacents. La solution selon la présente invention porte sur un dispositif d'imagerie à semi-conducteur qui est pourvu : d'un substrat semi-conducteur ayant une première surface sensiblement orthogonale à une direction d'épaisseur; d'un convertisseur photoélectrique qui est disposé sur le substrat semi-conducteur et génère, par conversion photoélectrique, des charges correspondant à la quantité de lumière incidente provenant d'une seconde surface du substrat semi-conducteur à l'opposé de la première surface; d'un support de charge qui est disposé dans la direction de l'épaisseur par rapport au convertisseur photoélectrique et qui maintient des charges transférées à partir du convertisseur photoélectrique; d'un transistor de transfert qui transfère les charges générées par le convertisseur photoélectrique du convertisseur photoélectrique au support de charge; d'une première partie de protection contre la lumière positionnée entre le convertisseur photoélectrique et le support de charge et disposée le long de la première surface; et d'une seconde partie de protection contre la lumière qui est disposée entre une pluralité de transistors de transfert adjacents les uns aux autres et qui s'étend de la première surface vers la seconde surface dans la direction de l'épaisseur.　
PCT/JP2020/041861 2019-12-05 2020-11-10 Dispositif d'imagerie à semi-conducteur et son procédé de fabrication WO2021111818A1 (fr)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010226005A (ja) * 2009-03-25 2010-10-07 Seiko Epson Corp 光電変換装置
JP2013098446A (ja) * 2011-11-04 2013-05-20 Sony Corp 固体撮像素子、固体撮像素子の製造方法、及び、電子機器
JP2016027663A (ja) * 2015-09-24 2016-02-18 キヤノン株式会社 固体撮像装置、それを用いた撮像システム及び固体撮像装置の製造方法
JP2018205685A (ja) * 2017-06-07 2018-12-27 凸版印刷株式会社 固体撮像素子の製造方法およびナノインプリントリソグラフィー用原版

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010226005A (ja) * 2009-03-25 2010-10-07 Seiko Epson Corp 光電変換装置
JP2013098446A (ja) * 2011-11-04 2013-05-20 Sony Corp 固体撮像素子、固体撮像素子の製造方法、及び、電子機器
JP2016027663A (ja) * 2015-09-24 2016-02-18 キヤノン株式会社 固体撮像装置、それを用いた撮像システム及び固体撮像装置の製造方法
JP2018205685A (ja) * 2017-06-07 2018-12-27 凸版印刷株式会社 固体撮像素子の製造方法およびナノインプリントリソグラフィー用原版

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