WO2021111572A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
WO2021111572A1
WO2021111572A1 PCT/JP2019/047531 JP2019047531W WO2021111572A1 WO 2021111572 A1 WO2021111572 A1 WO 2021111572A1 JP 2019047531 W JP2019047531 W JP 2019047531W WO 2021111572 A1 WO2021111572 A1 WO 2021111572A1
Authority
WO
WIPO (PCT)
Prior art keywords
current detection
circuit
value
wire
semiconductor device
Prior art date
Application number
PCT/JP2019/047531
Other languages
French (fr)
Japanese (ja)
Inventor
高田　潤一
中村　浩章
利浩 中野
Original Assignee
サンケン電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by サンケン電気株式会社 filed Critical サンケン電気株式会社
Priority to JP2021562274A priority Critical patent/JPWO2021111572A1/ja
Priority to PCT/JP2019/047531 priority patent/WO2021111572A1/en
Publication of WO2021111572A1 publication Critical patent/WO2021111572A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements

Definitions

  • the present invention relates to a semiconductor device having an IC chip built-in and connecting a pad on the IC chip side and an external terminal (lead) with a bonding wire.
  • connection between the pad on the IC chip side and the external terminal for the purpose of improving electrical reliability, the plurality of pads on the IC chip side and the same external terminal are connected by bonding wires (hereinafter, simply referred to as wires). Technology is used.
  • Patent Document 1 there is a problem that when a plurality of wires are struck in order to secure a current capacity such as a large current output, a defect cannot be detected because the functions are the same. Further, in Patent Document 2, since the wire open of a large current output is detected by the difference in drive capacity, it is difficult to detect it in actual operation.
  • the present invention has been made in view of the above problems, and provides a semiconductor device capable of detecting a wire open of a wire in which a plurality of pads having the same function and the same external terminal are connected to each other even during actual operation.
  • the purpose is to do.
  • the semiconductor device of the present invention is a semiconductor device in which a plurality of pads to which the same function is assigned on the IC chip side and an external terminal of the function are connected by a plurality of bonding wires, and a current flowing through the bonding wires. It is characterized by including a detection circuit for detecting each of the above and a comparison circuit for detecting a disconnection of the bonding wire and outputting an error signal by comparing the current detection values detected by the detection circuit.
  • the present invention it is possible to detect the wire open of the bonding wire in which a plurality of pads having the same function and the same external terminal are connected to each other by changing the current detection value even during actual operation.
  • FIG. 1 It is a figure which shows the example of the power supply circuit which used the embodiment of the semiconductor device which concerns on this invention. It is a figure which shows the connection example of the bonding wire of the semiconductor device shown in FIG. It is a circuit diagram which shows the structural sequence of the semiconductor device shown in FIG. It is a waveform diagram of the semiconductor device shown in FIG. It is a waveform diagram at the time of light load of the semiconductor device shown in FIG. It is a circuit diagram which shows the other structural row of the semiconductor device shown in FIG.
  • the semiconductor device 1 of the present embodiment is a power supply IC including at least a power input terminal Vin, a ground terminal GND, and an output terminal SW as external terminals, referring to FIG.
  • the power supply circuit shown in FIG. 1 is a step-down DC-DC converter in which an inductor L and an output capacitor C are connected in series between the power input terminal Vin and the ground terminal GND of the semiconductor device 1.
  • the semiconductor device 1 complementarily controls the built-in power element M1 of the upper arm and the power element M2 of the lower arm to turn on and off to chop the input voltage input to the power input terminal Vin and output terminal SW.
  • the desired output voltage is supplied to the load LOAD connected in parallel with the output capacitor C.
  • the semiconductor device 1 has an IC chip 2 built-in, and a pad on the IC chip 2 side and an external terminal (lead) are connected by a bonding wire (hereinafter referred to as a wire 3).
  • a wire 3 a bonding wire
  • the power input terminal Vin, the ground terminal GND, and the output terminal SW have a large current and are connected by a plurality of wires 3.
  • FIG. 2A is an example in which a plurality of wires 3 are connected to the same external terminal
  • FIG. 2B is an example in which the external terminals are individual and are connected on a substrate. ..
  • the power elements of the large current output stage are divided into a plurality of power elements.
  • the power element M1 of the upper arm is divided into power elements M1_1 and M1-2
  • the power element M2 of the lower arm is divided into power elements M2_1 and M2_2, respectively.
  • the disconnection (wire open) of the wire 3 is detected by detecting the current flowing through the power elements M1_1, M1-2, M2_1, M2_2, and the like.
  • the IC chip 2 incorporates four power elements M1_1, M1-2, M2_1, and M2_2 composed of n-channel type or p-channel type MOSFETs, and bonds flowing through the four power elements M1_1, M1-2, M2_1, and M2_2.
  • Detection circuits 41, 42, 43, 44 that detect the current of the wire, respectively
  • comparison circuits 51, 52, 53, 54 that compare the current detection values detected by the detection circuits 41, 42, 43, 44 with the threshold value, respectively.
  • a latch circuit 6 for latching the comparison result by the comparison circuits 51, 52, 53, 54 and a control circuit 7 for on / off control of the power elements M1-1, M1-2, M2_1, and M2_2 are provided.
  • the IC chip 2 includes three pads PIN1 , PIN2 , and PIN3 connected to the same power input terminal Vin, and the same power input terminal Vin and the pads PIN1 , PIN2 , and PIN3 are wires 3. They are connected by IN1 , 3 IN2 , and 3 IN3, respectively. Further, the IC chip 2 includes two pads P SW1 and P SW2 connected to the same output terminal SW, and the same output terminal SW and pads P SW1 and P SW2 are connected by wires 3 SW1 and 3 SW2 , respectively. It is connected.
  • IC chip 2 three pads P G1 to be connected to the same ground terminal GND, P G2, it comprises a P G3, the same ground terminal GND and the pad P G1, P G2, P G3 and the wire 3 They are connected by G1 , 3, G2 , and 3 G3, respectively.
  • FIG. 3 shows an example in which a plurality of wires 3 are connected to one external terminal, the external terminals are individual and may be connected on a substrate. That is, the same external terminal may be a plurality of external terminals electrically connected to the same potential.
  • a series circuit including the power element M1_1 and the power element M2_1 and a series circuit including the power element M1-2 and the power element M2_2 are connected in parallel between the input voltage and the ground.
  • Pad P IN1 to the source of the power element M1_1, pads P IN2 are respectively connected through the respective detection circuits 41 and 43 to the source of the power device M1_2. That is, the plurality of pads P IN1 and pads P IN2 and the power input terminal Vin are assigned the same functions as the power input to the power elements (power element M1_1, power element M1-2). Further, the pad P IN 3 is connected to the power input terminal of the control circuit 7.
  • the pad P SW1 is connected to the connection point between the drain of the power element M1_1 and the drain of the power element M2_1, and the pad P SW2 is connected to the connection point between the drain of the power element M1_2 and the drain of the power element M2_2. That is, the same function of output is assigned to the plurality of pads P SW1 and pads P SW2 and the output terminal SW.
  • the pad P G1 is connected to the source of the power element M2_1, and the pad P G2 is connected to the source of the power element M2_1 through detection circuits 42 and 44, respectively. That is, a plurality of pads P G1 and the pad P G2, the and the ground terminal GND, and the power element (power device M2_1, power element M2_2) have the same functions are assigned say ground. Further, the pad PG3 is connected to the ground terminal of the control circuit 7.
  • the control circuit 7 drives the power element M1_1 and the power element M1-2 on and off by the same first control signal, and the power element M2_1 and the power element M2_2 are complementary signals sandwiching the first control signal and the dead time. 2 Drives on and off by a control signal.
  • Detection circuit 41 the current value between the source pad P IN1 and the power element M1_1, detected as a current detection value I D1_1.
  • Detection circuit 43 the current value between the source pad P IN2 and the power element M1_2, detected as a current detection value I D1_2.
  • Detection circuit 42 the current value between the pad P G1 and the source of the power element M2_1, detected as a current detection value I D2_1.
  • Detection circuit 44 the current value between the pad P G2 and the source of the power element M2_2, detected as a current detection value I D2_2.
  • the current detection values ID1_1 , ID1_2 , ID2_1 , and ID2_1 may be detected by using a sense MOS or the like.
  • the comparison circuit 51 compares the current detection value I D1-1 detected by the detection circuit 41 with the threshold value I th, and outputs an error signal to the latch circuit 6 when the current detection value I D1_1 exceeds the threshold value I th.
  • Comparator circuit 52 compares the current detection value I D2_1 and the threshold -I th detected by the detection circuit 42, the current detection value I D2_1 is below the threshold -I th, and outputs an error signal to the latch circuit 6 .
  • the comparison circuit 53 compares the current detection value I D1-2 detected by the detection circuit 43 with the threshold value I th, and outputs an error signal to the latch circuit 6 when the current detection value I D1-2 exceeds the threshold value I th.
  • Comparator circuit 54 compares the current detection value I D2_2 and the threshold -I th detected by the detection circuit 44, the current detection value I D2_2 is below the threshold -I th, and outputs an error signal to the latch circuit 6 ..
  • FIG. 4 is a waveform diagram of the current detection values ID1_1 , ID1_2 , ID2_1 , and ID2_1 , where (a) is normal, (b) is wire 3 IN1 disconnection (wire open), and (c). ) Indicates the time when the wire 3 G1 is broken, and (d) indicates the time when the wire 3 SW1 is broken.
  • the peak value of the total current between the power input terminal Vin and the IC chip 2 that is, the wires 3 IN1 and 3IN2 (hereinafter referred to as the total peak value) is Io
  • the power input As for the current between the terminal Vin and the IC chip 2 since the currents of the power elements M1_1 and M1-2 are dispersed by the wires 3 IN1 and 3 IN2 , it can be seen that the peak values of the respective peaks are Io / 2.
  • the current between the ground terminal GND and the IC chip 2 is the wire 3 G1 , 3 G2. Since the currents of the power elements M2_1 and M2_2 are dispersed by the above, it can be seen that the peak values of the respective power elements are ⁇ Io / 2.
  • the power element M1_1 When the wire 3 IN1 is disconnected, the power element M1_1 is disconnected from the power input terminal Vin, as shown in FIG. 4 (b), with the current detection value I D1_1 becomes zero, the peak value of the current detection value I D1_2 It becomes the total peak value Io between the power input terminal Vin and the IC chip 2.
  • the change in the peak value of the current detection value I D1-2 is detected by the comparison circuit 53. That is, the comparison circuit 53 compares the current detection value I D1-2 detected by the detection circuit 43 with the threshold value I th set to be smaller than the total peak value Io and larger than 1/2 of the total peak value Io. , the current detection value I D1_2 exceeds the threshold value I th, and outputs an error signal to the latch circuit 6.
  • the power element M2_1 When the wire 3 G1 is disconnected, the power element M2_1 is disconnected from the ground terminal GND, and as shown in FIG. 4C, the current detection value I D2_1 becomes zero and the peak value of the current detection value I D2_2 becomes ground.
  • the total peak value between the terminal GND and the IC chip 2 is -Io.
  • the peak value change of the current detection value ID2_2 is detected by the comparison circuit 54.
  • the power element M2_2 When the wire 3 G2 is disconnected, the power element M2_2 is disconnected from the ground terminal GND, the current detection value I D2_2 becomes zero, and the peak value of the current detection value I D2_1 is the ground terminal GND and the IC chip 2. Since the total peak value between them is -Io, an error signal is output from the comparison circuit 52 to the latch circuit 6.
  • the power element M1-1 and the power element M2_1 are disconnected from the output terminal SW, and as shown in FIG. 4D , the current detection value I D1-1 and the current detection value I D2_1 become zero, and the current detection value I D2_1 becomes zero.
  • the peak value of the current detection value I D1-2 is the total peak value Io between the power input terminal Vin and the IC chip 2
  • the peak value of the current detection value I D2_2 is the total peak value between the ground terminal GND and the IC chip 2. -Io.
  • the latch circuit 6 has a function of latching the error signals from the comparison circuits 51 to 54 so that they can be referred to by an external device in a state of being distinguished from each other. Thereby, the disconnection point of the wire 3 can be determined based on the latch state of the latch circuit 6. That is, when the error signal only from the comparison circuit 51 is latched, the wire 3 IN2 is disconnected, and when the error signal only from the comparison circuit 52 is latched, the wire 3 G2 is disconnected and only from the comparison circuit 53. When the error signal is latched, it can be determined that the wire 3 IN1 is disconnected, and when the error signal only from the comparison circuit 54 is latched, it can be determined that the wire 3 G1 is disconnected.
  • the wire 3 SW2 is disconnected, and when the error signals from the comparison circuit 53 and the comparison circuit 54 are latched, the wire 3 SW1 is disconnected. Each can be judged. Further, when the operation is stopped in the state where the error signal is not latched, it can be determined that either or both of the wire 3 IN3 and the wire 3 G3 are disconnected.
  • the threshold value I th is set to a value smaller than the total peak value Io and larger than 1 / n of the total peak value Io
  • the threshold value- Th is larger than the total peak value-Io and the total peak value-Io. It is set to a value smaller than 1 / n of.
  • the threshold values I th and -I th may be preset values, but if they are configured to be linearly or stepwise changed according to output changes (changes in total peak values Io and -Io). , It becomes possible to detect the disconnection more accurately.
  • the voltage between the power input terminal Vin and the output terminal SW and the voltage between the output terminal SW and the ground terminal GND are monitored to monitor the wire 3 It is also possible to detect the disconnection of. In this case, when the power elements M1_1, M1-2, M2_1, and M2_2 are off, it is necessary to mask them.
  • the current detection value I D1_1 detected respectively by the detection circuits 41 ⁇ 44, I D1_2, I D2_1, I D2_2 may be used in other functions, such as overcurrent protection (OCP), for other functions
  • OCP overcurrent protection
  • the current detection values ID1_1 , ID1_2 , ID2_1 , and ID2_2 detected in 1 may be used.
  • the peak values of the current detection values ID1-1 , ID1-2 , ID2_1, and ID2_2 decrease. Therefore, even if the peak value is doubled, it is difficult to set the threshold values I th and -I th that can detect the current change when the heavy load is normally disconnected and when the light load is disconnected. .. Therefore, by comparing the current detection values I D1_1, I D1-2 , I D2_1 , and I D2_1 with each other, it is possible to configure the wire 3 to be detectable.
  • the current detection value I D1_1 and the current detection value I D1_2 are compared, and the current detection value I D1-1 and the current detection value I D1_2 are compared.
  • DOO compares a comparison circuit 55 for outputting a different a mismatch signal V E1 than the allowable amount as an error signal, and a current detection value I D2_1 and the current detection value I D2_2, the current detection value I D2_1 and the current detection value I D2_2
  • the comparison circuit 56 that outputs the mismatch signal VE2 as an error signal when the difference is more than the allowable amount, and the latch circuit 6a that latches the mismatch signal VE1 and the mismatch signal VE2 so that they can be referred to from an external device while being distinguished from each other. And are provided.
  • mismatch signal V E1 is outputted from the comparator circuit 55. Even if the wire 3 IN2 is disconnected, similarly, since the current detection value I D1_1 and the current detection value I D1_2 different, mismatch signal V E1 is outputted from the comparator circuit 55. Therefore, in the state where the mismatch signal VE1 only from the comparison circuit 55 is latched, it can be determined that either the wire 3 IN1 or the wire 3 IN2 is broken.
  • mismatch signal V E2 is output from the comparator circuit 56. Even if the wire 3 G2 is disconnected, similarly, since the current detection value I D2_1 and the current detection value I D2_2 different, mismatch signal V E2 is output from the comparator circuit 56. Therefore, in the state where the mismatch signal VE2 only from the comparison circuit 56 is latched, it can be determined that either the wire 3 G1 or the wire 3 G2 is broken.
  • the power input terminal Vin (or ground terminal GND) which is the same external terminal as the pad P of the same function on the IC chip 2 side connected to the power element M of the output stage.
  • Detect circuits 41, 43 (or 42, 44 or 41) that detect the current detection values I D1_1 , I D1-2 (or I D2_1 , I D2_2 or I D1_1 , I D1-2 , I D2_1 , I D2_2 ) flowing through the SW2), respectively.
  • the current detection values ID1_1 and ID1_2 detected by the detection circuits 41 and 43 are compared with the threshold value to disconnect the wires 3 IN1 , 3 IN2 (or 3 G1 , 3 G2 or 3 SW1 , 3 SW2 ). It is provided with comparison circuits 51 and 53 (or 52, 54 or 51 to 54) that detect the above and output an error signal.
  • the comparison circuit 51 and 53, detecting circuits 41 and 43 a plurality of power elements M1_1 detected by the respective current detection value I D1_1 flowing M1_2, and I D1_2 and the threshold I th To do.
  • the comparison circuit 55 (or 56) has the current detection values I D1-1 and I flowing through the plurality of power elements M1_1 and M1_2 detected by the detection circuits 41 and 43 (or 42 and 44), respectively.
  • D1-2 (or current detection values I D2_1 and I D2_2 flowing through a plurality of power elements M2_1 and M2_2) are compared with each other. With this configuration, even when the current detection values ID1_1 and ID1_2 peak values are low under a light load, disconnection can be detected by mutual current changes.
  • the detection circuits 41 to 44 and the comparison circuits 51 to 56 are provided for each different function, and a latch circuit that latches the error signals from the detection circuits 41 to 44 so that they can be referred to from a distinct external device. 6 and 6a are provided. With this configuration, the disconnection point can be grasped from the external device after the operation is stopped according to the latch state of the latch circuits 6 and 6a.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The present invention can, even when in operation, use a change in detected current values (ID1_1), (ID1_2) to detect a wire opening in wires (3IN1), (3IN2) respectively connected to the same external terminal and to a plurality of pads having the same function.　The present invention comprises: a plurality of pads (PIN1), (PIN2); a plurality of power elements (M1_1), (M1_2) respectively connected to the plurality of pads (PIN1), (PIN2); detection circuits (41), (43) respectively detecting the detected current values (ID1_1), (ID1_2) for a current flowing through the plurality of power elements (M1_1), (M1_2); and comparison circuits (51), (53) using a comparison of the detected current values (ID1_1), (ID1_2) that were detected by the detection circuits (41), (43) to detect a disconnect in the wires (3IN1), (3IN2) and output an error signal.

Description

半導体装置Semiconductor device
　本発明は、ＩＣチップを内蔵し、ＩＣチップ側のパッドと外部端子（リード）とをボンディングワイヤで接続した半導体装置に関する。 The present invention relates to a semiconductor device having an IC chip built-in and connecting a pad on the IC chip side and an external terminal (lead) with a bonding wire.
　ＩＣチップ側のパッドと外部端子との接続において、電気的信頼性の向上を目的とし、ＩＣチップ側の複数のパッドと同一の外部端子とをそれぞれボンディングワイヤ（以下、単にワイヤと称す）によって接続する技術が用いられている。 In the connection between the pad on the IC chip side and the external terminal, for the purpose of improving electrical reliability, the plurality of pads on the IC chip side and the same external terminal are connected by bonding wires (hereinafter, simply referred to as wires). Technology is used.
　このように、同一の外部端子に複数本のワイヤを打つ際、ＩＣチップ上のメタル配線によって、複数のパッドをそれぞれ独立した機能し、ワイヤーオープン時に特定の機能が停止することで不具合を検出する技術が提案されている（例えば、特許文献１参照）。 In this way, when multiple wires are struck on the same external terminal, the metal wiring on the IC chip causes the multiple pads to function independently, and when the wire is opened, a specific function is stopped to detect a defect. A technique has been proposed (see, for example, Patent Document 1).
　また、ダイオードを接続することで、ワイヤーオープン時の正常時と不具合時の特性差異を検出して、不具合品をリジェクトする技術が提案されている（例えば、特許文献２参照）。 Further, a technique has been proposed in which a defective product is rejected by detecting a characteristic difference between a normal state and a defective product when the wire is opened by connecting a diode (see, for example, Patent Document 2).
特開昭６３－５２４５８号公報Japanese Unexamined Patent Publication No. 63-52458 特開２００５－９３５６７号公報Japanese Unexamined Patent Publication No. 2005-93567
　しかしながら、特許文献１では、大電流の出力など、電流容量を確保するために複数本のワイヤを打つ場合、同一の機能であるため、不具合を検出することはできないという問題点があった。また、特許文献２では、大電流の出力のワイヤーオープンは、ドライブ能力の差異で検出するため、実働時に検出することは困難である。 However, in Patent Document 1, there is a problem that when a plurality of wires are struck in order to secure a current capacity such as a large current output, a defect cannot be detected because the functions are the same. Further, in Patent Document 2, since the wire open of a large current output is detected by the difference in drive capacity, it is difficult to detect it in actual operation.
　本発明は、上記課題に鑑みてなされたものであり、同一機能の複数のパッドと同一の外部端子とがそれぞれ接続されたワイヤのワイヤーオープンを、実働時でも検出することができる半導体装置を提供することを目的とする。 The present invention has been made in view of the above problems, and provides a semiconductor device capable of detecting a wire open of a wire in which a plurality of pads having the same function and the same external terminal are connected to each other even during actual operation. The purpose is to do.
　本発明の半導体装置は、ＩＣチップ側の同一の機能が割り当てられた複数のパッドと、前記機能の外部端子とを複数本のボンディングワイヤによって接続した半導体装置であって、前記ボンディングワイヤを流れる電流をそれぞれ検出する検出回路と、前記検出回路によって検出された電流検出値の比較によって、前記ボンディングワイヤの断線を検出してエラー信号を出力する比較回路と、を具備することを特徴とする。 The semiconductor device of the present invention is a semiconductor device in which a plurality of pads to which the same function is assigned on the IC chip side and an external terminal of the function are connected by a plurality of bonding wires, and a current flowing through the bonding wires. It is characterized by including a detection circuit for detecting each of the above and a comparison circuit for detecting a disconnection of the bonding wire and outputting an error signal by comparing the current detection values detected by the detection circuit.
　本発明によれば、実働時でも電流検出値の変化によって、同一機能の複数のパッドと同一の外部端子とがそれぞれ接続されたボンディングワイヤのワイヤーオープンを検出することができるという効果を奏する。 According to the present invention, it is possible to detect the wire open of the bonding wire in which a plurality of pads having the same function and the same external terminal are connected to each other by changing the current detection value even during actual operation.
本発明に係る半導体装置の実施の形態を使用した電源回路例を示す図である。It is a figure which shows the example of the power supply circuit which used the embodiment of the semiconductor device which concerns on this invention. 図１に示す半導体装置のボンディングワイヤの接続例を示す図である。It is a figure which shows the connection example of the bonding wire of the semiconductor device shown in FIG. 図１に示す半導体装置の構成列を示す回路図である。It is a circuit diagram which shows the structural sequence of the semiconductor device shown in FIG. 図１に示す半導体装置の波形図である。It is a waveform diagram of the semiconductor device shown in FIG. 図１に示す半導体装置の軽負荷時の波形図である。It is a waveform diagram at the time of light load of the semiconductor device shown in FIG. 図１に示す半導体装置の他の構成列を示す回路図である。It is a circuit diagram which shows the other structural row of the semiconductor device shown in FIG.
　以下に、本発明の好適な実施の形態を添付図面に基づいて説明する。なお、以下に説明する本実施形態は、特許請求の範囲に記載された本発明の内容を不当に限定するものではなく、本実施形態で説明される構成の全てが本発明の解決手段として必須であるとは限らない。 Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. The present embodiment described below does not unreasonably limit the content of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as a means for solving the present invention. Is not always the case.
　本実施の形態の半導体装置１は、図１を参照すると、電源入力端子Ｖｉｎと、グラウンド端子ＧＮＤと、出力端子ＳＷとを外部端子として少なくとも備えた電源ＩＣである。図１に示す電源回路は、半導体装置１の電源入力端子Ｖｉｎとグラウンド端子ＧＮＤとの間にインダクタＬと出力コンデンサＣとが直列に接続された降圧型ＤＣ－ＤＣコンバータである。半導体装置１は、内蔵された上アームのパワー素子Ｍ１と、下アームのパワー素子Ｍ２とを相補的にオンオフ制御することで、電源入力端子Ｖｉｎに入力される入力電圧をチョッピングして出力端子ＳＷから出力し、所望の出力電圧を出力コンデンサＣと並列に接続された負荷ＬＯＡＤに供給する。 The semiconductor device 1 of the present embodiment is a power supply IC including at least a power input terminal Vin, a ground terminal GND, and an output terminal SW as external terminals, referring to FIG. The power supply circuit shown in FIG. 1 is a step-down DC-DC converter in which an inductor L and an output capacitor C are connected in series between the power input terminal Vin and the ground terminal GND of the semiconductor device 1. The semiconductor device 1 complementarily controls the built-in power element M1 of the upper arm and the power element M2 of the lower arm to turn on and off to chop the input voltage input to the power input terminal Vin and output terminal SW. The desired output voltage is supplied to the load LOAD connected in parallel with the output capacitor C.
　半導体装置１は、図２に示すように、ＩＣチップ２を内蔵し、ＩＣチップ２側のパッドと外部端子（リード）とがボンディングワイヤ（以下、ワイヤ３と称す）で接続される。図２に示す例では、電源入力端子Ｖｉｎ、グラウンド端子ＧＮＤ及び出力端子ＳＷが大電流であり、複数本のワイヤ３で接続されている。なお、図２（ａ）は、同一の外部端子に複数本のワイヤ３が接続された例であり、図２（ｂ）は、外部端子は個別であり、基板上で接続される例となる。 As shown in FIG. 2, the semiconductor device 1 has an IC chip 2 built-in, and a pad on the IC chip 2 side and an external terminal (lead) are connected by a bonding wire (hereinafter referred to as a wire 3). In the example shown in FIG. 2, the power input terminal Vin, the ground terminal GND, and the output terminal SW have a large current and are connected by a plurality of wires 3. Note that FIG. 2A is an example in which a plurality of wires 3 are connected to the same external terminal, and FIG. 2B is an example in which the external terminals are individual and are connected on a substrate. ..
　半導体装置１（ＩＣチップ２）は、図３を参照すると、大電流出力段のパワー素子が複数に分けられている。図３に示す例では、上アームのパワー素子Ｍ１がパワー素子Ｍ１＿１、Ｍ１＿２に、下アームのパワー素子Ｍ２がパワー素子Ｍ２＿１、Ｍ２＿２にそれぞれ分けられている。そして、パワー素子Ｍ１＿１、Ｍ１＿２、Ｍ２＿１、Ｍ２＿２に流れる電流等を検出することで、ワイヤ３の断線（ワイヤオープン）を検出する。 In the semiconductor device 1 (IC chip 2), referring to FIG. 3, the power elements of the large current output stage are divided into a plurality of power elements. In the example shown in FIG. 3, the power element M1 of the upper arm is divided into power elements M1_1 and M1-2, and the power element M2 of the lower arm is divided into power elements M2_1 and M2_2, respectively. Then, the disconnection (wire open) of the wire 3 is detected by detecting the current flowing through the power elements M1_1, M1-2, M2_1, M2_2, and the like.
　ＩＣチップ２は、ｎチャネル型、又はｐチャンネル型のＭＯＳＦＥＴで構成された４個のパワー素子Ｍ１＿１、Ｍ１＿２、Ｍ２＿１、Ｍ２＿２を内蔵し、４個のパワー素子Ｍ１＿１、Ｍ１＿２、Ｍ２＿１、Ｍ２＿２を流れるボンディングワイヤの電流をそれぞれ検出する検出回路４１、４２、４３、４４と、検出回路４１、４２、４３、４４によってそれぞれ検出された電流検出値を閾値と比較する比較回路５１、５２、５３、５４と、比較回路５１、５２、５３、５４による比較結果をラッチするラッチ回路６と、パワー素子Ｍ１＿１、Ｍ１＿２、Ｍ２＿１、Ｍ２＿２をオンオフ制御する制御回路７と、を備えている。 The IC chip 2 incorporates four power elements M1_1, M1-2, M2_1, and M2_2 composed of n-channel type or p-channel type MOSFETs, and bonds flowing through the four power elements M1_1, M1-2, M2_1, and M2_2. Detection circuits 41, 42, 43, 44 that detect the current of the wire, respectively, and comparison circuits 51, 52, 53, 54 that compare the current detection values detected by the detection circuits 41, 42, 43, 44 with the threshold value, respectively. A latch circuit 6 for latching the comparison result by the comparison circuits 51, 52, 53, 54 and a control circuit 7 for on / off control of the power elements M1-1, M1-2, M2_1, and M2_2 are provided.
　ＩＣチップ２は、同一の電源入力端子Ｖｉｎと接続される３個のパッドＰＩＮ１、ＰＩＮ２、ＰＩＮ３を備え、同一の電源入力端子ＶｉｎとパッドＰＩＮ１、ＰＩＮ２、ＰＩＮ３とがワイヤ３ＩＮ１、３ＩＮ２、３ＩＮ３によってそれぞれ接続されている。また、ＩＣチップ２は、同一の出力端子ＳＷと接続される２個のパッドＰＳＷ１、ＰＳＷ２を備え、同一の出力端子ＳＷとパッドＰＳＷ１、ＰＳＷ２とがワイヤ３ＳＷ１、３ＳＷ２によってそれぞれ接続されている。さらに、ＩＣチップ２は、同一のグラウンド端子ＧＮＤと接続される３個のパッドＰＧ１、ＰＧ２、ＰＧ３を備え、同一のグラウンド端子ＧＮＤとパッドＰＧ１、ＰＧ２、ＰＧ３とがワイヤ３Ｇ１、３Ｇ２、３Ｇ３によってそれぞれ接続されている。なお、図３では、１つの外部端子に複数本のワイヤ３が接続された例を示したが、外部端子は個別であり、基板上で接続されていても良い。すなわち、同一の外部端子は、同電位に電気的に接続された複数の外部端子であっても良い。 The IC chip 2 includes three pads PIN1 , PIN2 , and PIN3 connected to the same power input terminal Vin, and the same power input terminal Vin and the pads PIN1 , PIN2 , and PIN3 are wires 3. They are connected by IN1 , 3 IN2 , and 3 IN3, respectively. Further, the IC chip 2 includes two pads P SW1 and P SW2 connected to the same output terminal SW, and the same output terminal SW and pads P SW1 and P SW2 are connected by wires 3 SW1 and 3 SW2 , respectively. It is connected. Furthermore, IC chip 2, three pads P G1 to be connected to the same ground terminal GND, P G2, it comprises a P G3, the same ground terminal GND and the pad P G1, P G2, P G3 and the wire 3 They are connected by G1 , 3, G2 , and 3 G3, respectively. Although FIG. 3 shows an example in which a plurality of wires 3 are connected to one external terminal, the external terminals are individual and may be connected on a substrate. That is, the same external terminal may be a plurality of external terminals electrically connected to the same potential.
　パワー素子Ｍ１＿１と、パワー素子Ｍ２＿１とからなる直列回路と、パワー素子Ｍ１＿２と、パワー素子Ｍ２＿２とからなる直列回路とが、入力電圧とグラウンドとの間に並列に接続されている。 A series circuit including the power element M1_1 and the power element M2_1 and a series circuit including the power element M1-2 and the power element M2_2 are connected in parallel between the input voltage and the ground.
　パッドＰＩＮ１はパワー素子Ｍ１＿１のソースに、パッドＰＩＮ２はパワー素子Ｍ１＿２のソースにそれぞれ検出回路４１、４３を通してそれぞれ接続されている。すなわち、複数のパッドＰＩＮ１及びパッドＰＩＮ２と、電源入力端子Ｖｉｎとには、パワー素子（パワー素子Ｍ１＿１、パワー素子Ｍ１＿２）への電源入力というと同一の機能が割り当てられている。また、パッドＰＩＮ３は制御回路７の電源入力端子に接続されている。 Pad P IN1 to the source of the power element M1_1, pads P IN2 are respectively connected through the respective detection circuits 41 and 43 to the source of the power device M1_2. That is, the plurality of pads P IN1 and pads P IN2 and the power input terminal Vin are assigned the same functions as the power input to the power elements (power element M1_1, power element M1-2). Further, the pad P IN 3 is connected to the power input terminal of the control circuit 7.
　パワー素子Ｍ１＿１のドレインとパワー素子Ｍ２＿１のドレインとの接続点にパッドＰＳＷ１が、パワー素子Ｍ１＿２のドレインとパワー素子Ｍ２＿２のドレインとの接続点にパッドＰＳＷ２がそれぞれ接続されている。すなわち、複数のパッドＰＳＷ１及びパッドＰＳＷ２と、出力端子ＳＷとには、出力という同一の機能が割り当てられている。 The pad P SW1 is connected to the connection point between the drain of the power element M1_1 and the drain of the power element M2_1, and the pad P SW2 is connected to the connection point between the drain of the power element M1_2 and the drain of the power element M2_2. That is, the same function of output is assigned to the plurality of pads P SW1 and pads P SW2 and the output terminal SW.
　パッドＰＧ１はパワー素子Ｍ２＿１のソースに、パッドＰＧ２はパワー素子Ｍ２＿２のソースにそれぞれ検出回路４２、４４を通してそれぞれ接続されている。すなわち、複数のパッドＰＧ１及びパッドＰＧ２と、グラウンド端子ＧＮＤとには、パワー素子（パワー素子Ｍ２＿１、パワー素子Ｍ２＿２）のグラウンドというと同一の機能が割り当てられている。また、パッドＰＧ３は制御回路７のグラウンド端子に接続されている。 The pad P G1 is connected to the source of the power element M2_1, and the pad P G2 is connected to the source of the power element M2_1 through detection circuits 42 and 44, respectively. That is, a plurality of pads P G1 and the pad P G2, the and the ground terminal GND, and the power element (power device M2_1, power element M2_2) have the same functions are assigned say ground. Further, the pad PG3 is connected to the ground terminal of the control circuit 7.
　制御回路７は、パワー素子Ｍ１＿１とパワー素子Ｍ１＿２とを同一の第１制御信号によってオンオフ駆動すると共に、パワー素子Ｍ２＿１とパワー素子Ｍ２＿２とを第１制御信号とデッドタイムを挟んだ相補信号である第２制御信号によってオンオフ駆動する。 The control circuit 7 drives the power element M1_1 and the power element M1-2 on and off by the same first control signal, and the power element M2_1 and the power element M2_2 are complementary signals sandwiching the first control signal and the dead time. 2 Drives on and off by a control signal.
　検出回路４１は、パッドＰＩＮ１とパワー素子Ｍ１＿１のソースとの間の電流値を、電流検出値ＩＤ１＿１として検出する。検出回路４３は、パッドＰＩＮ２とパワー素子Ｍ１＿２のソースとの間の電流値を、電流検出値ＩＤ１＿２として検出する。検出回路４２は、パッドＰＧ１とパワー素子Ｍ２＿１のソースとの間の電流値を、電流検出値ＩＤ２＿１として検出する。検出回路４４は、パッドＰＧ２とパワー素子Ｍ２＿２のソースとの間の電流値を、電流検出値ＩＤ２＿２として検出する。なお、電流検出値ＩＤ１＿１、ＩＤ１＿２、ＩＤ２＿１、ＩＤ２＿２は、センスＭＯＳ等も使用して検出するようにしても良い。 Detection circuit 41, the current value between the source pad P IN1 and the power element M1_1, detected as a current detection value I D1_1. Detection circuit 43, the current value between the source pad P IN2 and the power element M1_2, detected as a current detection value I D1_2. Detection circuit 42, the current value between the pad P G1 and the source of the power element M2_1, detected as a current detection value I D2_1. Detection circuit 44, the current value between the pad P G2 and the source of the power element M2_2, detected as a current detection value I D2_2. The current detection values ID1_1 , ID1_2 , ID2_1 , and ID2_1 may be detected by using a sense MOS or the like.
　比較回路５１は、検出回路４１によって検出された電流検出値ＩＤ１＿１と閾値Ｉｔｈとを比較し、電流検出値ＩＤ１＿１が閾値Ｉｔｈを上回ると、エラー信号をラッチ回路６に出力する。比較回路５２は、検出回路４２によって検出された電流検出値ＩＤ２＿１と閾値－Ｉｔｈとを比較し、電流検出値ＩＤ２＿１が閾値－Ｉｔｈを下回ると、エラー信号をラッチ回路６に出力する。比較回路５３は、検出回路４３によって検出された電流検出値ＩＤ１＿２と閾値Ｉｔｈとを比較し、電流検出値ＩＤ１＿２が閾値Ｉｔｈを上回ると、エラー信号をラッチ回路６に出力する。比較回路５４は、検出回路４４によって検出された電流検出値ＩＤ２＿２と閾値－Ｉｔｈとを比較し、電流検出値ＩＤ２＿２が閾値－Ｉｔｈを下回ると、エラー信号をラッチ回路６に出力する。 The comparison circuit 51 compares the current detection value I D1-1 detected by the detection circuit 41 with the threshold value I th, and outputs an error signal to the latch circuit 6 when the current detection value I D1_1 exceeds the threshold value I th. Comparator circuit 52 compares the current detection value I D2_1 and the threshold -I th detected by the detection circuit 42, the current detection value I D2_1 is below the threshold -I th, and outputs an error signal to the latch circuit 6 .. The comparison circuit 53 compares the current detection value I D1-2 detected by the detection circuit 43 with the threshold value I th, and outputs an error signal to the latch circuit 6 when the current detection value I D1-2 exceeds the threshold value I th. Comparator circuit 54 compares the current detection value I D2_2 and the threshold -I th detected by the detection circuit 44, the current detection value I D2_2 is below the threshold -I th, and outputs an error signal to the latch circuit 6 ..
　図４は、電流検出値ＩＤ１＿１、ＩＤ１＿２、ＩＤ２＿１、ＩＤ２＿２の波形図であり、（ａ）は正常時を、（ｂ）はワイヤ３ＩＮ１の断線（ワイヤオープン）時を、（ｃ）はワイヤ３Ｇ１の断線時を、（ｄ）はワイヤ３ＳＷ１の断線時をそれぞれ示している。 FIG. 4 is a waveform diagram of the current detection values ID1_1 , ID1_2 , ID2_1 , and ID2_1 , where (a) is normal, (b) is wire 3 IN1 disconnection (wire open), and (c). ) Indicates the time when the wire 3 G1 is broken, and (d) indicates the time when the wire 3 SW1 is broken.
　図４（ａ）を参照すると、電源入力端子ＶｉｎとＩＣチップ２との間、すなわちワイヤ３ＩＮ１、３ＩＮ２の合計電流のピーク値（以下、合計ピーク値と称す）をＩｏとすると、電源入力端子ＶｉｎとＩＣチップ２との間の電流は、ワイヤ３ＩＮ１、３ＩＮ２によってパワー素子Ｍ１＿１、Ｍ１＿２の電流が分散されるため、それぞれのピーク値がＩｏ／２になることが分かる。また、グラウンド端子ＧＮＤとＩＣチップ２との間、すなわちワイヤ３Ｇ１、３Ｇ２の合計ピーク値を－Ｉｏとすると、グラウンド端子ＧＮＤとＩＣチップ２との間の電流は、ワイヤ３Ｇ１、３Ｇ２によってパワー素子Ｍ２＿１、Ｍ２＿２の電流が分散されるため、それぞれのピーク値が－Ｉｏ／２になることが分かる。 With reference to FIG. 4A, assuming that the peak value of the total current between the power input terminal Vin and the IC chip 2, that is, the wires 3 IN1 and 3IN2 (hereinafter referred to as the total peak value) is Io, the power input As for the current between the terminal Vin and the IC chip 2, since the currents of the power elements M1_1 and M1-2 are dispersed by the wires 3 IN1 and 3 IN2 , it can be seen that the peak values of the respective peaks are Io / 2. Further, assuming that the total peak value between the ground terminal GND and the IC chip 2, that is, the wires 3 G1 and 3 G2 is -Io, the current between the ground terminal GND and the IC chip 2 is the wire 3 G1 , 3 G2. Since the currents of the power elements M2_1 and M2_2 are dispersed by the above, it can be seen that the peak values of the respective power elements are −Io / 2.
　ワイヤ３ＩＮ１が断線した場合、パワー素子Ｍ１＿１が電源入力端子Ｖｉｎから切り離され、図４（ｂ）に示すように、電流検出値ＩＤ１＿１がゼロになると共に、電流検出値ＩＤ１＿２のピーク値が電源入力端子ＶｉｎとＩＣチップ２との間の合計ピーク値Ｉｏとなる。この電流検出値ＩＤ１＿２のピーク値変化を比較回路５３によって検出する。すなわち、比較回路５３は、検出回路４３によって検出された電流検出値ＩＤ１＿２を、合計ピーク値Ｉｏよりも小さく合計ピーク値Ｉｏの１／２よりも大きい値に設定された閾値Ｉｔｈと比較し、電流検出値ＩＤ１＿２が閾値Ｉｔｈを上回ると、エラー信号をラッチ回路６に出力する。 When the wire 3 IN1 is disconnected, the power element M1_1 is disconnected from the power input terminal Vin, as shown in FIG. 4 (b), with the current detection value I D1_1 becomes zero, the peak value of the current detection value I D1_2 It becomes the total peak value Io between the power input terminal Vin and the IC chip 2. The change in the peak value of the current detection value I D1-2 is detected by the comparison circuit 53. That is, the comparison circuit 53 compares the current detection value I D1-2 detected by the detection circuit 43 with the threshold value I th set to be smaller than the total peak value Io and larger than 1/2 of the total peak value Io. , the current detection value I D1_2 exceeds the threshold value I th, and outputs an error signal to the latch circuit 6.
　なお、ワイヤ３ＩＮ２が断線した場合、パワー素子Ｍ１＿２が電源入力端子Ｖｉｎから切り離され、電流検出値ＩＤ１＿２がゼロになると共に、電流検出値ＩＤ１＿１のピーク値が電源入力端子ＶｉｎとＩＣチップ２との間の合計ピーク値Ｉｏとなるため、比較回路５１からラッチ回路６にエラー信号が出力されることになる。 When the wire 3 IN2 is disconnected, the power element M1-2 is disconnected from the power input terminal Vin, the current detection value I D1-2 becomes zero, and the peak value of the current detection value I D1-1 is the power input terminal Vin and the IC chip 2. Since the total peak value between and is the Io, an error signal is output from the comparison circuit 51 to the latch circuit 6.
　ワイヤ３Ｇ１が断線した場合、パワー素子Ｍ２＿１がグラウンド端子ＧＮＤから切り離され、図４（ｃ）に示すように、電流検出値ＩＤ２＿１がゼロになると共に、電流検出値ＩＤ２＿２のピーク値がグラウンド端子ＧＮＤとＩＣチップ２との間の合計ピーク値－Ｉｏとなる。この電流検出値ＩＤ２＿２のピーク値変化を比較回路５４によって検出する。すなわち、比較回路５４は、検出回路４４によって検出された電流検出値ＩＤ２＿２を、合計ピーク値－Ｉｏよりも大きく合計ピーク値－Ｉｏの１／２よりも小さい値に設定された閾値－Ｉｔｈと比較し、電流検出値ＩＤ２＿２が閾値－Ｉｔｈを下回ると、エラー信号をラッチ回路６に出力する。 When the wire 3 G1 is disconnected, the power element M2_1 is disconnected from the ground terminal GND, and as shown in FIG. 4C, the current detection value I D2_1 becomes zero and the peak value of the current detection value I D2_2 becomes ground. The total peak value between the terminal GND and the IC chip 2 is -Io. The peak value change of the current detection value ID2_2 is detected by the comparison circuit 54. That is, the comparison circuit 54, the detection circuit and the current detection value I D2_2 detected by 44, the threshold value set -I th to a value smaller than 1/2 of the larger total peak value -Io than the total peak value -Io compared with, the current detection value I D2_2 is below the threshold -I th, and outputs an error signal to the latch circuit 6.
　なお、ワイヤ３Ｇ２が断線した場合、パワー素子Ｍ２＿２がグラウンド端子ＧＮＤから切り離され、電流検出値ＩＤ２＿２がゼロになると共に、電流検出値ＩＤ２＿１のピーク値がグラウンド端子ＧＮＤとＩＣチップ２との間の合計ピーク値－Ｉｏとなるため、比較回路５２からラッチ回路６にエラー信号が出力されることになる。 When the wire 3 G2 is disconnected, the power element M2_2 is disconnected from the ground terminal GND, the current detection value I D2_2 becomes zero, and the peak value of the current detection value I D2_1 is the ground terminal GND and the IC chip 2. Since the total peak value between them is -Io, an error signal is output from the comparison circuit 52 to the latch circuit 6.
　ワイヤ３ＳＷ１が断線した場合、パワー素子Ｍ１＿１及びパワー素子Ｍ２＿１が出力端子ＳＷから切り離され、図４（ｄ）に示すように、電流検出値ＩＤ１＿１及び電流検出値ＩＤ２＿１がゼロになると共に、電流検出値ＩＤ１＿２のピーク値が電源入力端子ＶｉｎとＩＣチップ２との間の合計ピーク値Ｉｏとなり、電流検出値ＩＤ２＿２のピーク値がグラウンド端子ＧＮＤとＩＣチップ２との間の合計ピーク値－Ｉｏとなる。これにより、比較回路５３及び比較回路５４からラッチ回路６にエラー信号がそれぞれ出力されることになる。 When the wire 3 SW1 is disconnected, the power element M1-1 and the power element M2_1 are disconnected from the output terminal SW, and as shown in FIG. 4D , the current detection value I D1-1 and the current detection value I D2_1 become zero, and the current detection value I D2_1 becomes zero. The peak value of the current detection value I D1-2 is the total peak value Io between the power input terminal Vin and the IC chip 2, and the peak value of the current detection value I D2_2 is the total peak value between the ground terminal GND and the IC chip 2. -Io. As a result, error signals are output from the comparison circuit 53 and the comparison circuit 54 to the latch circuit 6, respectively.
　ワイヤ３ＳＷ２が断線した場合、パワー素子Ｍ１＿２及びパワー素子Ｍ２＿２が出力端子ＳＷから切り離され、電流検出値ＩＤ１＿２及び電流検出値ＩＤ２＿２がゼロになると共に、電流検出値ＩＤ１＿１のピーク値が電源入力端子ＶｉｎとＩＣチップ２との間の合計ピーク値Ｉｏとなり、電流検出値ＩＤ２＿１のピーク値がグラウンド端子ＧＮＤとＩＣチップ２との間の合計ピーク値－Ｉｏとなる。これにより、比較回路５１及び比較回路５２からラッチ回路６にエラー信号がそれぞれ出力されることになる。 When the wire 3 SW2 is disconnected, the power element M1-2 and the power element M2_2 are disconnected from the output terminal SW, the current detection value I D1-2 and the current detection value I D2_2 become zero, and the peak value of the current detection value I D1_1 becomes the power supply. The total peak value Io between the input terminal Vin and the IC chip 2 is obtained, and the peak value of the current detection value ID2_1 is the total peak value −Io between the ground terminal GND and the IC chip 2. As a result, error signals are output from the comparison circuit 51 and the comparison circuit 52 to the latch circuit 6, respectively.
　ラッチ回路６は、比較回路５１～５４からのエラー信号をそれぞれ区別した状態で外部装置から参照可能にラッチする機能を有している。これにより、ラッチ回路６のラッチ状態によってワイヤ３の断線箇所を判定することができる。すなわち、比較回路５１からのみのエラー信号がラッチされた状態では、ワイヤ３ＩＮ２の断線、比較回路５２からのみのエラー信号がラッチされた状態では、ワイヤ３Ｇ２の断線、比較回路５３からのみのエラー信号がラッチされた状態では、ワイヤ３ＩＮ１の断線、比較回路５４からのみのエラー信号がラッチされた状態では、ワイヤ３Ｇ１の断線とそれぞれ判断することができる。また、比較回路５１及び比較回路５２からのエラー信号がラッチされた状態では、ワイヤ３ＳＷ２の断線、比較回路５３及び比較回路５４からのエラー信号がラッチされた状態では、ワイヤ３ＳＷ１の断線とそれぞれ判断することができる。さらに、エラー信号がラッチされていない状態で動作を停止した場合には、ワイヤ３ＩＮ３とワイヤ３Ｇ３とのいずれか若しくは両方の断線と判断することができる。 The latch circuit 6 has a function of latching the error signals from the comparison circuits 51 to 54 so that they can be referred to by an external device in a state of being distinguished from each other. Thereby, the disconnection point of the wire 3 can be determined based on the latch state of the latch circuit 6. That is, when the error signal only from the comparison circuit 51 is latched, the wire 3 IN2 is disconnected, and when the error signal only from the comparison circuit 52 is latched, the wire 3 G2 is disconnected and only from the comparison circuit 53. When the error signal is latched, it can be determined that the wire 3 IN1 is disconnected, and when the error signal only from the comparison circuit 54 is latched, it can be determined that the wire 3 G1 is disconnected. Further, when the error signals from the comparison circuit 51 and the comparison circuit 52 are latched, the wire 3 SW2 is disconnected, and when the error signals from the comparison circuit 53 and the comparison circuit 54 are latched, the wire 3 SW1 is disconnected. Each can be judged. Further, when the operation is stopped in the state where the error signal is not latched, it can be determined that either or both of the wire 3 IN3 and the wire 3 G3 are disconnected.
　以上、出力段のパワー素子Ｍ１、Ｍ２をそれぞれ２つに分けた例を説明したが、出力段のパワー素子を３以上のｎ個に分け、それぞれの電流変化によって断線を検出するようにしても良い。この場合、閾値Ｉｔｈは、合計ピーク値Ｉｏよりも小さく合計ピーク値Ｉｏの１／ｎよりも大きい値に設定され、閾値－Ｉｔｈは、合計ピーク値－Ｉｏよりも大きく合計ピーク値－Ｉｏの１／ｎよりも小さい値に設定される。 The example in which the power elements M1 and M2 of the output stage are each divided into two has been described above, but even if the power elements of the output stage are divided into n elements of 3 or more and the disconnection is detected by each current change. good. In this case, the threshold value I th is set to a value smaller than the total peak value Io and larger than 1 / n of the total peak value Io, and the threshold value- Th is larger than the total peak value-Io and the total peak value-Io. It is set to a value smaller than 1 / n of.
　なお、閾値Ｉｔｈ、－Ｉｔｈは、予め設定した値であっても良いが、出力変化（合計ピーク値Ｉｏ、－Ｉｏの変化）に応じてリニアもしくは段階的に変更されるように構成すると、より正確に断線を検出することが可能になる。 The threshold values I th and -I th may be preset values, but if they are configured to be linearly or stepwise changed according to output changes (changes in total peak values Io and -Io). , It becomes possible to detect the disconnection more accurately.
　また、電流検出値ＩＤ１＿１、ＩＤ１＿２、ＩＤ２＿１、ＩＤ２＿２の代わりに、電源入力端子Ｖｉｎと出力端子ＳＷ間の電圧、出力端子ＳＷとグラウンド端子ＧＮＤ間の電圧をモニターすることで、ワイヤ３の断線を検出することもできる。なお、この場合には、パワー素子Ｍ１＿１、Ｍ１＿２、Ｍ２＿１、Ｍ２＿２がオフの時はマスクする必要がある。 Further , instead of the current detection values ID1-1 , ID1_2, ID2_1 , and ID2_2 , the voltage between the power input terminal Vin and the output terminal SW and the voltage between the output terminal SW and the ground terminal GND are monitored to monitor the wire 3 It is also possible to detect the disconnection of. In this case, when the power elements M1_1, M1-2, M2_1, and M2_2 are off, it is necessary to mask them.
　さらに、検出回路４１～４４によってそれぞれ検出した電流検出値ＩＤ１＿１、ＩＤ１＿２、ＩＤ２＿１、ＩＤ２＿２は、過電流保護機能（ＯＣＰ）等の他の機能に用いても良く、他の機能のために検出した電流検出値ＩＤ１＿１、ＩＤ１＿２、ＩＤ２＿１、ＩＤ２＿２を用いるようにしても良い。 Furthermore, the current detection value I D1_1 detected respectively by the detection circuits 41 ~ 44, I D1_2, I D2_1, I D2_2 may be used in other functions, such as overcurrent protection (OCP), for other functions The current detection values ID1_1 , ID1_2 , ID2_1 , and ID2_2 detected in 1 may be used.
　軽負荷の際は、図５（ａ）に示すように、電流検出値ＩＤ１＿１、ＩＤ１＿２、ＩＤ２＿１、ＩＤ２＿２のピーク値が減少する。従って、ピーク値が２倍になっても、重負荷の正常時は誤検出することなく、且つ軽負荷の断線時には電流変化を検出できる閾値Ｉｔｈ、－Ｉｔｈを設定することが困難となる。そこで、電流検出値ＩＤ１＿１、ＩＤ１＿２、ＩＤ２＿１、ＩＤ２＿２を相互に比較することで、ワイヤ３の断線を検出可能に構成することもできる。 When the load is light, as shown in FIG. 5A , the peak values of the current detection values ID1-1 , ID1-2 , ID2_1, and ID2_2 decrease. Therefore, even if the peak value is doubled, it is difficult to set the threshold values I th and -I th that can detect the current change when the heavy load is normally disconnected and when the light load is disconnected. .. Therefore, by comparing the current detection values I D1_1, I D1-2 , I D2_1 , and I D2_1 with each other, it is possible to configure the wire 3 to be detectable.
　図６に示す半導体装置１ａには、比較回路５１～５４及びラッチ回路６に代えて、電流検出値ＩＤ１＿１と電流検出値ＩＤ１＿２とを比較し、電流検出値ＩＤ１＿１と電流検出値ＩＤ１＿２とが許容量以上に異なると不一致信号ＶＥ１をエラー信号として出力する比較回路５５と、電流検出値ＩＤ２＿１と電流検出値ＩＤ２＿２とを比較し、電流検出値ＩＤ２＿１と電流検出値ＩＤ２＿２とが許容量以上に異なると不一致信号ＶＥ２をエラー信号として出力する比較回路５６と、不一致信号ＶＥ１と不一致信号ＶＥ２とをそれぞれ区別した状態で外部装置から参照可能にラッチするラッチ回路６ａとが設けられている。 In the semiconductor device 1a shown in FIG. 6, instead of the comparison circuits 51 to 54 and the latch circuit 6, the current detection value I D1_1 and the current detection value I D1_2 are compared, and the current detection value I D1-1 and the current detection value I D1_2 are compared. DOO compares a comparison circuit 55 for outputting a different a mismatch signal V E1 than the allowable amount as an error signal, and a current detection value I D2_1 and the current detection value I D2_2, the current detection value I D2_1 and the current detection value I D2_2 The comparison circuit 56 that outputs the mismatch signal VE2 as an error signal when the difference is more than the allowable amount, and the latch circuit 6a that latches the mismatch signal VE1 and the mismatch signal VE2 so that they can be referred to from an external device while being distinguished from each other. And are provided.
　ワイヤ３ＩＮ１が断線した場合、図５（ｂ）に示すように、電流検出値ＩＤ１＿１と電流検出値ＩＤ１＿２とが異なるため、比較回路５５から不一致信号ＶＥ１が出力される。ワイヤ３ＩＮ２が断線した場合も、同様に、電流検出値ＩＤ１＿１と電流検出値ＩＤ１＿２とが異なるため、比較回路５５から不一致信号ＶＥ１が出力される。従って、比較回路５５からのみの不一致信号ＶＥ１がラッチされた状態では、ワイヤ３ＩＮ１とワイヤ３ＩＮ２のいずれかの断線と判断することができる。 When the wire 3 IN1 is disconnected, as shown in FIG. 5 (b), since the current detection value I D1_1 and the current detection value I D1_2 different, mismatch signal V E1 is outputted from the comparator circuit 55. Even if the wire 3 IN2 is disconnected, similarly, since the current detection value I D1_1 and the current detection value I D1_2 different, mismatch signal V E1 is outputted from the comparator circuit 55. Therefore, in the state where the mismatch signal VE1 only from the comparison circuit 55 is latched, it can be determined that either the wire 3 IN1 or the wire 3 IN2 is broken.
　ワイヤ３Ｇ１が断線した場合、図５（ｃ）に示すように、電流検出値ＩＤ２＿１と電流検出値ＩＤ２＿２とが異なるため、比較回路５６から不一致信号ＶＥ２が出力される。ワイヤ３Ｇ２が断線した場合も、同様に、電流検出値ＩＤ２＿１と電流検出値ＩＤ２＿２とが異なるため、比較回路５６から不一致信号ＶＥ２が出力される。従って、比較回路５６からのみの不一致信号ＶＥ２がラッチされた状態では、ワイヤ３Ｇ１とワイヤ３Ｇ２のいずれかの断線と判断することができる。 When the wire 3 G1 is disconnected, as shown in FIG. 5 (c), since the current detection value I D2_1 and the current detection value I D2_2 different, mismatch signal V E2 is output from the comparator circuit 56. Even if the wire 3 G2 is disconnected, similarly, since the current detection value I D2_1 and the current detection value I D2_2 different, mismatch signal V E2 is output from the comparator circuit 56. Therefore, in the state where the mismatch signal VE2 only from the comparison circuit 56 is latched, it can be determined that either the wire 3 G1 or the wire 3 G2 is broken.
　ワイヤ３ＳＷ１が断線した場合、図５（ｄ）に示すように、電流検出値ＩＤ１＿１と電流検出値ＩＤ１＿２とが異なると共に、電流検出値ＩＤ２＿１と電流検出値ＩＤ２＿２とが異なるため、比較回路５５から不一致信号ＶＥ１が出力されると共に、比較回路５６から不一致信号ＶＥ２が出力される。ワイヤ３ＳＷ２が断線した場合も、同様に、電流検出値ＩＤ１＿１と電流検出値ＩＤ１＿２とが異なると共に、電流検出値ＩＤ２＿１と電流検出値ＩＤ２＿２とが異なるため、比較回路５５から不一致信号ＶＥ１が出力されると共に、比較回路５６から不一致信号ＶＥ２が出力される。従って、比較回路５５から不一致信号ＶＥ１と比較回路５６から不一致信号ＶＥ２とがラッチされた状態では、ワイヤ３ＳＷ１とワイヤ３ＳＷ２のいずれかの断線と判断することができる。 When the wire 3 SW1 is disconnected, as shown in FIG. 5D , the current detection value I D1-1 and the current detection value I D1-2 are different, and the current detection value I D2_1 and the current detection value I D2_2 are different. with mismatch signal V E1 is outputted from the comparison circuit 55, mismatch signal V E2 is output from the comparator circuit 56. Similarly, when the wire 3 SW2 is disconnected, the current detection value I D1-1 and the current detection value I D1-2 are different, and the current detection value I D2_1 and the current detection value I D2_2 are different. together V E1 is output, mismatch signal V E2 is output from the comparator circuit 56. Thus, in the state in which the comparison circuit 56 and the mismatch signal V E1 from the comparison circuit 55 and the mismatch signal V E2 is latched, it can be determined that any of the disconnection of the wire 3 SW1 and the wire 3 SW2.
　以上説明したように、本実施の形態によれば、出力段のパワー素子Ｍに接続されたＩＣチップ２側の同一機能のパッドＰと同一の外部端子である電源入力端子Ｖｉｎ（ｏｒ　グラウンド端子ＧＮＤ　ｏｒ　出力端子ＳＷ）とを複数本のボンディングワイヤであるワイヤ３ＩＮ１、３ＩＮ２（ｏｒ　３Ｇ１、３Ｇ２　ｏｒ　３ＳＷ１、３ＳＷ２）によって接続した半導体装置１であって、複数のパッドＰＩＮ１、ＰＩＮ２（ｏｒ　ＰＧ１、ＰＧ２　ｏｒ　ＰＳＷ１、ＰＳＷ２）と、複数のパッドＰＩＮ１、ＰＩＮ２にそれぞれ接続された複数のワイヤ３ＩＮ１、３ＩＮ２（ｏｒ　３Ｇ１、３Ｇ２　ｏｒ　３ＳＷ１、３ＳＷ２）を流れる電流検出値ＩＤ１＿１、ＩＤ１＿２（ｏｒ　ＩＤ２＿１、ＩＤ２＿２　ｏｒＩＤ１＿１、ＩＤ１＿２、ＩＤ２＿１、ＩＤ２＿２）をそれぞれ検出する検出回路４１、４３（ｏｒ　４２、４４　ｏｒ　４１～４４）と、検出回路４１、４３によって検出された電流検出値ＩＤ１＿１、ＩＤ１＿２を閾値と比較することによって、ワイヤ３ＩＮ１、３ＩＮ２（ｏｒ　３Ｇ１、３Ｇ２　ｏｒ　３ＳＷ１、３ＳＷ２）の断線を検出してエラー信号を出力する比較回路５１、５３（ｏｒ　５２、５４　ｏｒ　５１～５４）とを備えている。
　この構成により、実働時でも電流検出値ＩＤ１＿１、ＩＤ１＿２の変化によって、同一機能の複数のパッドＰＩＮ１、ＰＩＮ２と同一の電源入力端子Ｖｉｎとがそれぞれ接続されたワイヤ３ＩＮ１、３ＩＮ２のワイヤーオープンを検出することができる。 As described above, according to the present embodiment, the power input terminal Vin (or ground terminal GND) which is the same external terminal as the pad P of the same function on the IC chip 2 side connected to the power element M of the output stage. A semiconductor device 1 in which an output terminal SW) is connected by a plurality of bonding wires, wires 3 IN1 , 3 IN2 (or 3 G1 , 3 G2 or 3 SW1 , 3 SW2 ), and a plurality of pads P IN1 , P IN2 (or P G1 , P G2 or P SW1 , P SW2 ) and a plurality of wires 3 IN1 , 3 IN2 (or 3 G1 , 3 G2 or 3 SW1 , respectively) connected to a plurality of pads P IN1 , P IN 2, respectively. 3 Detect circuits 41, 43 (or 42, 44 or 41) that detect the current detection values I D1_1 , I D1-2 (or I D2_1 , I D2_2 or I D1_1 , I D1-2 , I D2_1 , I D2_2 ) flowing through the SW2), respectively. ) And the current detection values ID1_1 and ID1_2 detected by the detection circuits 41 and 43 are compared with the threshold value to disconnect the wires 3 IN1 , 3 IN2 (or 3 G1 , 3 G2 or 3 SW1 , 3 SW2 ). It is provided with comparison circuits 51 and 53 (or 52, 54 or 51 to 54) that detect the above and output an error signal.
With this configuration, production even at the current detection value I D1_1, a change in I D1_2, wire 3 IN1 and a plurality of pads P IN1, P IN2 and the same power supply input terminal Vin is connected to the same function, 3 IN2 of Wire open can be detected.
　さらに、本実施の形態において、比較回路５１、５３は、検出回路４１、４３によって検出された複数のパワー素子Ｍ１＿１、Ｍ１＿２を流れるそれぞれの電流検出値ＩＤ１＿１、ＩＤ１＿２と閾値Ｉｔｈとを比較する。また、複数のパッドＰＩＮ１、ＰＩＮ２と電源入力端子Ｖｉｎとの間の合計ピーク値の絶対値をＩｏ、複数のパワー素子Ｍ１＿１、Ｍ１＿２の数をｎとそれぞれした場合、比較回路５１、５３は、検出回路４１、４３によって検出された複数のパワー素子Ｍ１＿１、Ｍ１＿２を流れるそれぞれの電流検出値ＩＤ１＿１、ＩＤ１＿２の絶対値が、Ｉｏよりも小さく且つＩｏの１／ｎよりも大きい値に設定された閾値Ｉｔｈを越えると、ワイヤ３ＩＮ１、３ＩＮ２の断線を検出してエラー信号を出力する。
　この構成により、電流変化した電流検出値ＩＤ１＿１、ＩＤ１＿２を特定できるため、断線箇所を特定することができる。 Furthermore, comparison in the present embodiment, the comparison circuit 51 and 53, detecting circuits 41 and 43 a plurality of power elements M1_1 detected by the respective current detection value I D1_1 flowing M1_2, and I D1_2 and the threshold I th To do. The absolute value Io of total peak value between the plurality of pads P IN1, P IN2 and the power input terminal Vin, a plurality of power elements M1_1, if the number of M1_2 were respectively n, comparison circuits 51 and 53 , the detection circuit 41 and 43 a plurality of power elements M1_1 detected by the respective current detection value I D1_1 flowing M1_2, the absolute value of I D1_2 is set to a value larger than 1 / n of the smaller and Io than Io When the threshold value Is exceeded, the disconnection of the wires 3 IN1 and 3IN2 is detected and an error signal is output.
With this configuration, since the current detection values ID1_1 and ID1_2 whose current has changed can be specified, the disconnection point can be specified.
　さらに、本実施の形態において、比較回路５５（ｏｒ　５６）は、検出回路４１、４３（ｏｒ　４２、４４）によって検出された複数のパワー素子Ｍ１＿１、Ｍ１＿２を流れるそれぞれの電流検出値ＩＤ１＿１、ＩＤ１＿２（ｏｒ　複数のパワー素子Ｍ２＿１、Ｍ２＿２を流れるそれぞれの電流検出値ＩＤ２＿１、ＩＤ２＿２）相互に比較する。
　この構成により、軽負荷時で電流検出値ＩＤ１＿１、ＩＤ１＿２ピーク値が低い場合でも、相互の電流変化で断線を検出することができる。 Further, in the present embodiment, the comparison circuit 55 (or 56) has the current detection values I D1-1 and I flowing through the plurality of power elements M1_1 and M1_2 detected by the detection circuits 41 and 43 (or 42 and 44), respectively. D1-2 (or current detection values I D2_1 and I D2_2 flowing through a plurality of power elements M2_1 and M2_2) are compared with each other.
With this configuration, even when the current detection values ID1_1 and ID1_2 peak values are low under a light load, disconnection can be detected by mutual current changes.
　さらに、本実施の形態において、検出回路４１～４４及び比較回路５１～５６は、異なる機能毎に設けられ、検出回路４１～４４からのエラー信号を区別した外部装置から参照可能にラッチするラッチ回路６、６ａを備えている
　この構成により、ラッチ回路６、６ａのラッチ状態に応じて、動作停止後に外部装置から断線箇所を把握することができる。 Further, in the present embodiment, the detection circuits 41 to 44 and the comparison circuits 51 to 56 are provided for each different function, and a latch circuit that latches the error signals from the detection circuits 41 to 44 so that they can be referred to from a distinct external device. 6 and 6a are provided. With this configuration, the disconnection point can be grasped from the external device after the operation is stopped according to the latch state of the latch circuits 6 and 6a.
　なお、上記のように本発明の各実施形態及び各実施例について詳細に説明したが、本発明の新規事項及び効果から実体的に逸脱しない多くの変形が可能であることは、当業者には、容易に理解できるであろう。従って、このような変形例は、全て本発明の範囲に含まれるものとする。例えば、明細書又は図面において、少なくとも一度、より広義又は同義な異なる用語と共に記載された用語は、明細書又は図面のいかなる箇所においても、その異なる用語に置き換えることができる。 Although each embodiment and each embodiment of the present invention have been described in detail as described above, those skilled in the art will be able to make many modifications that do not substantially deviate from the new matters and effects of the present invention. , Will be easy to understand. Therefore, all such modifications are included in the scope of the present invention. For example, a term described at least once in a specification or drawing with a different term in a broader or synonymous manner may be replaced by that different term anywhere in the specification or drawing.
１、１ａ　半導体装置
２　ＩＣチップ
３、３ＩＮ１、３ＩＮ２、３ＩＮ３、３ＳＷ１、３ＳＷ２、３Ｇ１、３Ｇ２、３Ｇ３　ワイヤ
４１～４４　検出回路
５１～５６　比較回路
６、６ａ　ラッチ回路
Ｃ　出力コンデンサ
ＧＮＤ　グラウンド端子
ＩＤ１＿１、ＩＤ１＿２、ＩＤ２＿１、ＩＤ２＿２　電流検出値
Ｉｏ、－Ｉｏ　合計ピーク値
Ｉｔｈ、－Ｉｔｈ　閾値
Ｌ　インダクタ
ＬＯＡＤ　負荷
Ｍ１＿１、Ｍ１＿２、Ｍ２＿１、Ｍ２＿２　パワー素子
ＰＩＮ１、ＰＩＮ２、ＰＩＮ３、ＰＳＷ１、ＰＳＷ２、ＰＧ１、ＰＧ２、ＰＧ３　パッド
ＳＷ　出力端子
Ｖｉｎ　電源入力端子 1, 1a Semiconductor device 2 IC chip 3 , 3 IN1 , 3 IN2 , 3 IN3 , 3 SW1 , 3 SW2 , 3 G1 , 3 G2 , 3 G3 Wire 41-44 Detection circuit 51-56 Comparison circuit 6, 6a Latch circuit C output capacitor GND ground terminal I D1_1, I D1_2, I D2_1 , I D2_2 current detection value Io, -Io total peak value I th, -I th threshold L inductor lOAD load M1_1, M1_2, M2_1, M2_2 power element P IN1, P IN2, P IN3, P SW1, P SW2, P G1, P G2, P G3 pad SW output terminal Vin power input terminal

Claims (5)

  1. 　ＩＣチップ側の同一の機能が割り当てられた複数のパッドと、前記機能の外部端子とを複数本のボンディングワイヤによって接続した半導体装置であって、
    　前記ボンディングワイヤを流れる電流をそれぞれ検出する検出回路と、
    　前記検出回路によって検出された電流検出値の比較によって、前記ボンディングワイヤの断線を検出してエラー信号を出力する比較回路と、を具備することを特徴とする半導体装置。     A semiconductor device in which a plurality of pads to which the same function is assigned on the IC chip side and an external terminal of the function are connected by a plurality of bonding wires.
    A detection circuit that detects the current flowing through the bonding wire, and
    A semiconductor device including a comparison circuit that detects a disconnection of the bonding wire and outputs an error signal by comparing the current detection values detected by the detection circuit.
  2. 　前記比較回路は、前記検出回路によって検出された複数の電流検出値と閾値とを比較することを特徴とする請求項１記載の半導体装置。 The semiconductor device according to claim 1, wherein the comparison circuit compares a plurality of current detection values detected by the detection circuit with a threshold value.
  3. 　複数の前記パッドと前記外部端子との間に流れる電流の合計ピーク値の絶対値をＩｏ、複数の前記ボンディングワイヤの数をｎとそれぞれした場合、
    　前記比較回路は、前記検出回路によって検出された電流検出値の絶対値が、Ｉｏよりも小さく且つＩｏの１／ｎよりも大きい値に設定された前記閾値を越えると、前記ボンディングワイヤの断線を検出してエラー信号を出力することを特徴とする請求項２記載の半導体装置。     When the absolute value of the total peak value of the current flowing between the plurality of pads and the external terminals is Io and the number of the plurality of bonding wires is n, respectively.
    When the absolute value of the current detection value detected by the detection circuit exceeds the threshold value set to a value smaller than Io and larger than 1 / n of Io, the comparison circuit breaks the bonding wire. The semiconductor device according to claim 2, further comprising detecting and outputting an error signal.
  4. 　前記比較回路は、前記検出回路によって検出された複数の電流検出値を相互に比較することを特徴とする請求項１記載の半導体装置。 The semiconductor device according to claim 1, wherein the comparison circuit compares a plurality of current detection values detected by the detection circuit with each other.
  5. 　前記検出回路及び前記比較回路は、異なる機能毎に設けられ、
    　前記比較回路からのエラー信号を区別した外部装置から参照可能にラッチするラッチ回路を具備することを特徴とする請求項１乃至４のいずれかに記載の半導体装置。     The detection circuit and the comparison circuit are provided for different functions.
    The semiconductor device according to any one of claims 1 to 4, further comprising a latch circuit that latches an error signal from the comparison circuit so that it can be referred to by an external device.
PCT/JP2019/047531 2019-12-05 2019-12-05 Semiconductor device WO2021111572A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2021562274A JPWO2021111572A1 (en) 2019-12-05 2019-12-05
PCT/JP2019/047531 WO2021111572A1 (en) 2019-12-05 2019-12-05 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2019/047531 WO2021111572A1 (en) 2019-12-05 2019-12-05 Semiconductor device

Publications (1)

Publication Number Publication Date
WO2021111572A1 true WO2021111572A1 (en) 2021-06-10

Family

ID=76221722

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2019/047531 WO2021111572A1 (en) 2019-12-05 2019-12-05 Semiconductor device

Country Status (2)

Country Link
JP (1) JPWO2021111572A1 (en)
WO (1) WO2021111572A1 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007165368A (en) * 2005-12-09 2007-06-28 Denso Corp Wire testing system
JP2016145720A (en) * 2015-02-06 2016-08-12 トヨタ自動車株式会社 Semiconductor chip and method for detecting disconnection of wire bonded to semiconductor chip
JP2018017605A (en) * 2016-07-28 2018-02-01 ルネサスエレクトロニクス株式会社 Semiconductor device and semiconductor system having the same
WO2018225188A1 (en) * 2017-06-07 2018-12-13 新電元工業株式会社 Disconnection determining device and power module

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007165368A (en) * 2005-12-09 2007-06-28 Denso Corp Wire testing system
JP2016145720A (en) * 2015-02-06 2016-08-12 トヨタ自動車株式会社 Semiconductor chip and method for detecting disconnection of wire bonded to semiconductor chip
JP2018017605A (en) * 2016-07-28 2018-02-01 ルネサスエレクトロニクス株式会社 Semiconductor device and semiconductor system having the same
WO2018225188A1 (en) * 2017-06-07 2018-12-13 新電元工業株式会社 Disconnection determining device and power module

Also Published As

Publication number Publication date
JPWO2021111572A1 (en) 2021-06-10

Similar Documents

Publication Publication Date Title
KR102128137B1 (en) Protection of switched capacitor power converter
JP6342135B2 (en) Fault-tolerant fail-safe link
US7965095B2 (en) Separate testing of continuity between an internal terminal in each chip and an external terminal in a stacked semiconductor device
CN103973085B (en) System and method for drive circuit
US7397221B2 (en) Battery protection device, battery protection system using the same, and battery protection method
US7583109B2 (en) Apparatus and methods for monitoring parallel-connected power switching devices responsive to drive circuit parameters
JP5397571B2 (en) Control device
ES2527451T3 (en) Safe input circuit with single-channel peripheral connection for the input of a bus user
KR102021864B1 (en) Driving circuit of switching device for electric power control
CN112398086A (en) Intelligent semiconductor switch
WO2021111572A1 (en) Semiconductor device
JP7162755B2 (en) semiconductor equipment
JP6107949B2 (en) Semiconductor module
US20040075488A1 (en) Semiconductor device having voltage feedback circuit therein, and electronic apparatus using the same
US7755432B1 (en) Short circuit protection circuits and methods
US20220029410A1 (en) Current sense circuit
US20220345125A1 (en) Circuit arrangement for controlling a plurality of semiconductor switches connected in parallel
JP5268294B2 (en) Fault detection device for chopper circuit
US11916064B2 (en) Integrated circuit with fault reporting structure
US20210028786A1 (en) Semiconductor integrated circuit device
US20210080492A1 (en) Semiconductor device and power device
CN220511288U (en) LED breakpoint continuous transmission module
US20220224314A1 (en) Adaptive capacitve filter circuit
US20240154612A1 (en) Voltage supply
US20230261589A1 (en) Inverter unit with detection of voltage drops on semiconductor switches

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19955027

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2021562274

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19955027

Country of ref document: EP

Kind code of ref document: A1