WO2021102656A1 - 一种放大电路 - Google Patents

一种放大电路 Download PDF

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Publication number
WO2021102656A1
WO2021102656A1 PCT/CN2019/120753 CN2019120753W WO2021102656A1 WO 2021102656 A1 WO2021102656 A1 WO 2021102656A1 CN 2019120753 W CN2019120753 W CN 2019120753W WO 2021102656 A1 WO2021102656 A1 WO 2021102656A1
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Prior art keywords
submodule
load
switch
module
amplifier
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PCT/CN2019/120753
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English (en)
French (fr)
Inventor
李博
范硕
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深圳市汇顶科技股份有限公司
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Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to PCT/CN2019/120753 priority Critical patent/WO2021102656A1/zh
Priority to CN201980004198.1A priority patent/CN113316895A/zh
Publication of WO2021102656A1 publication Critical patent/WO2021102656A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
    • H03F3/08—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers

Definitions

  • This application relates to the field of electrical technology, in particular to an amplifier circuit.
  • Trans-Impedance Amplifier is a type of amplifier used to amplify electrical signals.
  • the purpose of some embodiments of the present application is to provide an amplifying circuit that reduces the influence of the equivalent ground capacitance on the SNR.
  • the embodiment of the application provides an amplifying circuit, including: an amplifier and a current follower; the input end of the current follower is used as the input end of the amplifying circuit, the output end of the current follower is connected to the input end of the amplifier, and the output end of the amplifier is used as The output terminal of the amplifying circuit.
  • the embodiment of the present application adopts a current follower and an amplifier cascade to form an amplifying circuit, and the transconductance of the current follower reduces the gain within the noise bandwidth of the amplifier, thereby reducing the equivalent input noise of the amplifier to the output.
  • the gain of achieves the purpose of reducing the output noise of the amplifier, and reduces the effect of the equivalent ground capacitance on the SNR.
  • the current follower includes a first load submodule, a first switch submodule, and a second load submodule; the first end of the first load submodule is connected to the first power signal line, and the second end of the first load submodule is connected to the The first end of the first switch submodule is connected, the second end of the first switch submodule is connected to the first end of the second load submodule, and the second end of the second load submodule is grounded.
  • the control of the first switch submodule is The terminal is connected to the first bias signal output terminal; the first terminal of the first switch submodule serves as the input terminal of the current follower, and the second terminal of the first switch submodule serves as the output terminal of the current follower.
  • the input terminal of the amplifying circuit is connected to the capacitor to be measured through a current conversion module, and the output terminal of the amplifying circuit is connected to the controller through an analog-to-digital converter; wherein the current conversion module is used to convert the capacitance change of the capacitor to be measured into a current change .
  • the output terminal of the amplifying circuit is connected to an analog-to-digital converter through a filter and a gain amplifier in sequence.
  • the input end of the amplifying circuit is connected to the photoelectric sensor module, and the output end of the amplifying circuit is connected to the controller through an analog-to-digital converter.
  • the amplifier is a transimpedance amplifier.
  • the first bias signal output terminal is the output terminal of the first bias signal generating module
  • the first bias signal generating module includes: a second switch submodule and a third load submodule; Terminal is connected to the second power signal line, the control terminal of the second switch sub-module is connected with the second terminal of the second switch sub-module, the second terminal of the second switch sub-module is connected with the first terminal of the third load sub-module, The second end of the three-load submodule is grounded, and the connection between the control end of the second switch submodule and the second end of the second switch submodule serves as the output end of the first bias signal generating module.
  • any one or each of the first load submodule and the second load submodule includes a switching element, the first end of the switching element is used as the first end of the load submodule, and the second end of the switching element is used as the first end of the load submodule.
  • the second end of the load submodule and the control end of the switching element are connected to the second bias signal output end.
  • any one or both of the first load submodule and the second load submodule include: a switching element and a resistance element, the first end of the resistance element serves as the first end of the load submodule, and the first end of the resistance element The two ends are connected with the first end of the switch element, the second end of the switch element is used as the second end of the load submodule, and the control end of the switch element is connected to the second bias signal output end.
  • the second bias signal output terminal is the output terminal of the second bias signal generating module.
  • the second bias signal generating module includes: a fourth switch sub-module and a fifth load sub-module, the first of the fourth switch sub-module Terminal is connected to the third power signal line, the second terminal of the fourth switch submodule is connected to the first terminal of the fifth load submodule, the second terminal of the fifth load submodule is grounded, and the control terminal of the fourth switch submodule is connected to the The first end of the fifth load submodule is connected, and the control end of the fourth switch submodule is used as the second bias signal output end.
  • Fig. 1 is a schematic structural diagram of an amplifying circuit according to a first embodiment of the present application
  • Fig. 2 is a schematic structural diagram of a current follower according to the first embodiment of the present application
  • Fig. 3 is a schematic structural diagram of a first bias signal generating module according to the first embodiment of the present application.
  • FIG. 4 is a schematic circuit diagram of a first bias signal generating module according to the first embodiment of the present application.
  • Fig. 5 is an equivalent circuit diagram of a current follower and amplifier according to the first embodiment of the present application.
  • FIG. 6 is a schematic diagram of the connection between the amplifying circuit and the first bias signal generating module according to the first embodiment of the present application;
  • Fig. 7 is a schematic circuit diagram of a current follower according to the first embodiment of the present application.
  • Fig. 8 is a schematic circuit diagram of another current follower according to the first embodiment of the present application.
  • Fig. 9 is a schematic structural diagram of a second bias signal generating module according to the first embodiment of the present application.
  • Fig. 10 is a schematic circuit diagram of a first bias signal generating module and a second bias signal generating module according to the first embodiment of the present application;
  • FIG. 11 is a schematic diagram of the connection between the amplifying circuit and the driving chip according to the second embodiment of the present application.
  • FIG. 12 is a circuit diagram of an amplifying circuit and a driving chip according to a second embodiment of the present application.
  • 13 is a schematic diagram of the connection relationship between the output terminal of the amplifier and the analog-to-digital converter according to the second embodiment of the present application;
  • Fig. 14 is a schematic circuit diagram of a detection device applying the amplifying circuit according to a third embodiment of the present application.
  • the first embodiment of the present application relates to an amplifying circuit.
  • the amplifying circuit includes an amplifier 11 and a current follower 12.
  • the input end of the current follower 12 is used as the input end of the amplifying circuit, and the output of the current follower 12 is The terminal is connected to the input terminal of the amplifier 11, and the output terminal of the amplifier 11 is used as the output terminal of the amplifying circuit.
  • the current follower 12 and the amplifier 11 are cascaded to form an amplifying circuit for amplifying the electrical signal received by the input terminal of the current follower 12. Since the current follower 12 is connected to the amplifying circuit, the transconductance of the current follower 12 can reduce the gain in the noise bandwidth of the amplifier 11, thereby reducing the gain from the equivalent input noise to the output of the amplifier 11, and reducing the output of the amplifier 11 The purpose of noise is to reduce the effect of equivalent ground capacitance on SNR.
  • the amplifier 11 may be a transimpedance amplifier (TIA) or other types of amplifiers, and there is no limitation here.
  • TIA transimpedance amplifier
  • the current follower 12 is shown in FIG. 2 and includes a first load submodule 21, a first switch submodule 22, and a second load submodule 23; the first end of the first load submodule 21 is connected to the first load submodule 21.
  • a power signal line (VDD1), the second end of the first load submodule 21 is connected to the first end of the first switch submodule 22, and the second end of the first switch submodule 22 is connected to the first end of the second load submodule 23 One end is connected, the second end of the second load submodule 23 is grounded (VSS), the control end of the first switch submodule 22 is connected to the first bias signal output end (Vb1); the first end of the first switch submodule 22 As the input terminal of the current follower 12, the second terminal of the first switch sub-module 22 serves as the output terminal of the current follower 12.
  • the first switch sub-module 22 is a P-type transistor, the first terminal of the first switch sub-module 22 is the drain of the P-type transistor, and the second terminal of the first switch sub-module 22 is the drain of the P-type transistor. Source level.
  • the first load submodule 21 and the second load submodule 23 may be various resistive devices, for example, current sources or high-resistance devices composed of transistors and other devices. Resistance etc., this embodiment does not limit the device types of the first load sub-module 21 and the second load sub-module 23.
  • first switch submodule 22 may also be other devices, and the device type of the first switch submodule 22 is not limited in this embodiment.
  • the voltage value output by the first power signal line (VDD1) can be determined according to the application scenario of the amplifying circuit, which is not limited in this embodiment.
  • the first bias signal output terminal is the output terminal (Vb1) of the first bias signal generation module, as shown in FIG. 3, including: a second switch submodule 31 and a third load submodule 32;
  • the first end of the second switch submodule 31 is connected to the second power signal line (VDD2), the control end of the second switch submodule 31 is connected to the second end of the second switch submodule 31, and the second end of the second switch submodule 31
  • the two ends are connected to the first end of the third load submodule 32, the second end of the third load submodule 32 is grounded (VSS), the control end of the second switch submodule M3 and the second end of the second switch submodule M3
  • the connection between the two is used as the output terminal (Vb1) of the first bias signal generating module.
  • the first end of the second switch submodule 31 is connected to the second power signal line (VDD2) through the fourth load submodule.
  • VDD2 represents the second power signal line
  • M2 represents the second switch submodule
  • S3 represents the third load submodule
  • M3 represents the fourth load submodule
  • Vb1 represents the output terminal of the first bias signal generating module
  • VSS represents the ground end.
  • the third load submodule may also be an N-type transistor or other resistive devices, and this embodiment does not limit the structure type of the third load submodule.
  • the magnitude of the first bias signal output by the first bias signal terminal can be set according to the actual application, and the magnitude of the voltage output by the second power signal line (VDD2),
  • the resistance value of the three-load submodule can be set according to the size of the first bias signal, which is not limited in this embodiment.
  • the first bias signal generating module may also adopt other circuit structures. This embodiment is only an example for illustration and does not limit the specific circuit of the first bias signal generating module. structure.
  • the first switch sub-module 22 is a transistor
  • the power follower is a common-gate amplifier.
  • the transconductance of the common-gate amplifier reduces the gain from the equivalent input noise to the output of the amplifier 11 to achieve the purpose of reducing the output noise of the amplifier 11.
  • the first load sub-module 21 and the second load sub-module 23 are loads, which may be current sources, or other circuits that can be equivalent to current sources.
  • the first switch sub-module 22 is a transistor
  • the equivalent circuit diagram of the current follower 12 and the amplifier 11 is shown in FIG.
  • the connection diagram of the set signal generating module is shown in Figure 6.
  • VDD1 represents the first power signal line
  • VSS represents the ground terminal
  • S1 represents the first load submodule
  • M1 represents the first switch submodule
  • Vb1 represents the first bias signal output terminal
  • S2 represents the second load submodule
  • Vout represents the output of the current follower
  • R 1 represents the feedback resistance of the transimpedance amplifier
  • C represents the feedback capacitance of the transimpedance amplifier
  • O represents the operational amplifier of the transimpedance amplifier
  • N represents the operational amplifier Equivalent input noise
  • VCM represents the common mode signal
  • V represents the output of the operational amplifier.
  • the gain of the equivalent input noise to the output of the transimpedance amplifier can be approximately equal to Among them, s represents the Laplace complex variable, Cc represents the equivalent capacitance to ground, g m represents the transconductance of the current follower 12, and Rds represents the drain-to-source resistance of the first switch submodule 22. Compared with the amplifying circuit using the amplifier 11 alone, the gain is reduced by a factor of g m R ds . Therefore, g m R ds can be used to offset the increase in the equivalent ground capacitance Cc, which reduces the final output noise, thereby avoiding a decrease in SNR.
  • the current follower 12 may use other circuits or devices with the same function, and the circuit structure of the current follower 12 is not limited in this embodiment.
  • any one or each of the first load submodule 21 and the second load submodule 23 includes a switching element, and the first end of the switching element serves as the first end of the load submodule, The second end of the switching element serves as the second end of the load submodule, and the control end of the switching element is connected to the second bias signal output end.
  • the switching element may be a transistor or other devices.
  • the first switching sub-module 22 is a transistor, and its control terminal is connected to the first bias signal terminal.
  • the first load sub-module 21 is a switching element, and the switching element is a transistor.
  • VDD1 represents the first power supply signal line
  • VSS represents the ground terminal
  • M1 represents the first switch sub-module
  • M4 represents the switching element
  • Vb1 represents the first bias signal terminal
  • Vb2 represents The second bias signal terminal
  • S2 represents the second load sub-module.
  • the second load submodule 23 may also be an N-type transistor or other resistive device, which is not limited in this embodiment.
  • any one or both of the first load submodule 21 and the second load submodule 23 includes: a switching element and a resistance element, and the first end of the resistance element is used as the first end of the load submodule. At one end, the second end of the resistance element is connected to the first end of the switching element, the second end of the switching element is used as the second end of the load submodule, and the control end of the switching element is connected to the second bias signal output end.
  • the switching element may be a transistor or other devices.
  • the first switching sub-module 22 is a transistor, and its control terminal is connected to the first bias signal output terminal
  • the first load sub-module 21 is a switching element
  • the switching element is a transistor, and its control terminal is connected to the second bias signal output terminal.
  • the circuit diagram of the current follower 12 is shown in Figure 8, where VDD1 represents the first power signal line, VSS represents the ground terminal, M1 represents the first switch sub-module, M4 represents the switching element, R2 represents the resistance element, and Vb1 represents the first The bias signal terminal, Vb2 represents the second bias signal terminal, and S2 represents the second load sub-module.
  • the switching element is connected to the power supply through the resistance element, which can make the low frequency noise of the amplifier circuit smaller.
  • the circuit structures of the first load submodule 21 and the second load submodule 23 may be the same or different.
  • the first load submodule 21 The second load sub-module 23 and the second load sub-module 23 may also adopt other circuit structures, and this embodiment does not limit the specific circuit structures of the first load sub-module 21 and the second load sub-module 23.
  • the second bias signal output terminal is the output terminal of the second bias signal generation module.
  • the second bias signal generating module includes: a fourth switch sub-module 91 and a fifth load sub-module 92, the first end of the fourth switch sub-module 91 is connected to the third power signal line (VDD3), The second end of the fourth switch submodule 91 is connected to the first end of the fifth load submodule 92, the second end of the fifth load submodule 92 is grounded (VSS), and the control end of the fourth switch submodule 91 is connected to the fifth end of the fifth load submodule 92.
  • the first terminal of the load submodule 92 is connected, and the control terminal of the fourth switch submodule serves as the second bias signal output terminal (Vb2).
  • the voltage value output by the third power signal line (VDD3) can be determined according to the application scenario of the amplifying circuit, which is not limited in this embodiment.
  • the second end of the fourth switch submodule 91 is connected to the first end of the fifth load submodule 92 through the fifth switch submodule.
  • the circuit diagrams of the first bias signal generating module and the second bias signal generating module are shown in FIG. 10.
  • VDD2 represents the second power signal line
  • VDD3 represents the third power signal line
  • VSS represents the ground terminal
  • M2 represents the second switch submodule
  • M3 represents the fourth load submodule
  • M5 represents the fourth switch submodule
  • M6 represents the first switch submodule.
  • Vb1 represents the first bias signal output terminal
  • Vb2 represents the second bias signal output terminal.
  • the second bias signal generating module may also adopt other circuit structures, and this embodiment is only an example for illustration.
  • this embodiment adopts the cascade connection of the current follower 12 and the amplifier 11 to form an amplifying circuit, and the transconductance of the current follower 12 reduces the gain in the noise bandwidth of the amplifier 11, thereby reducing the equivalent of the amplifier 11.
  • the gain from the input noise to the output achieves the purpose of reducing the output noise of the amplifier 11 and reduces the effect of the equivalent capacitance to ground on the SNR.
  • the second embodiment of the present application relates to an amplifying circuit.
  • This embodiment is substantially the same as the first embodiment, and mainly describes the application of the amplifying circuit in a touch device.
  • FIG. 11 the schematic diagram of the connection between the amplifying circuit and the driving chip of the touch device is shown in FIG. 11.
  • the input end of the amplifying circuit 81 is connected to the capacitor under test 83 through the current conversion module 82, and the output end of the amplifying circuit 81 is converted through analog-to-digital conversion.
  • the device 84 is connected to the controller 85; wherein, the current conversion module 82 is used to convert the capacitance change of the capacitor 83 to be measured into a current change.
  • the circuit diagram of the amplifying circuit and the driving chip is shown in Figure 12, where Cx represents the capacitance to be measured, S1 represents the first load submodule, M1 represents the first switch submodule, and S2 represents the second load submodule.
  • CTC represents the current conversion module
  • TIA represents the transimpedance amplifier
  • Vb1 represents the first bias signal output terminal
  • V represents the output terminal of the amplifying circuit.
  • the current conversion module converts the change of the capacitance to be measured into a current change, which is transmitted to the transimpedance amplifier through the current follower 12, and the current is converted into voltage through the feedback capacitance and feedback resistance of the transimpedance amplifier.
  • transimpedance amplifiers with other circuit structures can also be selected, and this embodiment does not limit the circuit structure of the transimpedance amplifier.
  • the connection relationship between the output terminal of the amplifier 11 and the analog-to-digital converter is shown in FIG. 13, and the output terminal of the amplifying circuit 81 is connected to the analog-to-digital converter 84 through the filter 86 and the gain amplifier 87 in sequence. That is, the output end of the amplifying circuit 81 is connected to the filter 86, the filter 86 is connected to the gain amplifier 87, and the gain amplifier 87 is connected to the analog-to-digital converter 84.
  • the filter may be an anti-aliasing filter
  • the gain amplifier may be a variable gain amplifier.
  • applying the amplifying circuit to the touch screen driver chip can improve the SNR performance of the original scheme on the basis of maintaining the original system scheme.
  • the current follower 12 and the amplifier 11 are cascaded to form an amplifying circuit.
  • the transconductance of the current follower 12 reduces the gain in the noise bandwidth of the amplifier 11, thereby reducing the gain from the equivalent input noise to the output of the amplifier 11, so as to reduce the amplifier.
  • the purpose of output noise is to reduce the effect of equivalent ground capacitance on SNR.
  • the third embodiment of the present application relates to an amplifying circuit.
  • This embodiment is substantially the same as the first embodiment, and mainly describes the application of the amplifying circuit in a detection device.
  • the detection device includes a light-emitting module and a photoelectric sensor module, the input end of the amplifying circuit is connected with the photoelectric sensor module, and the output end of the amplifying circuit is connected with the controller through an analog-to-digital converter.
  • the circuit diagram of the detection device applying the amplifying circuit is shown in Fig. 14, where LED DRV stands for LED drive module, LED stands for light emitting diode, VDD LED stands for drive power supply for light emitting diode, and TS stands for the object under test.
  • LED stands for photoelectric sensor module
  • S1 stands for first load submodule
  • M1 stands for first switch submodule
  • S2 stands for second load submodule
  • TIA transimpedance amplifier
  • Vb1 stands for first bias signal output terminal
  • V stands for The output terminal of the amplifying circuit.
  • the LED DRV drives the LED to emit light and project it onto the surface of the object to be measured.
  • the PD receives the light emitted by the LED to generate a photocurrent.
  • the photocurrent is transmitted to the transimpedance amplifier through the current follower 12, and the feedback capacitance and feedback of the transimpedance amplifier
  • the resistance forms a voltage output.
  • the detection device may be a heart rate detection device or other detection devices, which is not limited in this embodiment.
  • applying the amplifying circuit to the detection device can improve the SNR performance of the original scheme on the basis of maintaining the original system scheme.
  • the current follower 12 and the amplifier 11 are cascaded to form an amplifying circuit.
  • the transconductance of the current follower 12 reduces the gain in the noise bandwidth of the amplifier 11, thereby reducing the gain from the equivalent input noise to the output of the amplifier 11, so as to reduce the amplifier.
  • the purpose of output noise is to reduce the effect of equivalent ground capacitance on SNR.

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Abstract

一种放大电路，包括放大器(11)和电流跟随器(12)；电流跟随器(12)的输入端作为放大电路的输入端，电流跟随器(12)的输出端与放大器(11)的输入端连接，放大器(11)的输出端作为放大电路的输出端。通过上述结构减小了等效对地电容对SNR的影响。

Description

一种放大电路 技术领域
本申请涉及电学技术领域，特别涉及一种放大电路。
背景技术
跨阻放大器(Trans-Impedance Amplifier，TIA)是放大器类型的一种，用于放大电信号。
发明人发现现有技术至少存在以下问题：在TIA的应用中，信号源或信号采集部分的等效对地电容Cc(由寄生或者到地耦合产生的)过大会导致TIA输出信噪比(SIGNAL NOISE RATIO，SNR)的下降。
发明内容
本申请部分实施例的目的在于提供一种放大电路，减小了等效对地电容对SNR的影响。
本申请实施例提供了一种放大电路，包括：放大器和电流跟随器；电流跟随器的输入端作为放大电路的输入端，电流跟随器的输出端与放大器的输入端连接，放大器的输出端作为放大电路的输出端。
本申请实施例现对于现有技术而言，采用电流跟随器和放大器级联构成放大电路，通过电流跟随器的跨导减小放大器噪声带宽内的增益，从而降低放 大器的等效输入噪声到输出的增益，达到减小放大器输出噪声的目的，减少了等效对地电容对SNR的影响。
例如，电流跟随器包括第一负载子模块、第一开关子模块和第二负载子模块；第一负载子模块的第一端连接第一电源信号线，第一负载子模块的第二端与第一开关子模块的第一端连接，第一开关子模块的第二端与第二负载子模块的第一端连接，第二负载子模块的第二端接地，第一开关子模块的控制端连接第一偏置信号输出端；第一开关子模块的第一端作为电流跟随器的输入端，第一开关子模块的第二端作为电流跟随器的输出端。
例如，放大电路的输入端通过电流转换模块与待测电容连接，放大电路的输出端通过模数转换器与控制器连接；其中，电流转换模块用于将待测电容的电容变化转换为电流变化。
例如，放大电路的输出端依次通过滤波器和增益放大器与模数转换器连接。
例如，放大电路的输入端与光电感应模块连接，放大电路的输出端通过模数转换器与控制器连接。
例如，放大器为跨阻放大器。
例如，第一偏置信号输出端为第一偏置信号发生模块的输出端，第一偏置信号发生模块包括：第二开关子模块和第三负载子模块；第二开关子模块的第一端连接第二电源信号线，第二开关子模块的控制端与第二开关子模块的第二端连接，第二开关子模块的第二端与第三负载子模块的第一端连接，第三负载子模块的第二端接地，第二开关子模块的控制端和第二开关子模块的第二端之间的连接处作为第一偏置信号发生模块的输出端。
例如，第一负载子模块和第二负载子模块中的任意一个或每个负载子模块包括：开关元件，开关元件的第一端作为负载子模块的第一端，开关元件的第二端作为负载子模块的第二端，开关元件的控制端连接第二偏置信号输出端。
例如，第一负载子模块和第二负载子模块中的任意一个或两个负载子模块包括：开关元件和电阻元件，电阻元件的第一端作为负载子模块的第一端，电阻元件的第二端与开关元件的第一端连接，开关元件的第二端作为负载子模块的第二端，开关元件的控制端连接第二偏置信号输出端。
另外，第二偏置信号输出端为第二偏置信号发生模块的输出端，第二偏置信号发生模块包括：第四开关子模块和第五负载子模块，第四开关子模块的第一端与第三电源信号线连接，第四开关子模块的第二端与第五负载子模块的第一端连接，第五负载子模块的第二端接地，第四开关子模块的控制端和第五负载子模块的第一端连接，第四开关子模块的控制端作为第二偏置信号输出端。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。以下各个实施例的划分是为了描述方便，不应对本申请的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合相互引用。
图1是根据本申请第一实施例的放大电路的结构示意图；
图2是根据本申请第一实施例的电流跟随器的结构示意图；
图3是根据本申请第一实施例的第一偏置信号发生模块的结构示意图；
图4是根据本申请第一实施例的第一偏置信号发生模块的电路示意图；
图5是根据本申请第一实施例的电流跟随器和放大器的等效电路图；
图6是根据本申请第一实施例的放大电路和第一偏置信号发生模块的连接示意图；
图7是根据本申请第一实施例的电流跟随器的电路示意图；
图8是根据本申请第一实施例的另一电流跟随器的电路示意图；
图9是根据本申请第一实施例的第二偏置信号发生模块的结构示意图；
图10是根据本申请第一实施例的第一偏置信号发生模块和第二偏置信号发生模块的电路示意图；
图11是根据本申请第二实施例的放大电路和驱动芯片的连接示意图；
图12是根据本申请第二实施例的放大电路和驱动芯片的电路示意图；
图13是根据本申请第二实施例的放大器的输出端和模数转换器之间的连接关系示意图；
图14是根据本申请第三实施例的应用该放大电路的检测装置的电路示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请部分实施例进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
本申请第一实施例涉及一种放大电路，如图1所示，该放大电路包括放大器11和电流跟随器12，电流跟随器12的输入端作为放大电路的输入端，电 流跟随器12的输出端与放大器11的输入端连接，放大器11的输出端作为放大电路的输出端。
本实施例中，将电流跟随器12和放大器11级联构成放大电路，用于放大电流跟随器12的输入端接收到的电信号。由于放大电路中连接有电流跟随器12，通过电流跟随器12的跨导可以减小放大器11噪声带宽内的增益，从而降低放大器11的等效输入噪声到输出的增益，达到减小放大器11输出噪声的目的，减小等效对地电容对SNR的影响。
在一个实施例中，放大器11可以是跨阻放大器(TIA)，也可以是其他类型的放大器，此处不做限制。
在一个实施例中，电流跟随器12如图2所示，包括第一负载子模块21、第一开关子模块22和第二负载子模块23；第一负载子模块21的第一端连接第一电源信号线(VDD1)，第一负载子模块21的第二端与第一开关子模块22的第一端连接，第一开关子模块22的第二端与第二负载子模块23的第一端连接，第二负载子模块23的第二端接地(VSS)，第一开关子模块22的控制端连接第一偏置信号输出端(Vb1)；第一开关子模块22的第一端作为电流跟随器12的输入端，第一开关子模块22的第二端作为电流跟随器12的输出端。
在一个实施例中，第一开关子模块22为P型晶体管，第一开关子模块22的第一端为P型晶体管的漏级，第一开关子模块22的第二端为P型晶体管的源级。
需要说明的是，本领域技术人员可以理解，实际应用中，第一负载子模块21和第二负载子模块23可以是各种阻性器件，例如，由晶体管等器件构成的电流源或高阻电阻等，本实施方式不限制第一负载子模块21和第二负载子模 块23的器件类型。
需要说明的是，本领域技术人员可以理解，实际应用中，第一开关子模块22也可以是其他器件，本实施例不限制第一开关子模块22的器件类型。
需要说明的是，本领域技术人员可以理解，实际应用中，第一电源信号线(VDD1)输出的电压值可以根据放大电路的应用场景确定，本实施例不做限制。
在一个实施例中，第一偏置信号输出端为第一偏置信号发生模块的输出端(Vb1)，如图3所示，包括：第二开关子模块31和第三负载子模块32；第二开关子模块31的第一端连接第二电源信号线(VDD2)，第二开关子模块31的控制端与第二开关子模块31的第二端连接，第二开关子模块31的第二端与第三负载子模块32的第一端连接，第三负载子模块32的第二端接地(VSS)，第二开关子模块M3的控制端和第二开关子模块M3的第二端之间的连接处作为第一偏置信号发生模块的输出端(Vb1)。
在一个实施例中，第二开关子模块31的第一端通过第四负载子模块与第二电源信号线(VDD2)连接。假设，第四负载子模块为晶体管，第一偏置信号发生模块的电路示意图如图4所示。其中，VDD2表示第二电源信号线，M2表示第二开关子模块，S3表示第三负载子模块，M3表示第四负载子模块，Vb1表示第一偏置信号发生模块的输出端，VSS表示接地端。
需要说明的是，实际应用中，第三负载子模块也可以是N型晶体管或其他阻性器件，本实施方式不限制第三负载子模块的结构类型。
需要说明的是，本领域技术人员可以理解，实际应用中，第一偏置信号端输出的第一偏置信号大小可以根据实际应用设置，第二电源信号线(VDD2) 输出的电压大小、第三负载子模块的阻值大小等可以根据第一偏置信号大小设置，本实施例不做限制。
需要说明的是，本领域技术人员可以理解，实际应用中，第一偏置信号发生模块也可以采用其他电路结构，本实施例仅为举例说明，不限制第一偏置信号发生模块的具体电路结构。
在一个实施例中，第一开关子模块22为晶体管，电源跟随器为共栅放大器。通过共栅放大器的跨导降低放大器11的等效输入噪声到输出的增益，达到减小放大器11的输出噪声的目的。
在一个实施例中，第一负载子模块21和第二负载子模块23为负载，可以是电流源，也可以为其他可等效于电流源的其他电路。假设，第一开关子模块22为晶体管，电流跟随器12和放大器11的等效电路图如图5所示，以图4所示第一偏置信号发生模块为例时，放大电路和第一偏置信号发生模块的连接示意图如图6所示。其中，VDD1表示第一电源信号线，VSS表示接地端，S1表示第一负载子模块，M1表示第一开关子模块，Vb1表示第一偏置信号输出端，S2表示第二负载子模块，Vin表示电流跟随器的输入端，Vout表示电流跟随器的输出端，R 1表示跨阻放大器的反馈电阻，C表示跨阻放大器的反馈电容，O表示跨阻放大器的运算放大器，N表示运算放大器的等效输入噪声，VCM表示共模信号，V表示运算放大器的输出。由于S1和S2对等效输入噪声到跨阻放大器的输出端的增益的影响较小，等效输入噪声到跨阻放大器的输出端的增益可约等于
Figure PCTCN2019120753-appb-000001
其中，s表示拉普拉斯的复变量，Cc表示等效对地电容，g m表示电流跟随器12的跨导，R ds表示第一开关子模块22的漏级到源级的电阻。相对于单独使用放大器11的放大电路，增益缩小了g mR ds倍，所以， 可以用g mR ds抵消等效对地电容Cc的增加，减小了最终的输出噪声，从而避免SNR下降。
需要说明的是，本领域技术人员可以理解，实际应用中，电流跟随器12可以采用其他具有相同功能的电路或器件，本实施例不限制电流跟随器12的电路结构。
以下对第一负载子模块21和第二负载子模块23中的任意一个或每个负载子模块的电路结构进行举例说明。
在第一个例子中，第一负载子模块21和第二负载子模块23中的任意一个或每个负载子模块包括：开关元件，开关元件的第一端作为负载子模块的第一端，开关元件的第二端作为负载子模块的第二端，开关元件的控制端连接第二偏置信号输出端。其中，开关元件可以是晶体管或其他器件。例如，第一开关子模块22为晶体管，其控制端连接第一偏置信号端第一负载子模块21为开关元件，开关元件为晶体管，其控制端连接第二偏置信号输出端，电流跟随器12的电路示意图如图7所示，其中，VDD1表示第一电源信号线，VSS表示接地端，M1表示第一开关子模块，M4表示开关元件，Vb1表示第一偏置信号端，Vb2表示第二偏置信号端，S2表示第二负载子模块。
需要说明的是，第二负载子模块23也可以是N型晶体管或其他阻性器件，本实施方式不作限制。
在第二个例子中，第一负载子模块21和第二负载子模块23中的任意一个或两个负载子模块包括：开关元件和电阻元件，电阻元件的第一端作为负载子模块的第一端，电阻元件的第二端与开关元件的第一端连接，开关元件的第二端作为负载子模块的第二端，开关元件的控制端连接第二偏置信号输出端。 其中，开关元件可以是晶体管或其他器件。例如，第一开关子模块22为晶体管，其控制端连接第一偏置信号输出端，第一负载子模块21为开关元件，开关元件为晶体管，其控制端连接第二偏置信号输出端，电流跟随器12的电路示意图如图8所示，其中，VDD1表示第一电源信号线，VSS表示接地端，M1表示第一开关子模块，M4表示开关元件，R2表示电阻元件，Vb1表示第一偏置信号端，Vb2表示第二偏置信号端，S2表示第二负载子模块。
值得一提的是，开关元件通过电阻元件连接电源，可以使得放大电路的低频噪声更小。
需要说明的是，本领域技术人员可以理解，实际应用中，第一负载子模块21和第二负载子模块23的电路结构可以相同，也可以不同，除上述例子以外，第一负载子模块21和第二负载子模块23也可以采用其他电路结构，本实施例不限制第一负载子模块21和第二负载子模块23的具体电路结构。
在一个实施例中，第二偏置信号输出端为第二偏置信号发生模块的输出端。如图9所示，第二偏置信号发生模块包括：第四开关子模块91和第五负载子模块92，第四开关子模块91的第一端与第三电源信号线(VDD3)连接，第四开关子模块91的第二端与第五负载子模块92的第一端连接，第五负载子模块92的第二端接地(VSS)，第四开关子模块91的控制端和第五负载子模块92的第一端连接，第四开关子模块的控制端作为第二偏置信号输出端(Vb2)。
需要说明的是，本领域技术人员可以理解，实际应用中，第三电源信号线(VDD3)输出的电压值可以根据放大电路的应用场景确定，本实施例不做限制。
例如，在一个实施例中，第四开关子模块91的第二端通过第五开关子模 块与第五负载子模块92的第一端连接。假设，第二开关子模块、第四开关子模块和第五开关子模块为晶体管，第一偏置信号发生模块和第二偏置信号发生模块的电路示意图如图10所示。其中，VDD2表示第二电源信号线，VDD3表示第三电源信号线，VSS表示接地端，M2表示第二开关子模块，M3表示第四负载子模块，M5表示第四开关子模块，M6表示第五开关子模块，S3表示第三负载子模块，S4表示第五负载子模块，Vb1表示第一偏置信号输出端，Vb2表示第二偏置信号输出端。
需要说明的是，本领域技术人员可以理解，实际应用中，第二偏置信号发生模块也可以采用其他电路结构，本实施例仅为举例说明。
本实施例相对于现有技术而言，采用电流跟随器12和放大器11级联构成放大电路，通过电流跟随器12的跨导减小放大器11噪声带宽内的增益，从而降低放大器11的等效输入噪声到输出的增益，达到减小放大器11输出噪声的目的，减少了等效对地电容对SNR的影响。
本申请第二实施例涉及一种放大电路，本实施例与第一实施例大致相同，主要说明了该放大电路在触控装置中的应用。
具体地说，放大电路和触控装置的驱动芯片的连接示意图如图11所示，放大电路81的输入端通过电流转换模块82与待测电容83连接，放大电路81的输出端通过模数转换器84与控制器85连接；其中，电流转换模块82用于将待测电容83的电容变化转换为电流变化。
在一个实施例中，放大电路和驱动芯片的电路示意图如图12所示，其中，Cx表示待测电容，S1表示第一负载子模块，M1表示第一开关子模块，S2表示第二负载子模块，CTC表示电流转换模块，TIA表示跨阻放大器，Vb1表示 第一偏置信号输出端，V表示放大电路的输出端。图12中，电流转换模块将待测电容的变化转换为电流变化，通过电流跟随器12传输至跨阻放大器，通过跨阻放大器的反馈电容和反馈电阻将电流转化为电压。
需要说明的是，本领域技术人员可以理解，实际应用中，除图12所示的跨阻放大器外，还可以选择其他电路结构的跨阻放大器，本实施例不限制跨阻放大器的电路结构。
在一个实施例中，放大器11的输出端和模数转换器之间的连接关系如图13所示，放大电路81的输出端依次通过滤波器86和增益放大器87与模数转换器84连接。即放大电路81的输出端与滤波器86连接，滤波器86与增益放大器87连接，增益放大器87与模数转换器84连接。其中，滤波器可以是抗混叠滤波器，增益放大器可以是可变增益放大器。
本实施例相对于现有技术而言，将放大电路应用于触摸屏驱动芯片中，可以在维持原系统方案的基础上，提升原方案的SNR性能。采用电流跟随器12和放大器11级联构成放大电路，通过电流跟随器12的跨导减小放大器11噪声带宽内的增益，从而降低放大器11的等效输入噪声到输出的增益，达到减小放大器11输出噪声的目的，减少了等效对地电容对SNR的影响。
本申请第三实施例涉及一种放大电路，本实施例与第一实施例大致相同，主要说明了该放大电路在检测装置中的应用。
具体地说，检测装置包括发光模块和光电感应模块，放大电路的输入端与光电感应模块连接，放大电路的输出端通过模数转换器与控制器连接。
在一个实施例中，应用该放大电路的检测装置的电路示意图如图14所示，其中，LED DRV表示LED驱动模块，LED表示发光二极管，VDD LED表示 发光二极管的驱动电源，TS表示待测物体表面，PD表示光电感应模块，S1表示第一负载子模块，M1表示第一开关子模块，S2表示第二负载子模块，TIA表示跨阻放大器，Vb1表示第一偏置信号输出端，V表示放大电路的输出端。图14中，LED DRV驱动LED发光，投射到待测物体表面，PD接收LED发射过来的光产生光电流，光电流通过电流跟随器12传输到跨阻放大器，通过跨阻放大器的反馈电容和反馈电阻形成电压输出。
需要说明的是，检测装置可以是心率检测装置，也可以是其他检测装置，本实施例不做限制。
本实施例相对于现有技术而言，将放大电路应用于检测装置中，可以在维持原系统方案的基础上，提升原方案的SNR性能。采用电流跟随器12和放大器11级联构成放大电路，通过电流跟随器12的跨导减小放大器11噪声带宽内的增益，从而降低放大器11的等效输入噪声到输出的增益，达到减小放大器11输出噪声的目的，减少了等效对地电容对SNR的影响。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。

Claims (10)

  1. 一种放大电路，其特征在于，包括：放大器和电流跟随器；
    所述电流跟随器的输入端作为所述放大电路的输入端，所述电流跟随器的输出端与所述放大器的输入端连接，所述放大器的输出端作为所述放大电路的输出端。
  2. 如权利要求1所述的放大电路，其特征在于，所述电流跟随器包括第一负载子模块、第一开关子模块和第二负载子模块；
    所述第一负载子模块的第一端连接第一电源信号线，所述第一负载子模块的第二端与所述第一开关子模块的第一端连接，所述第一开关子模块的第二端与所述第二负载子模块的第一端连接，所述第二负载子模块的第二端接地，所述第一开关子模块的控制端连接第一偏置信号输出端；
    所述第一开关子模块的第一端作为所述电流跟随器的输入端，所述第一开关子模块的第二端作为所述电流跟随器的输出端。
  3. 如权利要求1或2所述的放大电路，其特征在于，所述放大电路的输入端通过电流转换模块与待测电容连接，所述放大电路的输出端通过模数转换器与控制器连接；其中，所述电流转换模块用于将所述待测电容的电容变化转换为电流变化。
  4. 如权利要求3所述的放大电路，其特征在于，所述放大电路的输出端依次通过滤波器和增益放大器与所述模数转换器连接。
  5. 如权利要求1或2所述的放大电路，其特征在于，所述放大电路的输入端与光电感应模块连接，所述放大电路的输出端通过模数转换器与控制器连接。
  6. 如权利要求1所述的放大电路，其特征在于，所述放大器为跨阻放大器。
  7. 如权利要求2所述的放大电路，其特征在于，所述第一偏置信号输出端为第一偏置信号发生模块的输出端，所述第一偏置信号发生模块包括：第二开关子模块和第三负载子模块；
    所述第二开关子模块的第一端连接第二电源信号线，所述第二开关子模块的控制端与所述第二开关子模块的第二端连接，所述第二开关子模块的第二端与所述第三负载子模块的第一端连接，所述第三负载子模块的第二端接地，所述第二开关子模块的控制端和所述第二开关子模块的第二端之间的连接处作为所述第一偏置信号发生模块的输出端。
  8. 如权利要求2所述的放大电路，其特征在于，所述第一负载子模块和所述第二负载子模块中的任意一个或每个负载子模块包括：开关元件，所述开关元件的第一端作为所述负载子模块的第一端，所述开关元件的第二端作为所述负载子模块的第二端，所述开关元件的控制端连接第二偏置信号输出端。
  9. 如权利要求2所述的放大电路，其特征在于，所述第一负载子模块和所述第二负载子模块中的任意一个或两个负载子模块包括：开关元件和电阻元件，所述电阻元件的第一端作为所述负载子模块的第一端，所述电阻元件的第二端与所述开关元件的第一端连接，所述开关元件的第二端作为所述负载子模块的第二端，所述开关元件的控制端连接第二偏置信号输出端。
  10. 如权利要求8或9所述的放大电路，其特征在于，所述第二偏置信号输出端为第二偏置信号发生模块的输出端，所述第二偏置信号发生模块包括：第四开关子模块和第五负载子模块，所述第四开关子模块的第一端与第三电源信号线连接，所述第四开关子模块的第二端与所述第五负载子模块的第一端连接，所述第五负载子模块的第二端接地，所述第四开关子模块的控制端和所述 第五负载子模块的第一端连接，所述第四开关子模块的控制端作为第二偏置信号输出端。
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