WO2021093346A1

WO2021093346A1 - Chip synchronization method and related apparatus

Info

Publication number: WO2021093346A1
Application number: PCT/CN2020/100392
Authority: WO
Inventors: 聂瑞杰; 雷张伟; 王文昌
Original assignee: 华为技术有限公司
Priority date: 2019-11-15
Filing date: 2020-07-06
Publication date: 2021-05-20
Also published as: CN112817368A; CN112817368B

Abstract

A chip synchronization method and a related apparatus, for use in reducing the complexity of chip design and layout. The method comprises: a first chip continuously sends a synchronization signal to a second chip (201); the first chip adds a rising edge or a falling edge to the synchronization signal, and after waiting for a first offset time (S2), enters a preset working mode (202); the second chip continuously receives the synchronization signal sent by the first chip (203), and after the received synchronization signal has a rising or falling edge, after waiting for a second offset time (S3), the second chip enters a preset working mode (204). According to the method, only one chip pin needs to be occupied to send a synchronization signal, so that multiple chips can enter the same working mode synchronously, thereby effectively reducing the complexity of chip design and layout.

Description

Chip synchronization method and related device

This application claims the priority of a Chinese patent application filed with the Chinese Patent Office on November 15, 2019, the application number is 201911124104.2, and the invention title is "A chip synchronization method and related device", the entire content of which is incorporated herein by reference. Applying.

Technical field

This application relates to the field of computer technology, and in particular to a method for synchronizing chips and related devices.

Background technique

At present, in many occasions, multiple chips are required to perform synchronous work. For example, in a laser detection and ranging (light detection and ranging (LIDAR) signal processing system, multiple cascaded chips are often required to achieve laser detection and Ranging.

However, the current inter-chip synchronization technology is relatively complicated, and requires too many chip pins and logic resources to implement multiple chips to enter a certain working mode synchronously, which increases the difficulty of chip design and layout.

Summary of the invention

The embodiment of the application provides a chip synchronization method and related device. The master chip adds a rising edge or a falling edge to the synchronization signal sent to the slave chip to trigger the slave chip to enter the working mode, and the master chip waits for a certain period of time. Then enter the working mode to ensure that the master chip and the slave chip can enter the working mode at the same time. In this solution, only one chip pin is needed to send a synchronization signal, and multiple chips can enter the same working mode synchronously. Reduce the complexity of chip design and layout.

The first aspect of the embodiments of the present application provides a method for synchronizing chips. The method includes: in a scenario where multiple chips need to work synchronously, the first chip may continuously send a synchronization signal to the second chip through the connection line between the chip pins. Specifically, the first chip may be a master chip, the second chip may be a slave chip, and the synchronization signal is a rectangular wave signal; while the first chip continues to send the synchronization signal, the first chip may be in the synchronization signal A rising edge or a falling edge is added to the synchronizing signal so that the second chip can enter the preset operating mode according to the rising or falling edge in the synchronization signal, and the first chip enters the preset operating mode after waiting for the first offset time, In order to realize that the first chip and the second chip enter the same working mode synchronously.

In the embodiment of the present application, the master chip adds a rising edge or a falling edge to the synchronization signal sent to the slave chip to trigger the slave chip to enter the working mode, and the master chip waits for a certain period of time before entering the working mode, ensuring that the master chip and the The slave chip can enter the working mode at the same time point, and in this solution, only one chip pin is needed to send the synchronization signal, so that multiple chips can enter the same working mode synchronously, which reduces the complexity of chip design and layout. degree.

With reference to the above first aspect, in the first possible implementation of the first aspect, the first chip adds a rising edge or a falling edge to the synchronization signal, and after waiting for the first offset time, the first chip enters the preset operation The mode includes: the first chip adds a rising edge to the synchronization signal, and after waiting for the first offset time, the first chip enters the first working mode; the first chip adds a falling edge to the synchronization signal, and is waiting for the first After the offset time, the first chip enters the second working mode, where the preset working mode includes the first working mode and the second working mode; that is, the rising edge has a corresponding relationship with the first working mode, and the falling edge is The second working mode has a corresponding relationship. The first chip can determine the working mode entered according to the type of the added signal edge or realize the switching of the working mode by changing the added signal edge.

In the embodiment of the application, the master chip adds a rising edge or a falling edge to the synchronization signal sent to the slave chip to trigger the slave chip to enter different working modes or realize the switching of the working mode, and the synchronization between multiple chips is realized through a single synchronization signal. Switching the working mode reduces the complexity of chip design and layout.

In combination with the first possible implementation of the first aspect, in the second possible implementation of the first aspect, when the number of times that the first chip adds rising edges to the synchronization signal reaches a preset value, the first chip stops entering The first working mode, that is, after the first chip enters the first working mode for a preset number of times, the first chip no longer enters the first working mode; or, the number of times that the first chip adds a falling edge to the synchronization signal reaches When the value is preset, the first chip stops entering the second working mode, that is, after the number of times the first chip enters the second working mode reaches the preset value, the first chip no longer enters the second working mode.

In the embodiment of the present application, after the number of times the chip enters a certain working mode reaches a preset value, the chip no longer enters the working mode, thereby saving the resource cost of the chip and improving the flexibility of the solution.

In combination with the above-mentioned first aspect, in the third possible implementation of the first aspect, in the case that the first chip and the second chip are chips in the laser detection and ranging system, the first chip adds the rising signal to the synchronization signal. Edge or falling edge, and after waiting for the first offset time, the first chip enters the preset working mode, including: the first chip adds the first signal edge to the synchronization signal, and after waiting for the first offset time, the The first chip enters the laser detection and ranging mode; the first chip adds the second signal edge to the synchronization signal, and after waiting for the first offset time, the first chip switches from the laser detection and ranging mode to the calibration mode , The preset working mode includes laser detection and ranging mode and calibration and calibration mode; wherein, the first signal edge may be a rising edge and the second signal edge may be a falling edge, or the first signal edge may be a falling edge and the first signal edge may be a falling edge. The second signal is a rising edge.

In the embodiment of the present application, the master chip determines the working mode entered according to the type of the signal edge added to the synchronization signal, which can realize that the master chip and the slave chip enter the laser detection and ranging mode at the same time, and switch from the laser detection and ranging mode. To the calibration calibration mode, the flexibility of the scheme is improved.

In combination with the above-mentioned first aspect, in the fourth possible implementation of the first aspect, the first chip adds a rising edge or a falling edge to the synchronization signal, and after waiting for the first offset time, the first chip enters the preset operation The mode includes: if the first signal edge added by the first chip to the synchronization signal is a rising edge, then after the first chip adds the rising edge to the synchronization signal, the first chip waits for the first offset time, Enter the calibration calibration mode, and when the first chip adds a falling edge to the synchronization signal, the first chip will switch from the calibration calibration mode to the laser detection and ranging mode after waiting for the second offset time; if the first chip is in synchronization The first signal edge added to the signal is the falling edge, then after the first chip adds the falling edge to the synchronization signal, the first chip enters the calibration mode after waiting for the first offset time, and when the first chip After adding the falling edge to the synchronization signal, the first chip switches from the calibration calibration mode to the laser detection and ranging mode after waiting for the second offset time; the preset working modes include calibration calibration mode and laser detection and ranging mode mode. That is to say, the first chip determines the corresponding relationship between the signal edge and the working mode according to the type of the first signal edge added to the synchronization signal; the first signal edge added to the synchronization signal is the rising edge In this case, it is determined that there is a corresponding relationship between the rising edge and the calibration mode, and the falling edge has a corresponding relationship with the laser detection and ranging mode; when the first signal edge added to the synchronization signal is a falling edge Next, it is determined that there is a corresponding relationship between the falling edge and the calibration mode, and the rising edge has a corresponding relationship with the laser detection and ranging mode.

In the embodiment of this application, the master chip determines the corresponding relationship between the signal edge and the working mode according to the type of the first signal edge added to the synchronization signal, which can ensure that under different circumstances, the master chip and the first one that enters the slave chip The working mode is a preset working mode, which improves the flexibility of the scheme.

The second aspect of the embodiments of the present application provides a chip synchronization method, which includes: in a scenario where multiple chips need to work synchronously, the second chip can continuously receive the synchronization signal sent by the first chip. Specifically, the first chip can It is the master chip, the second chip can be a slave chip, and the synchronization signal is a rectangular wave signal; when a rising or falling edge occurs in the synchronization signal received by the second chip, the second chip waits for the second offset time , The second chip enters the preset working mode, so that the first chip and the second chip enter the same working mode synchronously.

In the embodiment of this application, the slave chip enters the working mode according to the rising edge or the falling edge of the synchronization signal sent by the master chip, and the slave chip enters the working mode after waiting for a certain period of time, ensuring that the master chip and the slave chip can Enter the working mode at the same time point, and in this solution, only one chip pin is needed to send a synchronization signal, so that multiple chips can enter the same working mode synchronously, which reduces the complexity of chip design and layout.

In combination with the above second aspect, in the first possible implementation manner of the second aspect, when a rising or falling edge occurs in the synchronization signal received by the second chip, the second chip waits for the second offset time, and then the second chip waits for the second offset time. The second chip enters the preset working mode, including: when a rising edge appears in the synchronization signal received by the second chip, the second chip enters the first working mode after waiting for the second offset time; when the second chip receives After the falling edge appears in the synchronization signal, the second chip enters the second operating mode after waiting for the second offset time. The preset operating mode includes the first operating mode and the second operating mode; that is, the rising edge and the second operating mode The first operating mode has a corresponding relationship, and the falling edge has a corresponding relationship with the second operating mode. The second chip can determine the entered operating mode or switch the operating mode according to the type of the signal edge in the synchronization signal.

In the embodiment of the present application, the slave chip can determine the working mode it enters or realize the switching of the working mode according to the type of the signal edge in the synchronization signal. A single synchronization signal realizes the synchronous switching of the working mode among multiple chips, which reduces the chip design and layout. The complexity of the time.

In combination with the above-mentioned first possible implementation of the second aspect, in the second possible implementation of the second aspect, when the number of occurrences of rising edges in the synchronization signal received by the second chip reaches a preset value, the second chip Stop entering the first working mode, that is, after the second chip enters the first working mode for a preset number of times, the second chip no longer enters the first working mode; or, the falling edge of the synchronization signal received by the second chip When the number of occurrences reaches the preset value, the second chip stops entering the second working mode, that is, after the number of times the second chip enters the second working mode reaches the preset value, the second chip no longer enters the second working mode.

In combination with the second aspect described above, in the third possible implementation manner of the second aspect, when a rising or falling edge occurs in the synchronization signal received by the second chip, the second chip waits for the second offset time, and then the second chip waits for the second offset time. The second chip enters the preset working mode, which specifically includes: when the first signal edge appears in the synchronization signal received by the second chip, the second chip enters the laser detection and ranging mode after waiting for the second offset time; and After the second signal edge appears in the synchronization signal received by the second chip, the second chip switches from the laser detection and ranging mode to the calibration mode after waiting for the second offset time. The preset working mode includes Laser detection and ranging mode and calibration mode; wherein, the first signal edge is a rising edge and the second signal edge is a falling edge, or the first signal edge is a falling edge and the second signal edge is a rising edge.

In combination with the above second aspect, in the fourth possible implementation manner of the second aspect, after a rising edge or a falling edge appears in the synchronization signal received by the second chip, the second chip waits for the second offset time, the first The second chip enters the preset working mode, including: if the first signal edge appearing in the synchronization signal received by the second chip is a rising edge, then after the rising edge appears in the synchronization signal received by the second chip, the second chip After waiting for the second offset time, enter the calibration calibration mode, and after a falling edge appears in the synchronization signal received by the second chip, the second chip switches from the calibration calibration mode to the laser detection after waiting for the second offset time And ranging mode; if the first signal edge that appears in the synchronization signal received by the second chip is a falling edge, then after the falling edge appears in the synchronization signal received by the second chip, the second chip is waiting for the second offset After the shift time, enter the calibration calibration mode, and when a rising edge appears in the synchronization signal received by the second chip, the second chip will switch from the calibration calibration mode to the laser detection and ranging mode after waiting for the second offset time. Detection and ranging mode; among them, the preset working mode includes calibration mode and laser detection and ranging mode. That is to say, the second chip determines the corresponding relationship between the signal edge and the working mode according to the type of the first signal edge in the received synchronization signal; in the case where the first signal edge in the synchronization signal is a rising edge Under the condition that the rising edge and the calibration mode have a corresponding relationship, and the falling edge has a corresponding relationship with the laser detection and ranging mode; when the first signal edge in the synchronization signal is a falling edge, then It is determined that the falling edge has a corresponding relationship with the calibration mode, and the rising edge has a corresponding relationship with the laser detection and ranging mode.

In the embodiment of the present application, the slave chip determines the corresponding relationship between the signal edge and the working mode according to the type of the first signal edge in the received synchronization signal, which can ensure that the master chip and the slave chip enter the first signal edge under different conditions. A working mode is a preset working mode, which improves the flexibility of the scheme.

The third aspect of the embodiments of the present application provides a chip, including: a sending unit, configured to continuously send a synchronization signal to the second chip, the synchronization signal is a rectangular wave signal; and a processing unit, configured to add a rising edge or a falling edge to the synchronization signal And after waiting for the first offset time, it enters the preset working mode.

With reference to the above third aspect, in the first possible implementation of the third aspect, the processing unit is further configured to add a rising edge to the synchronization signal, and enter the first working mode after waiting for the first offset time; processing The unit is also used to add a falling edge to the synchronization signal, and after waiting for the first offset time, enter the second working mode, wherein the preset working mode includes the first working mode and the second working mode.

In combination with the first possible implementation manner of the third aspect described above, in the second possible implementation manner of the third aspect, the processing unit is further configured to stop entering the first aspect when the number of rising edges added to the synchronization signal reaches a preset value. A working mode; or, the processing unit is further configured to stop entering the second working mode when the number of times of adding falling edges to the synchronization signal reaches a preset value.

In combination with the above third aspect, in the third possible implementation of the third aspect, the processing unit is further configured to add the first signal edge to the synchronization signal, and after waiting for the first offset time, enter the laser detection and ranging Mode; the processing unit is also used to add a second signal edge to the synchronization signal, and after waiting for the first offset time, switch from the laser detection and ranging mode to the calibration calibration mode, the preset working mode includes laser detection and ranging Mode and calibration mode; wherein, the first signal edge is a rising edge and the second signal edge is a falling edge, or the first signal edge is a falling edge and the second signal edge is a rising edge.

In combination with the above third aspect, in the fourth possible implementation of the third aspect, if the first signal edge added by the processing unit to the synchronization signal is a rising edge, the processing unit enters calibration after waiting for the first offset time Calibration mode, and when the processing unit adds a falling edge to the synchronization signal, the processing unit switches from the calibration calibration mode to the laser detection and ranging mode after waiting for the first offset time; if the processing unit adds the first offset in the synchronization signal One signal edge is a falling edge. After the processing unit waits for the first offset time, it enters the calibration calibration mode, and when the processing unit adds the falling edge to the synchronization signal, the processing unit waits for the first offset time and then starts the calibration. The calibration mode is switched to laser detection and ranging mode; among them, the preset working mode includes calibration calibration mode and laser detection and ranging mode.

A fourth aspect of the embodiments of the present application provides a chip, including: a receiving unit, configured to continuously receive a synchronization signal sent by a first chip, the synchronization signal is a rectangular wave signal; a processing unit, used when the synchronization signal received by the receiving unit After the rising edge or the falling edge occurs, after waiting for the second offset time, the preset working mode is entered.

With reference to the above fourth aspect, in the first possible implementation of the fourth aspect, after a rising edge appears in the synchronization signal received by the receiving unit, the processing unit is further configured to enter the first after waiting for the second offset time. Operating mode;

After a falling edge occurs in the synchronization signal received by the receiving unit, the processing unit is further configured to enter the second working mode after waiting for the second offset time, wherein the preset working mode includes the first working mode and the second working mode .

In combination with the first possible implementation manner of the fourth aspect, in the second possible implementation manner of the fourth aspect, when the number of occurrences of rising edges in the synchronization signal received by the receiving unit reaches a preset value, the processing unit also uses Stop entering the first working mode;

Or, when the number of occurrences of falling edges in the synchronization signal received by the receiving unit reaches a preset value, the processing unit stops entering the second working mode.

In combination with the fourth aspect described above, in the third possible implementation manner of the fourth aspect, after the first signal edge appears in the synchronization signal received by the receiving unit, the processing unit enters the laser detection and detection after waiting for the second offset time. Ranging mode; when the second signal edge appears in the synchronization signal received by the receiving unit, the processing unit switches from laser detection and ranging mode to calibration mode after waiting for the second offset time. The preset working mode includes laser Detection and ranging mode and calibration calibration mode; wherein the first signal edge is a rising edge and the second signal edge is a falling edge, or the first signal edge is a falling edge and the second signal edge is a rising edge.

With reference to the above fourth aspect, in the fourth possible implementation manner of the fourth aspect, if the first signal edge that appears in the synchronization signal received by the receiving unit is a rising edge, the processing unit waits for the second offset time, Enter the calibration calibration mode, and when there is a falling edge in the synchronization signal received by the receiving unit, the processing unit will switch from the calibration calibration mode to the laser detection and ranging mode after waiting for the second offset time; if the receiving unit receives the signal The first signal edge that appears in the synchronization signal is the falling edge. After the processing unit waits for the second offset time, it enters the calibration calibration mode, and when the rising edge appears in the synchronization signal received by the receiving unit, the processing unit is waiting for the first signal edge. 2. After the offset time, switch from the calibration calibration mode to the laser detection and ranging mode; among them, the preset working mode includes the calibration calibration mode and the laser detection and ranging mode.

The fifth aspect of the embodiments of the present application provides a chip including a processor and a memory, and the processor is coupled with the memory, and is configured to read and execute instructions stored in the memory to implement the steps in the first aspect.

The sixth aspect of the embodiments of the present application provides a chip including a processor and a memory, and the processor is coupled with the memory, and is configured to read and execute instructions stored in the memory to implement the steps in the second aspect.

A seventh aspect of the embodiments of the present application provides a chip system, which is characterized in that it includes the chip in the third aspect and the chip in the fourth aspect.

It can be seen from the above technical solutions that the embodiments of the present application have the following advantages:

Description of the drawings

FIG. 1 is a schematic diagram of an application scenario of a chip synchronization method provided by an embodiment of the application;

FIG. 2 is a schematic flowchart of a chip synchronization method provided by an embodiment of the application;

FIG. 3 is a schematic diagram of a timing sequence of a synchronization signal provided by an embodiment of the application;

FIG. 4 is a schematic diagram of a working mode switching provided by an embodiment of the application;

FIG. 5 is another schematic diagram of a work mode switching provided by an embodiment of the application;

FIG. 6 is another schematic diagram of a working mode switching provided by an embodiment of the application;

FIG. 7 is another schematic diagram of a work mode switching provided by an embodiment of the application;

FIG. 8 is a schematic diagram of a circuit structure of a second chip provided by an embodiment of the application;

FIG. 9 is a schematic structural diagram of a first chip provided by an embodiment of the application;

FIG. 10 is a schematic structural diagram of a second chip provided by an embodiment of the application.

Detailed ways

In order to make the purpose, technical solutions and advantages of this application clearer, the following describes the embodiments of this application in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. . A person of ordinary skill in the art knows that with the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are equally applicable to similar technical problems.

The terms "first" and "second" in the specification and claims of the application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific sequence or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments described herein can be implemented in a sequence other than the content illustrated or described herein. In addition, the terms "including" and "having" and any variations of them are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or modules is not necessarily limited to those clearly listed. Those steps or modules may include other steps or modules that are not clearly listed or are inherent to these processes, methods, products, or equipment. The naming or numbering of steps appearing in this application does not mean that the steps in the method flow must be executed in the time/logical sequence indicated by the naming or numbering. The named or numbered process steps can be implemented according to the The technical purpose changes the execution order, as long as the same or similar technical effects can be achieved. The division of modules presented in this application is a logical division. In actual applications, there may be other divisions. For example, multiple modules can be combined or integrated in another system, or some features can be ignored In addition, the displayed or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, and the indirect coupling or communication connection between the modules may be electrical or other similar forms. There are no restrictions in the application. In addition, the modules or sub-modules described as separate components may or may not be physically separated, may or may not be physical modules, or may be distributed to multiple circuit modules, and some or all of them may be selected according to actual needs. Module to achieve the purpose of this application program.

At present, in many occasions, multiple chips are usually required to perform synchronous work to ensure processing performance; for example, in a laser detection and ranging (light detection and ranging, LIDAR) signal processing system, multiple chips are often required to work simultaneously To achieve laser detection and ranging.

In the LIDAR signal processing system, multiple synchronized chips must have a strict synchronization relationship in time to ensure the accuracy of the measurement results, and the accuracy of such synchronization often needs to reach the order of nanoseconds or even picoseconds. The current inter-chip synchronization technology is relatively complicated. Generally, it uses the same source clock and high-precision synchronization control trigger signal, or uses a complex time synchronization protocol to achieve such strict time synchronization between multiple chips; in addition, in the master-slave When synchronous mode switching and shutdown enable are required between chips, the complexity will be further increased. These current inter-chip synchronization methods require too many control signals and occupy too many chip pins and logic resources.

In view of this, the embodiment of the present application provides a simpler synchronization method. By triggering the corresponding operating mode according to different trigger signals in the synchronization signal, only one chip pin is needed to send the synchronization signal, and multiple synchronization signals can be realized. Each chip enters a certain working mode synchronously to achieve the purpose of multiple chips working synchronously, which simplifies the design and implementation of a multi-chip cascade system.

For ease of understanding, the application scenario of the chip synchronization method provided by the embodiment of the present application will be introduced below in conjunction with FIG. 1. Please refer to FIG. 1, which is a schematic diagram of an application scenario of the chip synchronization method provided by an embodiment of the application. As shown in Fig. 1, the application scenario may specifically include a master chip and one or more slave chips (the master chip, slave chip 1 and slave chip 2 in Fig. 1), where the master chip and one or more slave chips Chip connection. When working synchronously, the master chip generates a synchronization signal and continuously sends the synchronization signal to one or more slave chips connected to it. The master chip adds a rising or falling edge to the synchronization signal and waits for the first offset time. , Enter the preset working mode; the slave chip continues to receive the synchronization signal, after a rising or falling edge appears in the received synchronization signal, wait for the second offset time to enter the working mode, so as to achieve synchronization between the master and slave chips.

Refer to FIG. 2. FIG. 2 is a schematic flowchart of a chip synchronization method provided by an embodiment of the application; as shown in FIG. 2, a chip synchronization method provided by an embodiment of the application includes:

201. The first chip continuously sends a synchronization signal to the second chip, and the synchronization signal is a rectangular wave signal;

In this embodiment, the first chip may specifically be the master chip in the multi-chip system, and the second chip may specifically be the slave chip in the multi-chip system, wherein the pins of the first chip and the pins of the second chip are connected through Wire connection to realize the connection between the first chip and the second chip. After the first chip generates the synchronization signal, the first chip can continuously send the synchronization signal to the second chip through the connection line between the pins.

202. The first chip adds a rising edge or a falling edge to the synchronization signal, and after waiting for the first offset time, the first chip enters a preset operating mode;

In this embodiment, when the first chip and the second chip need to work synchronously, the first chip can add a rising edge or a falling edge to the synchronization signal continuously sent to the second chip to trigger the second chip to enter synchronously with it. Preset working mode. Considering that there is a transmission delay between the first chip and the second chip, that is, there is a certain delay from the first chip to the second chip sending the synchronization signal to the second chip receiving the second chip, the first chip can be After adding the rising edge or the falling edge to the synchronization signal, wait for the first offset time, and then enter the preset working mode to ensure that the first chip and the second chip can enter the preset working mode synchronously.

Among them, the time required for the first chip to send the synchronization signal to the second chip is the inherent delay between the first chip and the second chip, and the inherent delay is specifically determined by the inherent characteristics of the chip device and the connection line itself. Therefore, in practical applications, the inherent delay can be obtained by calibrating between chips.

203. The second chip continuously receives the synchronization signal sent by the first chip, and the synchronization signal is a rectangular wave signal;

204. After a rising edge or a falling edge occurs in the synchronization signal received by the second chip, the second chip enters a preset operating mode after waiting for the second offset time.

In this embodiment, after the second chip receives the synchronization signal, the second chip can continue to detect the synchronization signal. After the second chip detects the rising or falling edge in the synchronization signal, the second chip can wait for the first After the second offset time, it enters the preset working mode, so that it can enter the preset working mode at the same time as the first chip.

It can be understood that, in this embodiment, the first offset time and the second offset time are two different times, and the first offset time is the sum of the second offset time and the inherent delay, that is, In other words, the waiting time of the first chip is the sum of the waiting time of the second chip and the inherent delay. In this way, it can be ensured that after waiting for the first offset time, the first chip can enter the preset working mode synchronously with the second chip waiting for the second offset time.

For example, if there is a timer inside the first chip, if the inherent delay between the first chip and the second chip is 2 (that is, when the timer of the first chip counts from 0 to 2, the second chip will only After receiving the synchronization signal sent by the first chip), the first offset time can be set to 10, and the second offset time can be set to 8. Specifically, the first chip may start timing after adding a rising edge or a falling edge to the synchronization signal, and enter the preset working mode when the timer counts 10 (that is, after waiting for the first offset time); The second chip can start timing after detecting the rising or falling edge of the synchronization signal, and enter the preset working mode when the timer counts to 8 (that is, after waiting for the second offset time). In this way, the time point when the timer in the first chip counts to 10 is exactly the same time point when the timer in the second chip counts to 8. This ensures that the first chip and the second chip can be at the same time. Enter the preset working mode at a time point, that is, the synchronization between the first chip and the second chip is realized.

Optionally, in some embodiments, the first offset time and the second offset time are not fixed. In actual applications, they can be determined or adjusted according to the inherent delay between chips. In addition, in other embodiments, for example, when the first chip sends a synchronization signal to multiple second chips to achieve synchronization of multiple chips, it may also be based on the relationship between the first chip and each different second chip. The inherent delay determines the first offset time that the first chip waits and the second offset time that each second chip waits. For example, assuming that the first chip sends synchronization signals to two second chips at the same time, the inherent delay between the first chip and the first second chip is 2, and the inherent delay between the first chip and the second second chip is 2. If the delay is 5, then you can set the first offset time corresponding to the first chip to 10, the second offset time corresponding to the first second chip to 8, and the second offset time corresponding to the second second chip to The offset time is 5. In this way, the timer in the first chip counts to 10, the timer in the first second chip counts to 8 and the timer in the second second chip counts to 5 The point is exactly the same point in time, ensuring that both the first chip and the two second chips can enter the preset working mode at the same point in time, that is, the synchronization between the first chip and the second chip is realized.

Optionally, in some embodiments, the first offset time and the second offset time may be specifically quantified by the number of counts of a timer inside the chip, and the first offset time and the second offset time may also be one. The specific time value (for example, N nanoseconds, where N is a positive number). In practical applications, the quantization of the first offset time and the second offset time can be determined according to the configuration of the first chip and the second chip itself The method is not specifically limited here.

Optionally, in some embodiments, the first offset time may specifically be the inherent delay between the first chip and the second chip, and the second offset time is 0; that is, the first chip The waiting time is the inherent delay between the first chip and the second chip, and the second chip can directly enter the preset working mode after detecting a rising edge or a falling edge in the synchronization signal without waiting. In this way, it can also be ensured that the first chip can enter the preset working mode synchronously with the second chip after waiting for the first offset time. It is worth noting that the first offset time is the inherent delay between the first chip and the second chip and the second offset time is 0, which is specifically applicable to a chip system with only one first chip and one second chip , Or a chip system with the same inherent delay between the first chip and all second chips.

Optionally, in some embodiments, the preset working mode may include a first working mode and a second working mode. Specifically, the first chip may add a rising edge to the synchronization signal and wait for the first offset time before entering the first working mode; the second chip may include a rising edge in the received synchronization signal and wait for the second After the offset time, enter the first working mode. In addition, the first chip may specifically add a falling edge to the synchronization signal and wait for the first offset time before entering the second working mode; the second chip may have a falling edge in the received synchronization signal and wait After the second offset time, enter the second working mode. In other words, the first chip and the second chip can determine the working mode they enter according to whether the signal edge in the synchronization signal is a rising edge or a falling edge.

In addition, after the first chip has entered the first working mode, the first chip can add a falling edge to the synchronization signal, and after waiting for the first offset time, switch from the first working mode to the second working mode; similarly, After the first chip has entered the second working mode, the first chip may add a rising edge to the synchronization signal, and after waiting for the first offset time, switch from the second working mode to the first working mode. Similarly, for the second chip, after the second chip has entered the first working mode, the second chip can have a falling edge in the synchronization signal, and after waiting for the second offset time, switch from the first working mode to The second working mode; after the second chip has entered the second working mode, the first chip can have a rising edge in the synchronization signal, and after waiting for the second offset time, switch from the second working mode to the first working mode.

It is worth noting that in the above-mentioned embodiment, the first chip and the second chip decide to enter the first working mode according to the rising edge in the synchronization signal, and decide to enter the second working mode according to the falling edge in the synchronization signal. In other embodiments, the first chip and the second chip may also decide to enter the first working mode according to the falling edge in the synchronization signal, and decide to enter the second working mode according to the rising edge in the synchronization signal.

Optionally, in some embodiments, in a scenario where the chip synchronization method provided in the embodiments of the present application is applied to a LIDAR signal processing system, the preset working modes include laser detection and ranging mode and calibration mode, such as the first The working mode can be the laser detection and ranging mode in the LIDAR signal processing system. The first working mode can be the calibration mode in the LIDAR signal processing system. Of course, the first working mode can also be the LIDAR signal processing system. The second working mode is the laser detection and ranging mode in the LIDAR signal processing system, which is not specifically limited here. Among them, the laser detection and ranging mode is the normal working mode in the LIDAR signal processing system, which is mainly used to realize the laser detection and ranging; and the calibration mode is used to eliminate the first chip and the second chip in the LIDAR signal processing system. Two-chip measurement error mode. The calibration calibration mode usually includes calibration and calibration processes. Calibration means acquiring correction parameters, and calibration means calibrating the system according to the acquired correction parameters. Since the LIDAR signal processing system is a complex measurement system integrating light, machine, electricity, calculation and control, there will inevitably be measurement errors in the measurement process, and this measurement error will vary with the working environment and time. Changes have drifted. Therefore, in the working process of the LIDAR signal processing system, it is often necessary to periodically calibrate and calibrate. In view of this, in this embodiment, the first chip and the second chip can selectively enter the laser detection and ranging mode or the calibration mode according to the rising edge or the falling edge of the synchronization signal, so as to realize the synchronization of multiple chips. To a certain working mode, ensure the synchronization between the chips.

Optionally, in some embodiments, the rising edge can be used to trigger the laser detection and ranging mode and the falling edge can be used to trigger the calibration calibration mode, or the falling edge can be used to trigger the laser detection and ranging mode and the rising edge can be used to trigger Calibration calibration mode. In practical applications, the first chip and the second chip can enter the laser detection and ranging mode, switch from the laser detection and ranging mode to the calibration calibration mode, or switch from the calibration calibration mode according to the type of the signal edge in the synchronization signal To laser detection and ranging mode. For example, when laser detection and ranging is required, the first chip adds a rising edge to the synchronization signal, and after waiting for the first offset time, the first chip enters the laser detection and ranging mode; similarly, the second After the chip has a rising edge in the received synchronization signal, after waiting for the second offset time, it enters the laser detection and ranging mode synchronously with the first chip; when the inter-chip calibration is required, the first chip is in the laser detection and ranging mode. A falling edge is added to the synchronization signal, and after waiting for the first offset time, the first chip switches from the laser detection and ranging mode to the calibration calibration mode; the second chip displays the falling edge in the received synchronization signal, and then After waiting for the second offset time, switch from the laser detection and ranging mode to the calibration mode in synchronization with the first chip.

Optionally, in some embodiments, the duration of the first working mode and the second working mode may be determined according to a preset configuration. For example, after configuring the chip to enter the first working mode for M seconds and entering the second working mode for N seconds, the first chip adds a rising edge to the synchronization signal and waits for the first offset time to enter the first working mode After that, the first chip can start timing by the timer. When the timer counts up to M1 seconds, the first chip adds a falling edge to the synchronization signal, and switches from the first working mode to the first after waiting for the first offset time. Two working modes, where M1 is the difference between M and the first offset time; in the same way, after the first chip enters the second working mode, the first chip can start timing by the timer, and the timer counts to N1 seconds When, the first chip adds a rising edge to the synchronization signal, and switches from the second operating mode to the first operating mode after waiting for the first offset time, where N1 is the difference between N and the first offset time. In other words, by configuring the duration of the first working mode and the second working mode in advance, the first chip and the second chip can switch between the first working mode and the second working mode cyclically.

Optionally, in some embodiments, for the second chip, the rising edge or the falling edge appearing in the synchronization signal can be used as the trigger signal and the enable signal of a certain working mode at the same time, that is, in the second chip After detecting the rising edge or the falling edge in the synchronization signal, the corresponding working mode is triggered, and the working mode remains in the working mode until the second chip detects the next signal edge. For example, after the second chip detects the rising edge in the synchronization signal, the second chip triggers the first operating mode and remains in the first operating mode until the second chip detects the falling edge in the synchronization signal. The second chip turns off the first working mode, triggers the second working mode and remains in the second working mode until the second chip detects the next rising edge in the synchronization signal, and so on, you can pass different The signal edge is used to realize the triggering, enabling and shutting off of different working modes.

Optionally, in some embodiments, for the second chip, when the second chip performs delay processing on the continuously received synchronization signal, the rising or falling edge that appears in the synchronization signal can be used as a certain The trigger signal of the working mode, and the level state of the synchronization signal immediately following the rising edge or the falling edge can be used as the enable signal of the corresponding working mode. For example, when the rising edge is used as the trigger signal of the first working mode, the high-level state can be used as the enable signal of the first working mode, and the low-level state can be used as the turn-off signal of the first working mode. The trigger of the first working mode is controlled, and the enabling of the first working mode is controlled by the high-level state, and the turning off of the first working mode is controlled by the low-level state. In other words, after the second chip receives the synchronization signal, when a rising edge appears in the synchronization signal, the second chip enters the first working mode, and controls the use of the first working mode through the high-level state following the rising edge. Yes, the moment when the rising edge occurs is the start moment of the first working mode, and the duration of the high level state is the duration of the first working mode; when a falling edge appears in the synchronization signal, the second chip enters the second In the working mode, the enabling of the second working mode and the turning off of the first working mode are controlled through the low level state immediately following the falling edge, so as to realize the triggering, enabling and turning off of multiple working modes.

In this embodiment, by adopting a single synchronization signal to achieve synchronization and enabling of the two working modes, the pins occupied by the first chip and the second chip for synchronization can be effectively reduced, so that the communication between the first chip and the second chip The connection is simpler; and in this embodiment, the two working modes are automatically switched according to the level state of the synchronization signal, and there is no need to configure the working mode through software configuration or other configuration to realize the switching of the working mode, which simplifies the coupling relationship between chips.

In addition, in this embodiment, the signal edge and level state in the synchronization signal are respectively used as the starting time and enable of the working mode, so that this inter-chip synchronization method has a strong anti-burr interference ability and ensures The stability of the system. It should be noted that a glitch is a kind of noise interference signal that is often encountered in digital logic logic circuits. It is a short-term pulse signal generated due to interference in a normal signal. This short-term pulse signal has a rising edge or a falling edge. There is also a level state, which is easy to trigger the misoperation of the chip, so it usually needs to be filtered out. Because this embodiment uses a combination of signal edge and level status to synchronize, and the level status used to enable each operating mode is usually very long, so you can check the continuity of the level status Whether the time meets the requirements, to filter out some glitch signals that are much shorter than the normal level duration, so that the synchronization between the chips can have a strong anti-burr interference ability.

Specifically, refer to FIG. 3, which is a schematic diagram of a timing sequence of a synchronization signal provided in an embodiment of the application. As shown in Figure 3, the first signal curve represents the synchronization signal generated by the first chip; the second signal curve represents the rising edge detected by the second chip in the received synchronization signal; the third The signal curve shows the start signal of the first working mode; the fourth signal curve shows the enable of the first working mode; the fifth signal curve shows that the second chip detects in the received synchronization signal The falling edge of; the sixth signal curve represents the start signal of the second working mode; the seventh signal curve represents the enable of the second working mode; among them, S1 represents the first chip and the second chip The inherent delay between the first signal curve and the second signal curve can be seen. The rising edge detected by the second chip in the received synchronization signal is the same as the rising edge added by the first chip in the synchronization signal. The difference between the time interval S1, the time interval S1 is the inherent delay between the two chips; S2 represents the first offset time; s3 represents the second offset time; obviously, it can be seen from Figure 3 S2=S1+S3. By setting the first offset time in the first chip and the second offset time in the second chip, it can be ensured that the first chip and the second chip enter the same working mode synchronously. In addition, it can be seen from FIG. 3 that the high-level state and the low-level state are the enabling of the first working mode and the second working mode, respectively. Through the cooperation of the signal edge and the level state, the triggering, enabling and shutting off of different working modes can be realized, so that multiple chips can enter a certain working mode synchronously or switch between working modes synchronously.

Refer to FIG. 4, which is a schematic diagram of a working mode switching provided by an embodiment of the application. As shown in Figure 4, in the LIDAR signal processing system, the rising edge in the synchronization signal is used to trigger the laser detection and ranging mode of the chip, and the high level state in the synchronization signal is used as the enable of the laser detection and ranging mode. The falling edge in the signal is used to trigger the calibration and calibration mode of the chip, and the low level state in the synchronization signal is used as the enablement of the calibration and calibration mode. It can be seen from Figure 4 that in the synchronization signal, the rising edge represents the starting time of the laser detection and ranging mode, and the falling edge represents the starting time of the calibration mode, and the high-level state and low-level state of the synchronization signal It is used as the enable of laser detection and ranging mode and calibration mode respectively, that is, during the duration of high level, the first chip and the second chip both enter the laser detection and ranging mode, and during the duration of low level , The first chip and the second chip enter the calibration mode. In this way, through the cooperation of the trigger signal and the level state, the laser detection and ranging mode can be triggered and enabled, and during the period when the laser detection and ranging mode is turned off (that is, the period between two detection ranging Time gap) to achieve simultaneous calibration and calibration of multiple chips.

Optionally, in some embodiments, in the LIDAR signal processing system, calibration and calibration between multiple chips can also be performed periodically, without the need to perform multiple calibrations during each laser detection and ranging mode off period. Calibration and calibration between chips. For example, when the falling edge is used as the signal edge to trigger the second chip to enter the calibration mode, after the second chip turns off the calibration mode, the second chip continuously detects the number of occurrences of the falling edge in the synchronization signal, and the occurrence of the falling edge When the number of times reaches the first threshold, the second chip triggers the calibration mode again. Similarly, when the rising edge is used as the signal edge to trigger the second chip to enter the calibration mode, after the second chip turns off the calibration mode, the second chip continues to detect the number of occurrences of rising edges in the synchronization signal. When the number of occurrences reaches the first threshold, the second chip triggers the calibration calibration mode again. The first threshold may be determined or adjusted according to actual applications, for example, it may be an integer such as 1 or 2. The specific value of the first threshold is not limited here.

Specifically, reference may be made to FIG. 5, which is another schematic diagram of a working mode switching provided by an embodiment of the application. As shown in Fig. 5, the first chip and the second chip enter the calibration calibration mode after the calibration calibration mode is turned off, and only when the subsequent second falling edge is detected. That is to say, during the duration of the high level, the first chip and the second chip both enter the laser detection and ranging mode; while during the duration of the low level, the first chip and the second chip are periodic To enter the calibration calibration mode. In this way, the first chip and the second chip do not need to calibrate and calibrate between chips every time after laser detection and ranging are performed. Instead, calibration and calibration are performed periodically, and the measurement error changes little. In the case of, it can not only control the measurement error between the chips, but also save the resource overhead of the chips.

In some optional embodiments, in the LIDAR signal processing system, after the first chip and the second chip are powered on or reset, calibration and calibration are performed only once or N times (where N is a positive integer greater than 1 ); That is, after the first chip and the second chip are powered on or reset, when the number of triggers of the calibration calibration mode reaches the second threshold, the calibration calibration mode will no longer be triggered until the next power-on or reset , Then trigger the calibration calibration mode, that is, do not trigger the calibration calibration mode periodically. Wherein, the second threshold value may be a positive integer greater than or equal to 1, and the specific value of the second threshold value may be determined or adjusted according to actual application conditions, which is not limited here. Among them, the chip power-on refers to the chip's power-on startup; and the chip reset refers to the restoration of the chip to the initial default state and restarts work, the previous working state of the chip will be cleared. Generally, after the chip is powered on, the chip will be in the reset state by default. Only after power on and the reset state is withdrawn, the chip will start to work, that is, the chip triggers the corresponding working mode; therefore, in this embodiment, the chip can After each reset state is evacuated, the calibration calibration mode is triggered once or N times, and the calibration calibration mode is no longer triggered until the next reset state is evacuated. Specifically, refer to FIG. 6, which is another schematic diagram of a working mode switching provided by an embodiment of the application. As shown in Fig. 6, after powering on and starting to work, both the first chip and the second chip only trigger the calibration calibration mode once, and no longer trigger the calibration calibration mode.

In some optional embodiments, in the LIDAR signal processing system, after the first chip and the second chip are powered on or reset, the type of the first signal edge in the synchronization signal can be used to determine whether to pass the rising edge. Trigger calibration calibration mode or by falling edge trigger calibration calibration mode, that is, when the first signal edge in the synchronization signal is a rising edge, the rising edge is determined to trigger the chip to enter the calibration calibration mode, the first trigger signal in the synchronization signal When it is a falling edge, determine that the falling edge is used to trigger the chip to enter the calibration mode. In other words, regardless of whether the first signal edge in the synchronization signal is a rising edge or a falling edge, the first chip and the second chip enter the calibration mode first, and then the second signal is added to the synchronization signal in the first chip After the edge, the first chip switches from the calibration and calibration mode to the laser detection and ranging mode. Similarly, after the second signal edge appears in the synchronization signal received by the second chip, the second chip switches from the calibration and calibration mode to the laser In the detection and ranging mode, the calibration and calibration between the first chip and the second chip are performed before laser detection and ranging, so as to ensure the first laser detection after the chip is powered on or reset And ranging can obtain results with less error.

Specifically, refer to FIG. 7, which is another schematic diagram of a working mode switching provided by an embodiment of the application. As shown in Figure 7, when the initial level state of the synchronization signal 1 is a low level state (that is, the initial state is 0), the first edge of the synchronization signal 1 is a rising edge. At this time, it is used to trigger the first chip The trigger signal for entering the calibration mode with the second chip is a rising edge, and the signal edge used to trigger the first chip and the second chip to enter the laser detection and ranging mode is a falling edge; the initial level state of the synchronization signal 2 is In the high-level state (that is, the initial state is 1), the first edge of the synchronization signal 2 is the falling edge. At this time, the signal edge used to trigger the first chip and the second chip to enter the calibration mode is the falling edge. The signal edge that triggers the first chip and the second chip to enter the laser detection and ranging mode is the rising edge.

Of course, in some embodiments, the signal that triggers the laser detection and ranging mode can also be determined according to the first signal edge in the synchronization signal, that is, when the first signal edge in the synchronization signal is a rising edge, the rising edge is used to determine When triggering the laser detection and ranging mode, when the first signal edge in the synchronization signal is the falling edge, the falling edge is determined to trigger the laser detection and ranging mode. In other words, regardless of whether the first signal edge in the synchronization signal is a rising edge or a falling edge, the second chip enters the laser detection and ranging mode first, and then enters the calibration mode. In practical applications, it can be determined according to actual needs whether the first signal edge is used to trigger the laser detection and ranging mode or the calibration calibration mode; for example, in scenarios with high timeliness requirements, it can be determined The first signal edge is used to trigger the laser detection and ranging mode to quickly obtain the measurement results; in scenarios with high accuracy requirements, the first signal edge can be determined to be used to trigger the calibration mode to obtain the error Smaller measurement result.

For ease of understanding, the implementation process of the synchronization method of the chip in this embodiment will be described in detail below in conjunction with a specific circuit structure diagram. Refer to FIG. 8, which is a schematic diagram of a circuit structure of a second chip provided by an embodiment of the application. As shown in Figure 8, the second chip includes a programmable delay unit, a rising edge detection circuit, a falling edge detection circuit, a first working mode logic circuit, a second working mode logic circuit, and a data selector (multiplexer, MUX) ; Among them, the input end of the programmable delay unit is used to receive the synchronization signal, and its output end is respectively connected with the input end of the rising edge detection circuit and the input end of the falling edge detection circuit, and the programmable delay unit is used for the first After the synchronization signal sent by the chip is delayed, the delayed synchronization signal is sent to the rising edge detection circuit and the falling edge detection circuit; the output end of the rising edge detection circuit is connected to the first working mode circuit for detecting the delay time The rising edge in the synchronization signal of the falling edge, and after detecting the rising edge, sends a signal to the first working mode circuit to trigger the first working mode circuit to work; the output terminal of the falling edge detection circuit and the second working mode circuit are used for Detect the falling edge in the delayed synchronization signal, and send a signal to the second working mode circuit after detecting the falling edge to trigger the second working mode circuit to work; in addition, the output terminal of the programmable delay unit is also connected with The first working mode circuit is connected, and the delayed synchronization signal output by the programmable delay unit is used as the enable signal of the first working mode logic circuit; the output terminal of the programmable delay unit is also connected to the second working mode through an inverter The mode circuit is connected, the delayed synchronization signal output by the programmable delay unit is inverted by the inverter as the enable signal of the second working mode logic circuit; the output terminal of the first working mode logic circuit and the second working mode The output end of the mode logic circuit is connected to the input end of the MUX respectively, and the output end of the programmable delay unit is also connected to the MUX. The MUX is used to select the output of the first working mode logic circuit according to the delayed synchronization signal or The output of the logic circuit in the second working mode.

Specifically, after the synchronization signal enters the programmable delay unit, the programmable delay unit delays the synchronization signal according to the preset time length to obtain the delayed synchronization signal; then, the rising edge detection circuit performs the delayed synchronization The signal undergoes rising edge detection, and after the rising edge is detected, a trigger signal is sent to the first working mode logic circuit to trigger the first working mode circuit to work; and the delayed synchronization signal is also used as the first working mode logic circuit The logic circuit of the first working mode is in the working state only when the delayed synchronization signal is at a high level, otherwise the first working mode circuit is turned off; similarly, the falling edge detection circuit is After detecting the falling edge, send a trigger signal to the second working mode logic circuit to trigger the second working mode circuit to work; and the delayed synchronization signal is inverted by the inverter After that, it is also used as the enablement of the second working mode logic circuit. Only when the inverted synchronization signal is in the high level state, the second working mode logic circuit is in the working state, otherwise the second working mode circuit is turned off; That is to say, through the above circuit structure, the corresponding operating mode can be triggered by the rising edge or the falling edge in the synchronization signal, and the corresponding operating mode can be enabled with the level state in the synchronization signal. In addition, the delayed synchronization signal is also used as a reference signal for the MUX selection output. When the delayed synchronization signal is at a high level, the MUX selects and outputs the output result of the logic circuit of the first working mode; the synchronization after the delay When the signal is in a low level state, the MUX selects and outputs the output result of the logic circuit of the second working mode.

It should be noted that in some embodiments, the programmable delay unit may not be provided in the second chip, or the delay time of the programmable delay unit is set to 0, that is, the second chip does not delay the synchronization signal. . For example, in the case where the first chip delays the synchronization signal before sending it to the second chip, the second chip may no longer delay the synchronization signal, but directly receives the synchronization signal and detects the synchronization signal.

Refer to FIG. 9, which is a schematic structural diagram of a first chip provided by an embodiment of the application. As shown in FIG. 9, a first chip 90 provided by an embodiment of the present application includes: a sending unit 901, configured to continuously send a synchronization signal to the second chip, the synchronization signal being a rectangular wave signal; and a processing unit 902, configured to A rising edge or a falling edge is added to the synchronization signal, and after waiting for the first offset time, it enters the preset working mode.

Optionally, the processing unit 902 is also used to add a rising edge to the synchronization signal, and after waiting for the first offset time, enter the first working mode; the processing unit is also used to add a falling edge to the synchronization signal, and After waiting for the first offset time, enter the second working mode, where the preset working mode includes the first working mode and the second working mode.

Optionally, the processing unit 902 is further configured to stop entering the first working mode when the number of times of adding rising edges to the synchronization signal reaches a preset value; or, the processing unit 902 is further configured to add falling edges to the synchronization signal When the number of times reaches the preset value, stop entering the second working mode.

Optionally, if the first signal edge added by the processing unit 902 in the synchronization signal is a rising edge, the processing unit 902 is further configured to enter the first working mode after waiting for the first offset time, and when the processing unit 902 is at After the falling edge is added to the synchronization signal, the processing unit 902 enters the second working mode after waiting for the second offset time; if the first signal edge added by the processing unit 902 to the synchronization signal is a falling edge, the processing unit 902 also uses After waiting for the first offset time, enter the first operating mode, and when the processing unit 902 adds a falling edge to the synchronization signal, the processing unit 902 enters the second operating mode after waiting for the second offset time; wherein, The preset working mode includes a first working mode and a second working mode.

Refer to FIG. 10, which is a schematic structural diagram of a second chip provided by an embodiment of the application. As shown in FIG. 10, a second chip 100 provided by an embodiment of the present application includes: a receiving unit 1001, configured to continuously receive a synchronization signal sent by the first chip, the synchronization signal being a rectangular wave signal; and a processing unit 1002, configured to After a rising edge or a falling edge occurs in the synchronization signal received by the receiving unit 1001, it enters the preset working mode after waiting for the second offset time.

Optionally, after a rising edge occurs in the synchronization signal received by the receiving unit 1001, the processing unit 1002 is further configured to enter the first working mode after waiting for the second offset time;

After a falling edge occurs in the synchronization signal received by the receiving unit 1001, the processing unit 1002 is further configured to enter the second working mode after waiting for the second offset time, wherein the preset working mode includes the first working mode and the second working mode. Operating mode.

Optionally, when the number of occurrences of rising edges in the synchronization signal received by the receiving unit 1001 reaches a preset value, the processing unit 1002 is further configured to stop entering the first working mode;

Alternatively, when the number of occurrences of falling edges in the synchronization signal received by the receiving unit 1001 reaches a preset value, the processing unit 1002 stops entering the second working mode.

Optionally, if the first signal edge appearing in the synchronization signal received by the receiving unit 1001 is a rising edge, the processing unit 1002 is further configured to enter the first working mode after waiting for the second offset time, and when the receiving unit 1001 After a falling edge appears in the synchronization signal received by 1001, the processing unit 1002 is also used to enter the second working mode after waiting for the second offset time; if the first signal edge appears in the synchronization signal received by the receiving unit 1001 For the falling edge, the processing unit 1002 enters the first working mode after waiting for the second offset time, and when a rising edge appears in the synchronization signal received by the receiving unit 1001, the processing unit 1002 is also used to wait for the second offset After time, enter the second working mode; wherein, the preset working mode includes the first working mode and the second working mode.

The embodiment of the present application also provides a chip system, the chip system includes the first chip and the second chip in the embodiment corresponding to FIG. 2, the first chip is connected to the second chip, and is used to perform the implementation corresponding to FIG. 2 The synchronization method of the chip in the example.

Those skilled in the art can clearly understand that, for the convenience and conciseness of the description, the specific working process of the above-described system, device, and unit can refer to the corresponding process in the foregoing method embodiment, which will not be repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed system, device, and method may be implemented in other ways. For example, the device embodiments described above are merely illustrative, for example, the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components may be combined or It can be integrated into another system, or some features can be ignored or not implemented. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.

In addition, the functional units in the various embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or software functional unit.

If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, the technical solution of the present application essentially or the part that contributes to the existing technology or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , Including several instructions to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory, random access memory, magnetic disk or optical disk and other media that can store program codes.

Claims

A method for synchronizing chips, which is characterized in that it includes:

The first chip continuously sends a synchronization signal to the second chip, where the synchronization signal is a rectangular wave signal;

The first chip adds a rising edge or a falling edge to the synchronization signal, and after waiting for a first offset time, the first chip enters a preset working mode.
The chip synchronization method according to claim 1, wherein the first chip adds a rising edge or a falling edge to the synchronization signal, and after waiting for a first offset time, the first chip enters Preset working modes, including:

The first chip adds a first signal edge to the synchronization signal, and after waiting for the first offset time, the first chip enters a laser detection and ranging mode;

The first chip adds a second signal edge to the synchronization signal, and after waiting for the first offset time, the first chip switches from the laser detection and ranging mode to the calibration mode, so The preset working mode includes the laser detection and ranging mode and the calibration mode;

Wherein, the first signal edge is a rising edge and the second signal edge is a falling edge, or the first signal edge is a falling edge and the second signal edge is a rising edge.
The chip synchronization method according to claim 1, wherein the first chip adds a rising edge or a falling edge to the synchronization signal, and after waiting for a first offset time, the first chip enters Preset working modes, including:

If the first signal edge added by the first chip in the synchronization signal is a rising edge, the first chip enters the calibration calibration mode after waiting for the first offset time, and when the first chip After the chip adds a falling edge to the synchronization signal, the first chip switches from the calibration calibration mode to the laser detection and ranging mode after waiting for the first offset time;

If the first signal edge added by the first chip to the synchronization signal is a falling edge, the first chip enters the calibration calibration mode after waiting for the first offset time, and when the After the first chip adds a falling edge to the synchronization signal, the first chip switches from the calibration calibration mode to the laser detection and ranging mode after waiting for the first offset time;

Wherein, the preset working mode includes the calibration mode and the laser detection and ranging mode.
The chip synchronization method according to claim 1, wherein the first chip adds a rising edge or a falling edge to the synchronization signal, and after waiting for a first offset time, the first chip enters Preset working modes, including:

Adding a rising edge to the synchronization signal by the first chip, and after waiting for the first offset time, the first chip enters a first working mode;

Alternatively, the first chip adds a falling edge to the synchronization signal, and after waiting for the first offset time, the first chip enters the second working mode, wherein the preset working mode includes all The first working mode and the second working mode.
The chip synchronization method according to claim 4, wherein the first chip stops entering the first chip when the number of times that the first chip adds rising edges to the synchronization signal reaches a preset value. Operating mode;

Alternatively, when the number of times that the first chip adds falling edges to the synchronization signal reaches the preset value, the first chip stops entering the second working mode.
The method for synchronizing chips according to any one of claims 1 to 5, wherein the first chip is a master chip, and the second chip is a slave chip.
A method for synchronizing chips, which is characterized in that it includes:

The second chip continuously receives the synchronization signal sent by the first chip, where the synchronization signal is a rectangular wave signal;

After a rising edge or a falling edge occurs in the synchronization signal received by the second chip, the second chip enters a preset operating mode after waiting for a second offset time.
8. The chip synchronization method according to claim 7, wherein the second chip waits for a second offset time after a rising edge or a falling edge appears in the synchronization signal received by the second chip After that, the second chip enters a preset working mode, including:

After the first signal edge appears in the synchronization signal received by the second chip, the second chip enters the laser detection and ranging mode after waiting for the second offset time;

After a second signal edge appears in the synchronization signal received by the second chip, the second chip switches from the laser detection and ranging mode to the calibration calibration mode after waiting for the second offset time, The preset working mode includes the laser detection and ranging mode and the calibration mode;

Wherein, the first signal edge is a rising edge and the second signal edge is a falling edge, or the first signal edge is a falling edge and the second signal edge is a rising edge.
8. The chip synchronization method according to claim 7, wherein the second chip waits for a second offset time after a rising edge or a falling edge appears in the synchronization signal received by the second chip After that, the second chip enters a preset working mode, including:

If the first signal edge appearing in the synchronization signal received by the second chip is a rising edge, the second chip enters the calibration calibration mode after waiting for the second offset time, and when the second chip After a falling edge occurs in the synchronization signal received by the chip, the second chip switches from the calibration calibration mode to the laser detection and ranging mode after waiting for the second offset time;

If the first signal edge appearing in the synchronization signal received by the second chip is a falling edge, the second chip enters the calibration mode after waiting for the second offset time, and when the After a rising edge occurs in the synchronization signal received by the second chip, the second chip switches from the calibration mode to the laser detection and ranging mode after waiting for the second offset time;

Wherein, the preset working mode includes the calibration mode and the laser detection and ranging mode.
8. The chip synchronization method according to claim 7, wherein the second chip waits for a second offset time after a rising edge or a falling edge appears in the synchronization signal received by the second chip After that, the second chip enters a preset working mode, including:

After a rising edge occurs in the synchronization signal received by the second chip, the second chip enters the first working mode after waiting for the second offset time;

Or, after a falling edge occurs in the synchronization signal received by the second chip, the second chip enters the second working mode after waiting for the second offset time, wherein the preset working mode includes The first working mode and the second working mode.
The chip synchronization method according to claim 10, wherein when the number of occurrences of rising edges in the synchronization signal received by the second chip reaches a preset value, the second chip stops entering the first Operating mode;

Alternatively, when the number of occurrences of falling edges in the synchronization signal received by the second chip reaches a preset value, the second chip stops entering the second working mode.
The method for synchronizing chips according to any one of claims 7 to 11, wherein the first chip is a master chip, and the second chip is a slave chip.
A chip, characterized in that it comprises:

A sending unit, configured to continuously send a synchronization signal to the second chip, where the synchronization signal is a rectangular wave signal;

The processing unit is configured to add a rising edge or a falling edge to the synchronization signal, and enter the preset working mode after waiting for the first offset time.
The chip according to claim 13, wherein the processing unit is further configured to add a first signal edge to the synchronization signal, and after waiting for the first offset time, enter laser detection and ranging mode;

The processing unit is further configured to add a second signal edge to the synchronization signal, and after waiting for the first offset time, switch from the laser detection and ranging mode to the calibration calibration mode, the preset The working mode includes the laser detection and ranging mode and the calibration mode;

Wherein, the first signal edge is a rising edge and the second signal edge is a falling edge, or the first signal edge is a falling edge and the second signal edge is a rising edge.
The chip according to claim 13, wherein if the first signal edge added by the processing unit to the synchronization signal is a rising edge, the processing unit enters calibration after waiting for the first offset time Calibration mode, and after the processing unit adds a falling edge to the synchronization signal, the processing unit switches from the calibration calibration mode to the laser detection and ranging mode after waiting for the first offset time;

If the first signal edge added by the processing unit in the synchronization signal is a falling edge, the processing unit enters the calibration calibration mode after waiting for the first offset time, and when the processing unit is in synchronization After the falling edge is added to the signal, the processing unit switches from the calibration mode to the laser detection and ranging mode after waiting for the first offset time;

Wherein, the preset working mode includes the calibration mode and the laser detection and ranging mode.
The chip according to claim 13, wherein the processing unit is further configured to add a rising edge to the synchronization signal, and enter the first working mode after waiting for the first offset time;

Alternatively, the processing unit is further configured to add a falling edge to the synchronization signal, and after waiting for the first offset time, enter the second working mode, wherein the preset working mode includes the first A working mode and the second working mode.
The chip according to claim 16, wherein the processing unit is further configured to stop entering the first working mode when the number of times of adding rising edges to the synchronization signal reaches a preset value;

Alternatively, the processing unit is further configured to stop entering the second working mode when the number of times of adding falling edges to the synchronization signal reaches the preset value.
A chip, characterized in that it comprises:

A receiving unit, configured to continuously receive a synchronization signal sent by the first chip, where the synchronization signal is a rectangular wave signal;

The processing unit is configured to enter a preset working mode after waiting for a second offset time after a rising edge or a falling edge occurs in the synchronization signal received by the receiving unit.
18. The chip according to claim 18, wherein after a first signal edge appears in the synchronization signal received by the receiving unit, the processing unit enters laser detection and detection after waiting for the second offset time Ranging mode;

After the second signal edge appears in the synchronization signal received by the receiving unit, the processing unit switches from the laser detection and ranging mode to the calibration mode after waiting for the second offset time, and The preset working mode includes the laser detection and ranging mode and the calibration and calibration mode;

Wherein, the first signal edge is a rising edge and the second signal edge is a falling edge, or the first signal edge is a falling edge and the second signal edge is a rising edge.
18. The chip according to claim 18, wherein if the first signal edge appearing in the synchronization signal received by the receiving unit is a rising edge, the processing unit waits for the second offset time, Enter the calibration calibration mode, and when a falling edge appears in the synchronization signal received by the receiving unit, the processing unit switches from the calibration calibration mode to laser detection and ranging after waiting for the second offset time mode;

If the first signal edge appearing in the synchronization signal received by the receiving unit is a falling edge, the processing unit enters the calibration calibration mode after waiting for the second offset time, and when the receiving unit After a rising edge appears in the received synchronization signal, the processing unit switches from the calibration mode to the laser detection and ranging mode after waiting for the second offset time;

Wherein, the preset working mode includes the calibration mode and the laser detection and ranging mode.
18. The chip according to claim 18, wherein after a rising edge occurs in the synchronization signal received by the receiving unit, the processing unit is further configured to enter the first working mode after waiting for the second offset time ；

Alternatively, after a falling edge occurs in the synchronization signal received by the receiving unit, the processing unit is further configured to enter the second working mode after waiting for the second offset time, wherein the preset working mode Including the first working mode and the second working mode.
The chip according to claim 21, wherein when the number of occurrences of rising edges in the synchronization signal received by the receiving unit reaches a preset value, the processing unit is further configured to stop entering the first working mode ；

Alternatively, when the number of occurrences of falling edges in the synchronization signal received by the receiving unit reaches a preset value, the processing unit stops entering the second working mode.
A chip comprising a processor and a memory, wherein the processor is coupled with the memory, and is used to read and execute instructions stored in the memory to implement the steps according to any one of claims 1-6.
A chip comprising a processor and a memory, wherein the processor is coupled with the memory, and is configured to read and execute instructions stored in the memory to implement the steps according to any one of claims 7-12.
A chip system characterized by comprising the chip of any one of claims 13-17 and the chip of any one of claims 18-22.