WO2021081932A1

WO2021081932A1 - Driver circuit and method for controlling lens actuators

Info

Publication number: WO2021081932A1
Application number: PCT/CN2019/114839
Authority: WO
Inventors: Ishii TAKAO; Masaru Uno; Takamasa Sakuragi
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2019-10-31
Filing date: 2019-10-31
Publication date: 2021-05-06
Also published as: JP7326606B2; CN114586333A; JP2023500657A; CN114586333B

Abstract

The present invention provides a driver circuit for controlling a lens actuator, where the driver circuit is configured to output a Pulse Width Modulation (PWM) carrier to the lens actuator, wherein the PWM carrier contains a pulse train having two or more pulses with the same pulse width, the cycle of the pulse is equal to the time interval for sampling a reset level and a signal level when the reset level and the signal level, which are sampled by an Analog to Digital Converter (ADC), which performs Correlated Double Sampling (CDS) in an image sensor for detecting an image that passes through a lens, are the same, and the cycle of the PWM carrier is equal to integral multiple of the cycle of Analog to Digital Conversion. The present invention achieves mitigating noise on the image sensor in the camera module.

Description

DRIVER CIRCUIT AND METHOD FOR CONTROLLING LENS ACTUATORS

TECHNICAL FIELD

The present invention relates to controlling lens actuators in a camera module.

BACKGROUND

Various electronic devices have a camera module. The camera module includes a lens actuator such as Optical Image Stabilization (OIS) and Auto-Focus (AF) actuators. As a method of driving OIS/AF actuator, Pulse Width Modulation (PWM) technique can be a good candidate, because it makes possible to reduce power consumption of the camera module. However, since a PWM driver repeatedly outputs a PWM carrier with high and low levels, it can be an electric and magnetic noise emitting source. Especially, in a small camera module, a lens unit is placed close to an image sensor, and the OIS/AF actuator for moving the lens unit is also placed close to the image sensor. Thus it is difficult to implement the small camera module.

SUMMARY

A driver circuit is provided to achieve mitigating noise on the image sensor in the camera module.

According to a first aspect, a driver circuit for controlling a lens actuator is provided, where the driver circuit is configured to output a Pulse Width Modulation (PWM) carrier to the lens actuator, wherein the PWM career contains a pulse train having two or more pulses with the same pulse width, the cycle of the pulse is equal to the time interval for sampling a reset level and a signal level when the reset level and the signal level, which are sampled by an Analog to Digital Converter (ADC) , which performs Correlated Double Sampling (CDS) in an image sensor for detecting an image that passes through a lens, are the same, and the cycle of the PWM carrier is equal to integral multiple of the cycle of Analog to Digital Conversion.

In a possible implementation manner of the first aspect, the levels of the PWM carrier are the same when the ADC samples the reset level and the signal level

In a possible implementation manner of the first aspect, the PWM career is synchronized to the ADC operation by referring VSYNC, HSYNC, or the other signal that is generated by ADC.

In a possible implementation manner of the first aspect, the PWM career is generated with fixed delay relative to the signal generated by the ADC.

According to a second aspect, a method for controlling a lens actuator is provided, where the method comprises outputting, by a driver circuit, a Pulse Width Modulation (PWM) carrier to the lens actuator, wherein the PWM career contains a pulse train having two or more pulses with the same pulse width, the cycle of the pulse is equal to the time interval for sampling a reset level and a signal level when the reset level and the signal level, which are sampled by an Analog to Digital Converter (ADC) , which performs Correlated Double Sampling (CDS) in an image sensor for detecting an image that passes through a lens, are the same, and the cycle of the PWM carrier is equal to integral multiple of the cycle of Analog to Digital Conversion.

According to a third aspect, a camera module is provided where the camera module comprises: the driver circuit according to the first aspect, a lens actuator that the driver circuit drives, and an image sensor for outputting amount of light of each pixel by the ADC, to which the CDS is applied, as digital data.

The pulse train, which is generated by the PWM driver circuit described above, emits only the noise which is cancelable by CDS. The noise generated by PWM actuators is made to be cancelable by CDS implemented in the ADC in the image sensor. According to the present invention, PWM driving is synchronized with the ADC operation, thereby mitigating noise on the image sensor in the camera module. According to the PWM waveforms as stated above, by taking into account to fluctuations of PWM duty ratio and actual CDS time interval, the PWM noise to CDS Single Slope ADC (SS-ADC) can be mitigated.

BRIEF DESCRIPTION OF DRAWINGS

To describe the technical solutions in the embodiments of the present invention or in the prior art more clearly, the following briefly introduces the accompanying drawings required for describing the embodiments or the prior art. Apparently, the accompanying drawings in the following description show merely some embodiments of the present invention, and a person of ordinary skill in the art may still derive other drawings from these accompanying drawings without creative efforts.

FIG. 1 shows an example of a structure of SMA-OIS and an electrical connection between a PWM controller and SMA wires.

FIG. 2 shows an example of waveforms of PWM carriers applied to respective SMA wires;

FIG. 3 shows an example of a circuit diagram for estimating the temperature of the SMA wires;

FIG. 4 shows an example of implementation of CDS in actual CMOS image sensor;

FIG. 5 includes Fig. 5 (a) shows four cycles of the ADC period shown in Fig. 4; Fig. 5 (b) shows an example where PWM carrier period is identical to CDS time interval of the ADC during which there is no signal; and Fig. 5 (c) shows an example of PWM pulses according to an embodiment of the present invention;

Fig 6 includes Fig. 6 (a) shows four cycles of the ADC period shown in Fig. 4; Fig. 6 (b) shows an example of PWM waveforms that are inversion of the PWM waveforms in Fig. 5 (b) ; and Fig. 6 (c) shows an example of PWM waveform consisting of 3 pulses, which have the same pulse width and are generated with the CDS time interval.

DESCRIPTION OF EMBODIMENTS

The following clearly and completely describes the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. The described embodiments are merely some but not all of the embodiments of the present invention. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

Fig. 1 shows an example of a structure of SMA-OIS and an electrical connection between a PWM controller and SMA wires. A movable unit 2 has a lens unit in the circle area, and an image that passes through the lens unit is detected by an image sensor (not shown) . The movable unit 2 is connected to a fixed base 1 with four Shape Memorable Alloy (SMA) wires 31 to 34. For example, one fixed point at the upper right corner of the movable unit 2 is connected to the upper left corner of the fixed base 1 with the SMA wire 31, and another fixed point at the upper right corner of the movable unit 2 is connected to the lower right corner of the fixed base 1 with the SMA wire 32. One fixed point at the lower left corner of the movable unit 2 is connected to the upper left corner of the fixed base 1 with the SMA wire 33, and another fixed point at the lower left corner of the movable unit 2 is connected to the lower right corner of the fixed base 1 with the SMA wire 34. The four SMA wires 31 to 34 are separately controlled with PWM pulses generated by a controller. It should be noted that the number of the SMA wires are not limited to four. The embodiments describe the PWM control for moving the lens units in the horizontal direction relative to the surface of the image sensor, but the present invention can be applied to the PWM control for moving the lens units in the vertical direction relative to the surface of the image sensor.

The controller can control the position of the movable unit 2 by utilizing the principle that the length of the SMA wire shrinks as its temperature rises. The controller may be implemented as a driver circuit. The controller estimates the temperature of the SMA wires and updates the duty ratio of the PWM pulses. The temperature of the SMA wires are estimated, for example, by calculating the resistance values of the SMA wires because the resistance values of the SMA wires increase as their temperature rise. To heat wire, it is available to apply current to the SMA wires. The current control may be driven by PWM method for lowering its huge power consumption. Fig. 2 shows an example of waveforms of four cycles of PWM carriers applied to respective SMA wires.

In addition, a temperature sensor is also implemented to measure temperature of each wire to improve control accuracy. The structure, which contains one temperature sensor and multiple SMA wires driven by time division driving, may be applied to reduce camera module size. In Fig. 3, four SMA wires 31 to 34 share the temperature sensor 4, and the PWM carrier is applied to one of the four SMA wires 31 to 34 in a time division manner. The temperature of each SMA wire can be calculated from ADC input voltage, which is proportional to each SMA wire measurement. Specifically, in Fig. 3, assuming that the resistance value of a resister 35 does not change depending on the temperature, the resistance value of the SMA wires can be calculated based on the voltage measured by an ADC 40 in the controller, and the temperature of the SMA wires can be calculated based on the resistance value of the SMA wires.

The PWM pulses applied to the SMA wires as mentioned above may interfere with the image sensor. When controlling the SMA wires with PWM pulses, changing levels of the SMA wires between high and low generates electromagnetic field, and it may interfere with signals on the ADC (such as column ADC) in the image sensor (such as Charge-Coupled Device (CCD) , Complementary Metal-Oxide Semiconductor (CMOS) image sensor, etc. ) and the other parts within the camera module. Generally, the camera module includes an ADC in the image sensor as well as the above-mentioned PWM controller. For canceling several kind of noise, Correlated Double Sampling (CDS) is commonly implemented on the ADC in the image sensor. Fig. 4 shows an example of implementation of CDS in an actual CMOS image sensor. In the CDS operation, 2-sampling is executed for a reset level and a signal level, and output is defined as a differential value of them. Thus this operation can cancel noise commonly included between reset and signal sampling. As such a kind of noise of the image sensor, kTC noise, Vth offset and 1/f noise are well known. This technique is usually implemented with 2-times Single Slope type A/D conversion. In each ADC period, the waveform shown as RAMP in Fig. 4 is used.

In Fig. 4, the waveforms of the RAMP and the comparator output in one ADC period are shown. The horizontal dashed line indicates the reset level. The ADC receives signals from pixels of the image sensor, and the level of the signal is referred to as signal level. When the first descending slope intersects the reset level, the comparator outputs the first pulse. After that, if there is no signal from the pixel, namely, the signal level is identical to the reset level, when the second descending slope intersects the reset level (the horizontal dashed line in Fig. 4) , the comparator outputs the second pulse. If there is a signal from the pixel, the horizontal dashed line drops to the level corresponding to the signal below the reset level, and when the second descending slope intersects the horizontal dashed line (the signal level) , the comparator outputs the second pulse. Depending on the signal level, the rising edge of the second pulse is shifted from the position of the case where there is no signal.

As described above, the PWM pulses applied to the SMA wires may affect the above-mentioned comparator output in Fig. 4. The pixel output can fluctuate, namely, the signal level relative to the reset level can fluctuate, and thereby, the rising edge of the first pulse and the rising edge of the second pulse of the comparator output can fluctuate, and it also means effective CDS time interval may be changeable depending on them.

Figs. 5 (a) to 5 (c) show an example of the phase relation between the waveforms related to the ADC and the waveforms of the PWM carriers according to an embodiment of the present invention. Fig. 5 (a) shows four cycles of the ADC period (Analog to Digital Conversion period) shown in Fig. 4.

Fig. 5 (b) shows an example where PWM carrier period is identical to CDS time interval of the ADC during which there is no signal. Since the PWM carrier periods are not consistent with the ADC period, the phases of the PWM carriers gradually shift in relation to the timing of the sampling by the ADC. For example, in the second ADC period in Fig. 5 (a) , the second PWM2 pulse falls at the rising edge of the first pulse of the comparator output, and the third PWM2 pulse falls at the rising edge of the second pulse of the comparator output. In this case, the sampled value of the ADC is sensitive to jitter of the falling edge of the second or third PWM2 pulse because the levels of the PWM2 pulses may differ when the reset level and the signal level are sampled at the ADC, and thereby the difference value between the reset level and the signal level can fluctuate. Similarly, in the fourth ADC period in Fig. 5 (a) , the second PWM0 pulse rises at the rising edge of the first pulse of the comparator output, and the third PWM0 pulse rises at the rising edge of the second pulse of the comparator output. In this case, the sampled value of the ADC is sensitive to jitter of the rising edge of the second or third PWM0 pulse, because the levels of the PWM0 pulses may differ when the reset level and the signal level are sampled at the ADC, and thereby the difference value between the reset level and the signal level can fluctuate. In another case, during the third ADC period in Fig. 5 (a) , the duty of PWM3 is changed between the second and the third PWM3 pulses, and the level of the PWM3 pulse is high when the first pulse of the comparator output rises, but the level of the PWM3 pulse is low when the second pulse of the comparator output rises, and thereby the difference value between the reset level and the signal level can fluctuate.

For that reason, the PWM waveforms in Fig. 5 (b) cannot avoid the risk of changing PWM output status at reset and signal sampling by jitter of ADC's comparator output and PWM output waveform, because its comparator may toggle nearby level changing of PWM output. Also there are maximum pulse width limitation as CDS time interval /number of SMA wires for SMA actuator. It can cause to big pulse width difference between for normal driving and for measurement temperature of SMA wires.

Fig. 5 (c) shows an example of PWM pulses according to an embodiment of the present invention. In this embodiment, the four wires are controlled in a time division manner, the cycle of each PWM carrier is four times of the ADC period shown in Fig. 5 (a) , and PWM0 is output during the first ADC period, PWM1 is output during the second ADC period, and so on. However, the cycle of the PWM carriers may not be proportional to the number of the wires.

Each ADC period of Fig. 5 (c) includes two PWM pulses. Total periods of high level corresponds to the specified duty ratio. The periods of high level of the two PWM pulses are identical. The distance between the rising edges of the two PWM pulses (the cycle of the PWM pulses) is identical to the CDS time interval during which there is no signal from the pixel. The first PWM pulse rises before the rising edge of the first pulse of the comparator output, in order to ensure that the level of the PWM pulse is high when the first pulse of the comparator output rises, even if the position of the first pulse of the comparator output fluctuates due to noise. The period of high level of the two PWM pulses is set in order to ensure that the level of the PWM pulse is high when the second pulse of the comparator output rises, even if the rising edge of the second pulse of the comparator output is shifted depending on the signal level from the pixel, and in addition, the position of the second pulse of the comparator output fluctuates due to noise. Namely, when the sampling is performed at the ADC, the levels of the two PWM pluses are both high.

Therefore, the PWM waveforms in Fig. 5 (c) can adjust to reset and signal sampling timing for keep enough time margin to toggling of PWM and comparator, because it can completely synchronize to the ADC operation by its PWM career frequency matched to ADC period and the pulse train generated at CDS time interval.

Figs. 6 (a) to 6 (c) show an example of the phase relation between the waveforms related to the ADC and the waveforms of the PWM carriers according to another embodiment of the present invention. Fig. 6 (a) is the same as Fig. 5 (a) . Fig. 6 (b) shows an example of PWM waveforms that are inversion of the PWM waveforms in Fig. 5 (b) . Fig. 6 (c) shows an example of PWM waveform consisting of 3 pulses, which have the same pulse width and are generated with the CDS time interval. The number of the pulses may be an integer greater than 3. It is easy to keep enough margin for toggling between high and low levels with these waveforms. In any case, the PWM waveforms are set so that the level of the PWM carrier is the same when the ADC samples the reset level and the signal level of the pixel. In order to adjust the duty ratio, the controller may switch the PWM waveforms in Figs. 5 (c) , 6 (b) , 6 (c) , etc.

In general, PWM controller generates PWM waveform as follows:

(1) PWM career frequency is equal to integral multiple of the ADC period of the image sensor.

(2) PWM career has a pulse train that contains at least 2 or more pulses which have the same pulse width.

(3) The pulse train is generated at the same time interval as the CDS time interval.

(4) PWM career may be synchronized to the ADC operation by referring VSYNC /HSYNC or the other signal generated by the ADC.

(5) PWM career may be generated with fixed delay against to the above-mentioned sync signal with the ADC operation.

By the PWM waveform defined above, the noise emitted by the PWM controller is cancelable by CDS. Also, the career frequency is the same as the ADC period, so that there is no risk of causing beat noise too. For driving multiple SMA wires in a time division manner, also, the same pulse width is applied for the reset and signal sampling, so that ADC outputs through CDS is not affected by significantly duty ratio change between continuous PWM careers too.

The camera module may be constituted so that the mage sensor has the function to generate a mask signal which defines forbidden period of PWM toggling, and the mask signal period should cover reset and signal sampling phases, and the PWM controller has the function to avoid to toggle its own output within the mask signal, but also keeps the average of the duty ratio of several PWM careers is equal to the original duty ratio.

What is disclosed above are merely exemplary embodiments of the present invention, and are certainly not intended to limit the protection scope of the present invention. A person of ordinary skill in the art may understand that some or all of the processes that implement the foregoing embodiments and equivalent modifications made in accordance with the claims of the present invention shall fall within the scope of the present invention.

Claims

A driver circuit for controlling a lens actuator,

configured to output a Pulse Width Modulation (PWM) carrier to the lens actuator, wherein the PWM career contains a pulse train having two or more pulses with the same pulse width, the cycle of the pulse is equal to the time interval for sampling a reset level and a signal level when the reset level and the signal level, which are sampled by an Analog to Digital Converter (ADC) which performs Correlated Double Sampling (CDS) in an image sensor for detecting an image that passes through a lens, are the same, and the cycle of the PWM carrier is equal to integral multiple of the cycle of Analog to Digital Conversion.
The driver circuit according to claim 1, wherein the levels of the PWM carrier are the same when the ADC samples the reset level and the signal level.
The driver circuit according to claim 1, wherein the PWM career is synchronized to ADC operation by referring VSYNC, HSYNC, or the other signal that is generated by ADC.
The driver circuit according to claim 3, wherein the PWM career is generated with fixed delay relative to the signal generated by the ADC.
A method for controlling a lens actuator, comprising:

outputting, by a driver circuit, a Pulse Width Modulation (PWM) carrier to the lens actuator, wherein the PWM career contains a pulse train having two or more pulses with the same pulse width, the cycle of the pulse is equal to the time interval for sampling a reset level and a signal level when the reset level and the signal level, which are sampled by an Analog to Digital Converter (ADC) , which performs Correlated Double Sampling (CDS) in an image sensor for detecting an image that passes through a lens, are the same, and the cycle of the PWM carrier is equal to integral multiple of the cycle of Analog to Digital Conversion.
A camera module comprising:

the driver circuit according to claim 1,

a lens actuator that the driver circuit drives, and

an image sensor for outputting amount of light of each pixel by the ADC, to which the CDS is applied, as digital data.