WO2021081686A1 - 一种控制方法、设备、芯片及存储介质 - Google Patents

一种控制方法、设备、芯片及存储介质 Download PDF

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Publication number
WO2021081686A1
WO2021081686A1 PCT/CN2019/113540 CN2019113540W WO2021081686A1 WO 2021081686 A1 WO2021081686 A1 WO 2021081686A1 CN 2019113540 W CN2019113540 W CN 2019113540W WO 2021081686 A1 WO2021081686 A1 WO 2021081686A1
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flash memory
chip
data block
memory controller
instruction
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PCT/CN2019/113540
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English (en)
French (fr)
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高俊彰
王德君
江帆
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深圳市大疆创新科技有限公司
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Application filed by 深圳市大疆创新科技有限公司 filed Critical 深圳市大疆创新科技有限公司
Priority to PCT/CN2019/113540 priority Critical patent/WO2021081686A1/zh
Priority to CN201980030364.5A priority patent/CN112106031A/zh
Publication of WO2021081686A1 publication Critical patent/WO2021081686A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/16—Protection against loss of memory contents

Definitions

  • the present invention relates to the field of data processing, in particular to a control method, equipment, chip and storage medium.
  • flash memory can save data without current supply, it has the characteristics of non-volatile (non-volatile).
  • MCU Microcontroller Unit
  • the MCU can read or erase the data in the flash memory.
  • power-down protection mechanism for the flash memory.
  • the embodiment of the present invention discloses a control method, equipment, chip and storage medium, which can effectively protect the external memory from power failure without increasing the hardware cost.
  • an embodiment of the present invention provides a control method, including:
  • the flash memory controller is connected to the flash memory, and the initial state of the data in the flash memory is read-only.
  • the flash memory can respond to writing and/or erasing. In addition to instructions.
  • an embodiment of the present invention provides a control device, including: a memory and a processor,
  • the memory is used to store programs
  • the processor is configured to execute a program stored in the memory, and when the program is executed, the processor is configured to:
  • the flash memory controller is connected to the flash memory, and the initial state of the data in the flash memory is read-only.
  • the flash memory can respond to writing and/or erasing. In addition to instructions.
  • an embodiment of the present invention provides a chip, including:
  • an embodiment of the present invention provides a computer-readable storage medium in which a computer program is stored.
  • the computer program is executed by a processor, the method described in the first aspect is implemented. step.
  • the embodiment of the present invention can obtain the power supply voltage of the chip, and when the power supply voltage is less than the preset voltage threshold, the flash memory controller in the chip is turned off, wherein the flash memory controller is connected to the flash memory, and the flash memory in the flash memory The initial state of the data is read-only.
  • the flash memory obtains the unlocking instruction sent by the flash memory controller, the flash memory can respond to the write and/or erase instructions.
  • FIG. 1 is a schematic flowchart of a control method provided by an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a flash memory provided by an embodiment of the present invention.
  • Fig. 3 is a schematic structural diagram of a control device provided by an embodiment of the present invention.
  • the flash memory can save data without current supply and has the characteristics of non-volatile, currently, most embedded products use the design structure of the microcontroller unit MCU plus flash memory.
  • the above-mentioned MCU and flash memory design structure is set in an unmanned aerial vehicle, the battery of the unmanned aerial vehicle supplies power to the MCU after voltage division, and the MCU sends instructions to the flash memory through the flash memory controller in the MCU, including reading ( The READ command, the erase (ERASE) command, and the write (WRITE) command.
  • the computer program and operating parameters in the flash memory can be read to control the flight of the unmanned aerial vehicle.
  • the initial state of the data in the flash memory is set to read-only, and the flash memory can respond to the write and/or erase instructions only when the flash memory receives an unlock (UNLOCK) instruction sent by the flash memory controller.
  • UNLOCK unlock
  • the flash memory controller when the flash memory controller abnormally sends an erase command to the flash memory when the power supply voltage of the chip drops, it will respond to the erase command only when the flash memory receives the unlock command, otherwise it will not respond to the erase command.
  • the erase command in this way, can reduce the probability of the flash memory being erased abnormally.
  • the embodiment of the present invention detects the power supply voltage of the chip in real time and compares the power supply voltage with a preset voltage threshold.
  • the flash memory controller is turned off so that it cannot send any instructions to the flash memory. .
  • an unlocking instruction is abnormally generated.
  • the flash memory controller sends the unlocking instruction to the flash memory, the flash memory can respond to the write and/or erase instructions.
  • the data in the flash memory can be effectively protected from power failure without increasing the hardware cost, and the content in the flash memory can be prevented from being abnormally updated.
  • the control method provided in the embodiment of the present invention may be executed by a chip, where the chip may include a flash memory controller and a control device.
  • the flash memory is connected to a flash memory controller in the chip as an external memory of the chip.
  • the chip may be set on a mobile device such as an unmanned aerial vehicle, an unmanned ship, a mobile robot, etc., which is not specifically limited in the embodiment of the present invention.
  • FIG. 1 is a schematic flowchart of a control method provided by an embodiment of the present invention. The method may be executed by a control device, and the specific explanation of the control device is as described above. Specifically, the method of the embodiment of the present invention includes the following steps.
  • control device can obtain the power supply voltage of the chip.
  • control device may obtain the power supply voltage of the chip through a processor.
  • the chip may be an MCU chip.
  • the power supply battery is connected to multiple modules, the multiple modules include a chip, and the power supply voltage of the chip may be obtained by obtaining the voltage of the power supply battery, or the voltage provided by the power supply battery to the chip, or the power supply battery The voltage after processing, such as voltage division, etc. after processing.
  • S102 Turn off the flash memory controller in the chip when the power supply voltage is less than a preset voltage threshold.
  • the control device when the power supply voltage is less than a preset voltage threshold, the control device may turn off the flash memory controller in the chip.
  • the flash memory controller may be connected to the flash memory, and the initial state of the data in the flash memory is read-only.
  • the flash memory can respond Write and/or erase commands.
  • the chip includes a voltage comparator.
  • the voltage comparator may be an analog comparator (Analog Comparator, ACMP).
  • the control device after the control device monitors the power supply voltage of the chip, it can compare the real-time monitored power supply voltage with a preset voltage threshold through a voltage comparator in the chip, and when the comparison shows that the power supply voltage is less than When the voltage threshold is preset, the control device can turn off the flash memory controller in the chip.
  • the voltage required for the chip to work is at least 2.6v. That is to say, when the power supply voltage of the chip is less than 2.6v, the chip may trigger some abnormal commands.
  • the preset voltage threshold can be determined to be 2.6 v. If the real-time monitoring of the power supply voltage of the chip is 2.5v, the real-time monitoring of the power supply voltage of 2.5v is compared with the preset voltage threshold of 2.6v through the voltage comparator in the chip, and it is obtained that the power supply voltage of 2.5v is less than When the preset voltage threshold is 2.6v, the control device can turn off the flash memory controller in the chip.
  • the power supply voltage may be the voltage provided to the chip, and the preset voltage threshold may be determined according to the voltage required by the chip during operation. When the voltage provided to the chip is less than the preset voltage threshold , The chip may trigger an abnormal instruction.
  • the power supply voltage may also be a battery voltage
  • the preset voltage threshold may be determined according to the battery voltage and the voltage required by the chip during operation. Specifically, it may be determined according to the ratio of the battery voltage to the voltage required by the chip during operation. When the battery voltage is less than the preset voltage threshold, the chip may trigger an abnormal command.
  • the power supply voltage may also be the voltage of the battery voltage that has undergone processing such as voltage division
  • the preset voltage threshold may be based on the voltage of the battery voltage that has undergone processing such as voltage division and the voltage required by the chip during operation.
  • the voltage is determined. Specifically, it can be determined based on the ratio of the voltage after the battery voltage has been processed by dividing the voltage and the voltage required for the chip to work.
  • the chip may trigger an abnormality instruction.
  • the unmanned aerial vehicle includes a chip.
  • the flash memory controller in the chip is connected to the flash memory.
  • the initial state of the data in the flash memory is read-only. Only when the flash memory receives the unlock command sent by the flash memory controller, can it respond to write Enter and/or erase commands.
  • the computer program and operating parameters in the flash memory can be read to control the unmanned aerial vehicle's flight; when the unmanned aerial vehicle needs to be updated firmware, the chip generates an unlock command, and the flash memory After the controller sends the unlocking instruction to the flash memory, the flash memory can respond to the write and/or erase instructions to update the computer program or operating parameters in the flash memory.
  • the initial state of the data in the flash memory is set to read-only, and the flash memory can respond to the write and/or erase instructions only when the flash memory receives an unlock instruction.
  • the flash memory controller when the flash memory controller abnormally sends an erase command to the flash memory, it will respond to the erase command only when the flash memory receives the unlock command, which can effectively reduce the probability of the flash memory being erased abnormally.
  • the battery of the UAV supplies power to multiple modules including the chip.
  • the voltage comparator in the chip compares the chip's power supply voltage with a preset voltage threshold, and monitors the chip's power supply voltage in real time. When the power supply voltage decreases to less than the preset voltage threshold When, turn off the flash memory controller in the chip.
  • the power supply voltage can be the battery voltage of the UAV, the voltage provided to the chip, or the voltage after processing such as voltage division.
  • an unlock command may be generated abnormally.
  • the flash memory controller sends the unlock command to the flash memory, the flash memory can respond to write and/or erase commands. Therefore, when the power supply voltage is less than the preset voltage threshold, by turning off the flash memory controller in the chip, the power supply voltage of the chip can be prevented from dropping.
  • the flash memory controller sends the unlock command to the flash memory so that the flash memory can be Respond to write and/or erase commands.
  • control device when the control device turns off the flash memory controller in the chip, it may send an interrupt control instruction to the clock controller in the chip, and the interrupt control instruction is used to instruct to turn off the The clock of the flash memory controller.
  • control device compares the real-time monitored power supply voltage 2.5v with the preset voltage threshold 2.6v through the voltage comparator of the chip, and obtains that the power supply voltage 2.5v is less than the preset voltage threshold 2.6v, the control device can The clock controller sends an interrupt control instruction, so that the clock controller turns off the clock of the flash memory controller according to the instruction of the interrupt control instruction.
  • the flash memory controller of the chip can be turned off to ensure that the flash memory controller does not issue abnormal operation instructions.
  • the flash memory is an external memory of the chip, which stores computer programs and operating parameters.
  • the flash memory includes a plurality of data blocks
  • the unlock instruction carries a data block identifier
  • the data block in the flash memory corresponding to the data block identifier can respond to a write and/or erase instruction .
  • Figure 2 is a schematic structural diagram of a flash memory provided by an embodiment of the present invention.
  • the flash memory includes multiple data blocks, such as data block 0, data block 1 and data block. Block 30 and data block 31, data block 2 to data block 29 are not shown in FIG. 2.
  • the initial state of each data block is in a read-only state.
  • the flash memory can unlock the data block 1 corresponding to the data block identifier 1 according to the data block identifier 1 carried in the unlock instruction, that is, the data block 1. It can further respond to write and/or erase commands sent by the flash memory controller.
  • each data block in the flash memory can be further divided into multiple data blocks for protection.
  • data block 0 is divided into 16 data blocks for protection, that is, the 16 data blocks are data Block 0, data block 1,..., data block 14, data block 15.
  • Fig. 2 does not show the data blocks in the data block 1 and the data blocks in the data block 30.
  • each other data block can be equally divided into 16 data blocks for protection.
  • the data block identifier further includes the address information of the data block.
  • the flash memory controller when the data block corresponding to the data block identifier in the flash memory responds to a write and/or erase instruction, the flash memory controller is further configured to detect the data corresponding to the data block identifier The update status of the block.
  • control device may obtain an update completion instruction sent by the flash memory controller, and the update completion instruction carries the data block identifier, and sends the update completion instruction to the flash memory through the flash memory controller.
  • a lock (LOCK) instruction is used to instruct to lock the data block corresponding to the data block identifier.
  • the flash memory controller when the flash memory controller detects that the data block corresponding to the data block identifier is updated, the flash memory controller sends an update completion instruction to the control device, and the control device sends the update completion instruction to the flash memory control after receiving the update completion instruction.
  • the device sends a lock instruction so that the data in the data block is restored to a read-only state after the update is completed, which improves the security of the data in the flash memory.
  • the flash memory controller can generate an update completion instruction after detecting that the data block 1 corresponding to the data block identifier 1 is updated, and Send an update completion instruction to the control device.
  • the control device obtains the update completion instruction sent by the flash memory controller, it can generate a lock instruction according to the data block identifier 1 of the data block 1 carried in the update completion instruction, and send a lock to the flash memory through the flash memory controller. Command to lock data block 1 in the flash memory.
  • the updated data block can be locked again to prevent the data block from being abnormally modified or erased subsequently, which further improves the security of the data block.
  • the control device can obtain the power supply voltage of the chip, and when the power supply voltage is less than the preset voltage threshold, turn off the flash memory controller in the chip, wherein the flash memory controller is connected to the flash memory, so The initial state of the data in the flash memory is read-only, and when the flash memory obtains the unlocking instruction sent by the flash memory controller, it can respond to the write and/or erase instructions.
  • the data in the flash memory can be effectively protected from power failure without increasing the cost of the hardware.
  • FIG. 3 is a schematic structural diagram of a control device according to an embodiment of the present invention.
  • the control device includes: a memory 301 and a processor 302.
  • control device further includes a data interface 303, and the data interface 303 is used to transfer data information between the control device and other devices.
  • the memory 301 may include a volatile memory (volatile memory); the memory 301 may also include a non-volatile memory (non-volatile memory); the memory 301 may also include a combination of the foregoing types of memories.
  • the processor 302 may be a central processing unit (CPU).
  • the processor 302 may further include a hardware chip.
  • the aforementioned hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof.
  • the above-mentioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), or any combination thereof.
  • the memory 301 is used to store programs, and the processor 302 can call the programs stored in the memory 301 to perform the following steps:
  • the flash memory controller is connected to the flash memory, and the initial state of the data in the flash memory is read-only.
  • the flash memory can respond to writing and/or erasing. In addition to instructions.
  • the flash memory is an external memory of the chip, and a computer program and operating parameters are stored.
  • the chip includes a clock controller, and when the memory 301 turns off the flash memory controller in the chip, it is specifically used for:
  • the flash memory includes a plurality of data blocks
  • the unlock instruction carries a data block identifier
  • the data block in the flash memory corresponding to the data block identifier can respond to write and/or erase instructions.
  • the flash memory controller is also used to detect the update of the data block corresponding to the data block identifier status.
  • processor 302 is further configured to:
  • a lock instruction is sent to the flash memory through the flash memory controller, where the lock instruction is used to instruct to lock the data block corresponding to the data block identifier.
  • the preset voltage threshold is determined according to the voltage required by the chip during operation.
  • the control device can obtain the power supply voltage of the chip, and when the power supply voltage is less than the preset voltage threshold, turn off the flash memory controller in the chip, wherein the flash memory controller is connected to the flash memory, so The initial state of the data in the flash memory is read-only.
  • the flash memory obtains the unlocking instruction sent by the flash memory controller, the flash memory can respond to the write and/or erase instructions.
  • the embodiment of the present invention also provides a chip including: a flash memory controller and the above-mentioned control device.
  • the flash memory controller is connected to a flash memory, and the flash memory is an external memory of the chip, and a computer program and operating parameters are stored.
  • the embodiment of the present invention can obtain the power supply voltage of the chip, and when the power supply voltage is less than the preset voltage threshold, the flash memory controller in the chip is turned off, wherein the flash memory controller is connected to the flash memory, and the flash memory in the flash memory
  • the initial state of the data is read-only.
  • the flash memory obtains the unlocking instruction sent by the flash memory controller, the flash memory can respond to the write and/or erase instructions.
  • the embodiment of the present invention also provides a computer-readable storage medium, the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method described in the embodiment corresponding to FIG. 1 of the present invention is implemented , The device corresponding to the embodiment of the present invention described in FIG. 3 can also be implemented, which will not be repeated here.
  • the computer-readable storage medium may be an internal storage unit of the device described in any of the foregoing embodiments, such as a hard disk or memory of the device.
  • the computer-readable storage medium may also be an external storage device of the device, such as a plug-in hard disk equipped on the device, a Smart Media Card (SMC), or a Secure Digital (SD) card. , Flash Card, etc.
  • SMC Smart Media Card
  • SD Secure Digital
  • the computer-readable storage medium may also include both an internal storage unit of the device and an external storage device.
  • the computer-readable storage medium is used to store the computer program and other programs and data required by the terminal.
  • the computer-readable storage medium can also be used to temporarily store data that has been output or will be output.

Abstract

一种控制方法、设备、芯片及存储介质，其中，所述方法包括：获取芯片的供电电压；当所述供电电压小于预设电压阈值时，关断所述芯片中的闪存控制器；其中，所述闪存控制器与闪存连接，所述闪存中的数据的初始状态为只读，当所述闪存获取到闪存控制器发送的解锁指令时，所述闪存能够响应写入和/或擦除指令。通过这种实施方式，可以在不增加硬件成本的基础上，有效地对外部存储器进行掉电保护。

Description

一种控制方法、设备、芯片及存储介质 技术领域
本发明涉及数据处理领域，尤其涉及一种控制方法、设备、芯片及存储介质。
背景技术
由于闪存(Flash memory)在没有电流供应的条件下也能够保存数据，具有非易失性(Non-Volatile)的特性，目前，大部分嵌入式产品均使用微控制单元(Microcontroller Unit，MCU)加闪存的设计结构，MCU可以读取或擦写闪存中的数据。然而，大部分产品没有添加对于闪存的掉电保护机制，导致芯片掉电时，闪存中的数据可能被异常擦除。
发明内容
本发明实施例公开了一种控制方法、设备、芯片及存储介质，可以在不增加硬件成本的基础上，有效地对外部存储器进行掉电保护。
第一方面，本发明实施例提供了一种控制方法，包括：
获取芯片的供电电压；
当所述供电电压小于预设电压阈值时，关断所述芯片中的闪存控制器；
其中，所述闪存控制器与闪存连接，所述闪存中的数据的初始状态为只读，当所述闪存获取到闪存控制器发送的解锁指令时，所述闪存能够响应写入和/或擦除指令。
第二方面，本发明实施例提供了一种控制设备，包括：存储器和处理器，
所述存储器，用于存储程序；
所述处理器，用于执行所述存储器存储的程序，当所述程序被执行时，所述处理器用于：
获取芯片的供电电压；
当所述供电电压小于预设电压阈值时，关断所述芯片中的闪存控制器；
其中，所述闪存控制器与闪存连接，所述闪存中的数据的初始状态为只读， 当所述闪存获取到闪存控制器发送的解锁指令时，所述闪存能够响应写入和/或擦除指令。
第三方面，本发明实施例提供了一种芯片，包括：
闪存控制器和上述第二方面所述的控制设备。
第四方面，本发明实施例提供了一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机程序，所述计算机程序被处理器执行时实现如上述第一方面所述方法的步骤。
本发明实施例可以获取芯片的供电电压，当所述供电电压小于预设电压阈值时，关断所述芯片中的闪存控制器，其中，所述闪存控制器与闪存连接，所述闪存中的数据的初始状态为只读，当闪存获取到闪存控制器发送的解锁指令时，所述闪存能够响应写入和/或擦除指令。通过这种实施方式，可以在不增加硬件成本的基础上，有效地对外部存储器进行掉电保护。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的一种控制方法的流程示意图；
图2是本发明实施例提供的一种闪存的结构示意图；
图3是本发明实施例提供的一种控制设备的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
由于闪存在没有电流供应的条件下也能够保存数据，具有非易失性 (Non-Volatile)的特性，目前，大部分嵌入式产品均使用微控制单元MCU加闪存的设计结构。在一个示例中，上述MCU和闪存的设计结构设置于无人飞行器中，无人机飞行器的电池经过分压之后给MCU供电，MCU通过MCU中的闪存控制器向闪存发送指令，包括读取(READ)指令、擦除(ERASE)指令、写入(WRITE)指令，在一个示例中，闪存中的计算机程序和运行参数可被读取，以控制无人飞行器的飞行。
在实践过程中发现，当对无人飞行器进行关机操作时，给MCU提供的供电电压逐渐下降，MCU中的闪存控制器可能会异常地向闪存发送擦除指令，导致原来存储在闪存中的计算机程序和运行参数被擦除，从而导致用户下一次开机时，无人飞行器无法正常飞行。
目前，大部分产品没有添加对于外部闪存的掉电保护机制，无法达到对于外部闪存的掉电保护需求。
本发明实施例将闪存中的数据的初始状态设置为只读，在闪存接收到闪存控制器发送的解锁(UNLOCK)指令时，才能响应写入和/或擦除指令。也就是说，当闪存控制器在芯片的供电电压下降，异常地向闪存发送了擦除指令时，只有在闪存接收到解锁指令的条件下，才会响应该擦除指令，否则不会响应该擦除指令，如此，可减少闪存被异常擦除的概率。
此外，本发明实施例通过实时检测芯片的供电电压，并将供电电压与预设电压阈值进行比较，当供电电压小于预设电压阈值时，关断闪存控制器，使其无法向闪存发送任何指令。如此，可以避免芯片的供电电压下降时，异常生成解锁指令，闪存控制器向闪存发送该解锁指令后，使得闪存能够响应写入和/或擦除指令。
通过这种实施方式，可以在不增加硬件成本的基础上，有效地对闪存中的数据进行掉电保护，避免闪存中的内容被异常更新。
下面结合附图，对本发明的一些实施方式作详细说明。在不冲突的情况下，下述的实施例及实施例中的特征可以相互组合。
本发明实施例中提供的控制方法可以由一种芯片执行，其中，所述芯片可以包括闪存控制器和控制设备。在某些实施例中，所述闪存作为所述芯片的外部存储器与所述芯片中的闪存控制器连接。在某些实施例中，所述芯片可以设置在无人机、无人船、可移动机器人等可移动设备上，本发明实施例不做具体 限定。
下面结合附图对本发明实施例提供的控制方法进行示意性说明。
具体请参见图1，图1是本发明实施例提供的一种控制方法的流程示意图，所述方法可以由控制设备执行，其中，控制设备的具体解释如前所述。具体地，本发明实施例的所述方法包括如下步骤。
S101：获取芯片的供电电压。
本发明实施例中，控制设备可以获取芯片的供电电压。在某些实施例中，所述控制设备可以通过处理器获取芯片的供电电压，在某些实施例中，所述芯片可以为MCU芯片。
在一种实施方式中，供电电池与多个模块相连，该多个模块包括芯片，获取芯片的供电电压可以是获取该供电电池的电压，或者该供电电池提供给芯片的电压，或者该供电电池的电压经过处理，例如分压等处理之后的电压。
S102：当所述供电电压小于预设电压阈值时，关断所述芯片中的闪存控制器。
本发明实施例中，当所述供电电压小于预设电压阈值时，控制设备可以关断所述芯片中的闪存控制器。在某些实施例中，所述闪存控制器可以与闪存连接，所述闪存中的数据的初始状态为只读，当所述闪存获取到闪存控制器发送的解锁指令时，所述闪存能够响应写入和/或擦除指令。
在一些实施例中，所述芯片内部包括电压比较器，在一个示例中，所述电压比较器可以为模拟比较器(Analog Comparator，ACMP)。
在一个实施例中，控制设备在监测到芯片的供电电压之后，可以通过芯片内的电压比较器将所述实时监测到的供电电压与预设电压阈值进行比较，当比较得到所述供电电压小于预设电压阈值时，控制设备可以关断所述芯片中的闪存控制器。
在一个示例中，芯片工作时所需要的电压至少为2.6v，也就是说，当芯片的供电电压小于2.6v时，芯片可能会触发一些异常的指令，如此，可以确定预设电压阈值为2.6v，如果实时监测到芯片的供电电压为2.5v，通过芯片中的电压比较器将所述实时监测到的供电电压2.5v与预设电压阈值2.6v进行比较，得到所述供电电压2.5v小于预设电压阈值2.6v时，控制设备可以关断 所述芯片中的闪存控制器。
在某些实施例中，所述供电电压可以是提供给芯片的电压，所述预设电压阈值可以是根据芯片工作时所需要的电压确定的，当提供给芯片的电压小于预设电压阈值时，芯片可能会触发异常指令。
在某些实施例中，所述供电电压也可以是电池电压，所述预设电压阈值可以是根据电池电压和芯片工作时所需要的电压确定的。具体可以是根据电池电压和芯片工作时所需要的电压的比例确定的，当电池电压小于预设电压阈值时，芯片可能会触发异常指令。
在某些实施例中，所述供电电压还可以是电池电压经过分压等处理过后的电压，所述预设电压阈值可以是根据电池电压经过分压等处理过后的电压和芯片工作时所需要的电压确定的。具体可以是根据电池电压经过分压等处理过后的电压和芯片工作时所需要的电压的比例确定的，当电池电压经过分压等处理过后的电压小于预设电压阈值时，芯片可能会触发异常指令。
以无人飞行器为例，无人飞行器包括芯片，芯片中的闪存控制器与闪存相连，闪存中的数据的初始状态为只读，在闪存接收到闪存控制器发送的解锁指令时，才能响应写入和/或擦除指令。
示例的，在无人飞行器飞行的过程中，闪存中的计算机程序和运行参数可被读取用于控制无人飞行器飞行；在需要对无人飞行器进行固件更新时，芯片中生成解锁指令，闪存控制器将该解锁指令发送给闪存后，闪存可响应写入和/或擦除指令，以实现闪存中的计算机程序或运行参数的更新。
将闪存中的数据的初始状态设置为只读，在闪存接收到解锁指令时，才能响应写入和/或擦除指令。如此，当闪存控制器异常地向闪存发送了擦除指令时，只有在闪存接收到解锁指令的情况下，才会响应该擦除指令，这样可以有效减少闪存被异常擦除的概率。
无人飞行器的电池给包括芯片的多个模块供电，芯片中的电压比较器将芯片供电电压与预设电压阈值进行比较，实时监测芯片的供电电压，当供电电压减小至小于预设电压阈值时，则关断芯片中的闪存控制器。供电电压可以是无人飞行器的电池电压、提供给芯片的电压或者经过分压等处理之后的电压。
当芯片的供电电压小于预设电压阈值时，可能会异常生成解锁指令，闪 存控制器将该解锁指令发送给闪存后，使得闪存能够响应写入和/或擦除指令。因此，当供电电压小于预设电压阈值时，通过关断芯片中的闪存控制器，可以避免芯片的供电电压下降，异常生成解锁指令时，闪存控制器将该解锁指令发送给闪存，使得闪存能够响应写入和/或擦除指令。
通过这种实施方式，可以避免无人飞行器在关机时，芯片的供电电压逐渐下降的过程中，异常擦除闪存中的计算机程序和运行参数，导致无人飞行器在下次开机时无法正常启动。
在一个实施例中，所述控制设备在关断所述芯片中的闪存控制器时，可以向所述芯片中的时钟控制器发送中断控制指令，所述中断控制指令用于指示关断所述闪存控制器的时钟。
例如，如果控制设备通过芯片的电压比较器将实时监测到的供电电压2.5v与预设电压阈值2.6v进行比较，得到所述供电电压2.5v小于预设电压阈值2.6v时，控制设备可以向所述时钟控制器发送中断控制指令，以使时钟控制器根据中断控制指令的指示，关断闪存控制器的时钟。
可见，通过这种关断闪存控制器的时钟的实施方式，可以关断芯片的闪存控制器，以确保闪存控制器不会发出异常的操作指令。
在一个实施例中，所述闪存为所述芯片的外部存储器，存储有计算机程序以及运行参数。
在一个实施例中，所述闪存中包括多个数据块，所述解锁指令携带有数据块标识，所述闪存中与所述数据块标识对应的数据块能够响应写入和/或擦除指令。
具体可以图2为例进行说明，图2是本发明实施例提供的一种闪存的结构示意图，如图2所示，所述闪存包括多个数据块，如数据块0、数据块1至数据块30和数据块31，图2未将数据块2至数据块29示出。其中，每个数据块的初始状态均处于只读状态。假设闪存获取到的解锁指令中携带了数据块1对应的数据块标识1，则闪存可以根据解锁指令中携带的数据块标识1解锁数据块标识1对应的数据块1，也即该数据块1能够进一步响应闪存控制器发送的写入和/或擦除指令。
可见，通过这种实施方式可以在获取到针对某一个数据块的解锁指令时，只针对该数据块进行解锁，而不需要在更新某一数据块时，对闪存中的 所有数据进行解锁，从而可以实现数据的灵活更新，并在更新某一数据块的数据时，确保其他数据块的数据不被修改或擦除，提高了闪存中数据的安全性。
如图2所示，闪存中的每个数据块还可以进一步分为多个数据分块进行保护，如将数据块0分为16个数据分块进行保护，即该16个数据分块为数据分块0、数据分块1、......、数据分块14、数据分块15。图2中未将数据块1中的数据分块和数据块30中的数据分块示出，同理，其他每个数据块可以均分为16个数据分块进行保护。数据块标识进一步包括数据分块的地址信息，通过这种实施方式，可以更为灵活地解锁需要使用的数据分块，降低了影响其他数据分块的风险，进一步提高了其他数据分块的安全性。
在一个实施例中，当所述闪存中与所述数据块标识对应的数据块响应写入和/或擦除指令时，所述闪存控制器还用于检测与所述数据块标识对应的数据块的更新状态。
在一种实施方式中，所述控制设备可以获取所述闪存控制器发送的更新完成指令，所述更新完成指令中携带了所述数据块标识，并通过所述闪存控制器向所述闪存发送锁定(LOCK)指令，所述锁定指令用于指示锁定与所述数据块标识对应的数据块。
也就是说，当闪存控制器检测到与所述数据块标识对应的数据块被更新完成时，闪存控制器向控制设备发送更新完成指令，控制设备在接收到该更新完成指令后，向闪存控制器发送锁定指令，以使得数据块中的数据在被更新完成之后恢复到只读状态，提高了闪存中数据的安全性。
以图2为例，假设解锁指令中携带了数据块1的数据块标识1，则所述闪存控制器检测到对数据块标识1对应的数据块1更新完成后，可以生成更新完成指令，并向控制设备发送更新完成指令。所述控制设备在获取到所述闪存控制器发送的更新完成指令时，可以根据所述更新完成指令中携带的数据块1的数据块标识1生成锁定指令，并通过闪存控制器向闪存发送锁定指令，以使得闪存中的数据块1被锁定。
可见，通过这种实施方式可以将更新完成后的数据块再次进行锁定，以避免所述数据块后续被异常修改或擦除，进一步提高了所述数据块的安全性。
本发明实施例中，控制设备可以获取芯片的供电电压，当所述供电电压小于预设电压阈值时，关断所述芯片中的闪存控制器，其中，所述闪存控制器与闪存连接，所述闪存中的数据的初始状态为只读，当所述闪存获取到闪存控制器发送的解锁指令时，能够响应写入和/或擦除指令。通过这种实施方式，可以在不增加硬件成本的基础上，有效地对闪存中的数据进行掉电保护。
请参见图3，图3是本发明实施例提供的一种控制设备的结构示意图。具体的，所述控制设备包括：存储器301、处理器302。
在一种实施例中，所述控制设备还包括数据接口303，所述数据接口303，用于传递控制设备和其他设备之间的数据信息。
所述存储器301可以包括易失性存储器(volatile memory)；存储器301也可以包括非易失性存储器(non-volatile memory)；存储器301还可以包括上述种类的存储器的组合。所述处理器302可以是中央处理器(central processing unit，CPU)。所述处理器302还可以进一步包括硬件芯片。上述硬件芯片可以是专用集成电路(application-specific integrated circuit，ASIC)，可编程逻辑器件(programmable logic device，PLD)或其组合。上述PLD可以是复杂可编程逻辑器件(complex programmable logic device，CPLD)，现场可编程逻辑门阵列(field-programmable gate array，FPGA)或其任意组合。
所述存储器301用于存储程序，所述处理器302可以调用存储301中存储的程序，用于执行如下步骤：
获取芯片的供电电压；
当所述供电电压小于预设电压阈值时，关断所述芯片中的闪存控制器；
其中，所述闪存控制器与闪存连接，所述闪存中的数据的初始状态为只读，当所述闪存获取到闪存控制器发送的解锁指令时，所述闪存能够响应写入和/或擦除指令。
进一步地，所述闪存为所述芯片的外部存储器，存储有计算机程序以及运行参数。
进一步地，所述芯片包括时钟控制器，所述存储器301关断所述芯片中的闪存控制器时，具体用于：
向所述时钟控制器发送中断控制指令，所述中断控制指令用于指示关断所述闪存控制器的时钟。
进一步地，所述闪存中包括多个数据块，所述解锁指令携带有数据块标识，所述闪存中与所述数据块标识对应的数据块能够响应写入和/或擦除指令。
进一步地，当所述闪存中与所述数据块标识对应的数据块响应写入和/或擦除指令时，所述闪存控制器还用于检测与所述数据块标识对应的数据块的更新状态。
进一步地，所述处理器302还用于：
获取所述闪存控制器发送的更新完成指令，所述更新完成指令中携带了所述数据块标识；
通过所述闪存控制器向所述闪存发送锁定指令，所述锁定指令用于指示锁定与所述数据块标识对应的数据块。
进一步地，所述预设电压阈值是根据芯片工作时所需要的电压确定的。
本发明实施例中，控制设备可以获取芯片的供电电压，当所述供电电压小于预设电压阈值时，关断所述芯片中的闪存控制器，其中，所述闪存控制器与闪存连接，所述闪存中的数据的初始状态为只读，当所述闪存获取到闪存控制器发送的解锁指令时，所述闪存能够响应写入和/或擦除指令。通过这种实施方式，可以在不增加硬件成本的基础上，有效地对外部存储器进行掉电保护。
本发明实施例还提供了一种芯片，包括：闪存控制器以及上述控制设备。
进一步地，所述闪存控制器与闪存连接，所述闪存为所述芯片的外部存储器，存储有计算机程序以及运行参数。
本发明实施例可以获取芯片的供电电压，当所述供电电压小于预设电压阈值时，关断所述芯片中的闪存控制器，其中，所述闪存控制器与闪存连接，所述闪存中的数据的初始状态为只读，当所述闪存获取到闪存控制器发送的解锁指令时，所述闪存能够响应写入和/或擦除指令。通过这种实施方式，可以在不增加硬件成本的基础上，有效地对外部存储器进行掉电保护，降低了资源占用率。
本发明的实施例还提供了一种计算机可读存储介质，所述计算机可读存储介质存储有计算机程序，所述计算机程序被处理器执行时实现本发明图1所对应实施例中描述的方法，也可实现图3所述本发明所对应实施例的设备，在此 不再赘述。
所述计算机可读存储介质可以是前述任一实施例所述的设备的内部存储单元，例如设备的硬盘或内存。所述计算机可读存储介质也可以是所述设备的外部存储设备，例如所述设备上配备的插接式硬盘，智能存储卡(Smart Media Card,SMC)，安全数字(Secure Digital,SD)卡，闪存卡(Flash Card)等。
进一步地，所述计算机可读存储介质还可以既包括所述设备的内部存储单元也包括外部存储设备。所述计算机可读存储介质用于存储所述计算机程序以及所述终端所需的其他程序和数据。所述计算机可读存储介质还可以用于暂时地存储已经输出或者将要输出的数据。
以上所揭露的仅为本发明部分实施例而已，当然不能以此来限定本发明之权利范围，因此依本发明权利要求所作的等同变化，仍属本发明所涵盖的范围。

Claims (17)

  1. 一种控制方法，其特征在于，包括：
    获取芯片的供电电压；
    当所述供电电压小于预设电压阈值时，关断所述芯片中的闪存控制器；
    其中，所述闪存控制器与闪存连接，所述闪存中的数据的初始状态为只读，当所述闪存获取到闪存控制器发送的解锁指令时，所述闪存能够响应写入和/或擦除指令。
  2. 根据权利要求1所述的方法，其特征在于，
    所述闪存为所述芯片的外部存储器，存储有计算机程序以及运行参数。
  3. 根据权利要求1所述的方法，其特征在于，所述芯片包括时钟控制器，所述关断所述芯片中的闪存控制器，包括：
    向所述时钟控制器发送中断控制指令，所述中断控制指令用于指示关断所述闪存控制器的时钟。
  4. 根据权利要求1所述的方法，其特征在于，
    所述闪存中包括多个数据块，所述解锁指令携带有数据块标识，所述闪存中与所述数据块标识对应的数据块能够响应写入和/或擦除指令。
  5. 根据权利要求4所述的方法，其特征在于，当所述闪存中与所述数据块标识对应的数据块响应写入和/或擦除指令时，所述闪存控制器还用于检测与所述数据块标识对应的数据块的更新状态。
  6. 根据权利要求5所述的方法，其特征在于，还包括：
    获取所述闪存控制器发送的更新完成指令，所述更新完成指令中携带了所述数据块标识；
    通过所述闪存控制器向所述闪存发送锁定指令，所述锁定指令用于指示锁定与所述数据块标识对应的数据块。
  7. 根据权利要求1所述的方法，其特征在于，所述预设电压阈值是根据芯片工作时所需要的电压确定的。
  8. 一种控制设备，其特征在于，包括：存储器和处理器，
    所述存储器，用于存储程序；
    所述处理器，用于执行所述存储器存储的程序，当所述程序被执行时，所述处理器用于：
    获取芯片的供电电压；
    当所述供电电压小于预设电压阈值时，关断所述芯片中的闪存控制器；
    其中，所述闪存控制器与闪存连接，所述闪存中的数据的初始状态为只读，当所述闪存获取到闪存控制器发送的解锁指令时，所述闪存能够响应写入和/或擦除指令。
  9. 根据权利要求8所述的设备，其特征在于，
    所述闪存为所述芯片的外部存储器，存储有计算机程序以及运行参数。
  10. 根据权利要求8所述的设备，其特征在于，所述芯片包括时钟控制器，所述处理器关断所述芯片中的闪存控制器时，具体用于：
    向所述时钟控制器发送中断控制指令，所述中断控制指令用于指示关断所述闪存控制器的时钟。
  11. 根据权利要求8所述的设备，其特征在于，
    所述闪存中包括多个数据块，所述解锁指令携带有数据块标识，所述闪存中与所述数据块标识对应的数据块能够响应写入和/或擦除指令。
  12. 根据权利要求11所述的设备，其特征在于，
    当所述闪存中与所述数据块标识对应的数据块响应写入和/或擦除指令时，所述闪存控制器还用于检测与所述数据块标识对应的数据块的更新状态。
  13. 根据权利要求12所述的设备，其特征在于，所述处理器还用于：
    获取所述闪存控制器发送的更新完成指令，所述更新完成指令中携带了所述数据块标识；
    通过所述闪存控制器向所述闪存发送锁定指令，所述锁定指令用于指示锁定与所述数据块标识对应的数据块。
  14. 根据权利要求8所述的设备，其特征在于，所述预设电压阈值是根据芯片工作时所需要的电压确定的。
  15. 一种芯片，其特征在于，包括：
    闪存控制器和权利要求8-14任一项所述的控制设备。
  16. 根据权利要求15所述的芯片，其特征在于，
    所述闪存控制器与闪存连接，所述闪存为所述芯片的外部存储器，存储有计算机程序以及运行参数。
  17. 一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机程序，其特征在于：所述计算机程序被处理器执行时实现如权利要求1至7中任一项所述方法的步骤。
PCT/CN2019/113540 2019-10-28 2019-10-28 一种控制方法、设备、芯片及存储介质 WO2021081686A1 (zh)

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