WO2021079581A1 - Image-capturing element and image-capturing device - Google Patents

Image-capturing element and image-capturing device Download PDF

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Publication number
WO2021079581A1
WO2021079581A1 PCT/JP2020/028662 JP2020028662W WO2021079581A1 WO 2021079581 A1 WO2021079581 A1 WO 2021079581A1 JP 2020028662 W JP2020028662 W JP 2020028662W WO 2021079581 A1 WO2021079581 A1 WO 2021079581A1
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WIPO (PCT)
Prior art keywords
image signal
unit
signal
clip
image
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PCT/JP2020/028662
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French (fr)
Japanese (ja)
Inventor
智行 弘
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ソニーセミコンダクタソリューションズ株式会社
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Publication of WO2021079581A1 publication Critical patent/WO2021079581A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/62—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Definitions

  • the present disclosure relates to an image pickup device and an image pickup device. More specifically, the present invention relates to an image pickup device that generates an image signal based on holes generated and accumulated by photoelectric conversion, and an image pickup device that uses the image pickup device.
  • an image sensor in which a plurality of pixels are arranged has been used.
  • a charge generation unit that stores the electric charge generated by photoelectric conversion of incident light
  • a transfer unit that transfers the accumulated electric charge
  • a floating diffusion region floating diffusion
  • an amplification transistor for amplifying the potential change of the floating diffusion is arranged in the pixel, and an image signal is generated based on the electric charge held in the floating diffusion.
  • the pixel is further arranged with an initialization unit that discharges and resets the charge held in the charge holding unit.
  • Charges due to photoelectric conversion are accumulated in the charge generation unit during the exposure period, the floating diffusion is reset by the initialization unit after the exposure period elapses, and the charges are transferred to and held by the charge transfer unit to the floating diffusion.
  • An image signal is generated and output by the amplification transistor based on the retained electric charge.
  • the charge of floating diffusion is discharged and the black level of the image signal is set. That is, the image signal generated by the amplification transistor immediately after reset becomes an image signal corresponding to the black level.
  • the black level fluctuates for each pixel, and noise is generated in the image signal.
  • CDS Correlated Double Sampling
  • the process of generating an image signal at the reset level immediately after reset is called the P phase
  • the process of generating the image signal at the signal level after the charge generated by the photoelectric conversion is transferred is called the D phase.
  • the influence of the reset level (black level) fluctuation can be reduced.
  • an image sensor that employs this correlated double sampling there is a problem when imaging strong incident light. When imaging a high-intensity subject such as the sun, the amount of incident light of the pixels increases and charges exceeding the saturation level of the charge generation unit are generated.
  • an image sensor In order to prevent the occurrence of this blackening phenomenon, an image sensor has been proposed that detects that an incident light having an amount of light exceeding the saturation level is incident on a pixel by comparing the image signal of the reset level in the P phase with the determination level.
  • a comparator composed of differential pairs is used, an image signal output from a pixel is connected to a non-inverting input terminal of the comparator, and a signal corresponding to a determination level is a comparator. It is connected to the inverting input terminal of.
  • an image signal having a voltage higher than the determination level is input to the comparator, the incident light having an amount of light exceeding the saturation level is detected.
  • the image signal that caused this blackening phenomenon is corrected by the circuit in the subsequent stage.
  • a photoelectric conversion unit made of silicon (Si) is arranged.
  • This Si-based charge generator accumulates electrons in the charges generated by photoelectric conversion. Since the accumulated electrons are held in the floating diffusion, an image signal whose signal level decreases as the amount of incident light increases is generated.
  • a photoelectric conversion unit using a III-V compound semiconductor is used instead of Si.
  • the present disclosure has been made in view of the above-mentioned problems, and the saturation of the image signal is detected in the image sensor that generates the image signal based on the holes generated and accumulated by the photoelectric conversion, and the deterioration of the image quality is deteriorated.
  • the purpose is to prevent it.
  • the present disclosure has been made to solve the above-mentioned problems, and the first aspect thereof is a photoelectric conversion unit that performs photoelectric conversion of incident light and holes among the charges generated by the photoelectric conversion. It is provided with a charge holding unit for holding, and includes a pixel that generates an image signal based on the held holes and a clip circuit that performs clipping that limits the rise of the generated image signal to a predetermined clip voltage. It is an image sensor.
  • the clip circuit may be configured by a follower circuit that performs the clip by limiting the rise of the image signal based on the predetermined clip voltage supplied to the control terminal. ..
  • the predetermined clip voltage is supplied to the gate, the generated image signal is supplied to the drain, and the load is connected to the source by the follower circuit. It may be configured.
  • the reference signal as a reference when converting the generated image signal into a digital image signal is compared with the generated image signal, and the result of the comparison is output.
  • An analog digital that includes a comparison unit and a time measuring unit that measures the time from the start of the comparison to the output of the result of the comparison in the comparison unit, and converts the image signal into a digital image signal based on the result of the time measurement.
  • a conversion unit may be further provided.
  • the pixel further includes a reset unit that discharges holes held in the charge holding unit to perform reset, and generates a reset image signal that is an image signal after the reset.
  • the analog-to-digital converter may generate the digital image signal based on the difference between the generated image signal and the reset image signal.
  • the clip circuit may perform the clip at the time of generating the reset image signal.
  • the comparison unit includes a differential pair in which the generated image signal and the reference signal are input via a coupling capacitor, and an initialization circuit for initializing the differential pair.
  • the clip circuit may perform the clip at the time of initialization by the initialization circuit.
  • the initialization circuit may be initialized by holding the initial value of the generated image signal and the initial value of the reference signal in the respective coupling capacitors.
  • a saturation detection unit for detecting the saturation of the image signal may be further provided.
  • the saturation detection unit may detect the saturation based on the result of comparison in the comparison unit.
  • a correction unit that corrects the digital image signal based on the detection result of the saturation detection unit may be further provided.
  • a second aspect of the present disclosure includes a photoelectric conversion unit that performs photoelectric conversion of incident light and a charge holding unit that retains holes among the charges generated by the photoelectric conversion, and the retained holes.
  • the effect of limiting the rise of the image signal in the image sensor that generates the image signal based on the holes generated and accumulated by the photoelectric conversion to a predetermined voltage is brought about. It is assumed that saturation of the image signal is suppressed when capturing a high-brightness subject.
  • FIG. 1 is a diagram showing a configuration example of an image sensor according to an embodiment of the present disclosure.
  • the image sensor 1 in the figure includes a pixel array unit 10, a vertical drive unit 20, a column signal processing unit 30, and a control unit 40.
  • the pixel array unit 10 is configured by arranging the pixels 100 in a two-dimensional grid pattern.
  • the pixel 100 generates an image signal according to the irradiated light.
  • the pixel 100 has a photoelectric conversion unit that generates an electric charge according to the irradiated light.
  • the pixel 100 further has a pixel circuit. This pixel circuit generates an image signal based on the electric charge generated by the photoelectric conversion unit. The generation of the image signal is controlled by the control signal generated by the vertical drive unit 20 described later.
  • the signal lines 11 and 12 are arranged in the pixel array unit 10 in an XY matrix.
  • the signal line 11 is a signal line that transmits a control signal of the pixel circuit in the pixel 100, is arranged for each line of the pixel array unit 10, and is commonly wired to the pixel 100 arranged in each line.
  • the signal line 12 is a signal line for transmitting an image signal generated by the pixel circuit of the pixel 100, is arranged in each row of the pixel array unit 10, and is commonly wired to the pixel 100 arranged in each row. To. These photoelectric conversion units and pixel circuits are formed on a semiconductor substrate.
  • the vertical drive unit 20 generates a control signal for the pixel circuit of the pixel 100.
  • the vertical drive unit 20 transmits the generated control signal to the pixel 100 via the signal line 11 in the figure.
  • the column signal processing unit 30 processes the image signal generated by the pixel 100.
  • the column signal processing unit 30 processes the image signal transmitted from the pixel 100 via the signal line 12 in the figure.
  • the processing in the column signal processing unit 30 corresponds to, for example, analog-to-digital conversion that converts an analog image signal generated in the pixel 100 into a digital image signal. Further, the column signal processing unit 30 can perform the above-mentioned correlation double sampling processing.
  • the image signal processed by the column signal processing unit 30 is output as an image signal of the image sensor 1. The details of the configuration of the column signal processing unit 30 will be described later.
  • the control unit 40 controls the entire image sensor 1.
  • the control unit 40 controls the image sensor 1 by generating and outputting a control signal for controlling the vertical drive unit 20 and the column signal processing unit 30.
  • the control signal generated by the control unit 40 is transmitted to the vertical drive unit 20 and the column signal processing unit 30 by the signal lines 41 and 42, respectively.
  • FIG. 2 is a diagram showing a configuration example of pixels according to the first embodiment of the present disclosure.
  • the figure is a circuit diagram showing a configuration example of the pixel 100.
  • the pixel 100 in the figure includes a photoelectric conversion unit 101, charge holding units 102 and 103, and MOS transistors 104 to 108. Further, a power supply line Vdd, a power supply line Vdr, and a power supply line Vtop are arranged in the pixel 100 in the figure.
  • the power line Vdd supplies power to the pixel 100.
  • the power line Vdr transmits the reset potential.
  • the power line Vtop supplies the bias voltage of the photoelectric conversion unit 101.
  • a p-channel MOS transistor can be used for the MOS transistors 104 to 106. Further, n-channel MOS can be used for the MOS transistors 107 and 108.
  • the cathode of the photoelectric conversion unit 101 is connected to the power supply line Vtop, and the anode is connected to the source of the MOS transistor 104, the source of the MOS transistor 105, and one end of the charge holding unit 102. The other end of the charge holding portion 102 is grounded.
  • the gate of the MOS transistor 104 is connected to the overflow gate signal line OFG, and the drain is connected to the power supply line Vdr.
  • the gate of the MOS transistor 105 is connected to the transfer signal line TR, and the drain is connected to the source of the MOS transistor 106, the gate of the MOS transistor 107, and one end of the charge holding unit 103. The other end of the charge holding portion 103 is grounded.
  • the drain of the MOS transistor 106 is connected to the power supply line Vdr.
  • the drain of the MOS transistor 107 is connected to the power supply line Vdd, and the source is connected to the drain of the MOS transistor 108.
  • the gate of the MOS transistor 108 is connected to the selection signal line SEL, and the source is connected to the output signal line Vo.
  • the overflow gate signal line OFG, the transfer signal line TR, the reset signal line RST, and the selection signal line SEL constitute the signal line 11.
  • the output signal line Vo constitutes the signal line 12.
  • the photoelectric conversion unit 101 generates an electric charge according to the irradiated light as described above.
  • a photodiode can be used for the photoelectric conversion unit 101.
  • the cathode of the photoelectric conversion unit 101 is connected to the power supply line Vtop.
  • This power supply line Vtop can supply a voltage of, for example, 2.2V.
  • the anode of the photoelectric conversion unit 101 is connected to the charge holding unit 102, which will be described later. Therefore, of the charges generated by the photoelectric conversion of the photoelectric conversion unit 101, electrons are discharged to the power supply line Vtop, and holes are moved to the charge holding unit 102 and held.
  • the charge holding unit 102 is a capacitor that holds the electric charge generated by the photoelectric conversion unit 101. As described above, the charge holding unit 102 holds the holes generated by the photoelectric conversion unit 101. A capacitor composed of a semiconductor region arranged on a semiconductor substrate can be applied to the charge holding unit 102.
  • the MOS transistor 104 is a transistor that resets the photoelectric conversion unit 101 and the charge holding unit 102.
  • the reset of the photoelectric conversion unit 101 and the charge holding unit 102 by the MOS transistor 104 is controlled by the signal transmitted by the overflow gate signal line OFG.
  • the drain of the MOS transistor 104 is connected to the power supply line Vdr.
  • This power supply line Vdr can supply a voltage of, for example, 1.2V. Therefore, at the time of reset, a voltage of 1.2 V is applied to the photoelectric conversion unit 101 and the charge holding unit 102, and the holes held in the photoelectric conversion unit 101 and the charge holding unit 102 are discharged to the power supply line Vdr.
  • the MOS transistor 105 is a transistor that transfers the charges (holes) generated by the photoelectric conversion unit 101 and held in the charge holding unit 102 to the charge holding unit 103.
  • the charge transfer in the MOS transistor 105 is controlled by the signal transmitted by the transfer signal line TR.
  • the charge holding unit 103 is a capacitor that holds the charge (hole) transferred by the MOS transistor 105. Floating diffusion composed of a semiconductor region arranged on a semiconductor substrate can be applied to the charge holding unit 103.
  • the MOS transistor 107 is a transistor that generates a signal based on the electric charge (hole) held in the electric charge holding unit 103.
  • the MOS transistor 107 constitutes a floating diffusion amplifier together with the charge holding unit 103.
  • the image signal generated by the MOS transistor 107 has a black level of approximately 1.2 V, which is the voltage at the time of reset, and is a signal whose voltage increases as the amount of incident light increases. This is because the MOS transistor 107 generates an image signal based on the holes accumulated in the charge holding unit 103.
  • the MOS transistor 108 is a transistor that outputs the signal generated by the MOS transistor 107 as an image signal to the output signal line Vo.
  • the MOS transistor 108 is controlled by a signal transmitted by the selection signal line SEL.
  • the MOS transistor 106 is a transistor that resets the charge holding unit 103 by discharging the charge held by the charge holding unit 103 to the power supply line Vdr.
  • the reset by the MOS transistor 106 is controlled by the signal transmitted by the reset signal line RST, and is executed before the charge transfer by the MOS transistor 105.
  • the image signal in the pixel 100 in the figure can be generated as follows. First, a control signal is output to the overflow gate signal line OFG to conduct the MOS transistor 104, and the charge holding unit 102 is reset. As a result, the exposure period is started, and the electric charge generated by the photoelectric conversion unit 101 is accumulated in the charge holding unit 102. After the lapse of this exposure period, a control signal is output to the reset signal line RST to conduct the MOS transistor 106, and the charge holding unit 103 is reset. At this time, the MOS transistor 107 generates an image signal based on the charge of the reset charge holding unit 103. After the reset is completed, a control signal is output to the selection signal line SEL to conduct the MOS transistor 108. As a result, the reset image signal, which is the image signal after the reset, is output to the output signal line Vo, and the image signal in the P phase described above can be generated.
  • a control signal is output to the transfer signal line TR to conduct the MOS transistor 105, and the charge held in the charge holding unit 102 is distributed to the charge holding unit 103.
  • the distributed charge is held by the charge holding unit 103, and an image signal is generated by the MOS transistor 107 based on the held charge.
  • a control signal is output to the selection signal line SEL to conduct the MOS transistor 108.
  • the image signal generated by the MOS transistor 107 is output to the output signal line Vo, and the image signal in the D phase described above can be generated.
  • the pixel 100 When the pixel 100 is irradiated with incident light from a high-intensity subject such as the sun, the incident light leaks to the charge holding unit 103 to cause photoelectric conversion, and a charge is generated to saturate the charge holding unit 103. Since the charge of the charge holding unit 103 increases to the saturation level even immediately after the reset, the saturation level image signal is generated from the MOS transistor 107. This saturation level image signal is generated and output in the P phase and the D phase.
  • FIG. 3 is a diagram showing a configuration example of a column signal processing unit according to the embodiment of the present disclosure.
  • the figure is a diagram showing a configuration example of the column signal processing unit 30.
  • the column signal processing unit 30 in the figure includes a clip circuit 31, a constant current circuit 33, an analog-to-digital conversion (AD conversion) unit 32, a horizontal transfer unit 34, a reference signal generation unit 35, and a timing control unit 36. To be equipped.
  • the clip circuit 31, the constant current circuit 33, and the analog-to-digital conversion unit 32 are arranged for each of a plurality of output signal lines Vo of the signal lines 12 of the pixel array unit 10.
  • the reference signal generation unit 35 generates a reference signal.
  • the reference signal is a signal that serves as a reference for analog-to-digital conversion in the analog-to-digital conversion unit 32, which will be described later.
  • the reference signal for example, a signal in which the voltage rises like a ramp function can be used.
  • the reference signal generation unit 35 generates a reference signal according to the control of the control unit 40 described with reference to FIG. 1, and supplies the reference signal to the analog-digital conversion unit 32 via the signal line 303.
  • the timing control unit 36 controls the operation timing of each unit in the column signal processing unit 30.
  • the timing control unit 36 generates control signals for each unit of the column signal processing unit 30 according to the control of the control unit 40. Further, the timing control unit 36 generates a clip voltage of the clip circuit 31 described later. These control signals are output via the signal lines 301, 304 and 306.
  • the clip circuit 31 is a circuit that clips the image signal generated by the pixel 100.
  • the clip circuit 31 clips the image signal output via the output signal line Vo constituting the signal line 12.
  • the clip of the image signal is to limit the rise of the image signal to a predetermined clip voltage.
  • the image signal generated by the pixel 100 is a signal whose voltage increases as the amount of incident light increases.
  • the signal level (voltage) of an image signal corresponding to a high-luminance subject such as the sun rises excessively.
  • the clip circuit 31 limits the excessive rise of this image signal.
  • the clip voltage is supplied by a signal line 301 that is commonly wired to the plurality of clip circuits 31.
  • the clipped image signal is output to the signal line 302. The details of the configuration of the clip circuit 31 will be described later.
  • the constant current circuit 33 is a circuit that supplies a constant current.
  • the constant current circuit 33 is connected between the signal line 302 and the ground to supply a constant current sink current to the signal line 302.
  • the constant current circuit 33 is a circuit that constitutes a load of the MOS transistor 107 of the pixel 100 and the MOS transistor 311 of the clip circuit 31.
  • the analog-to-digital conversion unit 32 converts an analog image signal into a digital image signal.
  • the analog-digital conversion unit 32 in the figure converts the image signal output from the clip circuit 31.
  • the reference signal that serves as a reference for analog-to-digital conversion is supplied by a signal line 303 that is commonly wired to the plurality of analog-to-digital conversion units 32.
  • the converted digital image signal is output to the horizontal transfer unit 34 via the signal line 305.
  • the details of the configuration of the analog-to-digital conversion unit 32 will be described later.
  • the horizontal transfer unit 34 transfers a digital image signal.
  • the horizontal transfer unit 34 sequentially transfers the digital image signals generated by the plurality of analog-to-digital conversion units 32 and outputs them via the signal line 307.
  • FIG. 4 is a diagram showing a configuration example of a clip circuit according to the first embodiment of the present disclosure.
  • A represents a configuration example of the clip circuit 31
  • B in the figure represents the operation of the clip circuit 31.
  • the charge holding unit 103 of the pixel 100, the MOS transistor 108, and the constant current circuit 33 are shown.
  • the clip circuit 31 includes a MOS transistor 311.
  • the MOS transistor 311 is a transistor that constitutes a follower circuit together with the constant current circuit 33.
  • An n-channel MOS transistor can be used for the MOS transistor 311.
  • the gate of the MOS transistor 311 is connected to the signal line 301, and a clip voltage is applied.
  • the drain of the MOS transistor 311 is connected to the signal line 12, and the source is connected to the signal line 302.
  • the constant current circuit 33 is further connected to the signal line 302.
  • the MOS transistor 311 and the constant current circuit 33 form a source follower circuit.
  • the constant current circuit 33 also corresponds to the load of the MOS transistor 108 of the pixel 100.
  • the MOS transistor 311 of the clip circuit 31 is inserted between the source of the MOS transistor 108 and the constant current circuit 33.
  • B in the figure is a diagram showing a change in the signal level (voltage) of the clip circuit 31.
  • the vertical axis represents voltage and the horizontal axis represents time.
  • the dotted line graph 501 represents the voltage of the charge holding unit 103.
  • the broken line graph 502 represents the voltage of the image signal generated by the MOS transistor 108.
  • Graph 503 of the alternate long and short dash line represents the clip voltage.
  • the solid line graph 504 represents the source voltage of the MOS transistor 311 and represents the output voltage of the clip circuit 31.
  • Reference numeral B in the figure shows an example in which the charge held in the charge holding unit 103 increases with time and the voltage rises, and the voltage of the charge holding unit 103 increases in a ramp function shape.
  • the voltage of the image signal increases as the voltage of the charge holding unit 103 increases.
  • the drain voltage of the MOS transistor 311 is lower than the clip voltage applied to the gate, the drain and source of the MOS transistor are in a conductive state.
  • the source of the MOS transistor 311 has substantially the same voltage as the image signal, and a signal having substantially the same voltage as the image signal output from the pixel 100 is output from the clip circuit 31.
  • the source voltage of the MOS transistor 311 does not follow the image signal and is limited to a constant voltage. In this region, the MOS transistor 311 operates as a source follower. A voltage that is lower than the gate voltage by the threshold voltage Vgs between the gate sources is output to the source of the MOS transistor 311. In this way, the image signal is clipped by the clip circuit 31.
  • the operation of the clip circuit 31 can be controlled by the supplied clip voltage. Specifically, by supplying a clip voltage corresponding to a desired limit voltage, the clip circuit 31 can be made to perform a clip operation, and an increase in the image signal can be limited. Further, by supplying a high voltage such as the power supply voltage of the power supply line Vdd as the clip voltage, the clip operation of the clip circuit 31 can be stopped, and the image signal generated by the pixel 100 can be output (passed). it can.
  • the configuration of the clip circuit 31 is not limited to this example.
  • a follower circuit using an element other than the MOS transistor can also be used.
  • FIG. 5 is a diagram showing a configuration example of an analog-to-digital conversion unit according to the first embodiment of the present disclosure.
  • the figure is a diagram showing a configuration example of the analog-to-digital conversion unit 32.
  • the analog-to-digital conversion unit 32 includes a comparison unit 320, a counter 330, and a holding unit 340. Further, in the figure, as the signal line 304, the initialization signal line SET, the clock signal line CLK, the initialization signal line CLR, the up / down count signal line U / D, and the holding signal line HLD are shown.
  • the comparison unit 320 compares the analog image signal generated by the pixel 100 with the reference signal, and outputs the comparison result to the counter 330. For example, as a result of comparison, a value "0" is output when the reference signal has a voltage lower than that of the analog image signal, and a value "1" is output when the reference signal shifts to a voltage higher than that of the analog image signal. be able to. Thereby, it is possible to detect the timing when the reference signal becomes substantially the same value as the analog image signal.
  • the comparison result of the comparison unit 320 is output to the counter 330 via the signal line 307. Further, an initialization signal line SET is connected to the comparison unit 320.
  • the comparison unit 320 is initialized by the control signal from the initialization signal line SET before the start of the above-mentioned comparison. The details of the configuration of the comparison unit 320 will be described later.
  • the counter 330 measures the time from the start of comparison in the comparison unit 320 until the reference signal and the analog image signal have substantially the same value. Specifically, the time from the start of the output of the reference signal in the reference signal generation unit 35 to the transition of the output of the comparison unit 320 to the value "1" is measured.
  • the reference signal is a signal whose value changes like a ramp function. There is a one-to-one correspondence between the time until the reference signal becomes substantially the same value as the analog image signal and the voltage of the analog image signal. Therefore, analog-to-digital conversion can be performed by generating and outputting a digital signal corresponding to the elapsed time when the reference signal becomes substantially the same value as the analog image signal.
  • the counter 330 counts the clock signal during the period from the start of output of the reference signal to the transition of the output of the comparison unit 320 to the value "1", and outputs the count value as a result of analog-to-digital conversion. be able to. The output of this count value is performed via the signal line 308.
  • the clock signal is input from the clock signal line CLK. Further, the counter 330 is initialized to the value "0" by the control signal from the initialization signal line CLR. Further, the counter 330 can perform up-counting and down-counting. The switching between the up count and the down count can be performed by the control signal from the up / down count signal line U / D.
  • the holding unit 340 holds the count value of the counter 330.
  • the holding unit 340 holds the count value of the counter 330, which is the result of analog-to-digital conversion.
  • the count value held in the holding unit 340 corresponds to a digital image signal.
  • the holding unit 340 holds the count value based on the control signal from the holding signal line HLD.
  • FIG. 6 is a diagram showing a configuration example of a comparison unit according to the embodiment of the present disclosure.
  • the comparison unit 320 in the figure includes capacitors 321 and 322 and MOS transistors 323 to 329.
  • a p-channel MOS transistor can be used as the MOS transistor 323 to 326.
  • an n-channel MOS transistor can be used for the MOS transistors 327 to 329.
  • a power supply line Vdd for supplying power and a power supply line Vbias for supplying a bias voltage are wired in the comparison unit 320 in the figure.
  • the capacitor 321 is connected between the signal line 303 and the gate of the MOS transistor 327.
  • the drain of the MOS transistor 325 is further connected to the gate of the MOS transistor 327.
  • the drain of the MOS transistor 327 is connected to the source of the MOS transistor 325, the drain and gate of the MOS transistor 323, and the gate of the MOS transistor 324.
  • the source of the MOS transistor 323 and the source of the MOS transistor 324 are commonly connected to the power supply line Vdd.
  • the source of the MOS transistor 327 is connected to the source of the MOS transistor 328 and the drain of the MOS transistor 329.
  • the gate of the MOS transistor 329 is connected to the power supply line Vbias, and the source is grounded.
  • the capacitor 322 is connected between the signal line 302 and the gate of the MOS transistor 328.
  • the drain of the MOS transistor 326 is further connected to the gate of the MOS transistor 328.
  • the drain of the MOS transistor 328 is connected to the source of the MOS transistor 326, the drain of the MOS transistor 324, and the signal line 307.
  • the gate of the MOS transistor 325 and the gate of the MOS transistor 326 are commonly connected to the initialization signal line SET.
  • Capacitors 321 and 322 constitute a coupling capacitor.
  • capacitors 321 and 322 hold a reference signal and an analog image signal, respectively.
  • the MOS transistors 327 and 328 form a differential pair and amplify the difference between the reference signal and the analog image signal input via the capacitors 321 and 322.
  • the MOS transistor 329 constitutes a constant current circuit commonly connected to the sources of the MOS transistors 327 and 328. A source current corresponding to the bias voltage of the power supply line Vbias flows through the MOS transistor 329.
  • the MOS transistors 323 and 324 form a current mirror circuit and constitute a load connected to the drains of the MOS transistors 327 and 328, respectively. This current mirror circuit can improve the gain of the differential pair by the MOS transistors 327 and 328.
  • the reference signal and the analog image signal can be compared by amplifying the difference between the reference signal and the analog image signal using an amplifier having a high gain differential pair.
  • the MOS transistors 325 and 326 are switches that initialize the comparison unit 320.
  • the MOS transistors 325 and 326 are initialized based on the signal of the initialization signal line SET. Specifically, the control signal from the initialization signal line SET causes the MOS transistors 325 and 326 to conduct, and the gates of the MOS transistors 327 and 328 are initialized.
  • the initialization voltage of this gate is also applied to one end of the capacitors 321 and 322.
  • a reference signal is input to the other end of the capacitor 321 via the signal line 303, and an image signal is input to the other end of the capacitor 322 via the signal line 302. Therefore, at the time of this initialization, by inputting the initial value of the reference signal via the signal line 303, the voltage of the difference between the initialization voltage of the gate of the MOS transistor 327 and the initial value of the reference signal is held in the capacitor 321. Can be made to.
  • the capacitor 322 can hold the voltage of the difference between the initialization voltage of the gate of the MOS transistor 328 and the initial value of the image signal.
  • the input unit of the comparison unit 320 can be initialized.
  • the noise of the image signal based on the fluctuation of the initial value of the reference signal and the image signal can be reduced.
  • the above-mentioned reset image signal can be used as the initial value of the image signal.
  • the circuit by the MOS transistors 325 and 326 constitutes the initialization circuit of the differential pair by the MOS transistors 327 and 328.
  • FIG. 7 is a diagram showing an example of image signal conversion according to the embodiment of the present disclosure.
  • the figure is a time chart showing an example of an operation from the generation of an analog image signal in the pixel 100 to the conversion into a digital image signal in the analog-to-digital conversion unit 32.
  • OFG, SEL, RST, TR and SET are binarized control signals of overflow gate signal line OFG, selection signal line SEL, reset signal line RST, transfer signal line TR and initialization signal line SET, respectively.
  • HLD represents a binarized control signal of the holding signal line HLD.
  • the counter 330 output is represented by converting the digital count value, which is the output of the counter 330, into an analog quantity.
  • the alternate long and short dash line represents the waveform when the charge holding portion 103 of the pixel 100 is saturated.
  • the dotted line represents the waveform of the image signal when the charge holding portion 103 of the pixel 100 is saturated when the clip circuit 31 is not arranged.
  • a signal corresponding to the threshold voltage Vgs between the gate and source for transitioning the MOS transistor of the pixel 100 and the comparison unit 320 to the conduction state is referred to as an on signal.
  • the value "0" represents the control signal of the on signal.
  • the value "1" represents the control signal of the on signal.
  • a voltage corresponding to the value "1" is applied to the overflow gate signal line OFG, the reset signal line RST, the transfer signal line TR, and the initialization signal line SET. Further, a voltage corresponding to the value "0” is applied to the selection signal line SEL and the holding signal line HLD.
  • the clip voltage a high voltage for stopping the clip operation of the clip circuit 31 is supplied.
  • An initial value (initial voltage) is supplied as a reference signal. Further, as the output of the counter 330, the initial value "0" is output.
  • the overflow gate signal line OFG becomes a value "0" and an on signal is input.
  • the MOS transistor 104 becomes conductive and the charge holding unit 102 is reset.
  • the input of the ON signal of the overflow gate signal line OFG is stopped, and the reset of the charge holding unit 102 is completed. As a result, the exposure period in the pixel 100 is started.
  • the selection signal line SEL becomes a value "1" and an on signal is input.
  • the MOS transistor 108 conducts and an image signal corresponding to the charge of the charge holding unit 103 is output from the pixel 100.
  • a clip voltage (511 in the figure) corresponding to the limit voltage of the image signal is supplied.
  • the clip circuit 31 does not perform the clipping operation.
  • the image signal output from the pixel 100 passes through the clip circuit 31 and is input to the comparison unit 320.
  • the reset signal line RST becomes a value "0" and an on signal is input.
  • the MOS transistor 106 becomes conductive and the charge holding unit 103 is reset.
  • the reset image signal is output from the pixel 100, and the output of the clip circuit 31 also drops to the reset level voltage.
  • the reset signal line RST becomes the value "1", and the reset of the charge holding unit 103 is completed. Further, the initialization signal line SET becomes a value "0".
  • the MOS transistors 325 and 326 of the comparison unit 320 are electrically connected to initialize the comparison unit 320.
  • the initialization signal line SET becomes a value "1"
  • the clip voltage supplied to the clip circuit 31 returns to a high voltage.
  • the initialization of the comparison unit 320 is completed.
  • the P phase is started.
  • the supply of the reference signal in the form of a ramp function is started, and the counter 330 starts down counting. Since the voltage of the reference signal is lower than the output voltage of the clip circuit 31, the output of the comparison unit 320 has a value of “0”.
  • the output voltage of the clip circuit 31 and the voltage of the reference signal become equal, and the output of the comparison unit 320 transitions to the value "1". Based on the comparison result of the comparison unit 320, the counter 330 stops the down count.
  • the reference signal returns to the initial value. Therefore, the output of the comparison unit 320 transitions to the value "0".
  • the transfer signal line TR becomes a value "0"
  • an on signal is input.
  • the MOS transistor 105 becomes conductive, and the charge of the charge holding unit 102 is distributed (transferred) to the charge holding unit 103 and held.
  • the level of the image signal from the pixel 100 rises according to the transfer of the electric charge, and the output of the clip circuit 31 also rises.
  • the transfer of electric charge to the electric charge holding unit 103 is completed, and the transfer signal line TR returns to the value "1". Further, the D phase is started, the supply of the reference signal in the form of a ramp function is started, and the counter 330 starts up-counting. Since the voltage of the reference signal is lower than the output voltage of the clip circuit 31, the output of the comparison unit 320 has a value of “0”.
  • the output voltage of the clip circuit 31 and the voltage of the reference signal become equal, and the output of the comparison unit 320 transitions to the value "1". Based on the comparison result of the comparison unit 320, the counter 330 stops up-counting.
  • the selection signal line SEL becomes a value "0", and the output of the image signal from the pixel 100 is stopped.
  • the supply of the reference signal in the form of a ramp function is stopped.
  • the holding signal line HLD becomes a value "1”
  • the output (count value) of the counter 330 is held by the holding unit 340.
  • the count value of the held counter 330 corresponds to a digital image signal.
  • the counter 330 counts down in response to the reset image signal in the P phase.
  • the count value after the down count is up-counted according to the image signal based on the photoelectric conversion of the pixel 100.
  • the reset image signal is subtracted from the image signal based on the photoelectric conversion of the pixel 100, and the CDS is executed.
  • the image signal at the time of saturation is output from the pixel 100. Therefore, the image signal at the time of saturation (512 in the figure) is also output from the clip circuit 31, resulting in a high voltage.
  • the clip circuit 31 When the clip voltage is supplied in T4, the clip circuit 31 starts the clip operation, and the clipped image signal (513 in the figure) is output from the clip circuit 31.
  • the output of the clip circuit 31 becomes the reset level voltage due to the reset of the charge holding unit 103.
  • the reset is completed, and the clipped image signal (513 in the figure) is output from the clip circuit 31 again.
  • the initialization of the comparison unit 320 is started, and the image signal clipped to the capacitor 322 is held.
  • the clip voltage supplied to the clip circuit 31 returns to a high voltage.
  • the image signal at the time of saturation is output again from the clip circuit 31.
  • the saturated image signal and the reference signal are compared by the comparison unit 320.
  • the output of the value "1" from the comparison unit 320 in the P phase is not detected.
  • the saturated image signal and the reference signal are compared by the comparison unit 320.
  • the D phase ends before the voltage of the reference signal reaches the image signal at the time of saturation, and the output of the value “1” from the comparison unit 320 is not detected.
  • the comparison unit 320 is initialized by the clipped image signal, and the saturation level image signal and the reference signal can be compared in the P phase and the D phase. Saturation of the charge holding unit 103 of the pixel 100 can be detected, for example, when the P phase or the D phase ends before the reference signal has the same voltage as the image signal.
  • the image signal of the saturation level represented by the dotted line waveform in the figure is input to the comparison unit 320 and initialized.
  • the image signal at this saturation level is held in the capacitor 322. Therefore, the base of the MOS transistor 328 forming the differential pair of the comparison unit 320 does not change at a low voltage, and the image signal having the same voltage in the P phase and the D phase is compared with the reference signal.
  • a low-value digital image signal is output, causing a blackening phenomenon. In this way, if the clip circuit 31 is not arranged, the comparison unit 320 cannot be initialized.
  • the image sensor 1 of the first embodiment of the present disclosure arranges the clip circuit 31 to limit the rise of the image signal output from the pixel 100.
  • the comparison unit 320 of the analog-digital conversion unit 32 can be initialized, and the charge holding unit 103 of the pixel 100 is saturated. Can be detected. It is possible to prevent the occurrence of a blackening phenomenon and prevent deterioration of image quality.
  • the comparison unit 320 is initialized by arranging the clip circuit 31 even when the charge holding unit 103 is saturated.
  • the image sensor 1 of the second embodiment of the present disclosure is different from the above-described first embodiment in that the saturation of the charge holding unit 103 is detected based on the comparison result of the comparison unit 320. ..
  • FIG. 8 is a diagram showing a configuration example of the analog-to-digital conversion unit according to the second embodiment of the present disclosure. Similar to FIG. 5, FIG. 5 is a diagram showing a configuration example of the analog-to-digital conversion unit 32. It differs from the analog-to-digital conversion unit 32 of FIG. 5 in that it further includes a saturation detection unit and includes a holding unit 360 instead of the holding unit 340.
  • the saturation detection unit 350 detects the saturation of the charge holding unit 103 of the pixel 100.
  • the output signal of the comparison unit 320 is input to the saturation detection unit 350, and the saturation of the charge holding unit 103 is detected based on the comparison result of the comparison unit 320.
  • the saturation detection unit 350 is the charge holding unit 103 when the output signal of the value "1" from the comparison unit 320, which is output when the reference signal becomes equal to the image signal, is not detected in the P phase. Saturation can be detected. Further, the saturation detection unit 350 can also detect the saturation of the charge holding unit 103 when the output signal of the value "1" from the comparison unit 320 is not detected in the D phase.
  • the saturation detection result of the charge holding unit 103 of the saturation detecting unit 350 is output to the holding unit 360 via the signal line 309.
  • the saturation detection unit 350 can output a signal having a value of "1" when the saturation of the charge holding unit 103 is detected.
  • the holding unit 360 holds the digital image signal by holding the count value of the counter 330. Further, the holding unit 360 further corrects the digital image signal based on the saturation detection result of the charge holding unit 103 of the saturation detecting unit 350. Specifically, when a signal having a value of "1" when the saturation of the charge holding unit 103 is detected is output from the saturation detecting unit 350, the holding unit 360 outputs a digital image signal corresponding to the maximum brightness. It can be retained and output as a result of analog-to-digital conversion. As a result, even when the blackening phenomenon occurs, the image signal can be corrected and the deterioration of the image quality can be prevented.
  • the holding unit 360 is an example of the correction unit described in the claims.
  • the saturation detection unit 350 detects the saturation of the charge holding unit 103, and the holding unit 360 is based on the detection result of the saturation detection unit 350. Corrects the image signal. This makes it possible to prevent deterioration of image quality due to the occurrence of the blackening phenomenon.
  • the clip circuit 31 is arranged in the column signal processing unit 30.
  • the image sensor 1 of the third embodiment of the present disclosure is different from the above-described first embodiment in that the clip circuit is arranged in the pixel 100.
  • FIG. 9 is a diagram showing a configuration example of pixels according to the third embodiment of the present disclosure. Similar to FIG. 2, the figure is a circuit diagram showing a configuration example of the pixel 100. It differs from the pixel 100 in FIG. 2 in that it further includes a MOS transistor 109. Further, the signal line 11 in the figure further includes a clip signal line CLIP. This clip signal line CLIP is a signal line that transmits a clip voltage.
  • An n-channel MOS transistor can be used as the MOS transistor 109.
  • the drain of the MOS transistor 109 is connected to the MOS transistor 108, and the source is connected to the output signal line Vo.
  • the gate of the MOS transistor 109 is connected to the clip signal line CLIP.
  • the vertical drive unit 20 of the third embodiment of the present disclosure generates the clip voltage of the waveform described in FIG. 4 and transmits it to the pixel 100 via the clip signal line CLIP.
  • the MOS transistor 109 in the figure is configured in a source follower circuit together with the constant current circuit 33 described in FIG. 3, and limits the rise of the image signal output from the MOS transistor 108 based on the transmitted clip voltage.
  • the clip circuit 31 of the column signal processing unit 30 can be omitted.
  • the circuit by the MOS transistor 109 and the constant current circuit 33 is an example of the clip circuit described in the claims.
  • the image sensor 1 of the third embodiment of the present disclosure limits the rise of the image signal by the MOS transistor 109 arranged in the pixel 100.
  • the comparison unit 320 of the analog-digital conversion unit 32 can be initialized, and the saturation of the charge holding unit 103 of the pixel 100 can be detected.
  • the image sensor 1 of the third embodiment described above a MOS transistor 109 is added to the pixel 100 to limit the rise of the image signal.
  • the image sensor 1 of the fourth embodiment of the present disclosure has the third embodiment described above in that the selection signal line from which the clip voltage is output is arranged to limit the rise of the image signal. Different from.
  • FIG. 10 is a diagram showing a configuration example of a pixel according to a fourth embodiment of the present disclosure. Similar to FIG. 2, the figure is a circuit diagram showing a configuration example of the pixel 100. It differs from pixel 100 in FIG. 2 in that the selection signal line SEL / CLIP is arranged instead of the selection signal line SEL.
  • the selection signal line SEL / CLIP is connected to the gate of the MOS transistor 108.
  • the selection signal line SEL / CLIP is a signal line that supplies the selection signal and the clip voltage.
  • the selection signal line SEL / CLIP transmits an on signal when the pixel 100 is selected, and supplies a clip voltage during the period during which the image signal is clipped during the selected period. Specifically, the on signal is transmitted during the period of T3 to T4 and the period of T7 to T15 described in FIG. 7, and the clip voltage is supplied during the period of T4 to T7. As a result, it is possible to limit the rise of the image signal when the comparison unit 320 is initialized.
  • the vertical drive unit 20 of the fourth embodiment of the present disclosure switches the on signal and the clip voltage and outputs the output to the selection signal line SEL / CLIP.
  • the circuit by the MOS transistor 108 and the constant current circuit 33 is an example of the clip circuit described in the claims.
  • the selection signal line SEL / CLIP is arranged to supply the on signal and the clip voltage to the pixel 100, and the MOS transistor 108 is used as the image signal. It is used for selecting the pixel 100 to be output and limiting the rise of the image signal. Thereby, the configuration of the pixel 100 can be simplified.
  • the image pickup device 1 of the third embodiment described above uses an image pickup device that generates an image signal based on holes generated by the photoelectric effect.
  • the configuration of this image pickup device will be described.
  • FIG. 11 is a diagram showing a configuration example of a pixel according to a fifth embodiment of the present disclosure.
  • the figure is a cross-sectional view showing a configuration example of the pixel 100.
  • the pixel 100 in the figure includes an on-chip lens 170, a protective film 160, a transparent electrode 150, a compound semiconductor chip 192, and a silicon chip 191.
  • the compound semiconductor chip 192 is a semiconductor chip including a substrate of a compound semiconductor. This compound semiconductor chip 192 performs photoelectric conversion of incident light, and transmits holes in the charges generated by the photoelectric conversion to the silicon chip 191 described later.
  • the compound semiconductor chip 192 includes a compound semiconductor substrate 130, a first compound semiconductor layer 131, a second compound semiconductor layer 132, a separation region 133, a protective layer 134, an electrode 135, an insulating layer 141, and a bump. It is provided with an electrode 142.
  • the compound semiconductor substrate 130 is a substrate made of a compound semiconductor.
  • the compound semiconductor substrate 130 can be made of, for example, indium phosphide (InP). Further, the compound semiconductor substrate 130 can be configured as an n-type having a relatively high impurity concentration.
  • the first compound semiconductor layer 131 is a compound semiconductor layer formed on the compound semiconductor substrate 130.
  • the first compound semiconductor layer 131 can be made of, for example, indium gallium arsenide (InGaAs). Further, the first compound semiconductor layer 131 can be formed in an n-type. Photoelectric conversion of incident light is performed in the first compound semiconductor layer 131. Of the charges generated by photoelectric conversion, electrons are diffused to the n-type compound semiconductor substrate 130, and holes are diffused to the p-type second compound semiconductor layer 132, which will be described later.
  • the first compound semiconductor layer 131 is commonly arranged for the plurality of pixels 100.
  • the second compound semiconductor layer 132 is a semiconductor layer arranged for each pixel 100 and bonded to the first compound semiconductor layer 131.
  • the second compound semiconductor layer 132 can be configured by, for example, InP. Further, the second compound semiconductor layer 132 can be formed in a p-type having a relatively high impurity concentration.
  • the photodiode formed by the pn junction of the first compound semiconductor layer 131 and the second compound semiconductor layer 132 corresponds to the photoelectric conversion unit 101 described in FIG.
  • the separation region 133 separates the pixel 100.
  • the separation region 133 is arranged at the boundary of the pixel 100 and separates the adjacent second compound semiconductor layers 132 from each other.
  • the separation region 133 can be configured by an n-type InP.
  • the protective layer 134 protects the surface of the compound semiconductor layer.
  • the protective layer 134 can be made of an inorganic material such as silicon nitride (SiN), aluminum oxide (Al 2 O 3 ), silicon oxide (SiO 2 ) and hafnium oxide (HfO 2 ).
  • the electrode 135 is an electrode arranged adjacent to the second compound semiconductor layer 132.
  • the electrode 135 can be made of, for example, titanium (Ti) or tungsten (W).
  • the insulating layer 141 insulates and protects the surface of the compound semiconductor chip 192.
  • the insulating layer 141 can be made of, for example, SiO 2 .
  • the bump electrode 142 is a bump arranged on the surface of the insulating layer 141.
  • the bump electrode 142 is arranged so as to penetrate the insulating layer 141 and is connected to the electrode 135. Further, the bump electrode 142 is bonded to the bump electrode 126 of the silicon chip 191 described later and transmits holes generated by photoelectric conversion.
  • the bump electrode 142 can be made of, for example, copper (Cu).
  • Silicon chip 191 is a semiconductor chip including a substrate made of silicon (Si).
  • the silicon chip 191 generates an image signal based on the holes generated by the compound semiconductor chip 192.
  • the MOS transistor and the charge holding unit described in FIG. 2 are arranged on the silicon chip 191. Further, the vertical drive unit 20 and the like described in FIG. 1 can be arranged on the silicon chip 191.
  • the silicon chip 191 includes a semiconductor substrate 110 and a wiring region 120.
  • the semiconductor substrate 110 is a semiconductor substrate composed of Si.
  • a diffusion region such as an element of the pixel 100 is arranged in the well region formed on the semiconductor substrate 110.
  • a well region 111 configured in an n-shape is shown.
  • the p-channel MOS transistor described in FIG. 2 can be arranged in the n-type well region 111.
  • the p-channel MOS transistor can be arranged by arranging the p-type semiconductor region in the n-type well region 111.
  • MOS transistors 104 and 105 are shown.
  • the p-type semiconductor regions 112 and 113 in the figure constitute a source region and a drain region of the MOS transistor 104, and the gate electrode 119 is located close to the n-type well region 111 between the p-type semiconductor regions 112 and 113. Be placed.
  • a channel is formed in the n-type well region 111 between the p-type semiconductor regions 112 and 113.
  • the p-type semiconductor regions 112 and 114 constitute a source region and a drain region of the MOS transistor 105, and the gate electrode 118 is arranged in the vicinity of the n-type well region 111 between the p-type semiconductor regions 112 and 113. Will be done.
  • n-channel MOS transistors 107 and 108 and the charge holding portion 103 of FIG. 2 can be formed in a p-type well region (not shown).
  • the wiring region 120 is a wiring region formed on the surface side of the semiconductor substrate 110, and is a region in which wiring such as the above-mentioned MOS transistor is formed.
  • the wiring region 120 includes an insulating layer 121, a wiring layer 122, a contact plug 123, a via plug 124, a pad 125, and a bump electrode 126.
  • the wiring layer 122 transmits a signal to a MOS transistor or the like.
  • the wiring layer 122 can be made of a metal such as Cu.
  • the insulating layer 121 insulates the wiring layer 122.
  • the insulating layer 121 can be made of, for example, an insulating material such as SiO 2.
  • the wiring layer 122 and the insulating layer 121 can be configured in multiple layers.
  • the insulating layer 121 between the gate electrodes 118 and 119 and the semiconductor substrate 110 corresponds to a gate insulating film.
  • the pad 125 is an electrode arranged near the surface of the wiring region 120.
  • the pad 125 can be configured by, for example, W or the like.
  • the contact plug 123 connects the semiconductor region of the semiconductor substrate 110 and the wiring layer 122.
  • the contact plug 123 can be configured by, for example, W or the like.
  • the via plug 124 connects the wiring layers 122 to each other or the wiring layer 122 to the pad 125.
  • the bump electrode 126 is a bump arranged on the surface of the insulating layer 121.
  • the bump electrode 126 is arranged so as to penetrate the insulating layer 121 and is connected to the pad 125.
  • the bump electrode 126 is bonded to the bump electrode 142 of the compound semiconductor chip 192.
  • the image pickup device 1 provided with the pixel 100 in the figure is configured by laminating individually manufactured compound semiconductor chips 192 and silicon chips 191 respectively. At the time of this bonding, the bump electrodes 126 and 142 are joined to transmit signals between the respective chips.
  • the bump electrode 126 can be made of Cu in the same manner as the bump electrode 142.
  • the transparent electrode 150 is a transparent electrode arranged on the back surface of the compound semiconductor chip 192.
  • the power supply line Vtop described with reference to FIG. 2 is connected to the transparent electrode 150 to supply a bias voltage to the compound semiconductor substrate 130.
  • ITO Indium Tin Oxide
  • the protective film 160 is a film that protects the back surface of the compound semiconductor chip 192 and the transparent electrode 150.
  • the on-chip lens 170 is a lens that collects incident light on the photoelectric conversion unit.
  • the on-chip lens 170 collects incident light on the first compound semiconductor layer 131.
  • the on-chip lens 170 can be made of an inorganic material such as silicon nitride (SiN) or an organic material such as an acrylic resin.
  • the holes generated by the photoelectric conversion of the first compound semiconductor layer 131 of the compound semiconductor chip 192 are transmitted to the silicon chip 191 via the second compound semiconductor layer 132, the electrode 135, and the bump electrode 142.
  • the transmitted holes are transmitted to the semiconductor region 112 via the bump electrode 126, the pad 125, the via plug 124, the wiring layer 122, and the contact plug 123.
  • An image signal is generated based on the holes transmitted to the semiconductor region 112.
  • the pixel 100 provided with the photoelectric conversion unit using the compound semiconductor described above can be applied to the image pickup device of the present disclosure.
  • the configuration of the image sensor of the present disclosure is not limited to this example.
  • the image pickup device of the present disclosure comprises a pixel 100 provided with a photodiode of a type that stores holes generated by photoelectric conversion in a p-type semiconductor region formed in an n-type well region of a semiconductor substrate composed of Si. It can also be applied to.
  • the saturation detection unit 350 and the holding unit 360 of the second embodiment may be combined with the third and fourth embodiments.
  • the technology according to the present disclosure can be applied to various products.
  • the present technology may be realized as an image pickup device mounted on an image pickup device such as a camera.
  • FIG. 12 is a block diagram showing a schematic configuration example of a camera which is an example of an imaging device to which the present technology can be applied.
  • the camera 1000 in the figure includes a lens 1001, an image pickup element 1002, an image pickup control unit 1003, a lens drive unit 1004, an image processing unit 1005, an operation input unit 1006, a frame memory 1007, a display unit 1008, and the like.
  • a recording unit 1009 is provided.
  • the lens 1001 is a photographing lens of the camera 1000.
  • the lens 1001 collects light from the subject and causes the light to be incident on the image pickup device 1002 described later to form an image of the subject.
  • the image sensor 1002 is a semiconductor element that captures light from a subject focused by the lens 1001.
  • the image sensor 1002 generates an analog image signal according to the irradiated light, converts it into a digital image signal, and outputs the signal.
  • the image pickup control unit 1003 controls the image pickup in the image pickup device 1002.
  • the image pickup control unit 1003 controls the image pickup device 1002 by generating a control signal and outputting the control signal to the image pickup device 1002. Further, the image pickup control unit 1003 can perform autofocus on the camera 1000 based on the image signal output from the image pickup device 1002.
  • the autofocus is a system that detects the focal position of the lens 1001 and automatically adjusts it.
  • a method (image plane phase difference autofocus) in which the image plane phase difference is detected by the phase difference pixels arranged in the image sensor 1002 to detect the focal position can be used. It is also possible to apply a method (contrast autofocus) of detecting the position where the contrast of the image is highest as the focal position.
  • the image pickup control unit 1003 adjusts the position of the lens 1001 via the lens drive unit 1004 based on the detected focal position, and performs autofocus.
  • the image pickup control unit 1003 can be configured by, for example, a DSP (Digital Signal Processor) equipped with firmware.
  • DSP Digital Signal Processor
  • the lens driving unit 1004 drives the lens 1001 based on the control of the imaging control unit 1003.
  • the lens driving unit 1004 can drive the lens 1001 by changing the position of the lens 1001 using a built-in motor.
  • the image processing unit 1005 processes the image signal generated by the image sensor 1002. This processing includes, for example, demosaic to generate an image signal of a color that is insufficient among the image signals corresponding to red, green, and blue for each pixel, noise reduction to remove noise of the image signal, and coding of the image signal. Applicable.
  • the image processing unit 1005 can be configured by, for example, a microcomputer equipped with firmware.
  • the operation input unit 1006 receives the operation input from the user of the camera 1000.
  • a push button or a touch panel can be used for the operation input unit 1006.
  • the operation input received by the operation input unit 1006 is transmitted to the image pickup control unit 1003 and the image processing unit 1005. After that, processing according to the operation input, for example, processing such as imaging of the subject is activated.
  • the frame memory 1007 is a memory that stores a frame that is an image signal for one screen.
  • the frame memory 1007 is controlled by the image processing unit 1005 and holds frames in the process of image processing.
  • the display unit 1008 displays the image processed by the image processing unit 1005.
  • a liquid crystal panel can be used.
  • the recording unit 1009 records the image processed by the image processing unit 1005.
  • a memory card or a hard disk can be used for the recording unit 1009.
  • the cameras to which this disclosure can be applied have been described above.
  • the present technology can be applied to the image pickup device 1002 among the configurations described above.
  • the image pickup device 1 described with reference to FIG. 1 can be applied to the image pickup device 1002.
  • the image sensor 1 By applying the image sensor 1 to the image sensor 1002, infrared light can be imaged and saturation of the image signal can be detected. It is possible to prevent deterioration of image quality.
  • the image processing unit 1005 is an example of the processing circuit described in the claims.
  • the camera 1000 is an example of the image pickup apparatus described in the claims.
  • the present technology can have the following configurations.
  • a pixel having a photoelectric conversion unit that performs photoelectric conversion of incident light and a charge holding unit that retains holes among the charges generated by the photoelectric conversion, and generates an image signal based on the retained holes.
  • An image pickup device including a clip circuit that performs clipping that limits the rise of the generated image signal to a predetermined clip voltage.
  • the clip circuit is composed of a follower circuit that performs the clip by limiting the rise of the image signal based on the predetermined clip voltage supplied to the control terminal. element.
  • the clip circuit is composed of the follower circuit by a transistor in which the predetermined clip voltage is supplied to the gate, the generated image signal is supplied to the drain, and the load is connected to the source. ).
  • a comparison unit that compares the generated image signal with a reference signal that serves as a reference when converting the generated image signal into a digital image signal and outputs the result of the comparison, and the comparison.
  • the unit includes a time measuring unit for measuring the time from the start of the comparison to the output of the comparison result, and further includes an analog-digital conversion unit that converts the image signal into a digital image signal based on the measurement result.
  • the pixel further includes a reset unit that discharges holes held in the charge holding unit to perform reset, and generates a reset image signal that is an image signal after the reset.
  • the comparison unit includes a differential pair in which the generated image signal and the reference signal are input via a coupling capacitor, and an initialization circuit for initializing the differential pair.
  • the image pickup device according to (5) or (6), wherein the clip circuit performs the clip at the time of initialization by the initialization circuit.
  • the image pickup device initializes by holding the initial value of the generated image signal and the initial value of the reference signal in the respective coupling capacitors.
  • the image pickup device according to any one of (4) to (8), further comprising a saturation detection unit for detecting saturation of the image signal.
  • the image pickup device detects the saturation based on the result of comparison in the comparison unit.
  • the image pickup device according to (9) or (10), further comprising a correction unit that corrects the digital image signal based on the detection result of the saturation detection unit.
  • a pixel that includes a photoelectric conversion unit that performs photoelectric conversion of incident light and a charge holding unit that retains holes among the charges generated by the photoelectric conversion, and generates an image signal based on the retained holes.
  • a clip circuit that performs clipping that limits the rise of the generated image signal to a predetermined clip voltage
  • An imaging device including a processing circuit that processes the generated image signal.
  • Image sensor 10 Pixel array unit 30
  • Column signal processing unit 31 Clip circuit 32
  • Analog digital conversion unit 33 Constant current circuit 35
  • Reference signal generation unit 100 pixels 101
  • Photoelectric conversion unit 102, 103 Charge holding unit 104 to 109, 311, 323 to 329 MOS transistor 320 Comparison unit 321, 322 Capacitor 330

Abstract

This image-capturing element, which generates an image signal based on holes generated and accumulated by photoelectric conversion, detects the saturation of the image signal and prevents the image quality from being deteriorated.　The image-capturing element includes a pixel and a clip circuit. The pixel includes a photoelectric conversion unit for performing photoelectric conversion on incident light, and a charge holding unit for holding holes among the charges generated by the photoelectric conversion, and generates an image signal on the basis of the held holes. The clip circuit performs clipping for limiting the rise of the generated image signal to a predetermined clip voltage.

Description

撮像素子および撮像装置Image sensor and image sensor
　本開示は、撮像素子および撮像装置に関する。詳しくは、光電変換により生成されて蓄積された正孔に基づく画像信号を生成する撮像素子および当該撮像素子を使用する撮像装置に関する。 The present disclosure relates to an image pickup device and an image pickup device. More specifically, the present invention relates to an image pickup device that generates an image signal based on holes generated and accumulated by photoelectric conversion, and an image pickup device that uses the image pickup device.
　従来、複数の画素が配置された撮像素子が使用されている。この画素には、入射光の光電変換により生成された電荷を蓄積する電荷生成部、この蓄積された電荷を転送する転送部、この転送された電荷を保持する浮遊拡散領域（フローティングディフュージョン：Floating Diffusion）が配置される。また、画素には、フローティングディフュージョンの電位変化を増幅する増幅用トランジスタが配置され、フローティングディフュージョンに保持された電荷に基づいて画像信号が生成される。また、画素には、電荷保持部に保持された電荷を排出してリセットする初期化部がさらに配置される。露光期間に電荷生成部において光電変換による電荷が蓄積され、露光期間の経過後に初期化部によるフローティングディフュージョンのリセットが行われ、電荷転送部によりフローティングディフュージョンに電荷が転送されて保持される。この保持された電荷に基づいて増幅用トランジスタにより画像信号が生成されて出力される。 Conventionally, an image sensor in which a plurality of pixels are arranged has been used. In this pixel, a charge generation unit that stores the electric charge generated by photoelectric conversion of incident light, a transfer unit that transfers the accumulated electric charge, and a floating diffusion region (floating diffusion) that holds the transferred electric charge. ) Is placed. Further, an amplification transistor for amplifying the potential change of the floating diffusion is arranged in the pixel, and an image signal is generated based on the electric charge held in the floating diffusion. Further, the pixel is further arranged with an initialization unit that discharges and resets the charge held in the charge holding unit. Charges due to photoelectric conversion are accumulated in the charge generation unit during the exposure period, the floating diffusion is reset by the initialization unit after the exposure period elapses, and the charges are transferred to and held by the charge transfer unit to the floating diffusion. An image signal is generated and output by the amplification transistor based on the retained electric charge.
　リセットによりフローティングディフュージョンの電荷が排出され、画像信号の黒レベルが設定される。すなわち、リセット直後に増幅用トランジスタにより生成される画像信号は黒レベルに相当する画像信号となる。しかし、フローティングディフュージョンに保持された全ての電荷の排出は困難であり、リセット後にフローティングディフュージョンに残留する電荷が存在する。この残留する電荷が画素毎に異なるため、画素毎に黒レベルが変動し、画像信号にノイズが発生する。 By resetting, the charge of floating diffusion is discharged and the black level of the image signal is set. That is, the image signal generated by the amplification transistor immediately after reset becomes an image signal corresponding to the black level. However, it is difficult to discharge all the charges held in the floating diffusion, and there are charges remaining in the floating diffusion after reset. Since the residual charge is different for each pixel, the black level fluctuates for each pixel, and noise is generated in the image signal.
　このノイズの発生を防ぐため、画像信号の生成をリセット直後およびフローティングディフュージョンへの電荷の転送後の２回行う方式が使用されている。これら２つの画像信号の差分に基づく画像信号を生成することにより、フローティングディフュージョンに残留する電荷の影響を除去することができる。このような画像信号の生成方法は、相関２重サンプリング（ＣＤＳ：Correlated Double Sampling）と称される。 In order to prevent the generation of this noise, a method is used in which the image signal is generated twice, immediately after the reset and after the charge is transferred to the floating diffusion. By generating an image signal based on the difference between these two image signals, the influence of the electric charge remaining on the floating diffusion can be eliminated. Such a method of generating an image signal is called Correlated Double Sampling (CDS).
　上述のＣＤＳにおいて、リセット直後のリセットレベルの画像信号の生成過程はＰ相と称され、光電変換により生成された電荷が転送された後の信号レベルの画像信号の生成過程はＤ相と称される。Ｄ相において生成された信号レベルの画像信号からＰ相において生成されたリセットレベルの画像信号を差し引くことにより、リセットレベル（黒レベル）の変動の影響を低減することができる。この相関２重サンプリングを採用する撮像素子においては、強い入射光の撮像を行う際に問題となる。太陽等の高輝度の被写体を撮像する際、画素の入射光の光量が増加して電荷生成部の飽和レベルを超える電荷が生成される。この飽和レベルを超過した電荷がフローティングディフュージョンに流入することにより、フローティングディフュージョンの電荷が飽和し、Ｐ相において高いリセットレベルの画像信号が生成される。Ｄ相においても高い信号レベルの画像信号が生成され、これらの画像信号の差分に基づく画像信号が生成される結果、高輝度の被写体にも関わらず低輝度の画像信号が出力される。このため、太陽等の高輝度の被写体が黒く表示される黒化現象を生じ、画質が低下する。 In the above-mentioned CDS, the process of generating an image signal at the reset level immediately after reset is called the P phase, and the process of generating the image signal at the signal level after the charge generated by the photoelectric conversion is transferred is called the D phase. To. By subtracting the reset level image signal generated in the P phase from the signal level image signal generated in the D phase, the influence of the reset level (black level) fluctuation can be reduced. In an image sensor that employs this correlated double sampling, there is a problem when imaging strong incident light. When imaging a high-intensity subject such as the sun, the amount of incident light of the pixels increases and charges exceeding the saturation level of the charge generation unit are generated. When the charge exceeding the saturation level flows into the floating diffusion, the charge of the floating diffusion is saturated and an image signal having a high reset level is generated in the P phase. An image signal having a high signal level is also generated in the D phase, and an image signal based on the difference between these image signals is generated. As a result, a low-luminance image signal is output despite the high-luminance subject. For this reason, a blackening phenomenon occurs in which a high-brightness subject such as the sun is displayed in black, and the image quality is deteriorated.
　この黒化現象の発生を防ぐため、Ｐ相におけるリセットレベルの画像信号を判定レベルと比較することにより飽和レベルを超える光量の入射光が画素に入射したことを検出する撮像素子が提案されている（例えば、特許文献１参照。）。この従来技術の撮像素子においては、差動対により構成された比較器を使用し、画素から出力される画像信号が比較器の非反転入力端子に接続され、判定レベルに相当する信号が比較器の反転入力端子に接続される。判定レベルより高い電圧の画像信号が比較器に入力された際に、飽和レベルを超える光量の入射光の画素への入射が検出される。この黒化現象を生じた画像信号が後段の回路により補正される。 In order to prevent the occurrence of this blackening phenomenon, an image sensor has been proposed that detects that an incident light having an amount of light exceeding the saturation level is incident on a pixel by comparing the image signal of the reset level in the P phase with the determination level. (See, for example, Patent Document 1.). In this conventional image sensor, a comparator composed of differential pairs is used, an image signal output from a pixel is connected to a non-inverting input terminal of the comparator, and a signal corresponding to a determination level is a comparator. It is connected to the inverting input terminal of. When an image signal having a voltage higher than the determination level is input to the comparator, the incident light having an amount of light exceeding the saturation level is detected. The image signal that caused this blackening phenomenon is corrected by the circuit in the subsequent stage.
特開２００８－２８３５５７号公報Japanese Unexamined Patent Publication No. 2008-283557
　上述の従来技術では、画像信号の極性が反転する場合には、飽和レベルを超える光量の入射光の画素への入射が検出されず、黒化現象の発生を防ぐことができないという問題がある。上述の従来技術の撮像素子は、シリコン（Ｓｉ）により構成される光電変換部が配置される。このＳｉによる電荷生成部は、光電変換により生成された電荷のうちの電子を蓄積する。この蓄積された電子がフローティングディフュージョンに保持されるため、入射光量の増加に伴って信号のレベルが低下する画像信号が生成される。これに対し、赤外光等の長波長の光の撮像を行う撮像素子においては、Ｓｉの代わりにＩＩＩ－Ｖ族化合物半導体による光電変換部が使用される。赤色光等における感度を向上させるためである。このＩＩＩ－Ｖ族化合物半導体による光電変換部から光電変換により生成された電荷のうちの正孔が取り出されて蓄積される。この蓄積された正孔に基づいて画像信号が生成される。このため、入射光量の増加に伴ってレベルが上昇する画像信号が生成されることとなり、比較器による飽和レベルを超える光量の入射光の画素への入射が検出できず、黒化現象が発生する。 In the above-mentioned conventional technique, when the polarity of the image signal is inverted, there is a problem that the incident light of the incident light exceeding the saturation level is not detected in the pixel and the occurrence of the blackening phenomenon cannot be prevented. In the above-mentioned conventional image pickup device, a photoelectric conversion unit made of silicon (Si) is arranged. This Si-based charge generator accumulates electrons in the charges generated by photoelectric conversion. Since the accumulated electrons are held in the floating diffusion, an image signal whose signal level decreases as the amount of incident light increases is generated. On the other hand, in an image sensor that captures long-wavelength light such as infrared light, a photoelectric conversion unit using a III-V compound semiconductor is used instead of Si. This is to improve the sensitivity in red light and the like. Holes in the charges generated by the photoelectric conversion are taken out from the photoelectric conversion part of the III-V compound semiconductor and accumulated. An image signal is generated based on the accumulated holes. Therefore, an image signal whose level rises as the amount of incident light increases is generated, and the comparator cannot detect the incident of the incident light having an amount of light exceeding the saturation level on the pixel, and a blackening phenomenon occurs. ..
　本開示は、上述した問題点に鑑みてなされたものであり、光電変換により生成されて蓄積された正孔に基づく画像信号を生成する撮像素子において画像信号の飽和を検出し、画質の低下を防ぐことを目的としている。 The present disclosure has been made in view of the above-mentioned problems, and the saturation of the image signal is detected in the image sensor that generates the image signal based on the holes generated and accumulated by the photoelectric conversion, and the deterioration of the image quality is deteriorated. The purpose is to prevent it.
　本開示は、上述の問題点を解消するためになされたものであり、その第１の態様は、入射光の光電変換を行う光電変換部および上記光電変換により生成された電荷のうち正孔を保持する電荷保持部を備え、上記保持された正孔に基づいて画像信号を生成する画素と、上記生成された画像信号の上昇を所定のクリップ電圧に制限するクリップを行うクリップ回路とを具備する撮像素子である。 The present disclosure has been made to solve the above-mentioned problems, and the first aspect thereof is a photoelectric conversion unit that performs photoelectric conversion of incident light and holes among the charges generated by the photoelectric conversion. It is provided with a charge holding unit for holding, and includes a pixel that generates an image signal based on the held holes and a clip circuit that performs clipping that limits the rise of the generated image signal to a predetermined clip voltage. It is an image sensor.
　また、この第１の態様において、上記クリップ回路は、制御端子に供給された上記所定のクリップ電圧に基づいて上記画像信号の上昇を制限することにより上記クリップを行うフォロワ回路により構成されてもよい。 Further, in the first aspect, the clip circuit may be configured by a follower circuit that performs the clip by limiting the rise of the image signal based on the predetermined clip voltage supplied to the control terminal. ..
　また、この第１の態様において、上記クリップ回路は、ゲートに上記所定のクリップ電圧が供給され、上記生成された画像信号がドレインに供給され、ソースに負荷が接続されるトランジスタによる上記フォロワ回路により構成されてもよい。 Further, in the first aspect, in the clip circuit, the predetermined clip voltage is supplied to the gate, the generated image signal is supplied to the drain, and the load is connected to the source by the follower circuit. It may be configured.
　また、この第１の態様において、上記生成された画像信号をデジタルの画像信号に変換する際の基準となる参照信号と上記生成された画像信号との比較を行って当該比較の結果を出力する比較部と、上記比較部における上記比較の開始から上記比較の結果の出力までの計時を行う計時部とを備え、上記計時の結果に基づいて上記画像信号をデジタルの画像信号に変換するアナログデジタル変換部をさらに具備してもよい。 Further, in the first aspect, the reference signal as a reference when converting the generated image signal into a digital image signal is compared with the generated image signal, and the result of the comparison is output. An analog digital that includes a comparison unit and a time measuring unit that measures the time from the start of the comparison to the output of the result of the comparison in the comparison unit, and converts the image signal into a digital image signal based on the result of the time measurement. A conversion unit may be further provided.
　また、この第１の態様において、上記画素は、上記電荷保持部に保持された正孔を排出してリセットを行うリセット部をさらに備えて当該リセット後の画像信号であるリセット画像信号を生成し、上記アナログデジタル変換部は、上記生成された画像信号とリセット画像信号との差分に基づいて上記デジタルの画像信号を生成してもよい。 Further, in the first aspect, the pixel further includes a reset unit that discharges holes held in the charge holding unit to perform reset, and generates a reset image signal that is an image signal after the reset. The analog-to-digital converter may generate the digital image signal based on the difference between the generated image signal and the reset image signal.
　また、この第１の態様において、上記クリップ回路は、上記リセット画像信号の生成の際に上記クリップを行ってもよい。 Further, in the first aspect, the clip circuit may perform the clip at the time of generating the reset image signal.
　また、この第１の態様において、上記比較部は、上記生成された画像信号および上記参照信号がそれぞれ結合キャパシタを介して入力される差動対と、上記差動対を初期化する初期化回路とを備え、上記クリップ回路は、上記初期化回路による初期化の際に上記クリップを行ってもよい。 Further, in the first aspect, the comparison unit includes a differential pair in which the generated image signal and the reference signal are input via a coupling capacitor, and an initialization circuit for initializing the differential pair. The clip circuit may perform the clip at the time of initialization by the initialization circuit.
　また、この第１の態様において、上記初期化回路は、上記生成された画像信号の初期値および上記参照信号の初期値を上記それぞれの結合キャパシタに保持させることにより初期化してもよい。 Further, in the first aspect, the initialization circuit may be initialized by holding the initial value of the generated image signal and the initial value of the reference signal in the respective coupling capacitors.
　また、この第１の態様において、上記画像信号の飽和を検出する飽和検出部をさらに具備してもよい。 Further, in this first aspect, a saturation detection unit for detecting the saturation of the image signal may be further provided.
　また、この第１の態様において、上記飽和検出部は、上記比較部における比較の結果に基づいて上記飽和を検出してもよい。 Further, in this first aspect, the saturation detection unit may detect the saturation based on the result of comparison in the comparison unit.
　また、この第１の態様において、上記飽和検出部の検出結果に基づいて上記デジタルの画像信号の補正を行う補正部をさらに具備してもよい。 Further, in this first aspect, a correction unit that corrects the digital image signal based on the detection result of the saturation detection unit may be further provided.
　また、本開示の第２の態様は、入射光の光電変換を行う光電変換部および上記光電変換により生成された電荷のうち正孔を保持する電荷保持部を備え、上記保持された正孔に基づいて画像信号を生成する画素と、上記生成された画像信号の上昇を所定のクリップ電圧に制限するクリップを行うクリップ回路と、上記生成された画像信号の処理を行う処理回路とを具備する撮像装置である。 A second aspect of the present disclosure includes a photoelectric conversion unit that performs photoelectric conversion of incident light and a charge holding unit that retains holes among the charges generated by the photoelectric conversion, and the retained holes. Imaging with a pixel that generates an image signal based on the above, a clip circuit that performs clipping that limits the rise of the generated image signal to a predetermined clip voltage, and a processing circuit that processes the generated image signal. It is a device.
　このような態様を採ることにより、光電変換により生成されて蓄積された正孔に基づく画像信号を生成する撮像素子における画像信号の上昇を所定の電圧に制限するという作用をもたらす。高輝度の被写体の撮像の際の画像信号の飽和の抑制が想定される。 By adopting such an aspect, the effect of limiting the rise of the image signal in the image sensor that generates the image signal based on the holes generated and accumulated by the photoelectric conversion to a predetermined voltage is brought about. It is assumed that saturation of the image signal is suppressed when capturing a high-brightness subject.
本開示の実施の形態に係る撮像素子の構成例を示す図である。It is a figure which shows the structural example of the image pickup device which concerns on embodiment of this disclosure. 本開示の第1の実施の形態に係る画素の構成例を示す図である。It is a figure which shows the structural example of the pixel which concerns on 1st Embodiment of this disclosure. 本開示の実施の形態に係るカラム信号処理部の構成例を示す図である。It is a figure which shows the structural example of the column signal processing part which concerns on embodiment of this disclosure. 本開示の第１の実施の形態に係るクリップ回路の構成例を示す図である。It is a figure which shows the structural example of the clip circuit which concerns on 1st Embodiment of this disclosure. 本開示の第１の実施の形態に係るアナログデジタル変換部の構成例を示す図である。It is a figure which shows the structural example of the analog-digital conversion part which concerns on 1st Embodiment of this disclosure. 本開示の実施の形態に係る比較部の構成例を示す図である。It is a figure which shows the structural example of the comparison part which concerns on embodiment of this disclosure. 本開示の実施の形態に係る画像信号の変換の一例を示す図である。It is a figure which shows an example of the conversion of the image signal which concerns on embodiment of this disclosure. 本開示の第２の実施の形態に係るアナログデジタル変換部の構成例を示す図である。It is a figure which shows the structural example of the analog-digital conversion part which concerns on the 2nd Embodiment of this disclosure. 本開示の第３の実施の形態に係る画素の構成例を示す図である。It is a figure which shows the structural example of the pixel which concerns on the 3rd Embodiment of this disclosure. 本開示の第４の実施の形態に係る画素の構成例を示す図である。It is a figure which shows the structural example of the pixel which concerns on 4th Embodiment of this disclosure. 本開示の第５の実施の形態に係る画素の構成例を示す図である。It is a figure which shows the structural example of the pixel which concerns on 5th Embodiment of this disclosure. 本技術が適用され得る撮像装置の一例であるカメラの概略的な構成例を示すブロック図である。It is a block diagram which shows the schematic configuration example of the camera which is an example of the image pickup apparatus to which this technology can be applied.
　次に、図面を参照して、本開示を実施するための形態（以下、実施の形態と称する）を説明する。以下の図面において、同一または類似の部分には同一または類似の符号を付している。また、以下の順序で実施の形態の説明を行う。
　１．第１の実施の形態
　２．第２の実施の形態
　３．第３の実施の形態
　４．第４の実施の形態
　５．カメラへの応用例 Next, a mode for carrying out the present disclosure (hereinafter, referred to as an embodiment) will be described with reference to the drawings. In the drawings below, the same or similar parts are designated by the same or similar reference numerals. In addition, the embodiments will be described in the following order.
1. 1. First Embodiment 2. Second embodiment 3. Third embodiment 4. Fourth Embodiment 5. Application example to camera
　＜１．第１の実施の形態＞
　［撮像素子の構成］
　図１は、本開示の実施の形態に係る撮像素子の構成例を示す図である。同図の撮像素子１は、画素アレイ部１０と、垂直駆動部２０と、カラム信号処理部３０と、制御部４０とを備える。 <1. First Embodiment>
[Structure of image sensor]
FIG. 1 is a diagram showing a configuration example of an image sensor according to an embodiment of the present disclosure. The image sensor 1 in the figure includes a pixel array unit 10, a vertical drive unit 20, a column signal processing unit 30, and a control unit 40.
　画素アレイ部１０は、画素１００が２次元格子状に配置されて構成されたものである。ここで、画素１００は、照射された光に応じた画像信号を生成するものである。この画素１００は、照射された光に応じた電荷を生成する光電変換部を有する。また画素１００は、画素回路をさらに有する。この画素回路は、光電変換部により生成された電荷に基づく画像信号を生成する。画像信号の生成は、後述する垂直駆動部２０により生成された制御信号により制御される。画素アレイ部１０には、信号線１１および１２がＸＹマトリクス状に配置される。信号線１１は、画素１００における画素回路の制御信号を伝達する信号線であり、画素アレイ部１０の行毎に配置され、各行に配置される画素１００に対して共通に配線される。信号線１２は、画素１００の画素回路により生成された画像信号を伝達する信号線であり、画素アレイ部１０の列毎に配置され、各列に配置される画素１００に対して共通に配線される。これら光電変換部および画素回路は、半導体基板に形成される。 The pixel array unit 10 is configured by arranging the pixels 100 in a two-dimensional grid pattern. Here, the pixel 100 generates an image signal according to the irradiated light. The pixel 100 has a photoelectric conversion unit that generates an electric charge according to the irradiated light. Further, the pixel 100 further has a pixel circuit. This pixel circuit generates an image signal based on the electric charge generated by the photoelectric conversion unit. The generation of the image signal is controlled by the control signal generated by the vertical drive unit 20 described later. The signal lines 11 and 12 are arranged in the pixel array unit 10 in an XY matrix. The signal line 11 is a signal line that transmits a control signal of the pixel circuit in the pixel 100, is arranged for each line of the pixel array unit 10, and is commonly wired to the pixel 100 arranged in each line. The signal line 12 is a signal line for transmitting an image signal generated by the pixel circuit of the pixel 100, is arranged in each row of the pixel array unit 10, and is commonly wired to the pixel 100 arranged in each row. To. These photoelectric conversion units and pixel circuits are formed on a semiconductor substrate.
　垂直駆動部２０は、画素１００の画素回路の制御信号を生成するものである。この垂直駆動部２０は、生成した制御信号を同図の信号線１１を介して画素１００に伝達する。 The vertical drive unit 20 generates a control signal for the pixel circuit of the pixel 100. The vertical drive unit 20 transmits the generated control signal to the pixel 100 via the signal line 11 in the figure.
　カラム信号処理部３０は、画素１００により生成された画像信号を処理するものである。このカラム信号処理部３０は、同図の信号線１２を介して画素１００から伝達された画像信号の処理を行う。カラム信号処理部３０における処理には、例えば、画素１００において生成されたアナログの画像信号をデジタルの画像信号に変換するアナログデジタル変換が該当する。また、カラム信号処理部３０は、前述の相関２重サンプリングの処理を行うことができる。カラム信号処理部３０により処理された画像信号は、撮像素子１の画像信号として出力される。カラム信号処理部３０の構成の詳細については後述する。 The column signal processing unit 30 processes the image signal generated by the pixel 100. The column signal processing unit 30 processes the image signal transmitted from the pixel 100 via the signal line 12 in the figure. The processing in the column signal processing unit 30 corresponds to, for example, analog-to-digital conversion that converts an analog image signal generated in the pixel 100 into a digital image signal. Further, the column signal processing unit 30 can perform the above-mentioned correlation double sampling processing. The image signal processed by the column signal processing unit 30 is output as an image signal of the image sensor 1. The details of the configuration of the column signal processing unit 30 will be described later.
　制御部４０は、撮像素子１の全体を制御するものである。この制御部４０は、垂直駆動部２０およびカラム信号処理部３０を制御する制御信号を生成して出力することにより、撮像素子１の制御を行う。制御部４０により生成された制御信号は、信号線４１および４２により垂直駆動部２０およびカラム信号処理部３０に対してそれぞれ伝達される。 The control unit 40 controls the entire image sensor 1. The control unit 40 controls the image sensor 1 by generating and outputting a control signal for controlling the vertical drive unit 20 and the column signal processing unit 30. The control signal generated by the control unit 40 is transmitted to the vertical drive unit 20 and the column signal processing unit 30 by the signal lines 41 and 42, respectively.
　［画素の構成］
　図２は、本開示の第1の実施の形態に係る画素の構成例を示す図である。同図は、画素１００の構成例を表す回路図である。同図の画素１００は、光電変換部１０１と、電荷保持部１０２および１０３と、ＭＯＳトランジスタ１０４乃至１０８とを備える。また、同図の画素１００には、電源線Ｖｄｄ、電源線Ｖｄｒおよび電源線Ｖｔｏｐが配置される。電源線Ｖｄｄは、画素１００の電源を供給する。電源線Ｖｄｒは、リセット電位を伝達する。電源線Ｖｔｏｐは光電変換部１０１のバイアス電圧を供給する。ＭＯＳトランジスタ１０４乃至１０６には、ｐチャネルＭＯＳトランジスタを使用することができる。また、ＭＯＳトランジスタ１０７および１０８には、ｎチャネルＭＯＳを使用することができる。 [Pixel composition]
FIG. 2 is a diagram showing a configuration example of pixels according to the first embodiment of the present disclosure. The figure is a circuit diagram showing a configuration example of the pixel 100. The pixel 100 in the figure includes a photoelectric conversion unit 101, charge holding units 102 and 103, and MOS transistors 104 to 108. Further, a power supply line Vdd, a power supply line Vdr, and a power supply line Vtop are arranged in the pixel 100 in the figure. The power line Vdd supplies power to the pixel 100. The power line Vdr transmits the reset potential. The power line Vtop supplies the bias voltage of the photoelectric conversion unit 101. A p-channel MOS transistor can be used for the MOS transistors 104 to 106. Further, n-channel MOS can be used for the MOS transistors 107 and 108.
　光電変換部１０１のカソードは電源線Ｖｔｏｐに接続され、アノードはＭＯＳトランジスタ１０４のソース、ＭＯＳトランジスタ１０５のソースおよび電荷保持部１０２の一端に接続される。電荷保持部１０２の他の一端は接地される。ＭＯＳトランジスタ１０４の、ゲートはオーバーフローゲート信号線ＯＦＧに接続され、ドレインは電源線Ｖｄｒに接続される。ＭＯＳトランジスタ１０５のゲートは転送信号線ＴＲに接続され、ドレインはＭＯＳトランジスタ１０６のソース、ＭＯＳトランジスタ１０７のゲートおよび電荷保持部１０３の一端に接続される。電荷保持部１０３の他の一端は、接地される。ＭＯＳトランジスタ１０６のドレインは、電源線Ｖｄｒに接続される。ＭＯＳトランジスタ１０７のドレインは、電源線Ｖｄｄに接続され、ソースはＭＯＳトランジスタ１０８のドレインに接続される。ＭＯＳトランジスタ１０８のゲートは選択信号線ＳＥＬに接続され、ソースは出力信号線Ｖｏに接続される。なお、オーバーフローゲート信号線ＯＦＧ、転送信号線ＴＲ、リセット信号線ＲＳＴおよび選択信号線ＳＥＬは、信号線１１を構成する。出力信号線Ｖｏは、信号線１２を構成する。 The cathode of the photoelectric conversion unit 101 is connected to the power supply line Vtop, and the anode is connected to the source of the MOS transistor 104, the source of the MOS transistor 105, and one end of the charge holding unit 102. The other end of the charge holding portion 102 is grounded. The gate of the MOS transistor 104 is connected to the overflow gate signal line OFG, and the drain is connected to the power supply line Vdr. The gate of the MOS transistor 105 is connected to the transfer signal line TR, and the drain is connected to the source of the MOS transistor 106, the gate of the MOS transistor 107, and one end of the charge holding unit 103. The other end of the charge holding portion 103 is grounded. The drain of the MOS transistor 106 is connected to the power supply line Vdr. The drain of the MOS transistor 107 is connected to the power supply line Vdd, and the source is connected to the drain of the MOS transistor 108. The gate of the MOS transistor 108 is connected to the selection signal line SEL, and the source is connected to the output signal line Vo. The overflow gate signal line OFG, the transfer signal line TR, the reset signal line RST, and the selection signal line SEL constitute the signal line 11. The output signal line Vo constitutes the signal line 12.
　光電変換部１０１は、前述のように照射された光に応じた電荷を生成するものである。この光電変換部１０１には、フォトダイオードを使用することができる。同図に表したように、光電変換部１０１のカソードは電源線Ｖｔｏｐに接続される。この電源線Ｖｔｏｐは、例えば、２．２Ｖの電圧を供給することができる。光電変換部１０１のアノードは、後述する電荷保持部１０２に接続される。このため、光電変換部１０１の光電変換により生成される電荷のうち電子が電源線Ｖｔｏｐに排出され、正孔が電荷保持部１０２に移動して保持される。 The photoelectric conversion unit 101 generates an electric charge according to the irradiated light as described above. A photodiode can be used for the photoelectric conversion unit 101. As shown in the figure, the cathode of the photoelectric conversion unit 101 is connected to the power supply line Vtop. This power supply line Vtop can supply a voltage of, for example, 2.2V. The anode of the photoelectric conversion unit 101 is connected to the charge holding unit 102, which will be described later. Therefore, of the charges generated by the photoelectric conversion of the photoelectric conversion unit 101, electrons are discharged to the power supply line Vtop, and holes are moved to the charge holding unit 102 and held.
　電荷保持部１０２は、光電変換部１０１により生成される電荷を保持するキャパシタである。上述のように、電荷保持部１０２は、光電変換部１０１により生成される正孔を保持する。この電荷保持部１０２には、半導体基板に配置される半導体領域により構成されるキャパシタを適用することができる。 The charge holding unit 102 is a capacitor that holds the electric charge generated by the photoelectric conversion unit 101. As described above, the charge holding unit 102 holds the holes generated by the photoelectric conversion unit 101. A capacitor composed of a semiconductor region arranged on a semiconductor substrate can be applied to the charge holding unit 102.
　ＭＯＳトランジスタ１０４は、光電変換部１０１および電荷保持部１０２をリセットするトランジスタである。ＭＯＳトランジスタ１０４による光電変換部１０１および電荷保持部１０２のリセットは、オーバーフローゲート信号線ＯＦＧにより伝達される信号により制御される。同図に表したように、ＭＯＳトランジスタ１０４のドレインは電源線Ｖｄｒに接続される。この電源線Ｖｄｒは、例えば、１．２Ｖの電圧を供給することができる。このため、リセットの際、光電変換部１０１および電荷保持部１０２には１．２Ｖの電圧が印加され、光電変換部１０１および電荷保持部１０２に保持された正孔は、電源線Ｖｄｒに排出される。 The MOS transistor 104 is a transistor that resets the photoelectric conversion unit 101 and the charge holding unit 102. The reset of the photoelectric conversion unit 101 and the charge holding unit 102 by the MOS transistor 104 is controlled by the signal transmitted by the overflow gate signal line OFG. As shown in the figure, the drain of the MOS transistor 104 is connected to the power supply line Vdr. This power supply line Vdr can supply a voltage of, for example, 1.2V. Therefore, at the time of reset, a voltage of 1.2 V is applied to the photoelectric conversion unit 101 and the charge holding unit 102, and the holes held in the photoelectric conversion unit 101 and the charge holding unit 102 are discharged to the power supply line Vdr. To.
　ＭＯＳトランジスタ１０５は、光電変換部１０１により生成されて電荷保持部１０２に保持された電荷（正孔）を電荷保持部１０３に転送するトランジスタである。ＭＯＳトランジスタ１０５における電荷の転送は、転送信号線ＴＲにより伝達される信号により制御される。 The MOS transistor 105 is a transistor that transfers the charges (holes) generated by the photoelectric conversion unit 101 and held in the charge holding unit 102 to the charge holding unit 103. The charge transfer in the MOS transistor 105 is controlled by the signal transmitted by the transfer signal line TR.
　電荷保持部１０３は、ＭＯＳトランジスタ１０５により転送された電荷（正孔）を保持するキャパシタである。この電荷保持部１０３には、半導体基板に配置される半導体領域により構成されるフローティングディフュージョンを適用することができる。 The charge holding unit 103 is a capacitor that holds the charge (hole) transferred by the MOS transistor 105. Floating diffusion composed of a semiconductor region arranged on a semiconductor substrate can be applied to the charge holding unit 103.
　ＭＯＳトランジスタ１０７は、電荷保持部１０３に保持された電荷（正孔）に基づく信号を生成するトランジスタである。このＭＯＳトランジスタ１０７は、電荷保持部１０３とともにフローティングディフュージョンアンプを構成する。ＭＯＳトランジスタ１０７により生成される画像信号は、黒レベルがリセットの際の電圧である略１．２Ｖとなり、入射光の光量の増加に伴って電圧が上昇する信号となる。ＭＯＳトランジスタ１０７が電荷保持部１０３に蓄積される正孔に基づく画像信号を生成するためである。 The MOS transistor 107 is a transistor that generates a signal based on the electric charge (hole) held in the electric charge holding unit 103. The MOS transistor 107 constitutes a floating diffusion amplifier together with the charge holding unit 103. The image signal generated by the MOS transistor 107 has a black level of approximately 1.2 V, which is the voltage at the time of reset, and is a signal whose voltage increases as the amount of incident light increases. This is because the MOS transistor 107 generates an image signal based on the holes accumulated in the charge holding unit 103.
　ＭＯＳトランジスタ１０８は、ＭＯＳトランジスタ１０７により生成された信号を画像信号として出力信号線Ｖｏに出力するトランジスタである。このＭＯＳトランジスタ１０８は、選択信号線ＳＥＬにより伝達される信号により制御される。 The MOS transistor 108 is a transistor that outputs the signal generated by the MOS transistor 107 as an image signal to the output signal line Vo. The MOS transistor 108 is controlled by a signal transmitted by the selection signal line SEL.
　ＭＯＳトランジスタ１０６は、電荷保持部１０３に保持された電荷を電源線Ｖｄｒに排出することにより電荷保持部１０３をリセットするトランジスタである。このＭＯＳトランジスタ１０６によるリセットは、リセット信号線ＲＳＴにより伝達される信号により制御され、ＭＯＳトランジスタ１０５による電荷の転送の前に実行される。 The MOS transistor 106 is a transistor that resets the charge holding unit 103 by discharging the charge held by the charge holding unit 103 to the power supply line Vdr. The reset by the MOS transistor 106 is controlled by the signal transmitted by the reset signal line RST, and is executed before the charge transfer by the MOS transistor 105.
　同図の画素１００における画像信号の生成は、次のように行うことができる。まず、オーバーフローゲート信号線ＯＦＧに制御信号を出力してＭＯＳトランジスタ１０４を導通させ、電荷保持部１０２をリセットする。これにより、露光期間が開始され、光電変換部１０１により生成された電荷が電荷保持部１０２に蓄積される。この露光期間の経過後にリセット信号線ＲＳＴに制御信号を出力してＭＯＳトランジスタ１０６を導通させ、電荷保持部１０３をリセットする。この際、ＭＯＳトランジスタ１０７は、リセットされた電荷保持部１０３の電荷に基づいて画像信号を生成する。このリセット終了後に、選択信号線ＳＥＬに制御信号を出力してＭＯＳトランジスタ１０８を導通させる。これにより、リセット後の画像信号であるリセット画像信号が出力信号線Ｖｏに出力され、前述したＰ相における画像信号の生成を行うことができる。 The image signal in the pixel 100 in the figure can be generated as follows. First, a control signal is output to the overflow gate signal line OFG to conduct the MOS transistor 104, and the charge holding unit 102 is reset. As a result, the exposure period is started, and the electric charge generated by the photoelectric conversion unit 101 is accumulated in the charge holding unit 102. After the lapse of this exposure period, a control signal is output to the reset signal line RST to conduct the MOS transistor 106, and the charge holding unit 103 is reset. At this time, the MOS transistor 107 generates an image signal based on the charge of the reset charge holding unit 103. After the reset is completed, a control signal is output to the selection signal line SEL to conduct the MOS transistor 108. As a result, the reset image signal, which is the image signal after the reset, is output to the output signal line Vo, and the image signal in the P phase described above can be generated.
　次に、転送信号線ＴＲに制御信号を出力してＭＯＳトランジスタ１０５を導通させて電荷保持部１０２に保持された電荷を電荷保持部１０３に分配する。この分配された電荷は電荷保持部１０３に保持され、この保持された電荷に基づいてＭＯＳトランジスタ１０７により画像信号が生成される。次に、選択信号線ＳＥＬに制御信号を出力してＭＯＳトランジスタ１０８を導通させる。これにより、ＭＯＳトランジスタ１０７により生成された画像信号が出力信号線Ｖｏに出力され、前述したＤ相における画像信号の生成を行うことができる。 Next, a control signal is output to the transfer signal line TR to conduct the MOS transistor 105, and the charge held in the charge holding unit 102 is distributed to the charge holding unit 103. The distributed charge is held by the charge holding unit 103, and an image signal is generated by the MOS transistor 107 based on the held charge. Next, a control signal is output to the selection signal line SEL to conduct the MOS transistor 108. As a result, the image signal generated by the MOS transistor 107 is output to the output signal line Vo, and the image signal in the D phase described above can be generated.
　画素１００に太陽等の高輝度の被写体からの入射光が照射されると、電荷保持部１０３に入射光が漏洩して光電変換を生じ、電荷が生成されて電荷保持部１０３が飽和する。リセットの直後であっても電荷保持部１０３の電荷が飽和レベルに増加するため、ＭＯＳトランジスタ１０７からは飽和レベルの画像信号が生成される。この飽和レベルの画像信号は、Ｐ相およびＤ相において生成されて出力される。 When the pixel 100 is irradiated with incident light from a high-intensity subject such as the sun, the incident light leaks to the charge holding unit 103 to cause photoelectric conversion, and a charge is generated to saturate the charge holding unit 103. Since the charge of the charge holding unit 103 increases to the saturation level even immediately after the reset, the saturation level image signal is generated from the MOS transistor 107. This saturation level image signal is generated and output in the P phase and the D phase.
　［カラム信号処理部の構成］
　図３は、本開示の実施の形態に係るカラム信号処理部の構成例を示す図である。同図は、カラム信号処理部３０の構成例を表す図である。同図のカラム信号処理部３０は、クリップ回路３１と、定電流回路３３と、アナログデジタル変換（ＡＤ変換）部３２と、水平転送部３４と、参照信号生成部３５と、タイミング制御部３６とを備える。クリップ回路３１、定電流回路３３およびアナログデジタル変換部３２は、画素アレイ部１０の信号線１２の複数の出力信号線Ｖｏ毎に配置される。 [Structure of column signal processing unit]
FIG. 3 is a diagram showing a configuration example of a column signal processing unit according to the embodiment of the present disclosure. The figure is a diagram showing a configuration example of the column signal processing unit 30. The column signal processing unit 30 in the figure includes a clip circuit 31, a constant current circuit 33, an analog-to-digital conversion (AD conversion) unit 32, a horizontal transfer unit 34, a reference signal generation unit 35, and a timing control unit 36. To be equipped. The clip circuit 31, the constant current circuit 33, and the analog-to-digital conversion unit 32 are arranged for each of a plurality of output signal lines Vo of the signal lines 12 of the pixel array unit 10.
　参照信号生成部３５は、参照信号を生成するものである。ここで、参照信号とは、後述するアナログデジタル変換部３２におけるアナログデジタル変換の際の基準となる信号である。参照信号には、例えば、電圧がランプ関数状に上昇する信号を使用することができる。参照信号生成部３５は、図１において説明した制御部４０の制御に従って参照信号を生成し、信号線３０３を介してアナログデジタル変換部３２に供給する。 The reference signal generation unit 35 generates a reference signal. Here, the reference signal is a signal that serves as a reference for analog-to-digital conversion in the analog-to-digital conversion unit 32, which will be described later. As the reference signal, for example, a signal in which the voltage rises like a ramp function can be used. The reference signal generation unit 35 generates a reference signal according to the control of the control unit 40 described with reference to FIG. 1, and supplies the reference signal to the analog-digital conversion unit 32 via the signal line 303.
　タイミング制御部３６は、カラム信号処理部３０における各部の動作タイミングを制御するものである。このタイミング制御部３６は、制御部４０の制御に従ってカラム信号処理部３０の各部の制御信号を生成する。また、タイミング制御部３６は、後述するクリップ回路３１のクリップ電圧を生成する。これらの制御信号は、信号線３０１、３０４および３０６を介して出力される。 The timing control unit 36 controls the operation timing of each unit in the column signal processing unit 30. The timing control unit 36 generates control signals for each unit of the column signal processing unit 30 according to the control of the control unit 40. Further, the timing control unit 36 generates a clip voltage of the clip circuit 31 described later. These control signals are output via the signal lines 301, 304 and 306.
　クリップ回路３１は、画素１００により生成された画像信号のクリップを行う回路である。このクリップ回路３１は、信号線１２を構成する出力信号線Ｖｏを介して出力された画像信号のクリップを行う。ここで、画像信号のクリップとは、画像信号の上昇を所定のクリップ電圧に制限することである。前述のように、画素１００により生成される画像信号は、入射光の光量の増加に伴って電圧が上昇する信号である。太陽等の高輝度の被写体に対応する画像信号は、信号レベル（電圧）が過度に上昇する。クリップ回路３１は、この画像信号の過度の上昇を制限する。なお、クリップ電圧は、複数のクリップ回路３１に共通に配線される信号線３０１により供給される。クリップ後の画像信号は、信号線３０２に出力される。クリップ回路３１の構成の詳細については後述する。 The clip circuit 31 is a circuit that clips the image signal generated by the pixel 100. The clip circuit 31 clips the image signal output via the output signal line Vo constituting the signal line 12. Here, the clip of the image signal is to limit the rise of the image signal to a predetermined clip voltage. As described above, the image signal generated by the pixel 100 is a signal whose voltage increases as the amount of incident light increases. The signal level (voltage) of an image signal corresponding to a high-luminance subject such as the sun rises excessively. The clip circuit 31 limits the excessive rise of this image signal. The clip voltage is supplied by a signal line 301 that is commonly wired to the plurality of clip circuits 31. The clipped image signal is output to the signal line 302. The details of the configuration of the clip circuit 31 will be described later.
　定電流回路３３は、定電流を供給する回路である。この定電流回路３３は、信号線３０２と接地との間に接続されて信号線３０２に定電流のシンク電流を供給する。後述するように、定電流回路３３は、画素１００のＭＯＳトランジスタ１０７およびクリップ回路３１のＭＯＳトランジスタ３１１の負荷を構成する回路である。 The constant current circuit 33 is a circuit that supplies a constant current. The constant current circuit 33 is connected between the signal line 302 and the ground to supply a constant current sink current to the signal line 302. As will be described later, the constant current circuit 33 is a circuit that constitutes a load of the MOS transistor 107 of the pixel 100 and the MOS transistor 311 of the clip circuit 31.
　アナログデジタル変換部３２は、アナログの画像信号をデジタルの画像信号に変換するものである。同図のアナログデジタル変換部３２は、クリップ回路３１から出力された画像信号の変換を行う。アナログデジタル変換の際の基準となる参照信号は、複数のアナログデジタル変換部３２に共通に配線される信号線３０３により供給される。変換後のデジタルの画像信号は、信号線３０５を介して水平転送部３４に出力される。アナログデジタル変換部３２の構成の詳細ついては後述する。 The analog-to-digital conversion unit 32 converts an analog image signal into a digital image signal. The analog-digital conversion unit 32 in the figure converts the image signal output from the clip circuit 31. The reference signal that serves as a reference for analog-to-digital conversion is supplied by a signal line 303 that is commonly wired to the plurality of analog-to-digital conversion units 32. The converted digital image signal is output to the horizontal transfer unit 34 via the signal line 305. The details of the configuration of the analog-to-digital conversion unit 32 will be described later.
　水平転送部３４は、デジタルの画像信号を転送するものである。この水平転送部３４は、複数のアナログデジタル変換部３２により生成されたデジタルの画像信号を順次転送し、信号線３０７を介して出力する。 The horizontal transfer unit 34 transfers a digital image signal. The horizontal transfer unit 34 sequentially transfers the digital image signals generated by the plurality of analog-to-digital conversion units 32 and outputs them via the signal line 307.
　［クリップ回路の構成］
　図４は、本開示の第１の実施の形態に係るクリップ回路の構成例を示す図である。同図におけるＡはクリップ回路３１の構成例を表し、同図におけるＢはクリップ回路３１の動作を表す。同図におけるＡには、クリップ回路３１の他に、画素１００の電荷保持部１０３およびＭＯＳトランジスタ１０８ならびに定電流回路３３を記載した。クリップ回路３１は、ＭＯＳトランジスタ３１１を備える。 [Clip circuit configuration]
FIG. 4 is a diagram showing a configuration example of a clip circuit according to the first embodiment of the present disclosure. In the figure, A represents a configuration example of the clip circuit 31, and B in the figure represents the operation of the clip circuit 31. In A in the figure, in addition to the clip circuit 31, the charge holding unit 103 of the pixel 100, the MOS transistor 108, and the constant current circuit 33 are shown. The clip circuit 31 includes a MOS transistor 311.
　ＭＯＳトランジスタ３１１は、定電流回路３３とともにフォロワ回路を構成するトランジスタである。このＭＯＳトランジスタ３１１には、ｎチャネルＭＯＳトランジスタを使用することができる。ＭＯＳトランジスタ３１１のゲートは信号線３０１に接続され、クリップ電圧が印加される。ＭＯＳトランジスタ３１１のドレインは信号線１２に接続され、ソースは信号線３０２に接続される。この信号線３０２には、前述のように定電流回路３３がさらに接続される。ＭＯＳトランジスタ３１１および定電流回路３３は、ソースフォロワ回路を構成する。便宜上、クリップ回路３１にはＭＯＳトランジスタ３１１のみを記載したが、クリップ回路３１には定電流回路３３も含まれる。なお、定電流回路３３は、画素１００のＭＯＳトランジスタ１０８の負荷にも該当する。ＭＯＳトランジスタ１０８のソースと定電流回路３３との間にクリップ回路３１のＭＯＳトランジスタ３１１が挿入された構成となる。 The MOS transistor 311 is a transistor that constitutes a follower circuit together with the constant current circuit 33. An n-channel MOS transistor can be used for the MOS transistor 311. The gate of the MOS transistor 311 is connected to the signal line 301, and a clip voltage is applied. The drain of the MOS transistor 311 is connected to the signal line 12, and the source is connected to the signal line 302. As described above, the constant current circuit 33 is further connected to the signal line 302. The MOS transistor 311 and the constant current circuit 33 form a source follower circuit. For convenience, only the MOS transistor 311 is described in the clip circuit 31, but the clip circuit 31 also includes the constant current circuit 33. The constant current circuit 33 also corresponds to the load of the MOS transistor 108 of the pixel 100. The MOS transistor 311 of the clip circuit 31 is inserted between the source of the MOS transistor 108 and the constant current circuit 33.
　同図におけるＢは、クリップ回路３１の信号のレベル（電圧）の変化を表した図である。同図におけるＢにおいて、縦軸は電圧を表し、横軸は時間を表す。同図のおけるＢにおいて、点線のグラフ５０１は、電荷保持部１０３の電圧を表す。破線のグラフ５０２は、ＭＯＳトランジスタ１０８により生成される画像信号の電圧を表す。１点鎖線のグラフ５０３は、クリップ電圧を表す。実線のグラフ５０４は、ＭＯＳトランジスタ３１１のソースの電圧を表し、クリップ回路３１の出力電圧を表す。同図におけるＢは、電荷保持部１０３に保持された電荷が時間とともに増加して電圧が上昇し、電荷保持部１０３の電圧がランプ関数状に増加する場合の例を表したものである。 B in the figure is a diagram showing a change in the signal level (voltage) of the clip circuit 31. In B in the figure, the vertical axis represents voltage and the horizontal axis represents time. In B in the figure, the dotted line graph 501 represents the voltage of the charge holding unit 103. The broken line graph 502 represents the voltage of the image signal generated by the MOS transistor 108. Graph 503 of the alternate long and short dash line represents the clip voltage. The solid line graph 504 represents the source voltage of the MOS transistor 311 and represents the output voltage of the clip circuit 31. Reference numeral B in the figure shows an example in which the charge held in the charge holding unit 103 increases with time and the voltage rises, and the voltage of the charge holding unit 103 increases in a ramp function shape.
　電荷保持部１０３の電圧が低い領域において、電荷保持部１０３の電圧の上昇に伴って、画像信号の電圧は上昇する。この領域においては、ＭＯＳトランジスタ３１１のドレイン電圧がゲートに印加されるクリップ電圧より低いため、ＭＯＳトランジスタのドレインおよびソースの間が導通状態になる。ＭＯＳトランジスタ３１１のソースは画像信号と略同じ電圧となり、画素１００から出力された画像信号と略同じ電圧の信号がクリップ回路３１から出力される。 In the region where the voltage of the charge holding unit 103 is low, the voltage of the image signal increases as the voltage of the charge holding unit 103 increases. In this region, since the drain voltage of the MOS transistor 311 is lower than the clip voltage applied to the gate, the drain and source of the MOS transistor are in a conductive state. The source of the MOS transistor 311 has substantially the same voltage as the image signal, and a signal having substantially the same voltage as the image signal output from the pixel 100 is output from the clip circuit 31.
　しかし、画像信号がクリップ電圧に近い電圧に上昇すると、ＭＯＳトランジスタ３１１のソースの電圧は、画像信号に追従しなくなり、一定の電圧に制限される。この領域では、ＭＯＳトランジスタ３１１がソースフォロワとして動作する。ＭＯＳトランジスタ３１１のソースには、ゲートの電圧に対してゲートソース間の閾値電圧Ｖｇｓだけ低い電圧が出力される。このように、クリップ回路３１により画像信号がクリップされる。 However, when the image signal rises to a voltage close to the clip voltage, the source voltage of the MOS transistor 311 does not follow the image signal and is limited to a constant voltage. In this region, the MOS transistor 311 operates as a source follower. A voltage that is lower than the gate voltage by the threshold voltage Vgs between the gate sources is output to the source of the MOS transistor 311. In this way, the image signal is clipped by the clip circuit 31.
　クリップ回路３１の動作は、供給されるクリップ電圧により制御することができる。具体的には、所望の制限電圧に応じたクリップ電圧を供給することにより、クリップ回路３１にクリップ動作を行わせることができ、画像信号の上昇を制限することができる。また、電源線Ｖｄｄの電源電圧等の高い電圧をクリップ電圧として供給することにより、クリップ回路３１のクリップ動作を停止させることができ、画素１００により生成された画像信号を出力（通過）させることができる。 The operation of the clip circuit 31 can be controlled by the supplied clip voltage. Specifically, by supplying a clip voltage corresponding to a desired limit voltage, the clip circuit 31 can be made to perform a clip operation, and an increase in the image signal can be limited. Further, by supplying a high voltage such as the power supply voltage of the power supply line Vdd as the clip voltage, the clip operation of the clip circuit 31 can be stopped, and the image signal generated by the pixel 100 can be output (passed). it can.
　なお、クリップ回路３１の構成は、この例に限定されない。例えば、ＭＯＳトランジスタ以外の素子によるフォロワ回路を使用することもできる。 The configuration of the clip circuit 31 is not limited to this example. For example, a follower circuit using an element other than the MOS transistor can also be used.
　［アナログデジタル変換部の構成］
　図５は、本開示の第１の実施の形態に係るアナログデジタル変換部の構成例を示す図である。同図は、アナログデジタル変換部３２の構成例を表す図である。アナログデジタル変換部３２は、比較部３２０と、カウンタ３３０と、保持部３４０とを備える。また、同図には、信号線３０４として、初期化信号線ＳＥＴ、クロック信号線ＣＬＫ、初期化信号線ＣＬＲ、アップダウンカウント信号線Ｕ／Ｄおよび保持信号線ＨＬＤを記載した。 [Configuration of analog-to-digital converter]
FIG. 5 is a diagram showing a configuration example of an analog-to-digital conversion unit according to the first embodiment of the present disclosure. The figure is a diagram showing a configuration example of the analog-to-digital conversion unit 32. The analog-to-digital conversion unit 32 includes a comparison unit 320, a counter 330, and a holding unit 340. Further, in the figure, as the signal line 304, the initialization signal line SET, the clock signal line CLK, the initialization signal line CLR, the up / down count signal line U / D, and the holding signal line HLD are shown.
　比較部３２０は、画素１００により生成されたアナログの画像信号と参照信号との比較を行い、比較の結果をカウンタ３３０に対して出力するものである。例えば、比較の結果として、参照信号がアナログの画像信号より低い電圧の場合に値「０」を出力し、参照信号がアナログの画像信号より高い電圧に移行した場合に値「１」を出力することができる。これにより、参照信号がアナログの画像信号と略同じ値になったタイミングを検出することができる。比較部３２０の比較の結果は、信号線３０７を介してカウンタ３３０に出力される。また、比較部３２０には、初期化信号線ＳＥＴが接続される。比較部３２０は、上述の比較の開始前に、初期化信号線ＳＥＴからの制御信号によりを初期化される。比較部３２０の構成の詳細については後述する。 The comparison unit 320 compares the analog image signal generated by the pixel 100 with the reference signal, and outputs the comparison result to the counter 330. For example, as a result of comparison, a value "0" is output when the reference signal has a voltage lower than that of the analog image signal, and a value "1" is output when the reference signal shifts to a voltage higher than that of the analog image signal. be able to. Thereby, it is possible to detect the timing when the reference signal becomes substantially the same value as the analog image signal. The comparison result of the comparison unit 320 is output to the counter 330 via the signal line 307. Further, an initialization signal line SET is connected to the comparison unit 320. The comparison unit 320 is initialized by the control signal from the initialization signal line SET before the start of the above-mentioned comparison. The details of the configuration of the comparison unit 320 will be described later.
　カウンタ３３０は、比較部３２０における比較の開始から参照信号とアナログの画像信号とが略同じ値になるまでの時間を計時するものである。具体的には、参照信号生成部３５における参照信号の出力の開始から比較部３２０の出力が値「１」に遷移するまでの時間を計時する。上述のように、参照信号は、ランプ関数状に値が変化する信号である。この参照信号がアナログの画像信号と略同じ値になるまでの時間とアナログの画像信号の電圧とは１対１に対応する。このため、参照信号がアナログの画像信号と略同じ値になる際の経過時間に対応するデジタルの信号を生成して出力することにより、アナログデジタル変換を行うことができる。具体的には、カウンタ３３０は、参照信号の出力開始から比較部３２０の出力が値「１」に遷移するまでの期間にクロック信号のカウントを行い、カウント値をアナログデジタル変換の結果として出力することができる。このカウント値の出力は、信号線３０８を介して行われる。 The counter 330 measures the time from the start of comparison in the comparison unit 320 until the reference signal and the analog image signal have substantially the same value. Specifically, the time from the start of the output of the reference signal in the reference signal generation unit 35 to the transition of the output of the comparison unit 320 to the value "1" is measured. As described above, the reference signal is a signal whose value changes like a ramp function. There is a one-to-one correspondence between the time until the reference signal becomes substantially the same value as the analog image signal and the voltage of the analog image signal. Therefore, analog-to-digital conversion can be performed by generating and outputting a digital signal corresponding to the elapsed time when the reference signal becomes substantially the same value as the analog image signal. Specifically, the counter 330 counts the clock signal during the period from the start of output of the reference signal to the transition of the output of the comparison unit 320 to the value "1", and outputs the count value as a result of analog-to-digital conversion. be able to. The output of this count value is performed via the signal line 308.
　クロック信号は、クロック信号線ＣＬＫから入力される。また、カウンタ３３０は、初期化信号線ＣＬＲからの制御信号により値「０」に初期化される。また、カウンタ３３０は、アップカウントおよびダウンカウントを行うことができる。この、アップカウントおよびダウンカウントの切替えは、アップダウンカウント信号線Ｕ／Ｄからの制御信号により行うことができる。 The clock signal is input from the clock signal line CLK. Further, the counter 330 is initialized to the value "0" by the control signal from the initialization signal line CLR. Further, the counter 330 can perform up-counting and down-counting. The switching between the up count and the down count can be performed by the control signal from the up / down count signal line U / D.
　保持部３４０は、カウンタ３３０のカウント値を保持するものである。この保持部３４０は、アナログデジタル変換の結果であるカウンタ３３０のカウント値を保持する。この保持部３４０に保持されたカウント値がデジタルの画像信号に該当する。保持部３４０は、保持信号線ＨＬＤからの制御信号に基づいてカウント値の保持を行う。 The holding unit 340 holds the count value of the counter 330. The holding unit 340 holds the count value of the counter 330, which is the result of analog-to-digital conversion. The count value held in the holding unit 340 corresponds to a digital image signal. The holding unit 340 holds the count value based on the control signal from the holding signal line HLD.
　［比較部の構成］
　図６は、本開示の実施の形態に係る比較部の構成例を示す図である。同図の比較部３２０は、キャパシタ３２１および３２２と、ＭＯＳトランジスタ３２３乃至３２９とを備える。ＭＯＳトランジスタ３２３乃至３２６には、ｐチャネルＭＯＳトランジスタを使用することができる。また、ＭＯＳトランジスタ３２７乃至３２９には、ｎチャネルＭＯＳトランジスタを使用することができる。また、同図の比較部３２０には、電源を供給する電源線Ｖｄｄ、バイアス電圧を供給する電源線Ｖｂｉａｓが配線される。 [Structure of comparison part]
FIG. 6 is a diagram showing a configuration example of a comparison unit according to the embodiment of the present disclosure. The comparison unit 320 in the figure includes capacitors 321 and 322 and MOS transistors 323 to 329. A p-channel MOS transistor can be used as the MOS transistor 323 to 326. Further, an n-channel MOS transistor can be used for the MOS transistors 327 to 329. Further, a power supply line Vdd for supplying power and a power supply line Vbias for supplying a bias voltage are wired in the comparison unit 320 in the figure.
　キャパシタ３２１は、信号線３０３およびＭＯＳトランジスタ３２７のゲートの間に接続される。ＭＯＳトランジスタ３２７のゲートにはＭＯＳトランジスタ３２５のドレインがさらに接続される。ＭＯＳトランジスタ３２７のドレインは、ＭＯＳトランジスタ３２５のソース、ＭＯＳトランジスタ３２３のドレインおよびゲートならびにＭＯＳトランジスタ３２４のゲートに接続される。ＭＯＳトランジスタ３２３のソースおよびＭＯＳトランジスタ３２４のソースは、電源線Ｖｄｄに共通に接続される。ＭＯＳトランジスタ３２７のソースは、ＭＯＳトランジスタ３２８のソースおよびＭＯＳトランジスタ３２９のドレインに接続される。ＭＯＳトランジスタ３２９のゲートは電源線Ｖｂｉａｓに接続され、ソースは接地される。 The capacitor 321 is connected between the signal line 303 and the gate of the MOS transistor 327. The drain of the MOS transistor 325 is further connected to the gate of the MOS transistor 327. The drain of the MOS transistor 327 is connected to the source of the MOS transistor 325, the drain and gate of the MOS transistor 323, and the gate of the MOS transistor 324. The source of the MOS transistor 323 and the source of the MOS transistor 324 are commonly connected to the power supply line Vdd. The source of the MOS transistor 327 is connected to the source of the MOS transistor 328 and the drain of the MOS transistor 329. The gate of the MOS transistor 329 is connected to the power supply line Vbias, and the source is grounded.
　キャパシタ３２２は、信号線３０２およびＭＯＳトランジスタ３２８のゲートの間に接続される。ＭＯＳトランジスタ３２８のゲートにはＭＯＳトランジスタ３２６のドレインがさらに接続される。ＭＯＳトランジスタ３２８のドレインは、ＭＯＳトランジスタ３２６のソース、ＭＯＳトランジスタ３２４のドレインおよび信号線３０７に接続される。ＭＯＳトランジスタ３２５のゲートおよびＭＯＳトランジスタ３２６のゲートは、初期化信号線ＳＥＴに共通に接続される。 The capacitor 322 is connected between the signal line 302 and the gate of the MOS transistor 328. The drain of the MOS transistor 326 is further connected to the gate of the MOS transistor 328. The drain of the MOS transistor 328 is connected to the source of the MOS transistor 326, the drain of the MOS transistor 324, and the signal line 307. The gate of the MOS transistor 325 and the gate of the MOS transistor 326 are commonly connected to the initialization signal line SET.
　キャパシタ３２１および３２２は、結合キャパシタを構成する。また、キャパシタ３２１および３２２は、それぞれ参照信号およびアナログの画像信号を保持する。ＭＯＳトランジスタ３２７および３２８は、差動対を構成し、キャパシタ３２１および３２２を介して入力された参照信号およびアナログの画像信号の差分を増幅する。ＭＯＳトランジスタ３２９は、ＭＯＳトランジスタ３２７および３２８のソースに共通に接続される定電流回路を構成する。このＭＯＳトランジスタ３２９には、電源線Ｖｂｉａｓのバイアス電圧に応じたソース電流が流れる。ＭＯＳトランジスタ３２３および３２４は、カレントミラー回路を構成し、それぞれＭＯＳトランジスタ３２７および３２８のドレインに接続される負荷を構成する。このカレントミラー回路によりＭＯＳトランジスタ３２７および３２８による差動対の利得を向上させることができる。 Capacitors 321 and 322 constitute a coupling capacitor. In addition, capacitors 321 and 322 hold a reference signal and an analog image signal, respectively. The MOS transistors 327 and 328 form a differential pair and amplify the difference between the reference signal and the analog image signal input via the capacitors 321 and 322. The MOS transistor 329 constitutes a constant current circuit commonly connected to the sources of the MOS transistors 327 and 328. A source current corresponding to the bias voltage of the power supply line Vbias flows through the MOS transistor 329. The MOS transistors 323 and 324 form a current mirror circuit and constitute a load connected to the drains of the MOS transistors 327 and 328, respectively. This current mirror circuit can improve the gain of the differential pair by the MOS transistors 327 and 328.
　高い利得の差動対を有する増幅器を使用して参照信号およびアナログの画像信号の差分を増幅することにより、参照信号およびアナログの画像信号の比較を行うことができる。なお、ＭＯＳトランジスタ３２５および３２６は、比較部３２０を初期化するスイッチである。このＭＯＳトランジスタ３２５および３２６は、初期化信号線ＳＥＴの信号に基づいて初期化を行う。具体的には、初期化信号線ＳＥＴからの制御信号によりＭＯＳトランジスタ３２５および３２６が導通してＭＯＳトランジスタ３２７および３２８のゲートが初期化される。 The reference signal and the analog image signal can be compared by amplifying the difference between the reference signal and the analog image signal using an amplifier having a high gain differential pair. The MOS transistors 325 and 326 are switches that initialize the comparison unit 320. The MOS transistors 325 and 326 are initialized based on the signal of the initialization signal line SET. Specifically, the control signal from the initialization signal line SET causes the MOS transistors 325 and 326 to conduct, and the gates of the MOS transistors 327 and 328 are initialized.
　このゲートの初期化電圧は、キャパシタ３２１および３２２の一端にも印加される。キャパシタ３２１の他の一端には信号線３０３を介して参照信号が入力され、キャパシタ３２２の他の一端には信号線３０２を介して画像信号が入力される。そこで、この初期化の際、信号線３０３を介して参照信号の初期値を入力することにより、キャパシタ３２１にＭＯＳトランジスタ３２７のゲートの初期化電圧と参照信号の初期値との差分の電圧を保持させることができる。同様に、信号線３０２を介して画像信号の初期値を入力することにより、キャパシタ３２２にＭＯＳトランジスタ３２８のゲートの初期化電圧と画像信号の初期値との差分の電圧を保持させることができる。このように、比較部３２０の入力部を初期化することができる。この初期化により、参照信号および画像信号の初期値の変動に基づく画像信号のノイズを削減することができる。画像信号の初期値には、前述のリセット画像信号を使用することができる。なお、ＭＯＳトランジスタ３２５および３２６による回路は、ＭＯＳトランジスタ３２７および３２８による差動対の初期化回路を構成する。 The initialization voltage of this gate is also applied to one end of the capacitors 321 and 322. A reference signal is input to the other end of the capacitor 321 via the signal line 303, and an image signal is input to the other end of the capacitor 322 via the signal line 302. Therefore, at the time of this initialization, by inputting the initial value of the reference signal via the signal line 303, the voltage of the difference between the initialization voltage of the gate of the MOS transistor 327 and the initial value of the reference signal is held in the capacitor 321. Can be made to. Similarly, by inputting the initial value of the image signal via the signal line 302, the capacitor 322 can hold the voltage of the difference between the initialization voltage of the gate of the MOS transistor 328 and the initial value of the image signal. In this way, the input unit of the comparison unit 320 can be initialized. By this initialization, the noise of the image signal based on the fluctuation of the initial value of the reference signal and the image signal can be reduced. The above-mentioned reset image signal can be used as the initial value of the image signal. The circuit by the MOS transistors 325 and 326 constitutes the initialization circuit of the differential pair by the MOS transistors 327 and 328.
　［画像信号の変換］
　図７は、本開示の実施の形態に係る画像信号の変換の一例を示す図である。同図は、画素１００におけるアナログの画像信号の生成からアナログデジタル変換部３２におけるデジタルの画像信号への変換までの動作の一例を表すタイムチャートである。同図において、ＯＦＧ、ＳＥＬ、ＲＳＴ、ＴＲおよびＳＥＴは、それぞれオーバーフローゲート信号線ＯＦＧ、選択信号線ＳＥＬ、リセット信号線ＲＳＴ、転送信号線ＴＲおよび初期化信号線ＳＥＴの２値化された制御信号を表す。また、ＨＬＤは、保持信号線ＨＬＤの２値化された制御信号を表す。また、カウンタ３３０出力は、カウンタ３３０の出力であるデジタルのカウント値をアナログ量に変換して表したものである。また、同図のクリップ回路３１出力において、１点鎖線は画素１００の電荷保持部１０３が飽和した場合の波形を表す。点線は、クリップ回路３１が配置されない場合における画素１００の電荷保持部１０３が飽和した場合の画像信号の波形を表す。 [Conversion of image signal]
FIG. 7 is a diagram showing an example of image signal conversion according to the embodiment of the present disclosure. The figure is a time chart showing an example of an operation from the generation of an analog image signal in the pixel 100 to the conversion into a digital image signal in the analog-to-digital conversion unit 32. In the figure, OFG, SEL, RST, TR and SET are binarized control signals of overflow gate signal line OFG, selection signal line SEL, reset signal line RST, transfer signal line TR and initialization signal line SET, respectively. Represents. Further, HLD represents a binarized control signal of the holding signal line HLD. Further, the counter 330 output is represented by converting the digital count value, which is the output of the counter 330, into an analog quantity. Further, in the clip circuit 31 output in the figure, the alternate long and short dash line represents the waveform when the charge holding portion 103 of the pixel 100 is saturated. The dotted line represents the waveform of the image signal when the charge holding portion 103 of the pixel 100 is saturated when the clip circuit 31 is not arranged.
　なお、以下において、画素１００や比較部３２０のＭＯＳトランジスタを導通状態に遷移させるゲートソース間の閾値電圧Ｖｇｓに相当する信号をオン信号と称する。ｐチャネルＭＯＳトランジスタのゲートに接続されるオーバーフローゲート信号線ＯＦＧ、リセット信号線ＲＳＴ、転送信号線ＴＲおよび初期化信号線ＳＥＴにおいては、値「０」がオン信号の制御信号を表す。ｎチャネルＭＯＳトランジスタのゲートに接続される選択信号線ＳＥＬにおいては、値「１」がオン信号の制御信号を表す。 In the following, a signal corresponding to the threshold voltage Vgs between the gate and source for transitioning the MOS transistor of the pixel 100 and the comparison unit 320 to the conduction state is referred to as an on signal. In the overflow gate signal line OFG, reset signal line RST, transfer signal line TR, and initialization signal line SET connected to the gate of the p-channel MOS transistor, the value "0" represents the control signal of the on signal. In the selection signal line SEL connected to the gate of the n-channel MOS transistor, the value "1" represents the control signal of the on signal.
　まず、通常時（画素１００の電荷保持部１０３が飽和しない状態）の波形について説明する。 First, a waveform in a normal state (a state in which the charge holding portion 103 of the pixel 100 is not saturated) will be described.
　初期状態Ｔ０において、オーバーフローゲート信号線ＯＦＧ、リセット信号線ＲＳＴ、転送信号線ＴＲおよび初期化信号線ＳＥＴには、値「１」に相当する電圧が印加される。また、選択信号線ＳＥＬおよび保持信号線ＨＬＤには、値「０」に相当する電圧が印加される。クリップ電圧として、クリップ回路３１のクリップ動作を停止させる高い電圧が供給される。参照信号として、初期値（初期電圧）が供給される。また、カウンタ３３０の出力は、初期値である値「０」が出力される。 In the initial state T0, a voltage corresponding to the value "1" is applied to the overflow gate signal line OFG, the reset signal line RST, the transfer signal line TR, and the initialization signal line SET. Further, a voltage corresponding to the value "0" is applied to the selection signal line SEL and the holding signal line HLD. As the clip voltage, a high voltage for stopping the clip operation of the clip circuit 31 is supplied. An initial value (initial voltage) is supplied as a reference signal. Further, as the output of the counter 330, the initial value "0" is output.
　Ｔ１において、オーバーフローゲート信号線ＯＦＧが値「０」となって、オン信号が入力される。これにより、ＭＯＳトランジスタ１０４が導通して電荷保持部１０２がリセットされる。 At T1, the overflow gate signal line OFG becomes a value "0" and an on signal is input. As a result, the MOS transistor 104 becomes conductive and the charge holding unit 102 is reset.
　Ｔ２において、オーバーフローゲート信号線ＯＦＧのオン信号の入力が停止され、電荷保持部１０２のリセットが終了する。これにより、画素１００における露光期間が開始される。 At T2, the input of the ON signal of the overflow gate signal line OFG is stopped, and the reset of the charge holding unit 102 is completed. As a result, the exposure period in the pixel 100 is started.
　Ｔ３において、選択信号線ＳＥＬが値「１」となり、オン信号が入力される。これにより、ＭＯＳトランジスタ１０８が導通して電荷保持部１０３の電荷に応じた画像信号が画素１００から出力される。 At T3, the selection signal line SEL becomes a value "1" and an on signal is input. As a result, the MOS transistor 108 conducts and an image signal corresponding to the charge of the charge holding unit 103 is output from the pixel 100.
　Ｔ４において、画像信号の制限電圧に応じたクリップ電圧（同図における５１１）が供給される。しかし、通常時においては画像信号のレベルが低いため、クリップ回路３１はクリップ動作を行わない。画素１００から出力された画像信号はクリップ回路３１を通過して比較部３２０に入力される。 At T4, a clip voltage (511 in the figure) corresponding to the limit voltage of the image signal is supplied. However, since the level of the image signal is low in the normal state, the clip circuit 31 does not perform the clipping operation. The image signal output from the pixel 100 passes through the clip circuit 31 and is input to the comparison unit 320.
　Ｔ５において、リセット信号線ＲＳＴが値「０」となり、オン信号が入力される。これにより、ＭＯＳトランジスタ１０６が導通し、電荷保持部１０３がリセットされる。このリセットに伴って、リセット画像信号が画素１００から出力され、クリップ回路３１の出力もリセットレベルの電圧に低下する。 At T5, the reset signal line RST becomes a value "0" and an on signal is input. As a result, the MOS transistor 106 becomes conductive and the charge holding unit 103 is reset. Along with this reset, the reset image signal is output from the pixel 100, and the output of the clip circuit 31 also drops to the reset level voltage.
　Ｔ６において、リセット信号線ＲＳＴが値「１」となり、電荷保持部１０３のリセットが終了する。また、初期化信号線ＳＥＴが値「０」となる。比較部３２０のＭＯＳトランジスタ３２５および３２６が導通して比較部３２０が初期化される。 At T6, the reset signal line RST becomes the value "1", and the reset of the charge holding unit 103 is completed. Further, the initialization signal line SET becomes a value "0". The MOS transistors 325 and 326 of the comparison unit 320 are electrically connected to initialize the comparison unit 320.
　Ｔ７において、初期化信号線ＳＥＴが値「１」となり、クリップ回路３１に供給されるクリップ電圧が高い電圧に戻る。これにより、比較部３２０の初期化が終了する。 At T7, the initialization signal line SET becomes a value "1", and the clip voltage supplied to the clip circuit 31 returns to a high voltage. As a result, the initialization of the comparison unit 320 is completed.
　Ｔ８において、Ｐ相が開始される。ランプ関数状の参照信号の供給が開始され、カウンタ３３０がダウンカウントを開始する。クリップ回路３１の出力電圧より参照信号の電圧が低いため、比較部３２０の出力は値「０」となる。 At T8, the P phase is started. The supply of the reference signal in the form of a ramp function is started, and the counter 330 starts down counting. Since the voltage of the reference signal is lower than the output voltage of the clip circuit 31, the output of the comparison unit 320 has a value of “0”.
　Ｔ９において、クリップ回路３１の出力電圧および参照信号の電圧が等しくなり、比較部３２０の出力は値「１」に遷移する。この比較部３２０の比較結果に基づいて、カウンタ３３０はダウンカウントを停止する。 At T9, the output voltage of the clip circuit 31 and the voltage of the reference signal become equal, and the output of the comparison unit 320 transitions to the value "1". Based on the comparison result of the comparison unit 320, the counter 330 stops the down count.
　Ｔ１０において、ランプ関数状の参照信号の供給が停止される。これにより、Ｐ相が終了する。 At T10, the supply of the reference signal in the form of a ramp function is stopped. As a result, the P phase ends.
　Ｔ１１において、参照信号が初期値に戻る。このため、比較部３２０の出力が値「０」遷移する。 At T11, the reference signal returns to the initial value. Therefore, the output of the comparison unit 320 transitions to the value "0".
　Ｔ１２において、露光期間が終了し、転送信号線ＴＲが値「０」となってオン信号が入力される。これにより、ＭＯＳトランジスタ１０５が導通し、電荷保持部１０２の電荷が電荷保持部１０３に分配（転送）されて保持される。この電荷の転送に応じて画素１００からの画像信号のレベルが上昇し、クリップ回路３１の出力も上昇する。 At T12, the exposure period ends, the transfer signal line TR becomes a value "0", and an on signal is input. As a result, the MOS transistor 105 becomes conductive, and the charge of the charge holding unit 102 is distributed (transferred) to the charge holding unit 103 and held. The level of the image signal from the pixel 100 rises according to the transfer of the electric charge, and the output of the clip circuit 31 also rises.
　Ｔ１３において、電荷保持部１０３への電荷の転送が終了し、転送信号線ＴＲが値「１」に戻る。また、Ｄ相が開始され、ランプ関数状の参照信号の供給が開始されるとともにカウンタ３３０がアップカウントを開始する。クリップ回路３１の出力電圧より参照信号の電圧が低いため、比較部３２０の出力は値「０」となる。 At T13, the transfer of electric charge to the electric charge holding unit 103 is completed, and the transfer signal line TR returns to the value "1". Further, the D phase is started, the supply of the reference signal in the form of a ramp function is started, and the counter 330 starts up-counting. Since the voltage of the reference signal is lower than the output voltage of the clip circuit 31, the output of the comparison unit 320 has a value of “0”.
　Ｔ１４において、クリップ回路３１の出力電圧および参照信号の電圧が等しくなり、比較部３２０の出力は値「１」に遷移する。この比較部３２０の比較結果に基づいて、カウンタ３３０はアップカウントを停止する。 At T14, the output voltage of the clip circuit 31 and the voltage of the reference signal become equal, and the output of the comparison unit 320 transitions to the value "1". Based on the comparison result of the comparison unit 320, the counter 330 stops up-counting.
　Ｔ１５において、選択信号線ＳＥＬが値「０」になり、画素１００からの画像信号の出力が停止される。また、ランプ関数状の参照信号の供給が停止される。これにより、Ｄ相が終了する。また、保持信号線ＨＬＤが値「１」になり、カウンタ３３０の出力（カウント値）が保持部３４０に保持される。この保持されたカウンタ３３０のカウント値がデジタルの画像信号に該当する。 At T15, the selection signal line SEL becomes a value "0", and the output of the image signal from the pixel 100 is stopped. In addition, the supply of the reference signal in the form of a ramp function is stopped. As a result, the D phase ends. Further, the holding signal line HLD becomes a value "1", and the output (count value) of the counter 330 is held by the holding unit 340. The count value of the held counter 330 corresponds to a digital image signal.
　上述のように、Ｐ相においてリセット画像信号に応じてカウンタ３３０がダウンカウントを行う。次にＤ相において、ダウンカウント後のカウント値から画素１００の光電変換に基づく画像信号に応じてアップカウントを行う。これにより、画素１００の光電変換に基づく画像信号からリセット画像信号が減算され、ＣＤＳが実行される。 As described above, the counter 330 counts down in response to the reset image signal in the P phase. Next, in the D phase, the count value after the down count is up-counted according to the image signal based on the photoelectric conversion of the pixel 100. As a result, the reset image signal is subtracted from the image signal based on the photoelectric conversion of the pixel 100, and the CDS is executed.
　次に、高輝度の被写体の撮像により画素１００の電荷保持部１０３が飽和した場合の動作について説明する。なお、上述の通常時と同じ部分については説明を省略する。 Next, the operation when the charge holding portion 103 of the pixel 100 is saturated by imaging a high-brightness subject will be described. The description of the same parts as those in the normal case described above will be omitted.
　Ｔ３において、画素１００からは、飽和時の画像信号が出力される。このため、クリップ回路３１からも飽和時の画像信号（同図における５１２）が出力され、高い電圧となる。 At T3, the image signal at the time of saturation is output from the pixel 100. Therefore, the image signal at the time of saturation (512 in the figure) is also output from the clip circuit 31, resulting in a high voltage.
　Ｔ４において、クリップ電圧が供給されると、クリップ回路３１はクリップ動作を開始し、クリップされた画像信号（同図における５１３）がクリップ回路３１から出力される。 When the clip voltage is supplied in T4, the clip circuit 31 starts the clip operation, and the clipped image signal (513 in the figure) is output from the clip circuit 31.
　Ｔ５において、電荷保持部１０３のリセットにより、クリップ回路３１の出力はリセットレベルの電圧になる。 At T5, the output of the clip circuit 31 becomes the reset level voltage due to the reset of the charge holding unit 103.
　Ｔ６において、リセットが終了し、クリップされた画像信号（同図における５１３）が再度クリップ回路３１から出力される。同時に比較部３２０の初期化が開始され、キャパシタ３２２にクリップされた画像信号が保持される。 At T6, the reset is completed, and the clipped image signal (513 in the figure) is output from the clip circuit 31 again. At the same time, the initialization of the comparison unit 320 is started, and the image signal clipped to the capacitor 322 is held.
　Ｔ７において、クリップ回路３１に供給されるクリップ電圧が高い電圧に戻る。クリップ回路３１からは飽和時の画像信号が再度出力される。 At T7, the clip voltage supplied to the clip circuit 31 returns to a high voltage. The image signal at the time of saturation is output again from the clip circuit 31.
　その後、Ｐ相（Ｔ８乃至Ｔ１０）において、飽和時の画像信号と参照信号とが比較部３２０により比較される。同図の例においては、参照信号の電圧が飽和時の画像信号に達する前にＰ相が終了するため、Ｐ相における比較部３２０からの値「１」の出力は検出されない。 After that, in the P phase (T8 to T10), the saturated image signal and the reference signal are compared by the comparison unit 320. In the example of the figure, since the P phase ends before the voltage of the reference signal reaches the image signal at the time of saturation, the output of the value "1" from the comparison unit 320 in the P phase is not detected.
　また、Ｄ相（Ｔ１３乃至Ｔ１５）においても、飽和時の画像信号と参照信号とが比較部３２０により比較される。同図の例においては、Ｐ相と同様に、参照信号の電圧が飽和時の画像信号に達する前にＤ相が終了し、比較部３２０からの値「１」の出力は検出されない。 Also, in the D phase (T13 to T15), the saturated image signal and the reference signal are compared by the comparison unit 320. In the example of the figure, similarly to the P phase, the D phase ends before the voltage of the reference signal reaches the image signal at the time of saturation, and the output of the value “1” from the comparison unit 320 is not detected.
　このように、クリップされた画像信号により比較部３２０が初期化され、Ｐ相およびＤ相において飽和レベルの画像信号と参照信号との比較を行うことができる。画素１００の電荷保持部１０３の飽和は、例えば、参照信号が画像信号と同じ電圧になる前にＰ相やＤ相が終了する場合に検出することができる。 In this way, the comparison unit 320 is initialized by the clipped image signal, and the saturation level image signal and the reference signal can be compared in the P phase and the D phase. Saturation of the charge holding unit 103 of the pixel 100 can be detected, for example, when the P phase or the D phase ends before the reference signal has the same voltage as the image signal.
　次に、クリップ回路３１が配置されない場合の動作について説明する。Ｔ６において、同図の点線の波形に表した飽和レベルの画像信号が比較部３２０に入力されて初期化される。キャパシタ３２２には、この飽和レベルの画像信号が保持される。このため、比較部３２０の差動対を構成するＭＯＳトランジスタ３２８のベースは低い電圧のまま変化せず、Ｐ相およびＤ相において同じ電圧の画像信号が参照信号と比較される。ＣＤＳの結果、低い値のデジタルの画像信号が出力され、黒化現象を生じる。このように、クリップ回路３１が配置されない場合、比較部３２０の初期化を行うことができなくなる。 Next, the operation when the clip circuit 31 is not arranged will be described. At T6, the image signal of the saturation level represented by the dotted line waveform in the figure is input to the comparison unit 320 and initialized. The image signal at this saturation level is held in the capacitor 322. Therefore, the base of the MOS transistor 328 forming the differential pair of the comparison unit 320 does not change at a low voltage, and the image signal having the same voltage in the P phase and the D phase is compared with the reference signal. As a result of CDS, a low-value digital image signal is output, causing a blackening phenomenon. In this way, if the clip circuit 31 is not arranged, the comparison unit 320 cannot be initialized.
　以上説明したように、本開示の第１の実施の形態の撮像素子１は、クリップ回路３１を配置して画素１００から出力された画像信号の上昇を制限する。これにより、光電効果により生成された正孔に基づく画像信号を生成する撮像素子１において、アナログデジタル変換部３２の比較部３２０の初期化を行うことができ、画素１００の電荷保持部１０３の飽和を検出することができる。黒化現象の発生を防ぐことができ、画質の低下を防止することができる。 As described above, the image sensor 1 of the first embodiment of the present disclosure arranges the clip circuit 31 to limit the rise of the image signal output from the pixel 100. As a result, in the image sensor 1 that generates an image signal based on the holes generated by the photoelectric effect, the comparison unit 320 of the analog-digital conversion unit 32 can be initialized, and the charge holding unit 103 of the pixel 100 is saturated. Can be detected. It is possible to prevent the occurrence of a blackening phenomenon and prevent deterioration of image quality.
　＜２．第２の実施の形態＞
　上述の第１の実施の形態の撮像素子１は、電荷保持部１０３が飽和した場合であっても、クリップ回路３１を配置することにより比較部３２０の初期化を行っていた。これに対し、本開示の第２の実施の形態の撮像素子１は、比較部３２０の比較結果に基づいて電荷保持部１０３の飽和を検出する点で、上述の第１の実施の形態と異なる。 <2. Second Embodiment>
In the image sensor 1 of the first embodiment described above, the comparison unit 320 is initialized by arranging the clip circuit 31 even when the charge holding unit 103 is saturated. On the other hand, the image sensor 1 of the second embodiment of the present disclosure is different from the above-described first embodiment in that the saturation of the charge holding unit 103 is detected based on the comparison result of the comparison unit 320. ..
　［アナログデジタル変換部の構成］
　図８は、本開示の第２の実施の形態に係るアナログデジタル変換部の構成例を示す図である。同図は、図５と同様に、アナログデジタル変換部３２の構成例を表す図である。飽和検出部をさらに備え、保持部３４０の代わりに保持部３６０を備える点で、図５のアナログデジタル変換部３２と異なる。 [Configuration of analog-to-digital converter]
FIG. 8 is a diagram showing a configuration example of the analog-to-digital conversion unit according to the second embodiment of the present disclosure. Similar to FIG. 5, FIG. 5 is a diagram showing a configuration example of the analog-to-digital conversion unit 32. It differs from the analog-to-digital conversion unit 32 of FIG. 5 in that it further includes a saturation detection unit and includes a holding unit 360 instead of the holding unit 340.
　飽和検出部３５０は、画素１００の電荷保持部１０３の飽和を検出するものである。この飽和検出部３５０には、比較部３２０の出力信号が入力され、比較部３２０の比較結果に基づいて電荷保持部１０３の飽和を検出する。具体的には、飽和検出部３５０は、参照信号が画像信号と等しくなった際に出力される比較部３２０からの値「１」の出力信号がＰ相において検出されない場合に、電荷保持部１０３の飽和を検出することができる。また、飽和検出部３５０は、Ｄ相において比較部３２０からの値「１」の出力信号が検出されない場合に、電荷保持部１０３の飽和を検出することもできる。飽和検出部３５０の電荷保持部１０３の飽和の検出結果は、信号線３０９を介して保持部３６０に出力される。例えば、飽和検出部３５０は、電荷保持部１０３の飽和を検出した際に値「１」の信号を出力することができる。 The saturation detection unit 350 detects the saturation of the charge holding unit 103 of the pixel 100. The output signal of the comparison unit 320 is input to the saturation detection unit 350, and the saturation of the charge holding unit 103 is detected based on the comparison result of the comparison unit 320. Specifically, the saturation detection unit 350 is the charge holding unit 103 when the output signal of the value "1" from the comparison unit 320, which is output when the reference signal becomes equal to the image signal, is not detected in the P phase. Saturation can be detected. Further, the saturation detection unit 350 can also detect the saturation of the charge holding unit 103 when the output signal of the value "1" from the comparison unit 320 is not detected in the D phase. The saturation detection result of the charge holding unit 103 of the saturation detecting unit 350 is output to the holding unit 360 via the signal line 309. For example, the saturation detection unit 350 can output a signal having a value of "1" when the saturation of the charge holding unit 103 is detected.
　保持部３６０は、保持部３４０と同様に、カウンタ３３０のカウント値を保持することによりデジタルの画像信号を保持するものである。また、保持部３６０は、飽和検出部３５０の電荷保持部１０３の飽和の検出結果に基づいてデジタルの画像信号の補正をさらに行う。具体的には、飽和検出部３５０から電荷保持部１０３の飽和を検出した際の値「１」の信号が出力された際に、保持部３６０は、最大の輝度に対応するデジタルの画像信号をアナログデジタル変換の結果として保持して出力することができる。これにより、黒化現象を生じた場合であっても、画像信号の補正を行うことができ、画質の低下を防ぐことができる。なお、保持部３６０は、請求の範囲に記載の補正部の一例である。 Like the holding unit 340, the holding unit 360 holds the digital image signal by holding the count value of the counter 330. Further, the holding unit 360 further corrects the digital image signal based on the saturation detection result of the charge holding unit 103 of the saturation detecting unit 350. Specifically, when a signal having a value of "1" when the saturation of the charge holding unit 103 is detected is output from the saturation detecting unit 350, the holding unit 360 outputs a digital image signal corresponding to the maximum brightness. It can be retained and output as a result of analog-to-digital conversion. As a result, even when the blackening phenomenon occurs, the image signal can be corrected and the deterioration of the image quality can be prevented. The holding unit 360 is an example of the correction unit described in the claims.
　これ以外の撮像素子１の構成は本開示の第１の実施の形態において説明した撮像素子１の構成と同様であるため、説明を省略する。 Since the other configurations of the image sensor 1 are the same as the configurations of the image sensor 1 described in the first embodiment of the present disclosure, the description thereof will be omitted.
　以上説明したように、本開示の第２の実施の形態の撮像素子１は、飽和検出部３５０により電荷保持部１０３の飽和を検出し、この飽和検出部３５０の検出結果に基づいて保持部３６０が画像信号の補正を行う。これにより、黒化現象の発生による画質の低下を防止することができる。 As described above, in the image sensor 1 of the second embodiment of the present disclosure, the saturation detection unit 350 detects the saturation of the charge holding unit 103, and the holding unit 360 is based on the detection result of the saturation detection unit 350. Corrects the image signal. This makes it possible to prevent deterioration of image quality due to the occurrence of the blackening phenomenon.
　＜３．第３の実施の形態＞
　上述の第１の実施の形態の撮像素子１は、クリップ回路３１がカラム信号処理部３０に配置されていた。これに対し、本開示の第３の実施の形態の撮像素子１は、クリップ回路が画素１００に配置される点で、上述の第１の実施の形態と異なる。 <3. Third Embodiment>
In the image sensor 1 of the first embodiment described above, the clip circuit 31 is arranged in the column signal processing unit 30. On the other hand, the image sensor 1 of the third embodiment of the present disclosure is different from the above-described first embodiment in that the clip circuit is arranged in the pixel 100.
　［画素の構成］
　図９は、本開示の第３の実施の形態に係る画素の構成例を示す図である。同図は、図２と同様に、画素１００の構成例を表す回路図である。ＭＯＳトランジスタ１０９をさらに備える点で、図２の画素１００と異なる。また、同図の信号線１１は、クリップ信号線ＣＬＩＰをさらに備える。このクリップ信号線ＣＬＩＰは、クリップ電圧を伝達する信号線である。 [Pixel composition]
FIG. 9 is a diagram showing a configuration example of pixels according to the third embodiment of the present disclosure. Similar to FIG. 2, the figure is a circuit diagram showing a configuration example of the pixel 100. It differs from the pixel 100 in FIG. 2 in that it further includes a MOS transistor 109. Further, the signal line 11 in the figure further includes a clip signal line CLIP. This clip signal line CLIP is a signal line that transmits a clip voltage.
　ＭＯＳトランジスタ１０９には、ｎチャネルＭＯＳトランジスタを使用することができる。ＭＯＳトランジスタ１０９のドレインは、ＭＯＳトランジスタ１０８に接続され、ソースは出力信号線Ｖｏに接続される。ＭＯＳトランジスタ１０９のゲートは、クリップ信号線ＣＬＩＰに接続される。本開示の第３の実施の形態の垂直駆動部２０は、図４において説明した波形のクリップ電圧を生成し、クリップ信号線ＣＬＩＰを介して画素１００に伝達する。同図のＭＯＳトランジスタ１０９は、図３において説明した定電流回路３３とともにソースフォロワ回路に構成され、伝達されたクリップ電圧に基づいてＭＯＳトランジスタ１０８から出力される画像信号の上昇を制限する。これにより、電荷保持部１０３が飽和した場合であっても、リセット画像信号の上昇を制限することができ、比較部３２０の初期化が可能になる。なお、カラム信号処理部３０のクリップ回路３１は省略することができる。なお、ＭＯＳトランジスタ１０９および定電流回路３３による回路は、請求の範囲に記載のクリップ回路の一例である。 An n-channel MOS transistor can be used as the MOS transistor 109. The drain of the MOS transistor 109 is connected to the MOS transistor 108, and the source is connected to the output signal line Vo. The gate of the MOS transistor 109 is connected to the clip signal line CLIP. The vertical drive unit 20 of the third embodiment of the present disclosure generates the clip voltage of the waveform described in FIG. 4 and transmits it to the pixel 100 via the clip signal line CLIP. The MOS transistor 109 in the figure is configured in a source follower circuit together with the constant current circuit 33 described in FIG. 3, and limits the rise of the image signal output from the MOS transistor 108 based on the transmitted clip voltage. As a result, even when the charge holding unit 103 is saturated, the rise of the reset image signal can be limited, and the comparison unit 320 can be initialized. The clip circuit 31 of the column signal processing unit 30 can be omitted. The circuit by the MOS transistor 109 and the constant current circuit 33 is an example of the clip circuit described in the claims.
　これ以外の撮像素子１の構成は本開示の第１の実施の形態において説明した撮像素子１の構成と同様であるため、説明を省略する。 Since the other configurations of the image sensor 1 are the same as the configurations of the image sensor 1 described in the first embodiment of the present disclosure, the description thereof will be omitted.
　以上説明したように、本開示の第３の実施の形態の撮像素子１は、画素１００に配置したＭＯＳトランジスタ１０９により、画像信号の上昇を制限する。これにより、アナログデジタル変換部３２の比較部３２０の初期化を行うことができ、画素１００の電荷保持部１０３の飽和を検出することができる。 As described above, the image sensor 1 of the third embodiment of the present disclosure limits the rise of the image signal by the MOS transistor 109 arranged in the pixel 100. As a result, the comparison unit 320 of the analog-digital conversion unit 32 can be initialized, and the saturation of the charge holding unit 103 of the pixel 100 can be detected.
　＜４．第４の実施の形態＞
　上述の第３の実施の形態の撮像素子１は、画素１００にＭＯＳトランジスタ１０９追加して画像信号の上昇を制限していた。これに対し、本開示の第４の実施の形態の撮像素子１は、クリップ電圧が出力される選択信号線を配置して画像信号の上昇を制限する点で、上述の第３の実施の形態と異なる。 <4. Fourth Embodiment>
In the image sensor 1 of the third embodiment described above, a MOS transistor 109 is added to the pixel 100 to limit the rise of the image signal. On the other hand, the image sensor 1 of the fourth embodiment of the present disclosure has the third embodiment described above in that the selection signal line from which the clip voltage is output is arranged to limit the rise of the image signal. Different from.
　［画素の構成］
　図１０は、本開示の第４の実施の形態に係る画素の構成例を示す図である。同図は、図２と同様に、画素１００の構成例を表す回路図である。選択信号線ＳＥＬの代わりに選択信号線ＳＥＬ／ＣＬＩＰが配置される点で、図２の画素１００と異なる。 [Pixel composition]
FIG. 10 is a diagram showing a configuration example of a pixel according to a fourth embodiment of the present disclosure. Similar to FIG. 2, the figure is a circuit diagram showing a configuration example of the pixel 100. It differs from pixel 100 in FIG. 2 in that the selection signal line SEL / CLIP is arranged instead of the selection signal line SEL.
　選択信号線ＳＥＬ／ＣＬＩＰは、ＭＯＳトランジスタ１０８のゲートに接続される。この選択信号線ＳＥＬ／ＣＬＩＰは、選択信号およびクリップ電圧を供給する信号線である。選択信号線ＳＥＬ／ＣＬＩＰは、当該画素１００が選択される際にオン信号を伝達し、この選択される期間のうち画像信号のクリップを行う期間にクリップ電圧を供給する。具体的には、図７において説明したＴ３乃至Ｔ４の期間およびＴ７乃至Ｔ１５の期間にオン信号が伝達され、Ｔ４乃至Ｔ７の期間にクリップ電圧が供給される。これにより、比較部３２０の初期化の際に画像信号の上昇を制限することができる。本開示の第４の実施の形態の垂直駆動部２０は、オン信号およびクリップ電圧を切り替えて選択信号線ＳＥＬ／ＣＬＩＰに出力する。なお、ＭＯＳトランジスタ１０８および定電流回路３３による回路は、請求の範囲に記載のクリップ回路の一例である。 The selection signal line SEL / CLIP is connected to the gate of the MOS transistor 108. The selection signal line SEL / CLIP is a signal line that supplies the selection signal and the clip voltage. The selection signal line SEL / CLIP transmits an on signal when the pixel 100 is selected, and supplies a clip voltage during the period during which the image signal is clipped during the selected period. Specifically, the on signal is transmitted during the period of T3 to T4 and the period of T7 to T15 described in FIG. 7, and the clip voltage is supplied during the period of T4 to T7. As a result, it is possible to limit the rise of the image signal when the comparison unit 320 is initialized. The vertical drive unit 20 of the fourth embodiment of the present disclosure switches the on signal and the clip voltage and outputs the output to the selection signal line SEL / CLIP. The circuit by the MOS transistor 108 and the constant current circuit 33 is an example of the clip circuit described in the claims.
　これ以外の撮像素子１の構成は本開示の第３の実施の形態において説明した撮像素子１の構成と同様であるため、説明を省略する。 Since the other configurations of the image sensor 1 are the same as the configurations of the image sensor 1 described in the third embodiment of the present disclosure, the description thereof will be omitted.
　以上説明したように、本開示の第４の実施の形態の撮像素子１は、選択信号線ＳＥＬ／ＣＬＩＰを配置してオン信号およびクリップ電圧を画素１００に供給し、ＭＯＳトランジスタ１０８を画像信号の出力対象の画素１００の選択と画像信号の上昇の制限とに使用する。これにより、画素１００の構成を簡略化することができる。 As described above, in the image sensor 1 of the fourth embodiment of the present disclosure, the selection signal line SEL / CLIP is arranged to supply the on signal and the clip voltage to the pixel 100, and the MOS transistor 108 is used as the image signal. It is used for selecting the pixel 100 to be output and limiting the rise of the image signal. Thereby, the configuration of the pixel 100 can be simplified.
　＜５．第５の実施の形態＞
　上述の第３の実施の形態の撮像素子１は、光電効果により生成された正孔に基づく画像信号を生成する撮像素子を使用していた。本開示の第５の実施の形態では、この撮像素子の構成について説明する。 <5. Fifth Embodiment>
The image pickup device 1 of the third embodiment described above uses an image pickup device that generates an image signal based on holes generated by the photoelectric effect. In the fifth embodiment of the present disclosure, the configuration of this image pickup device will be described.
　［画素の構成］
　図１１は、本開示の第５の実施の形態に係る画素の構成例を示す図である。同図は、画素１００の構成例を表す断面図である。同図の画素１００は、オンチップレンズ１７０と、保護膜１６０と、透明電極１５０と、化合物半導体チップ１９２と、シリコンチップ１９１とを備える。 [Pixel composition]
FIG. 11 is a diagram showing a configuration example of a pixel according to a fifth embodiment of the present disclosure. The figure is a cross-sectional view showing a configuration example of the pixel 100. The pixel 100 in the figure includes an on-chip lens 170, a protective film 160, a transparent electrode 150, a compound semiconductor chip 192, and a silicon chip 191.
　化合物半導体チップ１９２は、化合物半導体の基板を備える半導体チップである。この化合物半導体チップ１９２は、入射光の光電変換を行い、光電変換により生成された電荷のうちの正孔を後述するシリコンチップ１９１に伝達する。化合物半導体チップ１９２は、化合物半導体基板１３０と、第１の化合物半導体層１３１と、第２の化合物半導体層１３２と、分離領域１３３と、保護層１３４と、電極１３５と、絶縁層１４１と、バンプ電極１４２とを備える。 The compound semiconductor chip 192 is a semiconductor chip including a substrate of a compound semiconductor. This compound semiconductor chip 192 performs photoelectric conversion of incident light, and transmits holes in the charges generated by the photoelectric conversion to the silicon chip 191 described later. The compound semiconductor chip 192 includes a compound semiconductor substrate 130, a first compound semiconductor layer 131, a second compound semiconductor layer 132, a separation region 133, a protective layer 134, an electrode 135, an insulating layer 141, and a bump. It is provided with an electrode 142.
　化合物半導体基板１３０は、化合物半導体により構成される基板である。この化合物半導体基板１３０は、例えば、リン化インジウム（ＩｎＰ）により構成することができる。また、化合物半導体基板１３０は、比較的高い不純物濃度のｎ型に構成することができる。 The compound semiconductor substrate 130 is a substrate made of a compound semiconductor. The compound semiconductor substrate 130 can be made of, for example, indium phosphide (InP). Further, the compound semiconductor substrate 130 can be configured as an n-type having a relatively high impurity concentration.
　第１の化合物半導体層１３１は、化合物半導体基板１３０に形成される化合物半導体層である。この第１の化合物半導体層１３１は、例えば、ヒ化インジウムガリウム（ＩｎＧａＡｓ）により構成することができる。また、第１の化合物半導体層１３１は、ｎ型に構成することができる。第１の化合物半導体層１３１において入射光の光電変換が行われる。光電変換により生成された電荷のうち、電子はｎ型の化合物半導体基板１３０に拡散し、正孔は後述するｐ型の第２の化合物半導体層１３２に拡散する。なお、第１の化合物半導体層１３１は、複数の画素１００に対して共通に配置される。 The first compound semiconductor layer 131 is a compound semiconductor layer formed on the compound semiconductor substrate 130. The first compound semiconductor layer 131 can be made of, for example, indium gallium arsenide (InGaAs). Further, the first compound semiconductor layer 131 can be formed in an n-type. Photoelectric conversion of incident light is performed in the first compound semiconductor layer 131. Of the charges generated by photoelectric conversion, electrons are diffused to the n-type compound semiconductor substrate 130, and holes are diffused to the p-type second compound semiconductor layer 132, which will be described later. The first compound semiconductor layer 131 is commonly arranged for the plurality of pixels 100.
　第２の化合物半導体層１３２は、画素１００毎に配置され、第１の化合物半導体層１３１に接合される半導体層である。この第２の化合物半導体層１３２は、例えば、ＩｎＰにより構成することができる。また、第２の化合物半導体層１３２は、比較的高い不純物濃度のｐ型に構成することができる。第１の化合物半導体層１３１および第２の化合物半導体層１３２によるｐｎ接合によるフォトダイオードが図２において説明した光電変換部１０１に該当する。 The second compound semiconductor layer 132 is a semiconductor layer arranged for each pixel 100 and bonded to the first compound semiconductor layer 131. The second compound semiconductor layer 132 can be configured by, for example, InP. Further, the second compound semiconductor layer 132 can be formed in a p-type having a relatively high impurity concentration. The photodiode formed by the pn junction of the first compound semiconductor layer 131 and the second compound semiconductor layer 132 corresponds to the photoelectric conversion unit 101 described in FIG.
　分離領域１３３は、画素１００を分離するものである。この分離領域１３３は、画素１００の境界に配置され、隣接する第２の化合物半導体層１３２同士を分離する。分離領域１３３は、ｎ型のＩｎＰにより構成することができる。 The separation region 133 separates the pixel 100. The separation region 133 is arranged at the boundary of the pixel 100 and separates the adjacent second compound semiconductor layers 132 from each other. The separation region 133 can be configured by an n-type InP.
　保護層１３４は、化合物半導体層の表面を保護するものである。この保護層１３４は、無機材料、例えば、窒化シリコン（ＳｉＮ）、酸化アルミニウム（Ａｌ２Ｏ３）、酸化シリコン（ＳｉＯ２）および酸化ハフニウム（ＨｆＯ２）により構成することができる。 The protective layer 134 protects the surface of the compound semiconductor layer. The protective layer 134 can be made of an inorganic material such as silicon nitride (SiN), aluminum oxide (Al 2 O 3 ), silicon oxide (SiO 2 ) and hafnium oxide (HfO 2 ).
　電極１３５は、第２の化合物半導体層１３２に隣接して配置される電極である。この電極１３５は、例えば、チタン（Ｔｉ）やタングステン（Ｗ）により構成することができる。 The electrode 135 is an electrode arranged adjacent to the second compound semiconductor layer 132. The electrode 135 can be made of, for example, titanium (Ti) or tungsten (W).
　絶縁層１４１は、化合物半導体チップ１９２の表面を絶縁するとともに保護するものである。この絶縁層１４１は、例えば、ＳｉＯ２により構成することができる。 The insulating layer 141 insulates and protects the surface of the compound semiconductor chip 192. The insulating layer 141 can be made of, for example, SiO 2 .
　バンプ電極１４２は、絶縁層１４１の表面に配置されるバンプである。このバンプ電極１４２は、絶縁層１４１を貫通して配置され、電極１３５に接続される。また、バンプ電極１４２は、後述するシリコンチップ１９１のバンプ電極１２６に接合されて光電変換により生成された正孔を伝達する。バンプ電極１４２は、例えば、銅（Ｃｕ）により構成することができる。 The bump electrode 142 is a bump arranged on the surface of the insulating layer 141. The bump electrode 142 is arranged so as to penetrate the insulating layer 141 and is connected to the electrode 135. Further, the bump electrode 142 is bonded to the bump electrode 126 of the silicon chip 191 described later and transmits holes generated by photoelectric conversion. The bump electrode 142 can be made of, for example, copper (Cu).
　シリコンチップ１９１は、シリコン（Ｓｉ）により構成される基板を備える半導体チップである。このシリコンチップ１９１は、化合物半導体チップ１９２により生成された正孔に基づいて画像信号を生成する。図２において説明したＭＯＳトランジスタおよび電荷保持部は、シリコンチップ１９１に配置される。また、図１において説明した垂直駆動部２０等をシリコンチップ１９１に配置することもできる。シリコンチップ１９１は、半導体基板１１０と、配線領域１２０とを備える。 Silicon chip 191 is a semiconductor chip including a substrate made of silicon (Si). The silicon chip 191 generates an image signal based on the holes generated by the compound semiconductor chip 192. The MOS transistor and the charge holding unit described in FIG. 2 are arranged on the silicon chip 191. Further, the vertical drive unit 20 and the like described in FIG. 1 can be arranged on the silicon chip 191. The silicon chip 191 includes a semiconductor substrate 110 and a wiring region 120.
　半導体基板１１０は、Ｓｉにより構成される半導体の基板である。この半導体基板１１０に形成されたウェル領域に画素１００の素子等の拡散領域が配置される。同図には、ｎ型に構成されたウェル領域１１１を記載した。このｎ型のウェル領域１１１には、図２において説明したｐチャネルＭＯＳトランジスタを配置することができる。具体的には、ｎ型のウェル領域１１１にｐ型の半導体領域を配置することにより、ｐチャネルＭＯＳトランジスタを配置することができる。 The semiconductor substrate 110 is a semiconductor substrate composed of Si. A diffusion region such as an element of the pixel 100 is arranged in the well region formed on the semiconductor substrate 110. In the figure, a well region 111 configured in an n-shape is shown. The p-channel MOS transistor described in FIG. 2 can be arranged in the n-type well region 111. Specifically, the p-channel MOS transistor can be arranged by arranging the p-type semiconductor region in the n-type well region 111.
　同図には、ＭＯＳトランジスタ１０４および１０５を記載した。同図のｐ型の半導体領域１１２および１１３はＭＯＳトランジスタ１０４のソース領域およびドレイン領域を構成し、ｐ型の半導体領域１１２および１１３の間のｎ型のウェル領域１１１に近接してゲート電極１１９が配置される。ｐ型の半導体領域１１２および１１３の間のｎ型のウェル領域１１１にチャネルが形成される。また、ｐ型の半導体領域１１２および１１４はＭＯＳトランジスタ１０５のソース領域およびドレイン領域を構成し、ｐ型の半導体領域１１２および１１３の間のｎ型のウェル領域１１１に近接してゲート電極１１８が配置される。また、ｐ型の半導体領域１１２は、化合物半導体チップ１９２により伝達される正孔が蓄積され、図２において説明した電荷保持部１０２を構成する。なお、図２のｎチャネルＭＯＳトランジスタ１０７および１０８ならびに電荷保持部１０３は、不図示のｐ型のウェル領域に形成することができる。 In the figure, MOS transistors 104 and 105 are shown. The p- type semiconductor regions 112 and 113 in the figure constitute a source region and a drain region of the MOS transistor 104, and the gate electrode 119 is located close to the n-type well region 111 between the p- type semiconductor regions 112 and 113. Be placed. A channel is formed in the n-type well region 111 between the p- type semiconductor regions 112 and 113. Further, the p- type semiconductor regions 112 and 114 constitute a source region and a drain region of the MOS transistor 105, and the gate electrode 118 is arranged in the vicinity of the n-type well region 111 between the p- type semiconductor regions 112 and 113. Will be done. Further, in the p-type semiconductor region 112, holes transmitted by the compound semiconductor chip 192 are accumulated, and form the charge holding portion 102 described with reference to FIG. The n- channel MOS transistors 107 and 108 and the charge holding portion 103 of FIG. 2 can be formed in a p-type well region (not shown).
　配線領域１２０は、半導体基板１１０の表面側に形成される配線領域であり、上述のＭＯＳトランジスタ等の配線が形成される領域である。この配線領域１２０は、絶縁層１２１と、配線層１２２と、コンタクトプラグ１２３と、ビアプラグ１２４と、パッド１２５と、バンプ電極１２６とを備える。 The wiring region 120 is a wiring region formed on the surface side of the semiconductor substrate 110, and is a region in which wiring such as the above-mentioned MOS transistor is formed. The wiring region 120 includes an insulating layer 121, a wiring layer 122, a contact plug 123, a via plug 124, a pad 125, and a bump electrode 126.
　配線層１２２は、ＭＯＳトランジスタ等に信号を伝達するものである。この配線層１２２は、Ｃｕ等の金属により構成することができる。絶縁層１２１は、配線層１２２を絶縁するものである。この絶縁層１２１は、例えば、ＳｉＯ２等の絶縁物により構成することができる。これら配線層１２２および絶縁層１２１は、多層に構成することができる。なお、ゲート電極１１８および１１９と半導体基板１１０との間の絶縁層１２１は、ゲート絶縁膜に該当する。パッド１２５は、配線領域１２０の表面近傍に配置される電極である。このパッド１２５は、例えば、Ｗ等により構成することができる。コンタクトプラグ１２３は、半導体基板１１０の半導体領域と配線層１２２とを接続するものである。このコンタクトプラグ１２３は、例えば、Ｗ等により構成することができる。ビアプラグ１２４は、配線層１２２同士や配線層１２２とパッド１２５とを接続するものである。このビアプラグ１２４は、例えば、Ｃｕ等により構成することができる。 The wiring layer 122 transmits a signal to a MOS transistor or the like. The wiring layer 122 can be made of a metal such as Cu. The insulating layer 121 insulates the wiring layer 122. The insulating layer 121 can be made of, for example, an insulating material such as SiO 2. The wiring layer 122 and the insulating layer 121 can be configured in multiple layers. The insulating layer 121 between the gate electrodes 118 and 119 and the semiconductor substrate 110 corresponds to a gate insulating film. The pad 125 is an electrode arranged near the surface of the wiring region 120. The pad 125 can be configured by, for example, W or the like. The contact plug 123 connects the semiconductor region of the semiconductor substrate 110 and the wiring layer 122. The contact plug 123 can be configured by, for example, W or the like. The via plug 124 connects the wiring layers 122 to each other or the wiring layer 122 to the pad 125. The via plug 124 can be made of, for example, Cu or the like.
　バンプ電極１２６は、絶縁層１２１の表面に配置されるバンプである。このバンプ電極１２６は、絶縁層１２１を貫通して配置され、パッド１２５に接続される。前述のように、バンプ電極１２６は、化合物半導体チップ１９２のバンプ電極１４２に接合される。同図の画素１００を備える撮像素子１は、それぞれ個別に製造された化合物半導体チップ１９２およびシリコンチップ１９１を貼り合わされて構成される。この貼り合わせの際、バンプ電極１２６および１４２が接合され、それぞれのチップの間の信号の伝達を行う。バンプ電極１２６は、バンプ電極１４２と同様に、Ｃｕにより構成することができる。 The bump electrode 126 is a bump arranged on the surface of the insulating layer 121. The bump electrode 126 is arranged so as to penetrate the insulating layer 121 and is connected to the pad 125. As described above, the bump electrode 126 is bonded to the bump electrode 142 of the compound semiconductor chip 192. The image pickup device 1 provided with the pixel 100 in the figure is configured by laminating individually manufactured compound semiconductor chips 192 and silicon chips 191 respectively. At the time of this bonding, the bump electrodes 126 and 142 are joined to transmit signals between the respective chips. The bump electrode 126 can be made of Cu in the same manner as the bump electrode 142.
　透明電極１５０は、化合物半導体チップ１９２の裏面に配置される透明な電極である。この透明電極１５０は、図２において説明した電源線Ｖｔｏｐが接続され、化合物半導体基板１３０にバイアス電圧を供給する。透明電極１５０には、例えば、ＩＴＯ（Indium Tin Oxide）を使用することができる。 The transparent electrode 150 is a transparent electrode arranged on the back surface of the compound semiconductor chip 192. The power supply line Vtop described with reference to FIG. 2 is connected to the transparent electrode 150 to supply a bias voltage to the compound semiconductor substrate 130. For the transparent electrode 150, for example, ITO (Indium Tin Oxide) can be used.
　保護膜１６０は、化合物半導体チップ１９２の裏面および透明電極１５０を保護する膜である。 The protective film 160 is a film that protects the back surface of the compound semiconductor chip 192 and the transparent electrode 150.
　オンチップレンズ１７０は、光電変換部に入射光を集光するレンズである。このオンチップレンズ１７０は、第１の化合物半導体層１３１に入射光を集光する。オンチップレンズ１７０は、窒化シリコン（ＳｉＮ）等の無機材料やアクリル樹脂等の有機材料により構成することができる。 The on-chip lens 170 is a lens that collects incident light on the photoelectric conversion unit. The on-chip lens 170 collects incident light on the first compound semiconductor layer 131. The on-chip lens 170 can be made of an inorganic material such as silicon nitride (SiN) or an organic material such as an acrylic resin.
　化合物半導体チップ１９２の第１の化合物半導体層１３１の光電変換により生成された正孔は、第２の化合物半導体層１３２、電極１３５およびバンプ電極１４２を介してシリコンチップ１９１に伝達される。この伝達された正孔は、バンプ電極１２６、パッド１２５、ビアプラグ１２４、配線層１２２およびコンタクトプラグ１２３を介して半導体領域１１２に伝達される。この半導体領域１１２に伝達された正孔に基づいて画像信号が生成される。 The holes generated by the photoelectric conversion of the first compound semiconductor layer 131 of the compound semiconductor chip 192 are transmitted to the silicon chip 191 via the second compound semiconductor layer 132, the electrode 135, and the bump electrode 142. The transmitted holes are transmitted to the semiconductor region 112 via the bump electrode 126, the pad 125, the via plug 124, the wiring layer 122, and the contact plug 123. An image signal is generated based on the holes transmitted to the semiconductor region 112.
　以上説明した化合物半導体による光電変換部を備える画素１００を本開示の撮像素子に適用することができる。なお、本開示の撮像素子の構成は、この例に限定されない。例えば、Ｓｉにより構成される半導体基板のｎ型のウェル領域に形成されたｐ型の半導体領域に光電変換により生成された正孔を蓄積する形式のフォトダイオードを備える画素１００を本開示の撮像素子に適用することもできる。 The pixel 100 provided with the photoelectric conversion unit using the compound semiconductor described above can be applied to the image pickup device of the present disclosure. The configuration of the image sensor of the present disclosure is not limited to this example. For example, the image pickup device of the present disclosure comprises a pixel 100 provided with a photodiode of a type that stores holes generated by photoelectric conversion in a p-type semiconductor region formed in an n-type well region of a semiconductor substrate composed of Si. It can also be applied to.
　なお、第２の実施の形態の飽和検出部３５０および保持部３６０は、第３および第４の実施の形態に組み合わせてもよい。 The saturation detection unit 350 and the holding unit 360 of the second embodiment may be combined with the third and fourth embodiments.
　＜５．カメラへの応用例＞
　本開示に係る技術（本技術）は、様々な製品に応用することができる。例えば、本技術は、カメラ等の撮像装置に搭載される撮像素子として実現されてもよい。 <5. Application example to camera>
The technology according to the present disclosure (the present technology) can be applied to various products. For example, the present technology may be realized as an image pickup device mounted on an image pickup device such as a camera.
　図１２は、本技術が適用され得る撮像装置の一例であるカメラの概略的な構成例を示すブロック図である。同図のカメラ１０００は、レンズ１００１と、撮像素子１００２と、撮像制御部１００３と、レンズ駆動部１００４と、画像処理部１００５と、操作入力部１００６と、フレームメモリ１００７と、表示部１００８と、記録部１００９とを備える。 FIG. 12 is a block diagram showing a schematic configuration example of a camera which is an example of an imaging device to which the present technology can be applied. The camera 1000 in the figure includes a lens 1001, an image pickup element 1002, an image pickup control unit 1003, a lens drive unit 1004, an image processing unit 1005, an operation input unit 1006, a frame memory 1007, a display unit 1008, and the like. A recording unit 1009 is provided.
　レンズ１００１は、カメラ１０００の撮影レンズである。このレンズ１００１は、被写体からの光を集光し、後述する撮像素子１００２に入射させて被写体を結像させる。 The lens 1001 is a photographing lens of the camera 1000. The lens 1001 collects light from the subject and causes the light to be incident on the image pickup device 1002 described later to form an image of the subject.
　撮像素子１００２は、レンズ１００１により集光された被写体からの光を撮像する半導体素子である。この撮像素子１００２は、照射された光に応じたアナログの画像信号を生成し、デジタルの画像信号に変換して出力する。 The image sensor 1002 is a semiconductor element that captures light from a subject focused by the lens 1001. The image sensor 1002 generates an analog image signal according to the irradiated light, converts it into a digital image signal, and outputs the signal.
　撮像制御部１００３は、撮像素子１００２における撮像を制御するものである。この撮像制御部１００３は、制御信号を生成して撮像素子１００２に対して出力することにより、撮像素子１００２の制御を行う。また、撮像制御部１００３は、撮像素子１００２から出力された画像信号に基づいてカメラ１０００におけるオートフォーカスを行うことができる。ここでオートフォーカスとは、レンズ１００１の焦点位置を検出して、自動的に調整するシステムである。このオートフォーカスとして、撮像素子１００２に配置された位相差画素により像面位相差を検出して焦点位置を検出する方式（像面位相差オートフォーカス）を使用することができる。また、画像のコントラストが最も高くなる位置を焦点位置として検出する方式（コントラストオートフォーカス）を適用することもできる。撮像制御部１００３は、検出した焦点位置に基づいてレンズ駆動部１００４を介してレンズ１００１の位置を調整し、オートフォーカスを行う。なお、撮像制御部１００３は、例えば、ファームウェアを搭載したＤＳＰ（Digital Signal Processor）により構成することができる。 The image pickup control unit 1003 controls the image pickup in the image pickup device 1002. The image pickup control unit 1003 controls the image pickup device 1002 by generating a control signal and outputting the control signal to the image pickup device 1002. Further, the image pickup control unit 1003 can perform autofocus on the camera 1000 based on the image signal output from the image pickup device 1002. Here, the autofocus is a system that detects the focal position of the lens 1001 and automatically adjusts it. As this autofocus, a method (image plane phase difference autofocus) in which the image plane phase difference is detected by the phase difference pixels arranged in the image sensor 1002 to detect the focal position can be used. It is also possible to apply a method (contrast autofocus) of detecting the position where the contrast of the image is highest as the focal position. The image pickup control unit 1003 adjusts the position of the lens 1001 via the lens drive unit 1004 based on the detected focal position, and performs autofocus. The image pickup control unit 1003 can be configured by, for example, a DSP (Digital Signal Processor) equipped with firmware.
　レンズ駆動部１００４は、撮像制御部１００３の制御に基づいて、レンズ１００１を駆動するものである。このレンズ駆動部１００４は、内蔵するモータを使用してレンズ１００１の位置を変更することによりレンズ１００１を駆動することができる。 The lens driving unit 1004 drives the lens 1001 based on the control of the imaging control unit 1003. The lens driving unit 1004 can drive the lens 1001 by changing the position of the lens 1001 using a built-in motor.
　画像処理部１００５は、撮像素子１００２により生成された画像信号を処理するものである。この処理には、例えば、画素毎の赤色、緑色および青色に対応する画像信号のうち不足する色の画像信号を生成するデモザイク、画像信号のノイズを除去するノイズリダクションおよび画像信号の符号化等が該当する。画像処理部１００５は、例えば、ファームウェアを搭載したマイコンにより構成することができる。 The image processing unit 1005 processes the image signal generated by the image sensor 1002. This processing includes, for example, demosaic to generate an image signal of a color that is insufficient among the image signals corresponding to red, green, and blue for each pixel, noise reduction to remove noise of the image signal, and coding of the image signal. Applicable. The image processing unit 1005 can be configured by, for example, a microcomputer equipped with firmware.
　操作入力部１００６は、カメラ１０００の使用者からの操作入力を受け付けるものである。この操作入力部１００６には、例えば、押しボタンやタッチパネルを使用することができる。操作入力部１００６により受け付けられた操作入力は、撮像制御部１００３や画像処理部１００５に伝達される。その後、操作入力に応じた処理、例えば、被写体の撮像等の処理が起動される。 The operation input unit 1006 receives the operation input from the user of the camera 1000. For example, a push button or a touch panel can be used for the operation input unit 1006. The operation input received by the operation input unit 1006 is transmitted to the image pickup control unit 1003 and the image processing unit 1005. After that, processing according to the operation input, for example, processing such as imaging of the subject is activated.
　フレームメモリ１００７は、１画面分の画像信号であるフレームを記憶するメモリである。このフレームメモリ１００７は、画像処理部１００５により制御され、画像処理の過程におけるフレームの保持を行う。 The frame memory 1007 is a memory that stores a frame that is an image signal for one screen. The frame memory 1007 is controlled by the image processing unit 1005 and holds frames in the process of image processing.
　表示部１００８は、画像処理部１００５により処理された画像を表示するものである。この表示部１００８には、例えば、液晶パネルを使用することができる。 The display unit 1008 displays the image processed by the image processing unit 1005. For this display unit 1008, for example, a liquid crystal panel can be used.
　記録部１００９は、画像処理部１００５により処理された画像を記録するものである。この記録部１００９には、例えば、メモリカードやハードディスクを使用することができる。 The recording unit 1009 records the image processed by the image processing unit 1005. For example, a memory card or a hard disk can be used for the recording unit 1009.
　以上、本開示が適用され得るカメラについて説明した。本技術は以上において説明した構成のうち、撮像素子１００２に適用され得る。具体的には、図１において説明した撮像素子１は、撮像素子１００２に適用することができる。撮像素子１００２に撮像素子１を適用することにより赤外光の撮像を行うとともに、画像信号の飽和を検出することができる。画質の低下を防ぐことが可能になる。なお、画像処理部１００５は、請求の範囲に記載の処理回路の一例である。カメラ１０００は、請求の範囲に記載の撮像装置の一例である。 The cameras to which this disclosure can be applied have been described above. The present technology can be applied to the image pickup device 1002 among the configurations described above. Specifically, the image pickup device 1 described with reference to FIG. 1 can be applied to the image pickup device 1002. By applying the image sensor 1 to the image sensor 1002, infrared light can be imaged and saturation of the image signal can be detected. It is possible to prevent deterioration of image quality. The image processing unit 1005 is an example of the processing circuit described in the claims. The camera 1000 is an example of the image pickup apparatus described in the claims.
　最後に、上述した各実施の形態の説明は本開示の一例であり、本開示は上述の実施の形態に限定されることはない。このため、上述した各実施の形態以外であっても、本開示に係る技術的思想を逸脱しない範囲であれば、設計等に応じて種々の変更が可能であることは勿論である。 Finally, the description of each embodiment described above is an example of the present disclosure, and the present disclosure is not limited to the above-described embodiment. Therefore, it goes without saying that various changes can be made according to the design and the like as long as the technical concept of the present disclosure is not deviated from the above-described embodiments.
　また、本明細書に記載された効果はあくまで例示であって限定されるものでは無い。また、他の効果があってもよい。 In addition, the effects described in this specification are merely examples and are not limited. It may also have other effects.
　また、上述の実施の形態における図面は、模式的なものであり、各部の寸法の比率等は現実のものとは必ずしも一致しない。また、図面相互間においても互いの寸法の関係や比率が異なる部分が含まれることは勿論である。 Further, the drawings in the above-described embodiment are schematic, and the dimensional ratios of each part do not always match the actual ones. In addition, it goes without saying that parts of the drawings having different dimensional relationships and ratios are included.
　なお、本技術は以下のような構成もとることができる。
（１）入射光の光電変換を行う光電変換部および前記光電変換により生成された電荷のうち正孔を保持する電荷保持部を備え、前記保持された正孔に基づいて画像信号を生成する画素と、
　前記生成された画像信号の上昇を所定のクリップ電圧に制限するクリップを行うクリップ回路と
を具備する撮像素子。
（２）前記クリップ回路は、制御端子に供給された前記所定のクリップ電圧に基づいて前記画像信号の上昇を制限することにより前記クリップを行うフォロワ回路により構成される前記（１）に記載の撮像素子。
（３）前記クリップ回路は、ゲートに前記所定のクリップ電圧が供給され、前記生成された画像信号がドレインに供給され、ソースに負荷が接続されるトランジスタによる前記フォロワ回路により構成される前記（２）に記載の撮像素子。
（４）前記生成された画像信号をデジタルの画像信号に変換する際の基準となる参照信号と前記生成された画像信号との比較を行って当該比較の結果を出力する比較部と、前記比較部における前記比較の開始から前記比較の結果の出力までの計時を行う計時部とを備え、前記計時の結果に基づいて前記画像信号をデジタルの画像信号に変換するアナログデジタル変換部をさらに具備する前記（１）から（３）の何れかに記載の撮像素子。
（５）前記画素は、前記電荷保持部に保持された正孔を排出してリセットを行うリセット部をさらに備えて当該リセット後の画像信号であるリセット画像信号を生成し、
　前記アナログデジタル変換部は、前記生成された画像信号とリセット画像信号との差分に基づいて前記デジタルの画像信号を生成する
前記（４）に記載の撮像素子。
（６）前記クリップ回路は、前記リセット画像信号の生成の際に前記クリップを行う前記（５）に記載の撮像素子。
（７）前記比較部は、前記生成された画像信号および前記参照信号がそれぞれ結合キャパシタを介して入力される差動対と、前記差動対を初期化する初期化回路とを備え、
　前記クリップ回路は、前記初期化回路による初期化の際に前記クリップを行う
前記（５）または（６）に記載の撮像素子。
（８）前記初期化回路は、前記生成された画像信号の初期値および前記参照信号の初期値を前記それぞれの結合キャパシタに保持させることにより初期化する前記（７）に記載の撮像素子。
（９）前記画像信号の飽和を検出する飽和検出部をさらに具備する前記（４）から（８）の何れかに記載の撮像素子。
（１０）前記飽和検出部は、前記比較部における比較の結果に基づいて前記飽和を検出する前記（９）に記載の撮像素子。
（１１）前記飽和検出部の検出結果に基づいて前記デジタルの画像信号の補正を行う補正部をさらに具備する前記（９）または（１０）に記載の撮像素子。
（１２）入射光の光電変換を行う光電変換部および前記光電変換により生成された電荷のうち正孔を保持する電荷保持部を備え、前記保持された正孔に基づいて画像信号を生成する画素と、
　前記生成された画像信号の上昇を所定のクリップ電圧に制限するクリップを行うクリップ回路と、
　前記生成された画像信号の処理を行う処理回路と
を具備する撮像装置。 The present technology can have the following configurations.
(1) A pixel having a photoelectric conversion unit that performs photoelectric conversion of incident light and a charge holding unit that retains holes among the charges generated by the photoelectric conversion, and generates an image signal based on the retained holes. When,
An image pickup device including a clip circuit that performs clipping that limits the rise of the generated image signal to a predetermined clip voltage.
(2) The image pickup according to (1) above, wherein the clip circuit is composed of a follower circuit that performs the clip by limiting the rise of the image signal based on the predetermined clip voltage supplied to the control terminal. element.
(3) The clip circuit is composed of the follower circuit by a transistor in which the predetermined clip voltage is supplied to the gate, the generated image signal is supplied to the drain, and the load is connected to the source. ).
(4) A comparison unit that compares the generated image signal with a reference signal that serves as a reference when converting the generated image signal into a digital image signal and outputs the result of the comparison, and the comparison. The unit includes a time measuring unit for measuring the time from the start of the comparison to the output of the comparison result, and further includes an analog-digital conversion unit that converts the image signal into a digital image signal based on the measurement result. The image pickup device according to any one of (1) to (3).
(5) The pixel further includes a reset unit that discharges holes held in the charge holding unit to perform reset, and generates a reset image signal that is an image signal after the reset.
The image pickup device according to (4), wherein the analog-to-digital conversion unit generates the digital image signal based on the difference between the generated image signal and the reset image signal.
(6) The image pickup device according to (5), wherein the clip circuit performs the clip when the reset image signal is generated.
(7) The comparison unit includes a differential pair in which the generated image signal and the reference signal are input via a coupling capacitor, and an initialization circuit for initializing the differential pair.
The image pickup device according to (5) or (6), wherein the clip circuit performs the clip at the time of initialization by the initialization circuit.
(8) The image pickup device according to (7), wherein the initialization circuit initializes by holding the initial value of the generated image signal and the initial value of the reference signal in the respective coupling capacitors.
(9) The image pickup device according to any one of (4) to (8), further comprising a saturation detection unit for detecting saturation of the image signal.
(10) The image pickup device according to (9), wherein the saturation detection unit detects the saturation based on the result of comparison in the comparison unit.
(11) The image pickup device according to (9) or (10), further comprising a correction unit that corrects the digital image signal based on the detection result of the saturation detection unit.
(12) A pixel that includes a photoelectric conversion unit that performs photoelectric conversion of incident light and a charge holding unit that retains holes among the charges generated by the photoelectric conversion, and generates an image signal based on the retained holes. When,
A clip circuit that performs clipping that limits the rise of the generated image signal to a predetermined clip voltage, and
An imaging device including a processing circuit that processes the generated image signal.
　１　撮像素子
　１０　画素アレイ部
　３０　カラム信号処理部
　３１　クリップ回路
　３２　アナログデジタル変換部
　３３　定電流回路
　３５　参照信号生成部
　１００　画素
　１０１　光電変換部
　１０２、１０３　電荷保持部
　１０４～１０９、３１１、３２３～３２９　ＭＯＳトランジスタ
　３２０　比較部
　３２１、３２２　キャパシタ
　３３０　カウンタ
　３４０、３６０　保持部
　３５０　飽和検出部
　１００２　撮像素子
　１００５　画像処理部 1 Image sensor 10 Pixel array unit 30 Column signal processing unit 31 Clip circuit 32 Analog digital conversion unit 33 Constant current circuit 35 Reference signal generation unit 100 pixels 101 Photoelectric conversion unit 102, 103 Charge holding unit 104 to 109, 311, 323 to 329 MOS transistor 320 Comparison unit 321, 322 Capacitor 330 Counter 340, 360 Holding unit 350 Saturation detection unit 1002 Image sensor 1005 Image processing unit

Claims (12)

  1. 　入射光の光電変換を行う光電変換部および前記光電変換により生成された電荷のうち正孔を保持する電荷保持部を備え、前記保持された正孔に基づいて画像信号を生成する画素と、
    　前記生成された画像信号の上昇を所定のクリップ電圧に制限するクリップを行うクリップ回路と
    を具備する撮像素子。     A pixel that includes a photoelectric conversion unit that performs photoelectric conversion of incident light and a charge holding unit that retains holes among the charges generated by the photoelectric conversion, and generates an image signal based on the retained holes.
    An image pickup device including a clip circuit that performs clipping that limits the rise of the generated image signal to a predetermined clip voltage.
  2. 　前記クリップ回路は、制御端子に供給された前記所定のクリップ電圧に基づいて前記画像信号の上昇を制限することにより前記クリップを行うフォロワ回路により構成される請求項１記載の撮像素子。 The image pickup device according to claim 1, wherein the clip circuit is composed of a follower circuit that performs the clip by limiting an increase in the image signal based on the predetermined clip voltage supplied to the control terminal.
  3. 　前記クリップ回路は、ゲートに前記所定のクリップ電圧が供給され、前記生成された画像信号がドレインに供給され、ソースに負荷が接続されるトランジスタによる前記フォロワ回路により構成される請求項２記載の撮像素子。 The image pickup according to claim 2, wherein the clip circuit is composed of the follower circuit by a transistor in which the predetermined clip voltage is supplied to the gate, the generated image signal is supplied to the drain, and the load is connected to the source. element.
  4. 　前記生成された画像信号をデジタルの画像信号に変換する際の基準となる参照信号と前記生成された画像信号との比較を行って当該比較の結果を出力する比較部と、前記比較部における前記比較の開始から前記比較の結果の出力までの計時を行う計時部とを備え、前記計時の結果に基づいて前記画像信号をデジタルの画像信号に変換するアナログデジタル変換部をさらに具備する請求項１記載の撮像素子。 A comparison unit that compares the generated image signal with a reference signal that serves as a reference when converting the generated image signal into a digital image signal and outputs the result of the comparison, and the comparison unit in the comparison unit. Claim 1 further includes an analog-digital conversion unit that includes a time measurement unit that performs time measurement from the start of comparison to the output of the comparison result, and converts the image signal into a digital image signal based on the measurement result. The image pickup device described.
  5. 　前記画素は、前記電荷保持部に保持された正孔を排出してリセットを行うリセット部をさらに備えて当該リセット後の画像信号であるリセット画像信号を生成し、
    　前記アナログデジタル変換部は、前記生成された画像信号とリセット画像信号との差分に基づいて前記デジタルの画像信号を生成する
    請求項４記載の撮像素子。     The pixel further includes a reset unit that discharges holes held in the charge holding unit to perform reset, and generates a reset image signal that is an image signal after the reset.
    The image pickup device according to claim 4, wherein the analog-to-digital conversion unit generates the digital image signal based on the difference between the generated image signal and the reset image signal.
  6. 　前記クリップ回路は、前記リセット画像信号の生成の際に前記クリップを行う請求項５記載の撮像素子。 The image pickup device according to claim 5, wherein the clip circuit performs the clip when the reset image signal is generated.
  7. 　前記比較部は、前記生成された画像信号および前記参照信号がそれぞれ結合キャパシタを介して入力される差動対と、前記差動対を初期化する初期化回路とを備え、
    　前記クリップ回路は、前記初期化回路による初期化の際に前記クリップを行う
    請求項５記載の撮像素子。     The comparison unit includes a differential pair in which the generated image signal and the reference signal are input via a coupling capacitor, and an initialization circuit for initializing the differential pair.
    The image pickup device according to claim 5, wherein the clip circuit performs the clip at the time of initialization by the initialization circuit.
  8. 　前記初期化回路は、前記生成された画像信号の初期値および前記参照信号の初期値を前記それぞれの結合キャパシタに保持させることにより初期化する請求項７記載の撮像素子。 The image pickup device according to claim 7, wherein the initialization circuit initializes by holding the initial value of the generated image signal and the initial value of the reference signal in the respective coupling capacitors.
  9. 　前記画像信号の飽和を検出する飽和検出部をさらに具備する請求項４記載の撮像素子。 The image pickup device according to claim 4, further comprising a saturation detection unit that detects saturation of the image signal.
  10. 　前記飽和検出部は、前記比較部における比較の結果に基づいて前記飽和を検出する請求項９記載の撮像素子。 The image pickup device according to claim 9, wherein the saturation detection unit detects the saturation based on the result of comparison in the comparison unit.
  11. 　前記飽和検出部の検出結果に基づいて前記デジタルの画像信号の補正を行う補正部をさらに具備する請求項９記載の撮像素子。 The image pickup device according to claim 9, further comprising a correction unit that corrects the digital image signal based on the detection result of the saturation detection unit.
  12. 　入射光の光電変換を行う光電変換部および前記光電変換により生成された電荷のうち正孔を保持する電荷保持部を備え、前記保持された正孔に基づいて画像信号を生成する画素と、
    　前記生成された画像信号の上昇を所定のクリップ電圧に制限するクリップを行うクリップ回路と、
    　前記生成された画像信号の処理を行う処理回路と
    を具備する撮像装置。     A pixel that includes a photoelectric conversion unit that performs photoelectric conversion of incident light and a charge holding unit that retains holes among the charges generated by the photoelectric conversion, and generates an image signal based on the retained holes.
    A clip circuit that performs clipping that limits the rise of the generated image signal to a predetermined clip voltage, and
    An imaging device including a processing circuit that processes the generated image signal.
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