WO2021073473A1 - Procédé et appareil de traitement de paquet de données, dispositif de communication et support de stockage - Google Patents

Procédé et appareil de traitement de paquet de données, dispositif de communication et support de stockage Download PDF

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Publication number
WO2021073473A1
WO2021073473A1 PCT/CN2020/120353 CN2020120353W WO2021073473A1 WO 2021073473 A1 WO2021073473 A1 WO 2021073473A1 CN 2020120353 W CN2020120353 W CN 2020120353W WO 2021073473 A1 WO2021073473 A1 WO 2021073473A1
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data packet
cpu core
core
processed
cpu
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PCT/CN2020/120353
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English (en)
Chinese (zh)
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刘学彬
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中兴通讯股份有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication

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  • multi-core CPU central processing unit, central processing unit
  • multi-core CPU central processing unit, central processing unit
  • the data receiving hardware device can only send the data packet to one CPU core in the multi-core CPU (or the number of CPU cores sent is less than the total number of CPU cores), resulting in other CPU cores being idle Status, unable to make full use of all CPU cores, reducing the data processing performance of communication equipment.
  • the data packet processing method, device, communication device, and storage medium provided by the embodiments of the present invention mainly aim to solve the technical problem at least to a certain extent that the data receiving hardware device can only send the data packet to one CPU core in the multi-core CPU ( Or the number of CPU cores sent is less than the total number of CPU cores), it is impossible to make full use of all the CPU cores, and the data processing performance of the communication equipment is low.
  • embodiments of the present invention provide a data packet processing method, which is applied to a communication device including a multi-core CPU central processing unit, and the multi-core CPU includes at least two CPU cores.
  • the method includes: receiving a data packet to be processed and determining a target CPU core for the data packet to be processed from all CPU cores included in the multi-core CPU; and tagging the data packet to be processed based on the target CPU core Information, the tag information includes the target CPU core; the data packet to be processed with the tag information is sent to a designated CPU core; the designated CPU core sends the data packet to the designated CPU core based on the label information of the data packet to be processed The data packet to be processed is sent to the target CPU core for processing.
  • the embodiment of the present invention also provides a data packet processing device, the data packet processing device includes a multi-core CPU and a hardware data receiving module, one of the CPU cores in the multi-core CPU is a designated CPU core; the hardware data receiving module, For receiving a data packet to be processed and determining a target CPU core for the data packet to be processed from at least two CPU cores included in the multi-core CPU, and adding label information to the data packet to be processed based on the target CPU core, Send the to-be-processed data packet with tag information to the designated CPU core, the tag information includes the target CPU core; the designated CPU core includes a sub-core module, used for processing based on the to-be-processed data packet The label information sends the data packet to be processed to the target CPU core; the target CPU core includes a processing module for processing the data packet to be processed.
  • the embodiment of the present invention further provides a storage medium, the readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the above-mentioned data packet processing method. step.
  • FIG. 1 is a flowchart of a data packet processing method according to Embodiment 1 of the present invention
  • FIG. 2 is a flowchart of determining a target CPU core for a data packet to be processed by specifying a CPU core according to Embodiment 1 of the present invention
  • FIG. 5 is a schematic structural diagram of a data packet processing device according to the third embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a detailed structure of a data packet processing device according to the fourth embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of a communication device according to Embodiment 5 of the present invention.
  • the data receiving hardware device can only send the data packet to one CPU core in the multi-core CPU or the number of CPU cores sent to is less than the total number of CPU cores, and cannot make full use of all the CPU cores, thus Leading to the problem of low data processing performance of communication devices, embodiments of the present invention provide a data packet processing method, which is applied to a communication device including a multi-core CPU. It should be understood that a multi-core CPU includes at least two CPUs. The core CPU. As shown in Figure 1, the data packet processing method includes:
  • S101 Receive a to-be-processed data packet and determine a target CPU core from all CPU cores included in the multi-core CPU for the to-be-processed data packet.
  • the communication device receives the data packet sent by the external device. At this time, the data packet has not been processed, so it is regarded as the data packet to be processed. After receiving the data packet to be processed, the communication device determines the target CPU core from all the CPU cores included in the multi-core CPU for the data packet to be processed, that is, selects a CPU core from all the CPU cores included in the multi-core CPU for the data packet to be processed As the target CPU core.
  • the communication device determines the target CPU core from all the CPU cores included in the multi-core CPU for the data packet to be processed, which may be: selecting a CPU core from all the CPU cores included in the multi-core CPU based on a preset algorithm as the target CPU core , Where the preset algorithm includes at least one of the following algorithms: round robin, hash (hash) method, and least idle method.
  • the target CPU core is selected in turn. For example, suppose a multi-core CPU includes CPU core 1, CPU core 2, and CPU core 3. After receiving the data packet to be processed, select CPU core 1 as the target CPU core After receiving the to-be-processed data packet again, select CPU core 2 as the target CPU core.
  • select CPU core 3 After receiving the to-be-processed data packet again, select CPU core 3 as the target CPU core. After receiving the to-be-processed data packet again, select CPU core 1 is used as the target CPU core and loops.
  • select CPU core 1 For the hash method, by calculating certain fields in the data packet to be processed (such as 5-TUPLE, which is a five-tuple, it should be noted that the 5-TUPLE of the data packet is the source IP (Internet Protocol, The protocol for interconnection between networks) address, destination IP address, source port, destination port, protocol parameters consisting of 5 fields) hash value, and the selection of the target CPU core is determined by a few bits in the hash value.
  • the most idle method according to the load status of each CPU core, the CPU core with the least load (that is, the most idle) is selected as the target CPU core.
  • the preset algorithm may also be other algorithms.
  • the communication device determines the target CPU core from all the CPU cores included in the multi-core CPU for the data packet to be processed, or it may be: find the CPU core corresponding to the 5 TUPLE of the data packet to be processed from the CPU core information look-up table As the target CPU core.
  • the CPU core information look-up table includes 5 TUPLE and the CPU core mapping relationship. It should be understood that the CPU core included in the CPU core information look-up table is the CPU core in the multi-core CPU of the communication device. See Table 1, which is An optional lookup table for CPU core information. Assuming that the 5 TUPLE of the data packet to be processed matches the first 5 TUPLE data, see Table 1. The corresponding CPU core is the first CPU core, so the first CPU core As the target CPU core of the packet to be processed.
  • the mapping relationship between the 5 TUPLE and the CPU core in the CPU core information lookup table can be preset by the developer, or the 5 TUPLE of the to-be-processed data packet received in history, and the CPU core that processes the data packet To determine, that is, after receiving the to-be-processed data packet and sending the to-be-processed data packet to the corresponding CPU core for processing, save the 5 TUPLE of the to-be-processed data packet and the corresponding CPU core update to the CPU core information Lookup table.
  • the data packet to be processed can also be directly sent to the designated CPU core.
  • tag information is added to the data packet to be processed based on the target CPU core, where the tag information includes the target CPU core.
  • the label information can be inserted into the data packet to be processed, and can also be inserted into other fields associated with the data packet to be processed.
  • S103 Send the to-be-processed data packet with tag information added to the designated CPU core.
  • the designated CPU core is the CPU core in the multi-core CPU, which can be flexibly set according to actual needs.
  • S101-S103 can be executed by the data receiving hardware device in the communication device.
  • the data receiving hardware device it can be an Ethernet card, PON MAC (hardware for receiving optical fiber downlink data in a passive optical network device) Wait.
  • the CPU core information look-up table may be stored in the data receiving hardware device.
  • the CPU core information look-up table may also be stored in other hardware devices.
  • the CPU core reachable by the data receiving hardware device that is, the data hardware receiving device can send the data packet to be processed to the CPU core
  • S104 The designated CPU core sends the to-be-processed data packet to the target CPU core for processing based on the label information of the to-be-processed data packet.
  • the target CPU core processing the data packet to be processed includes forwarding the data packet to be processed.
  • the data packet to be processed needs to be sent to an external device, and the target CPU core will wait The processed data packet is sent to the corresponding external device, among which the to-be-processed data packet can be sent to the corresponding external device through the egress network card; another case is that the to-be-processed data packet needs to be terminated locally, and the target CPU core will be processed The data packet is sent to the corresponding local data packet processing process for processing.
  • the target CPU core when the target CPU core performs forwarding processing on the data packet to be processed, it may also perform ordinary forwarding processing on the data packet to be processed.
  • S201 Specify a CPU core to select a CPU core from all CPU cores included in the multi-core CPU according to a preset algorithm as a target CPU core for the data packet to be processed.
  • the designated CPU core may also determine the target CPU core for the to-be-processed data packet according to the CPU core information look-up table.
  • the designated CPU core can first determine the target CPU core for the data packet to be processed according to the CPU core information look-up table. If there is no 5 TUPLE of the data packet to be processed in the CPU core information look-up table, the designated CPU core can be based on a preset algorithm A CPU core is selected from all the CPU cores included in the multi-core CPU as the target CPU core of the data packet to be processed, or the designated CPU core can directly use itself as the target CPU core.
  • the data packet processing method provided by the embodiment of the present invention determines the target CPU core from all the CPU cores included in the multi-core CPU by receiving the to-be-processed data packet and determines the target CPU core for the to-be-processed data packet, and adds label information to the to-be-processed data packet based on the target CPU core,
  • the tag information includes the target CPU core
  • the data packet to be processed with the tag information is sent to the designated CPU core
  • the designated CPU core sends the data packet to be processed to the target CPU core for processing based on the label information of the data packet to be processed.
  • the target CPU core is selected from all the CPU cores of the multi-core CPU to process the data packet to be processed, so that each CPU core of the multi-core CPU can be fully utilized and the data processing performance of the communication device is improved.
  • FIG. 3 is a flowchart of a data packet processing method provided by an embodiment of the present invention.
  • the data packet processing method is applied to a communication device including a multi-core CPU. It should be understood that a multi-core CPU includes at least two CPUs.
  • the core CPU, the data packet processing method includes:
  • the data receiving hardware device in the communication device receives data packets sent by other external devices.
  • S302 Determine whether there are 5 TUPLEs of the data packet to be processed in the CPU core information look-up table.
  • the CPU core information lookup table includes 5 TUPLE and the CPU core mapping relationship. It should be understood that the CPU core included in the CPU core information lookup table is the CPU core in the multi-core CPU of the communication device.
  • the data receiving hardware device judges whether there is 5TUPLE of the data packet to be processed in the CPU core information lookup table based on the CPU core information lookup table stored in the data receiving hardware device. , Go to S303; if not, go to S304.
  • the data receiving hardware device finds the mapping relationship between the corresponding 5 TUPLE and the CPU core from the CPU core information table based on the 5 TUPLE of the data packet to be processed, and uses the CPU core as the target CPU core.
  • the data receiving hardware device adds tag information to the data packet to be processed based on the target CPU core.
  • the tag information includes the target CPU core, where the tag information can be inserted into the data packet to be processed.
  • the data receiving hardware device sends the to-be-processed data packet with the tag information added to the designated CPU core, and the designated CPU core can be flexibly set according to actual needs.
  • S306 Send the to-be-processed data packet directly to the designated CPU core.
  • S307 The designated CPU core judges whether there is label information in the data packet to be processed.
  • the designated CPU core determines whether there is label information in the data packet to be processed, if yes, go to S308; if not, go to S309.
  • S308 The designated CPU core sends the to-be-processed data packet to the target CPU core according to the label information of the to-be-processed data packet.
  • the method of specifying the CPU core as the data packet to be processed and determining the target CPU core includes:
  • S401 The designated CPU core judges whether there are 5 TUPLEs of the data packet to be processed in the CPU core information look-up table.
  • the designated CPU core searches the CPU core information lookup table for the CPU core corresponding to the 5 TUPLE of the to-be-processed data packet as the target CPU core.
  • the designated CPU core selects a CPU core from all the CPU cores included in the multi-core CPU according to a preset algorithm as the target CPU core of the data packet to be processed.
  • the preset algorithm is the most idle method, that is, according to the load status of each CPU core, the CPU core with the least load (that is, the most idle) is selected as the target CPU core.
  • the preset algorithm may also be a round robin method or a hash method.
  • the designated CPU core sends the to-be-processed data packet to the target CPU core.
  • S311 The target CPU core forwards the data packet to be processed.
  • the target CPU core sends the to-be-processed data packet to the corresponding external device; if the to-be-processed data packet needs to be terminated locally, the target CPU core sends the to-be-processed data packet to The local packet processing process performs processing.
  • the target CPU core can quickly forward the data packet to be processed based on the fast forwarding table; or, the target CPU core can also perform ordinary forwarding processing on the data packet to be processed.
  • the data packet processing method provided by the embodiment of the present invention determines the target CPU core from all the CPU cores included in the multi-core CPU by receiving the to-be-processed data packet and determines the target CPU core for the to-be-processed data packet, and adds label information to the to-be-processed data packet based on the target CPU core,
  • the tag information includes the target CPU core
  • the data packet to be processed with the tag information is sent to the designated CPU core
  • the designated CPU core sends the data packet to be processed to the target CPU core for processing based on the label information of the data packet to be processed.
  • the target CPU core is selected from all the CPU cores of the multi-core CPU to process the data packet to be processed, so that each CPU core of the multi-core CPU can be fully utilized and the data processing performance of the communication device is improved.
  • the embodiment of the present invention provides a data packet processing device on the basis of the first and second embodiments. As shown in FIG. 5, it includes a multi-core CPU 51 and a hardware data receiving module 52.
  • the multi-core CPU 51 includes N CPU cores, and N is greater than An integer equal to 2, one of the CPU cores in the multi-core CPU 51 is a designated CPU core.
  • Each CPU core includes a processing module, and a designated CPU core also includes a sub-core module.
  • the CPU core 1 is the designated CPU core 511.
  • each CPU core includes a processing module 512, and the designated CPU core also includes a sub-core module 513.
  • the hardware data receiving module 52 is used to receive the to-be-processed data packet and determine the target CPU core from all the CPU cores included in the multi-core CPU 51 for the to-be-processed data packet, and add a tag to the to-be-processed data packet based on the target CPU core Information, the data packet to be processed with tag information is sent to the designated CPU core 511, and the tag information includes the target CPU core.
  • the hardware data receiving module 52 determines the target CPU core from all the CPU cores included in the multi-core CPU 51 for the data packet to be processed, which may be: selecting a CPU core from all the CPU cores included in the multi-core CPU 51 as the target CPU core based on a preset algorithm,
  • the preset algorithm may include at least one of the following algorithms: round robin method, hash method, and least idle method.
  • round robin method that is to say, the target CPU core is selected in turn.
  • the hash method the hash value of certain fields (such as 5-TUPLE) in the data packet to be processed is calculated, and the target CPU core is determined by certain bits in the hash value.
  • the most idle method that is, according to the load status of each CPU core, the CPU core with the least load (that is, the most idle) is selected as the target CPU core.
  • the preset algorithm may also be other algorithms.
  • the hardware data receiving module 52 determines the target CPU core from all the CPU cores included in the multi-core CPU 51 for the data packet to be processed. It can also be: look up the 5 TUPLE (five tuple) corresponding to the data packet to be processed from the CPU core information lookup table.
  • the CPU core serves as the target CPU core.
  • the 5 TUPLE of the data packet is a parameter composed of 5 fields of the data packet's source IP (Internet Protocol, interconnection protocol between networks) address, destination IP address, source port, destination port, and protocol.
  • the CPU core information lookup table includes the mapping relationship between 5 TUPLE and the CPU core. It should be understood that the CPU core included in the CPU core information lookup table is the CPU core in the multi-core CPU51 of the communication device.
  • Table 1 is An optional lookup table for CPU core information. Assuming that the 5 TUPLE of the data packet to be processed matches the third 5 TUPLE data, see Table 1. The corresponding CPU core is the second CPU core, so the second CPU core As the target CPU core of the packet to be processed.
  • mapping relationship between 5 TUPLE and CPU core in the CPU core information lookup table can be preset by the developer, or based on the 5 TUPLE of the pending data packet received in history and the CPU core that processes the data packet.
  • OK that is to say, after receiving the to-be-processed data packet and sending the to-be-processed data packet to the corresponding CPU core for processing, save the 5 TUPLE of the to-be-processed data packet and the corresponding CPU core update to the CPU core information search table.
  • the above-mentioned two hardware data receiving modules 52 can also be combined to determine the target CPU core for the data packet to be processed.
  • the CPU core information look-up table can be first searched for the 5 TUPLE corresponding to the data packet to be processed.
  • one CPU core can be selected from all the CPU cores included in the multi-core CPU 51 as the target CPU core based on a preset algorithm.
  • the hardware data receiving module 52 After the hardware data receiving module 52 determines the target CPU core for the data packet to be processed, it adds tag information to the data packet to be processed based on the target CPU core and sends it to the designated CPU core 511.
  • the tag information includes the target CPU core and tag information. It can be inserted into the to-be-processed data packet or into other fields associated with the to-be-processed data packet.
  • the processing module 512 of the target CPU core is configured to process the data packet to be processed after receiving the data packet to be processed.
  • the processing module 512 processes the to-be-processed data packet including forwarding the to-be-processed data packet. There are two cases.
  • the to-be-processed data packet needs to be sent to an external device, and the processing module 512 sends the to-be-processed data packet to the corresponding In the external device, the to-be-processed data packet can be sent to the corresponding external device through the egress network card; in another case, the to-be-processed data packet needs to be terminated locally, and the processing module 512 sends the to-be-processed data packet to the corresponding The local packet processing process performs processing.
  • the processing module 512 may include a fast forwarding module 5121 and a normal forwarding module 5122.
  • the data packet to be processed can be quickly forwarded by the fast forwarding module 5121.
  • the data packet to be processed can be quickly forwarded based on the fast forwarding table.
  • the fast forwarding table is established based on the 5-TUPLE of the data packet, which includes the egress of the data packet and the fields that need to be modified.
  • the fast forwarding process is performed on the data packet to be processed, it is based on the 5-TUPLE of the data packet to be processed.
  • the ordinary forwarding module 5122 may also perform ordinary forwarding processing on the data packet to be processed.
  • the to-be-processed data packet received by the sub-core module 513 from the hardware data receiving module 52 may not include tag information or the target CPU core may not be included in the tag information. Therefore, as shown in FIG. 6, the designated CPU core 511 also A decision module 514 is included, which is used to determine a target CPU core from all the CPU cores included in the multi-core CPU 51 for a data packet to be processed that does not include tag information or does not include the target CPU core in the tag information.
  • the decision module 514 can directly use the CPU core (that is, the designated CPU core 511) as the target CPU core, or the decision module 514 can also select a CPU core from all the CPU cores included in the multi-core CPU 51 based on a preset algorithm.
  • a learning module (not shown in FIG. 6) may also be included for obtaining 5 TUPLE and corresponding processing of the data packet to be processed after the decision module 514 selects the target CPU core for the data packet to be processed
  • the CPU core information of the data packet to be processed is sent to the hardware data receiving module 52, and the hardware data receiving module 52 adds it to the CPU core information look-up table based on the received 5 TUPLE and corresponding CPU core information.
  • the learning module can be set in the designated CPU core 511 and/or the target CPU core.
  • the learning module can obtain the 5 TUPLE of the data packet to be processed and the corresponding CPU core information for processing the data packet from the decision module 514, or obtain the 5 TUPLE of the data packet to be processed and the corresponding processing from the processing module 512
  • the CPU core information of the data packet to be processed is obtained, for example, from a fast forwarding module or a common forwarding module.
  • the hardware data receiving module 52 may be implemented by a data receiving hardware device, and the data receiving hardware device may be an Ethernet card, or a PON MAC or other hardware devices.
  • the data packet processing device determines the target CPU core from all the CPU cores included in the multi-core CPU by receiving the to-be-processed data packet and determines the target CPU core for the to-be-processed data packet, and adds label information to the to-be-processed data packet based on the target CPU core,
  • the tag information includes the target CPU core
  • the data packet to be processed with the tag information is sent to the designated CPU core
  • the designated CPU core sends the data packet to be processed to the target CPU core for processing based on the label information of the data packet to be processed.
  • the target CPU core is selected from all the CPU cores of the multi-core CPU to process the data packet to be processed, so that each CPU core of the multi-core CPU can be fully utilized and the data processing performance of the communication device is improved.
  • the data packet processing device includes a multi-core CPU 51 and a hardware data receiving module 52.
  • the multi-core CPU 51 includes N CPU cores, where N is an integer greater than or equal to 2, and the CPU core 1 in the multi-core CPU is the designated CPU core 511.
  • each CPU core includes a processing module 512 and a learning module 515.
  • the processing module 512 includes a fast forwarding module 5121 and a normal forwarding module 5122; the designated CPU core 511 also includes a sub-core module 513 and a decision module 514.
  • the hardware data receiving module 52 is used to find the CPU core corresponding to 5 TUPLE of the to-be-processed data packet from the CPU core information look-up table as the target CPU core after receiving the to-be-processed data packet, and based on the target CPU core in the to-be-processed
  • the tag information is inserted into the field of the data packet, and the to-be-processed data packet with the tag information inserted is sent to the sub-core module 513 of the designated CPU core 511.
  • the tag information includes the target CPU core.
  • the CPU core information lookup table includes 5 TUPLE and CPU core mapping relationships. If there is no 5TUPLE of the data packet to be processed in the CPU core information look-up table, the hardware data receiving module 52 directly sends the data packet to be processed to the sub-core module 513.
  • the sub-core module 513 is configured to, after receiving the to-be-processed data packet sent by the hardware data receiving module 52, determine whether the to-be-processed data packet has tag information and whether there is a target CPU core in the tag information, and if the to-be-processed data packet has tag information , And the tag information includes the target CPU core. In order to improve the forwarding speed, the sub-core module 513 can directly send the to-be-processed data packet to the fast forwarding module 5121 in the target CPU core; if the tag information does not exist, or the tag information does not If the target CPU core exists, the to-be-divided core module 513 sends the to-be-processed data packet to the decision module 514.
  • the decision module 514 After receiving the data packet to be processed, the decision module 514 searches the CPU core information look-up table for the CPU core corresponding to 5 TUPLE of the data packet to be processed as the target CPU core. If there is no data packet to be processed in the CPU core information look-up table 5 TUPLE, the decision module 514 selects a CPU core from all the CPU cores included in the multi-core CPU 51 as the target CPU core of the data packet to be processed according to the preset algorithm, and sends it to the normal forwarding module 5122 of the target CPU core.
  • the preset algorithm may be at least one of a round robin method, a hash method, and a least idle method.
  • the fast forwarding module 5121 is configured to fast forward the to-be-processed data packet based on the fast-forwarding table after receiving the to-be-processed data packet sent by the sub-core module 513.
  • the specific process can be referred to the foregoing record and will not be repeated here.
  • the normal forwarding module 5122 is configured to perform normal forwarding processing on the to-be-processed data packet sent by the decision module 514.
  • the data packet processing device determines the target CPU core from all the CPU cores included in the multi-core CPU for the data packet to be processed through the hardware data receiving module, adds tag information based on the target CPU core, and adds the tag information to be processed
  • the data packet is sent to the designated CPU core, so that the designated CPU core can directly send the to-be-processed data packet to the fast forwarding module of the target CPU core for fast forwarding according to the label information, so that the forwarding module of the device can be executed in parallel on multiple cores, which improves Data processing performance of communication equipment.
  • This embodiment also provides a communication device. As shown in FIG. 8, it includes a processor 801, a memory 802, and a communication bus 803.
  • the processor 801 includes at least one multi-core CPU, and the multi-core CPU includes at least two CPU cores, wherein:
  • the communication bus 803 is used to implement connection and communication between the processor 801 and the memory 802;
  • the processor 801 is configured to execute one or more computer programs stored in the memory 802 to implement at least one step in the data packet processing method in the first embodiment and the second embodiment.
  • This embodiment also provides a storage medium that includes volatile or non-volatile memory implemented in any method or technology for storing information (such as computer-readable instructions, data structures, computer program modules, or other data). Volatile, removable or non-removable media.
  • Computer-readable storage media include but are not limited to RAM (Random Access Memory), ROM (Read-Only Memory, read-only memory), EEPROM (Electrically Erasable Programmable Read-Only Memory, charged erasable programmable read-only memory) Storage), flash memory or other storage technologies, CD-ROM (Compact Disc Read-Only Memory), digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices Or any other medium that can be used to store desired information and can be accessed by a computer.
  • the storage medium in this embodiment can be used to store one or more computer programs, and the stored one or more computer programs can be executed by a processor to implement the data packet processing methods in the first embodiment and the second embodiment. At least one step.
  • the data packet processing method, device, communication device and storage medium determine the target CPU core from all the CPU cores included in the multi-core CPU by receiving the to-be-processed data packet and determine the target CPU core for the to-be-processed data packet, based on the target CPU core being Add label information to the data packet to be processed, where the label information includes the target CPU core, and send the data packet to be processed after adding the label information to the designated CPU core, and the designated CPU core sends the data packet to be processed based on the label information of the data packet to be processed Send to the target CPU core for processing.
  • the target CPU core is selected from all the CPU cores of the multi-core CPU to process the data packets to be processed, so that each CPU core of the multi-core CPU can be fully utilized and the communication equipment's performance is improved. Data processing performance.

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Abstract

Procédé et appareil de traitement de paquet de données, dispositif de communication et support de stockage. Le procédé consiste à : recevoir un paquet de données à traiter et déterminer pour le paquet de données un cœur de CPU cible parmi tous les cœurs de CPU compris dans une CPU multicœur (S101) ; sur la base du cœur de CPU cible, ajouter des informations d'étiquette au paquet de données (S102), les informations d'étiquette comprenant le cœur de CPU cible ; envoyer à un cœur de CPU désigné le paquet de données auquel les informations d'étiquette ont été ajoutées (S103) ; et sur la base des informations d'étiquette du paquet de données, envoyer par le cœur de CPU désigné le paquet de données au cœur de CPU cible pour le traitement (S104).
PCT/CN2020/120353 2019-10-16 2020-10-12 Procédé et appareil de traitement de paquet de données, dispositif de communication et support de stockage WO2021073473A1 (fr)

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