WO2021073473A1

WO2021073473A1 - Data packet processing method and apparatus, communication device, and storage medium

Info

Publication number: WO2021073473A1
Application number: PCT/CN2020/120353
Authority: WO
Inventors: 刘学彬
Original assignee: 中兴通讯股份有限公司
Priority date: 2019-10-16
Filing date: 2020-10-12
Publication date: 2021-04-22
Also published as: CN112667554A

Abstract

A data packet processing method and apparatus, a communication device, and a storage medium. The method comprises: receiving a data packet to be processed and determining for the data packet a target CPU core from among all CPU cores comprised by a multi-core CPU (S101); on the basis of the target CPU core, adding tag information to the data packet (S102), the tag information comprising the target CPU core; sending to a designated CPU core the data packet to which the tag information has been added (S103); and on the basis of the tag information of the data packet, the designated CPU core sends the data packet to the target CPU core for processing (S104).

Description

Data packet processing method, device, communication equipment and storage medium

Cross-references to related applications

This application is based on a Chinese patent application whose application number is 201910984845.1, and the filing date is October 16, 2019, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby incorporated into this application by reference.

Technical field

The embodiments of the present invention relate to, but are not limited to, the field of communications, in particular, to, but are not limited to, data packet processing methods, devices, communication equipment, and storage media.

Background technique

Data processing performance has always been an important indicator of communication equipment. Nowadays, multi-core CPU (central processing unit, central processing unit) has become more and more popular, from two-core, four-core to eight-core, and more and more multi-core CPUs are used in communication equipment. However, in some cases, the data receiving hardware device can only send the data packet to one CPU core in the multi-core CPU (or the number of CPU cores sent is less than the total number of CPU cores), resulting in other CPU cores being idle Status, unable to make full use of all CPU cores, reducing the data processing performance of communication equipment.

Summary of the invention

The data packet processing method, device, communication device, and storage medium provided by the embodiments of the present invention mainly aim to solve the technical problem at least to a certain extent that the data receiving hardware device can only send the data packet to one CPU core in the multi-core CPU ( Or the number of CPU cores sent is less than the total number of CPU cores), it is impossible to make full use of all the CPU cores, and the data processing performance of the communication equipment is low.

In order to solve the above-mentioned technical problems in some situations at least to a certain extent, embodiments of the present invention provide a data packet processing method, which is applied to a communication device including a multi-core CPU central processing unit, and the multi-core CPU includes at least two CPU cores. , The method includes: receiving a data packet to be processed and determining a target CPU core for the data packet to be processed from all CPU cores included in the multi-core CPU; and tagging the data packet to be processed based on the target CPU core Information, the tag information includes the target CPU core; the data packet to be processed with the tag information is sent to a designated CPU core; the designated CPU core sends the data packet to the designated CPU core based on the label information of the data packet to be processed The data packet to be processed is sent to the target CPU core for processing.

The embodiment of the present invention also provides a data packet processing device, the data packet processing device includes a multi-core CPU and a hardware data receiving module, one of the CPU cores in the multi-core CPU is a designated CPU core; the hardware data receiving module, For receiving a data packet to be processed and determining a target CPU core for the data packet to be processed from at least two CPU cores included in the multi-core CPU, and adding label information to the data packet to be processed based on the target CPU core, Send the to-be-processed data packet with tag information to the designated CPU core, the tag information includes the target CPU core; the designated CPU core includes a sub-core module, used for processing based on the to-be-processed data packet The label information sends the data packet to be processed to the target CPU core; the target CPU core includes a processing module for processing the data packet to be processed.

An embodiment of the present invention also provides a communication device, including a processor, a memory, and a communication bus. The processor includes at least one multi-core CPU; the communication bus is used to implement connection and communication between the processor and the memory; The processor is used to execute one or more computer programs stored in the memory to implement the steps of the foregoing data packet processing method.

The embodiment of the present invention further provides a storage medium, the readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the above-mentioned data packet processing method. step.

Other features and corresponding beneficial effects of the present invention are described in the latter part of the specification, and it should be understood that at least part of the beneficial effects will become apparent from the description in the specification of the present invention.

Description of the drawings

FIG. 1 is a flowchart of a data packet processing method according to Embodiment 1 of the present invention;

2 is a flowchart of determining a target CPU core for a data packet to be processed by specifying a CPU core according to Embodiment 1 of the present invention;

Fig. 3 is a flowchart of a data packet processing method according to the second embodiment of the present invention;

4 is a flowchart of determining a target CPU core for a designated CPU core as a data packet to be processed according to the second embodiment of the present invention;

FIG. 5 is a schematic structural diagram of a data packet processing device according to the third embodiment of the present invention;

FIG. 6 is a schematic diagram of a detailed structure of a data packet processing device according to the third embodiment of the present invention;

FIG. 7 is a schematic diagram of a detailed structure of a data packet processing device according to the fourth embodiment of the present invention;

FIG. 8 is a schematic structural diagram of a communication device according to Embodiment 5 of the present invention.

Detailed ways

In order to make the objectives, technical solutions, and advantages of the present invention clearer, the following further describes the embodiments of the present invention in detail through specific implementations in conjunction with the accompanying drawings. It should be understood that the specific embodiments described here are only used to explain the present invention, but not to limit the present invention.

Example one:

In order to solve at least to a certain extent, the data receiving hardware device can only send the data packet to one CPU core in the multi-core CPU or the number of CPU cores sent to is less than the total number of CPU cores, and cannot make full use of all the CPU cores, thus Leading to the problem of low data processing performance of communication devices, embodiments of the present invention provide a data packet processing method, which is applied to a communication device including a multi-core CPU. It should be understood that a multi-core CPU includes at least two CPUs. The core CPU. As shown in Figure 1, the data packet processing method includes:

S101. Receive a to-be-processed data packet and determine a target CPU core from all CPU cores included in the multi-core CPU for the to-be-processed data packet.

In the embodiment of the present invention, the communication device receives the data packet sent by the external device. At this time, the data packet has not been processed, so it is regarded as the data packet to be processed. After receiving the data packet to be processed, the communication device determines the target CPU core from all the CPU cores included in the multi-core CPU for the data packet to be processed, that is, selects a CPU core from all the CPU cores included in the multi-core CPU for the data packet to be processed As the target CPU core.

In the embodiment of the present invention, the communication device determines the target CPU core from all the CPU cores included in the multi-core CPU for the data packet to be processed, which may be: selecting a CPU core from all the CPU cores included in the multi-core CPU based on a preset algorithm as the target CPU core , Where the preset algorithm includes at least one of the following algorithms: round robin, hash (hash) method, and least idle method. For the round robin method, the target CPU core is selected in turn. For example, suppose a multi-core CPU includes CPU core 1, CPU core 2, and CPU core 3. After receiving the data packet to be processed, select CPU core 1 as the target CPU core After receiving the to-be-processed data packet again, select CPU core 2 as the target CPU core. After receiving the to-be-processed data packet again, select CPU core 3 as the target CPU core. After receiving the to-be-processed data packet again, select CPU core 1 is used as the target CPU core and loops. For the hash method, by calculating certain fields in the data packet to be processed (such as 5-TUPLE, which is a five-tuple, it should be noted that the 5-TUPLE of the data packet is the source IP (Internet Protocol, The protocol for interconnection between networks) address, destination IP address, source port, destination port, protocol parameters consisting of 5 fields) hash value, and the selection of the target CPU core is determined by a few bits in the hash value. For the most idle method, according to the load status of each CPU core, the CPU core with the least load (that is, the most idle) is selected as the target CPU core. Of course, in the embodiment of the present invention, the preset algorithm may also be other algorithms.

In the embodiment of the present invention, the communication device determines the target CPU core from all the CPU cores included in the multi-core CPU for the data packet to be processed, or it may be: find the CPU core corresponding to the 5 TUPLE of the data packet to be processed from the CPU core information look-up table As the target CPU core. The CPU core information look-up table includes 5 TUPLE and the CPU core mapping relationship. It should be understood that the CPU core included in the CPU core information look-up table is the CPU core in the multi-core CPU of the communication device. See Table 1, which is An optional lookup table for CPU core information. Assuming that the 5 TUPLE of the data packet to be processed matches the first 5 TUPLE data, see Table 1. The corresponding CPU core is the first CPU core, so the first CPU core As the target CPU core of the packet to be processed.

Table 1

CPU core information lookup table

In the embodiment of the present invention, the mapping relationship between the 5 TUPLE and the CPU core in the CPU core information lookup table can be preset by the developer, or the 5 TUPLE of the to-be-processed data packet received in history, and the CPU core that processes the data packet To determine, that is, after receiving the to-be-processed data packet and sending the to-be-processed data packet to the corresponding CPU core for processing, save the 5 TUPLE of the to-be-processed data packet and the corresponding CPU core update to the CPU core information Lookup table.

In the embodiment of the present invention, the above two methods of determining the target CPU core for the data packet to be processed can also be combined. For example, the CPU core corresponding to the 5 TUPLE of the data packet to be processed can be searched from the CPU core information lookup table as the target. CPU core, when there is no 5 TUPLE of the data packet to be processed in the CPU core information lookup table, one CPU core may be selected as the target CPU core from at least two CPU cores included in the multi-core CPU based on a preset algorithm.

It should be noted that, in the embodiment of the present invention, when there is no 5TUPLE of the data packet to be processed in the CPU core information look-up table, the data packet to be processed can also be directly sent to the designated CPU core.

S102: Add label information to the data packet to be processed based on the target CPU core.

In the embodiment of the present invention, after the target CPU core corresponding to the data packet to be processed is determined, tag information is added to the data packet to be processed based on the target CPU core, where the tag information includes the target CPU core.

In the embodiment of the present invention, the label information can be inserted into the data packet to be processed, and can also be inserted into other fields associated with the data packet to be processed.

S103: Send the to-be-processed data packet with tag information added to the designated CPU core.

In the embodiment of the present invention, after adding label information to the data packet to be processed, it is sent to the designated CPU core, where the designated CPU core is the CPU core in the multi-core CPU, which can be flexibly set according to actual needs. Specify the CPU core. That is to say, in the embodiment of the present invention, before sending the to-be-processed data packet to the multi-core CPU, a CPU core needs to be allocated to the to-be-processed data packet to process the to-be-processed data packet.

In the embodiment of the present invention, S101-S103 can be executed by the data receiving hardware device in the communication device. For the data receiving hardware device, it can be an Ethernet card, PON MAC (hardware for receiving optical fiber downlink data in a passive optical network device) Wait. Among them, the CPU core information look-up table may be stored in the data receiving hardware device. Of course, the CPU core information look-up table may also be stored in other hardware devices. In the embodiment of the present invention, the CPU core reachable by the data receiving hardware device (that is, the data hardware receiving device can send the data packet to be processed to the CPU core) can be set as the designated CPU core.

S104: The designated CPU core sends the to-be-processed data packet to the target CPU core for processing based on the label information of the to-be-processed data packet.

In the embodiment of the present invention, after receiving the data packet to be processed, the designated CPU core sends the data packet to be processed to the target CPU core for processing based on the label information of the data packet to be processed. If the target CPU core and the designated CPU core are the same CPU core, the designated CPU core directly processes the data packet to be processed.

In the embodiment of the present invention, the target CPU core processing the data packet to be processed includes forwarding the data packet to be processed. There are two cases. In one case, the data packet to be processed needs to be sent to an external device, and the target CPU core will wait The processed data packet is sent to the corresponding external device, among which the to-be-processed data packet can be sent to the corresponding external device through the egress network card; another case is that the to-be-processed data packet needs to be terminated locally, and the target CPU core will be processed The data packet is sent to the corresponding local data packet processing process for processing.

In the embodiment of the present invention, when the target CPU core performs forwarding processing on the data packet to be processed, it may perform fast forwarding processing on the data packet to be processed based on the fast forwarding table. In the embodiment of the present invention, the fast forwarding table is established based on the 5-TUPLE of the data packet, which includes the egress of the data packet and the fields that need to be modified. When the fast forwarding process is performed on the data packet to be processed, it is based on the 5-TUPLE of the data packet to be processed. Find the corresponding fast forwarding table, modify the data packet to be processed based on the fields that need to be modified in the fast forwarding table and send it directly to the corresponding exit (ie, external device or local data packet processing process), so as to achieve the purpose of fast data forwarding.

In the embodiment of the present invention, when the target CPU core performs forwarding processing on the data packet to be processed, it may also perform ordinary forwarding processing on the data packet to be processed.

In the embodiment of the present invention, in some cases, the data packet to be processed received by the designated CPU core may not have the target CPU (for example, the tag information of the data packet to be processed does not exist or the target CPU core does not exist in the tag information). At this time, the designated CPU can determine the target CPU core from all the CPU cores included in the multi-core CPU for the data packet to be processed, and send the data packet to be processed to the target CPU core for processing. Among them, the designated CPU core can directly process the data packet to be processed as the target CPU core. Or, as shown in Figure 2, the designated CPU core can also be used to determine the target CPU core in the following ways:

S201: Specify a CPU core to select a CPU core from all CPU cores included in the multi-core CPU according to a preset algorithm as a target CPU core for the data packet to be processed.

For the preset algorithm, please refer to the aforementioned record, which will not be repeated here.

S202: The designated CPU core sends the to-be-processed data packet to the target CPU core for processing.

Alternatively, the designated CPU core may also determine the target CPU core for the to-be-processed data packet according to the CPU core information look-up table.

The above-mentioned method of specifying the CPU core to determine the target CPU core for the to-be-processed data packet may also be combined. For example, the designated CPU core can first determine the target CPU core for the data packet to be processed according to the CPU core information look-up table. If there is no 5 TUPLE of the data packet to be processed in the CPU core information look-up table, the designated CPU core can be based on a preset algorithm A CPU core is selected from all the CPU cores included in the multi-core CPU as the target CPU core of the data packet to be processed, or the designated CPU core can directly use itself as the target CPU core.

In the embodiment of the present invention, after the designated CPU core selects the target CPU core for the to-be-processed data packet, it can update the CPU core information look-up table based on the 5 TUPLE of the to-be-processed data packet and the CPU core that processes the to-be-processed data packet. The mapping relationship between the 5 TUPLE and the CPU core that processes the data packet is added to the CPU core information lookup table.

The data packet processing method provided by the embodiment of the present invention determines the target CPU core from all the CPU cores included in the multi-core CPU by receiving the to-be-processed data packet and determines the target CPU core for the to-be-processed data packet, and adds label information to the to-be-processed data packet based on the target CPU core, Wherein, the tag information includes the target CPU core, the data packet to be processed with the tag information is sent to the designated CPU core, and the designated CPU core sends the data packet to be processed to the target CPU core for processing based on the label information of the data packet to be processed. In some implementations, the target CPU core is selected from all the CPU cores of the multi-core CPU to process the data packet to be processed, so that each CPU core of the multi-core CPU can be fully utilized and the data processing performance of the communication device is improved.

Embodiment two:

In order to better understand the present invention, this embodiment is described in conjunction with more specific examples. Referring to FIG. 3, FIG. 3 is a flowchart of a data packet processing method provided by an embodiment of the present invention. The data packet processing method is applied to a communication device including a multi-core CPU. It should be understood that a multi-core CPU includes at least two CPUs. The core CPU, the data packet processing method includes:

S301. Receive a data packet to be processed.

In the embodiment of the present invention, the data receiving hardware device in the communication device receives data packets sent by other external devices.

The data receiving hardware device can be an Ethernet card or a PON MAC.

S302: Determine whether there are 5 TUPLEs of the data packet to be processed in the CPU core information look-up table.

If yes, go to S303; if not, go to S306.

It should be noted that the CPU core information lookup table includes 5 TUPLE and the CPU core mapping relationship. It should be understood that the CPU core included in the CPU core information lookup table is the CPU core in the multi-core CPU of the communication device.

In the embodiment of the present invention, after receiving the data packet to be processed, the data receiving hardware device judges whether there is 5TUPLE of the data packet to be processed in the CPU core information lookup table based on the CPU core information lookup table stored in the data receiving hardware device. , Go to S303; if not, go to S304.

S303: Find a CPU core corresponding to 5 TUPLE of the data packet to be processed from the CPU core information look-up table as the target CPU core.

In the embodiment of the present invention, the data receiving hardware device finds the mapping relationship between the corresponding 5 TUPLE and the CPU core from the CPU core information table based on the 5 TUPLE of the data packet to be processed, and uses the CPU core as the target CPU core.

S304: Add label information to the data packet to be processed based on the target CPU core.

The data receiving hardware device adds tag information to the data packet to be processed based on the target CPU core. The tag information includes the target CPU core, where the tag information can be inserted into the data packet to be processed.

S305: Send the to-be-processed data packet with the tag information added to the designated CPU core.

The data receiving hardware device sends the to-be-processed data packet with the tag information added to the designated CPU core, and the designated CPU core can be flexibly set according to actual needs.

S306: Send the to-be-processed data packet directly to the designated CPU core.

S307: The designated CPU core judges whether there is label information in the data packet to be processed.

If yes, go to S308; if not, go to S309.

In the embodiment of the present invention, after receiving the data packet to be processed, the designated CPU core determines whether there is label information in the data packet to be processed, if yes, go to S308; if not, go to S309.

S308: The designated CPU core sends the to-be-processed data packet to the target CPU core according to the label information of the to-be-processed data packet.

S309. Specify the CPU core as the data packet to be processed and determine the target CPU core from all the CPU cores included in the multi-core CPU.

Among them, referring to Figure 4, the method of specifying the CPU core as the data packet to be processed and determining the target CPU core includes:

S401: The designated CPU core judges whether there are 5 TUPLEs of the data packet to be processed in the CPU core information look-up table.

If yes, go to S402; if not, go to S403.

S402: The designated CPU core searches the CPU core information lookup table for the CPU core corresponding to the 5 TUPLE of the to-be-processed data packet as the target CPU core.

S403: The designated CPU core selects a CPU core from all the CPU cores included in the multi-core CPU according to a preset algorithm as the target CPU core of the data packet to be processed.

Among them, the preset algorithm is the most idle method, that is, according to the load status of each CPU core, the CPU core with the least load (that is, the most idle) is selected as the target CPU core. Of course, in other embodiments, the preset algorithm may also be a round robin method or a hash method.

In the embodiment of the present invention, after S403, based on the 5 TUPLE of the data packet to be processed and the target CPU core determined for the data packet to be processed, it is updated to the CPU core information lookup table, that is, the data packet to be processed is 5 The mapping relationship between TUPLE and CPU core is added to the CPU core information lookup table.

S310. The designated CPU core sends the to-be-processed data packet to the target CPU core.

S311: The target CPU core forwards the data packet to be processed.

Among them, if the to-be-processed data packet needs to be sent to an external device, the target CPU core sends the to-be-processed data packet to the corresponding external device; if the to-be-processed data packet needs to be terminated locally, the target CPU core sends the to-be-processed data packet to The local packet processing process performs processing.

Among them, the target CPU core can quickly forward the data packet to be processed based on the fast forwarding table; or, the target CPU core can also perform ordinary forwarding processing on the data packet to be processed.

Example three:

The embodiment of the present invention provides a data packet processing device on the basis of the first and second embodiments. As shown in FIG. 5, it includes a multi-core CPU 51 and a hardware data receiving module 52. The multi-core CPU 51 includes N CPU cores, and N is greater than An integer equal to 2, one of the CPU cores in the multi-core CPU 51 is a designated CPU core. Each CPU core includes a processing module, and a designated CPU core also includes a sub-core module. In the embodiment of the present invention, it is assumed that the CPU core 1 is the designated CPU core 511. In the embodiment of the present invention, each CPU core includes a processing module 512, and the designated CPU core also includes a sub-core module 513.

In the embodiment of the present invention, the hardware data receiving module 52 is used to receive the to-be-processed data packet and determine the target CPU core from all the CPU cores included in the multi-core CPU 51 for the to-be-processed data packet, and add a tag to the to-be-processed data packet based on the target CPU core Information, the data packet to be processed with tag information is sent to the designated CPU core 511, and the tag information includes the target CPU core.

Wherein, the hardware data receiving module 52 determines the target CPU core from all the CPU cores included in the multi-core CPU 51 for the data packet to be processed, which may be: selecting a CPU core from all the CPU cores included in the multi-core CPU 51 as the target CPU core based on a preset algorithm, Wherein, the preset algorithm may include at least one of the following algorithms: round robin method, hash method, and least idle method. For the round robin method, that is to say, the target CPU core is selected in turn. For the hash method, the hash value of certain fields (such as 5-TUPLE) in the data packet to be processed is calculated, and the target CPU core is determined by certain bits in the hash value. For the most idle method, that is, according to the load status of each CPU core, the CPU core with the least load (that is, the most idle) is selected as the target CPU core. Of course, in the embodiment of the present invention, the preset algorithm may also be other algorithms.

The hardware data receiving module 52 determines the target CPU core from all the CPU cores included in the multi-core CPU 51 for the data packet to be processed. It can also be: look up the 5 TUPLE (five tuple) corresponding to the data packet to be processed from the CPU core information lookup table. The CPU core serves as the target CPU core. It should be noted that the 5 TUPLE of the data packet is a parameter composed of 5 fields of the data packet's source IP (Internet Protocol, interconnection protocol between networks) address, destination IP address, source port, destination port, and protocol. The CPU core information lookup table includes the mapping relationship between 5 TUPLE and the CPU core. It should be understood that the CPU core included in the CPU core information lookup table is the CPU core in the multi-core CPU51 of the communication device. See Table 1, which is An optional lookup table for CPU core information. Assuming that the 5 TUPLE of the data packet to be processed matches the third 5 TUPLE data, see Table 1. The corresponding CPU core is the second CPU core, so the second CPU core As the target CPU core of the packet to be processed.

It should be noted that the mapping relationship between 5 TUPLE and CPU core in the CPU core information lookup table can be preset by the developer, or based on the 5 TUPLE of the pending data packet received in history and the CPU core that processes the data packet. OK, that is to say, after receiving the to-be-processed data packet and sending the to-be-processed data packet to the corresponding CPU core for processing, save the 5 TUPLE of the to-be-processed data packet and the corresponding CPU core update to the CPU core information search table.

In the embodiment of the present invention, the above-mentioned two hardware data receiving modules 52 can also be combined to determine the target CPU core for the data packet to be processed. For example, the CPU core information look-up table can be first searched for the 5 TUPLE corresponding to the data packet to be processed. When there is no 5 TUPLE of the data packet to be processed in the CPU core information look-up table, one CPU core can be selected from all the CPU cores included in the multi-core CPU 51 as the target CPU core based on a preset algorithm.

After the hardware data receiving module 52 determines the target CPU core for the data packet to be processed, it adds tag information to the data packet to be processed based on the target CPU core and sends it to the designated CPU core 511. The tag information includes the target CPU core and tag information. It can be inserted into the to-be-processed data packet or into other fields associated with the to-be-processed data packet.

The sub-core module 513 of the designated CPU core 511 is configured to send the to-be-processed data packet to the target CPU core based on the label information of the to-be-processed data packet after receiving the to-be-processed data packet sent by the hardware data receiving module 52. It should be noted that, in some cases, the target CPU core may be the designated CPU core 511. At this time, the processing module 512 of the designated CPU core 511 is to process the data packet to be processed.

The processing module 512 of the target CPU core is configured to process the data packet to be processed after receiving the data packet to be processed. The processing module 512 processes the to-be-processed data packet including forwarding the to-be-processed data packet. There are two cases. In one case, the to-be-processed data packet needs to be sent to an external device, and the processing module 512 sends the to-be-processed data packet to the corresponding In the external device, the to-be-processed data packet can be sent to the corresponding external device through the egress network card; in another case, the to-be-processed data packet needs to be terminated locally, and the processing module 512 sends the to-be-processed data packet to the corresponding The local packet processing process performs processing.

In the embodiment of the present invention, referring to FIG. 6, the processing module 512 may include a fast forwarding module 5121 and a normal forwarding module 5122. When the data packet to be processed is forwarded, the data packet to be processed can be quickly forwarded by the fast forwarding module 5121. Among them, the data packet to be processed can be quickly forwarded based on the fast forwarding table. In the embodiment of the present invention, the fast forwarding table is established based on the 5-TUPLE of the data packet, which includes the egress of the data packet and the fields that need to be modified. When the fast forwarding process is performed on the data packet to be processed, it is based on the 5-TUPLE of the data packet to be processed. Find the corresponding fast forwarding table, modify the data packet to be processed based on the fields that need to be modified in the fast forwarding table and send it directly to the corresponding exit (ie, external device or local data packet processing process), so as to achieve the purpose of fast data forwarding. In the embodiment of the present invention, the ordinary forwarding module 5122 may also perform ordinary forwarding processing on the data packet to be processed.

In some cases, the to-be-processed data packet received by the sub-core module 513 from the hardware data receiving module 52 may not include tag information or the target CPU core may not be included in the tag information. Therefore, as shown in FIG. 6, the designated CPU core 511 also A decision module 514 is included, which is used to determine a target CPU core from all the CPU cores included in the multi-core CPU 51 for a data packet to be processed that does not include tag information or does not include the target CPU core in the tag information. Among them, the decision module 514 can directly use the CPU core (that is, the designated CPU core 511) as the target CPU core, or the decision module 514 can also select a CPU core from all the CPU cores included in the multi-core CPU 51 based on a preset algorithm. The target CPU core, where the preset algorithm can be a round robin method, a hash method, or a least idle method. Alternatively, the decision module 514 may also search for the CPU core corresponding to the 5 TUPLE of the data packet to be processed from the CPU core information look-up table as the target CPU core. Alternatively, the above three methods can also be combined. For example, the decision module 514 can first determine the target CPU core for the data packet to be processed according to the CPU core information look-up table. , The decision module 514 can select a CPU core from all the CPU cores included in the multi-core CPU 51 as the target CPU core of the data packet to be processed according to a preset algorithm, or the decision module 514 can directly use itself as the target CPU core. After selecting the target CPU core, the decision module 514 sends the to-be-processed data packet to the target CPU core for processing.

In the embodiment of the present invention, a learning module (not shown in FIG. 6) may also be included for obtaining 5 TUPLE and corresponding processing of the data packet to be processed after the decision module 514 selects the target CPU core for the data packet to be processed The CPU core information of the data packet to be processed is sent to the hardware data receiving module 52, and the hardware data receiving module 52 adds it to the CPU core information look-up table based on the received 5 TUPLE and corresponding CPU core information. Among them, the learning module can be set in the designated CPU core 511 and/or the target CPU core. The learning module can obtain the 5 TUPLE of the data packet to be processed and the corresponding CPU core information for processing the data packet from the decision module 514, or obtain the 5 TUPLE of the data packet to be processed and the corresponding processing from the processing module 512 The CPU core information of the data packet to be processed is obtained, for example, from a fast forwarding module or a common forwarding module.

In the embodiment of the present invention, the hardware data receiving module 52 may be implemented by a data receiving hardware device, and the data receiving hardware device may be an Ethernet card, or a PON MAC or other hardware devices.

The data packet processing device provided by the embodiment of the present invention determines the target CPU core from all the CPU cores included in the multi-core CPU by receiving the to-be-processed data packet and determines the target CPU core for the to-be-processed data packet, and adds label information to the to-be-processed data packet based on the target CPU core, Wherein, the tag information includes the target CPU core, the data packet to be processed with the tag information is sent to the designated CPU core, and the designated CPU core sends the data packet to be processed to the target CPU core for processing based on the label information of the data packet to be processed. In some implementations, the target CPU core is selected from all the CPU cores of the multi-core CPU to process the data packet to be processed, so that each CPU core of the multi-core CPU can be fully utilized and the data processing performance of the communication device is improved.

Example four

In order to better understand the present invention, this embodiment is described in conjunction with more specific examples. As shown in FIG. 7, the data packet processing device includes a multi-core CPU 51 and a hardware data receiving module 52. The multi-core CPU 51 includes N CPU cores, where N is an integer greater than or equal to 2, and the CPU core 1 in the multi-core CPU is the designated CPU core 511. In the embodiment of the present invention, each CPU core includes a processing module 512 and a learning module 515. The processing module 512 includes a fast forwarding module 5121 and a normal forwarding module 5122; the designated CPU core 511 also includes a sub-core module 513 and a decision module 514.

The hardware data receiving module 52 is used to find the CPU core corresponding to 5 TUPLE of the to-be-processed data packet from the CPU core information look-up table as the target CPU core after receiving the to-be-processed data packet, and based on the target CPU core in the to-be-processed The tag information is inserted into the field of the data packet, and the to-be-processed data packet with the tag information inserted is sent to the sub-core module 513 of the designated CPU core 511. Among them, the tag information includes the target CPU core. The CPU core information lookup table includes 5 TUPLE and CPU core mapping relationships. If there is no 5TUPLE of the data packet to be processed in the CPU core information look-up table, the hardware data receiving module 52 directly sends the data packet to be processed to the sub-core module 513.

The sub-core module 513 is configured to, after receiving the to-be-processed data packet sent by the hardware data receiving module 52, determine whether the to-be-processed data packet has tag information and whether there is a target CPU core in the tag information, and if the to-be-processed data packet has tag information , And the tag information includes the target CPU core. In order to improve the forwarding speed, the sub-core module 513 can directly send the to-be-processed data packet to the fast forwarding module 5121 in the target CPU core; if the tag information does not exist, or the tag information does not If the target CPU core exists, the to-be-divided core module 513 sends the to-be-processed data packet to the decision module 514.

After receiving the data packet to be processed, the decision module 514 searches the CPU core information look-up table for the CPU core corresponding to 5 TUPLE of the data packet to be processed as the target CPU core. If there is no data packet to be processed in the CPU core information look-up table 5 TUPLE, the decision module 514 selects a CPU core from all the CPU cores included in the multi-core CPU 51 as the target CPU core of the data packet to be processed according to the preset algorithm, and sends it to the normal forwarding module 5122 of the target CPU core. Among them, the preset algorithm may be at least one of a round robin method, a hash method, and a least idle method.

The fast forwarding module 5121 is configured to fast forward the to-be-processed data packet based on the fast-forwarding table after receiving the to-be-processed data packet sent by the sub-core module 513. The specific process can be referred to the foregoing record and will not be repeated here.

The normal forwarding module 5122 is configured to perform normal forwarding processing on the to-be-processed data packet sent by the decision module 514.

The learning module 515 is used to obtain the 5 TUPLE and corresponding CPU core information of the data packet to be processed in the ordinary forwarding module 5122 from the ordinary forwarding module 5122 in the CPU core where it is located, and send it to the hardware data receiving module 52. After receiving 5 TUPLE and corresponding CPU core information, the hardware data receiving module 52 adds it to the CPU core information look-up table.

The data packet processing device provided by the embodiment of the present invention determines the target CPU core from all the CPU cores included in the multi-core CPU for the data packet to be processed through the hardware data receiving module, adds tag information based on the target CPU core, and adds the tag information to be processed The data packet is sent to the designated CPU core, so that the designated CPU core can directly send the to-be-processed data packet to the fast forwarding module of the target CPU core for fast forwarding according to the label information, so that the forwarding module of the device can be executed in parallel on multiple cores, which improves Data processing performance of communication equipment.

Example five

This embodiment also provides a communication device. As shown in FIG. 8, it includes a processor 801, a memory 802, and a communication bus 803. The processor 801 includes at least one multi-core CPU, and the multi-core CPU includes at least two CPU cores, wherein:

The communication bus 803 is used to implement connection and communication between the processor 801 and the memory 802;

The processor 801 is configured to execute one or more computer programs stored in the memory 802 to implement at least one step in the data packet processing method in the first embodiment and the second embodiment.

This embodiment also provides a storage medium that includes volatile or non-volatile memory implemented in any method or technology for storing information (such as computer-readable instructions, data structures, computer program modules, or other data). Volatile, removable or non-removable media. Computer-readable storage media include but are not limited to RAM (Random Access Memory), ROM (Read-Only Memory, read-only memory), EEPROM (Electrically Erasable Programmable Read-Only Memory, charged erasable programmable read-only memory) Storage), flash memory or other storage technologies, CD-ROM (Compact Disc Read-Only Memory), digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices Or any other medium that can be used to store desired information and can be accessed by a computer.

The storage medium in this embodiment can be used to store one or more computer programs, and the stored one or more computer programs can be executed by a processor to implement the data packet processing methods in the first embodiment and the second embodiment. At least one step.

The beneficial effects of the present invention are:

The data packet processing method, device, communication device and storage medium provided by the embodiments of the present invention determine the target CPU core from all the CPU cores included in the multi-core CPU by receiving the to-be-processed data packet and determine the target CPU core for the to-be-processed data packet, based on the target CPU core being Add label information to the data packet to be processed, where the label information includes the target CPU core, and send the data packet to be processed after adding the label information to the designated CPU core, and the designated CPU core sends the data packet to be processed based on the label information of the data packet to be processed Send to the target CPU core for processing. In some implementations, the target CPU core is selected from all the CPU cores of the multi-core CPU to process the data packets to be processed, so that each CPU core of the multi-core CPU can be fully utilized and the communication equipment's performance is improved. Data processing performance.

It can be seen that those skilled in the art should understand that all or some of the steps, functional modules/units in the system, and devices in the methods disclosed above can be implemented as software (which can be implemented by computer program code executable by a computing device). ), firmware, hardware and their appropriate combination. In the hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may consist of several physical components. The components are executed cooperatively. Some physical components or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit .

In addition, as is well known to those of ordinary skill in the art, communication media usually contain computer-readable instructions, data structures, computer program modules, or other data in a modulated data signal such as carrier waves or other transmission mechanisms, and may include any information delivery medium. Therefore, the present invention is not limited to any specific combination of hardware and software.

The above content is a further detailed description of the embodiments of the present invention in combination with specific implementations, and it cannot be considered that the specific implementations of the present invention are limited to these descriptions. For those of ordinary skill in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as belonging to the protection scope of the present invention.

Claims

A data packet processing method is applied to a communication device including a multi-core CPU central processing unit, the multi-core CPU including at least two CPU cores, and the method includes:

Receiving a data packet to be processed and determining a target CPU core for the data packet to be processed from all CPU cores included in the multi-core CPU;

Adding tag information to the data packet to be processed based on the target CPU core, where the tag information includes the target CPU core;

Sending the to-be-processed data packet with tag information added to the designated CPU core;

The designated CPU core sends the to-be-processed data packet to the target CPU core for processing based on the label information of the to-be-processed data packet.
8. The data packet processing method of claim 1, wherein the target CPU core processing the to-be-processed data packet comprises:

The target CPU core sends the to-be-processed data packet to the corresponding external device;

or,

The target CPU core sends the to-be-processed data packet to a corresponding local data packet processing process for processing.
8. The data packet processing method of claim 1, wherein the target CPU core processing the to-be-processed data packet comprises:

The target CPU core quickly forwards the to-be-processed data packet based on a fast forwarding table.
3. The data packet processing method according to any one of claims 1 to 3, wherein the determining the target CPU core for the data packet to be processed from all the CPU cores included in the multi-core CPU comprises:

Based on a preset algorithm, a CPU core is selected from all the CPU cores included in the multi-core CPU as the target CPU core.
3. The data packet processing method according to any one of claims 1 to 3, wherein the determining the target CPU core for the data packet to be processed from all the CPU cores included in the multi-core CPU comprises:

The CPU core corresponding to the 5-TUPLE quintuple of the data packet to be processed is searched from the CPU core information look-up table as the target CPU core, and the CPU core information look-up table includes the mapping relationship between the 5 TUPLE and the CPU core.
The data packet processing method according to claim 5, wherein, when the data packet to be processed received by the designated CPU core does not have a corresponding target CPU core, the method further comprises

The designated CPU core selects one CPU core from all the CPU cores included in the multi-core CPU according to a preset algorithm as the target CPU core of the data packet to be processed;

The designated CPU core sends the to-be-processed data packet to the target CPU core for processing.
8. The data packet processing method according to claim 6, wherein the preset algorithm is at least one of the following algorithms: round robin method, hash method, and least idle method.
The data packet processing method according to claim 6, wherein the designated CPU core selects a CPU core from all the CPU cores included in the multi-core CPU as the target CPU core of the data packet to be processed according to a preset algorithm ,Also includes:

The CPU core information look-up table is updated based on the 5 TUPLE of the data packet to be selected and the target CPU core.
A data packet processing device, the data packet processing device includes a multi-core CPU and a hardware data receiving module, and one of the CPU cores in the multi-core CPU is a designated CPU core;

The hardware data receiving module is configured to receive a data packet to be processed and determine a target CPU core for the data packet to be processed from all the CPU cores included in the multi-core CPU, based on the target CPU core being the data to be processed Adding tag information to the package, sending the data packet to be processed with tag information added to the designated CPU core, and the tag information includes the target CPU core;

The designated CPU core includes a sub-core module, configured to send the to-be-processed data packet to the target CPU core based on the label information of the to-be-processed data packet;

The target CPU core includes a processing module for processing the to-be-processed data packet.
A communication device includes a processor, a memory, and a communication bus. The processor includes at least one multi-core CPU;

The communication bus is used to implement connection and communication between the processor and the memory;

The processor is configured to execute one or more computer programs stored in the memory to implement the steps of the data packet processing method according to any one of claims 1 to 8.
A storage medium storing one or more computer programs, wherein the one or more computer programs can be executed by one or more processors to realize the data according to any one of claims 1 to 8 The steps of the packet processing method.