WO2021073126A1 - 片内参考电流产生电路 - Google Patents

片内参考电流产生电路 Download PDF

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Publication number
WO2021073126A1
WO2021073126A1 PCT/CN2020/095337 CN2020095337W WO2021073126A1 WO 2021073126 A1 WO2021073126 A1 WO 2021073126A1 CN 2020095337 W CN2020095337 W CN 2020095337W WO 2021073126 A1 WO2021073126 A1 WO 2021073126A1
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pull
reference current
unit
transistor
generating circuit
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PCT/CN2020/095337
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English (en)
French (fr)
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季汝敏
应战
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长鑫存储技术有限公司
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Priority to EP20877533.8A priority Critical patent/EP3893079B1/en
Priority to US17/190,405 priority patent/US20210208618A1/en
Publication of WO2021073126A1 publication Critical patent/WO2021073126A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0005—Modifications of input or output impedance
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/561—Voltage to current converters
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load

Definitions

  • the invention relates to the field of integrated circuits, in particular to an on-chip reference current generating circuit.
  • the reference current is a current that is not sensitive to changes in factors such as temperature, voltage, and process, and is widely used in integrated circuit design.
  • an oscillator circuit formed by charging and discharging a capacitor with a reference current can be applied to a charge pump circuit in a DRAM.
  • Figure 1 is an oscillator circuit diagram.
  • the capacitors C 1 and C 2 are charged by the reference currents I ch1 and I ch2 .
  • the comparators comp 1 and comp 2 are flipped to set or reset the DFF; the output signal S 1 or S 2 is flipped and the corresponding capacitor is discharged, cyclically, to generate a clock signal.
  • factors such as process deviation and temperature change will cause the reference current to change, and the change of the reference current will affect the charging time of the capacitor, and then affect the frequency of the clock signal, resulting in insufficient accuracy of the oscillator frequency.
  • Figure 2 is a commonly used reference current generation circuit inside a chip. Please refer to Figure 2.
  • the voltage on the resistor R0 is also Vref, so that the current flowing through the resistor is Vref/R0.
  • Vref can be obtained by dividing the internal bandgap voltage, and Vref is usually adjusted (Trimming) to obtain a high-precision reference voltage Vref. The Vref thus obtained is not sensitive to changes in process, voltage, and temperature.
  • R0 is an on-chip resistor, which is usually realized by a polycrystalline resistor.
  • R0 is realized by an off-chip resistor, it will take up extra pin resources, which is not conducive to the miniaturization of components, and it will inevitably consume a lot of space, increase production costs, and is not economical.
  • the technical problem to be solved by the present invention is to provide an on-chip reference current generating circuit which can output a stable reference current.
  • the present invention provides an on-chip reference current generating circuit for supplying at least one reference current to at least one load.
  • the on-chip reference current generating circuit includes: a transistor; an operational amplifier unit, the positive input terminal of which Input a reference voltage, the negative input terminal is coupled to the source of the transistor, and the output terminal is coupled to the gate of the transistor; the first pull-down resistor unit is coupled between the source of the transistor and the ground, so The first pull-down resistance unit is a resistance unit calibrated by a ZQ calibration circuit; a current mirror unit, coupled between the drain of the transistor and the power supply voltage, is used to output the generated current for use by the load.
  • the ZQ calibration circuit has a second pull-down resistance unit and a pull-down calibration code for calibrating the second pull-down resistance unit, and the first pull-down resistance unit duplicates the second pull-down resistance unit and uses the pull-down resistance unit.
  • the calibration code is used as the pull-down calibration code of the first pull-down resistor unit.
  • first pull-down resistance unit and the second pull-down resistance unit are arranged adjacent to each other.
  • the reference voltage is much less than 2 (V GS -V TH ).
  • the reference voltage is 1/100-1/10 of 2 (V GS -V TH ).
  • the on-chip reference current generating circuit further includes a bypass resistance unit connected in parallel with the first pull-down resistance unit, and before the first pull-down resistance unit is not calibrated by the ZQ calibration circuit, the bypass resistance unit The circuit resistance unit is turned on, and after the first pull-down resistance unit is calibrated by the ZQ calibration circuit, the bypass resistance unit is turned off.
  • the shunt resistance unit includes at least one transistor.
  • the source of the transistor in the shunt resistance unit is grounded.
  • the first pull-down resistance unit includes a plurality of transistors coupled in parallel.
  • the on-chip reference current generating circuit further includes a bandgap voltage generator, which is coupled to the positive input terminal of the operational amplifier unit, and is used for generating the reference voltage.
  • the transistor is an N-type transistor.
  • the advantage of the present invention is that the first pull-down resistance unit of the on-chip reference current generation circuit is calibrated by the ZQ calibration circuit, and its equivalent resistance is not sensitive to changes in process, voltage and temperature, and the output of the current mirror unit The reference current will not change greatly with changes in process, voltage and temperature, and the on-chip reference current generating circuit of the present invention can provide a stable reference current.
  • Figure 1 is a circuit diagram of an existing oscillator
  • Figure 2 is a commonly used reference current generating circuit inside the existing chip
  • FIG. 3 is a circuit diagram of the first specific implementation of the on-chip reference current generating circuit of the present invention.
  • FIG. 4 is a circuit diagram of a second specific embodiment of the on-chip reference current generating circuit of the present invention.
  • the on-chip reference current generating circuit of the present invention is arranged in the chip 1 to supply at least one reference current to at least one load.
  • Fig. 3 is a circuit diagram of the first specific embodiment of the on-chip reference current generating circuit of the present invention. Please refer to FIG. 3, the on-chip reference current generating circuit includes a transistor M1, an operational amplifier unit opamp, a current mirror unit 12 and a first pull-down resistor unit 10. Wherein, in this specific embodiment, the transistor M1 is an N-type transistor.
  • the positive input terminal of the operational amplifier unit opamp inputs a reference voltage Vref1, the negative input terminal is coupled to the source of the transistor M1, and the output terminal is coupled to the gate of the transistor M1.
  • the reference voltage is generated by the bandgap voltage generator 102.
  • the bandgap voltage generator 13 is coupled to the positive input terminal of the operational amplifier unit opamp, and is used for transmitting the generated reference voltage to the positive input terminal of the operational amplifier unit opamp.
  • the current mirror unit 12 is coupled between the drain of the transistor M1 and the power supply voltage, and is used for outputting the current generated by the on-chip reference current generating circuit for the load.
  • the current mirror unit 12 is composed of a P-type transistor M12 and a P-type transistor M13.
  • the P-type transistor M12 has a source connected to the power supply potential, and a gate and drain connected to the drain of the transistor M1;
  • the P-type transistor M13 has a source connected to the power supply potential, and a source connected to the P-type transistor M12
  • the gate and the drain connected to the gate, and the drain of the P-type transistor M13 outputs a reference current.
  • the current mirror unit 12 can replicate or multiply the current signal. Specifically, in this specific embodiment, the current mirror unit 12 replicates the current flowing through the first pull-down resistor unit 10, and combines It is output as a reference current.
  • the first pull-down resistance unit 10 is coupled between the source of the transistor M1 and the ground, and its equivalent resistance value is R0.
  • the on-chip reference current generating circuit is clamped by the operational amplifier unit 11 to make the voltage on the first pull-down resistor unit 10 the same as the reference voltage Vref1, and its magnitude is also Vref1, then the first pull-down resistor
  • the current on the resistance unit 10 is Vref1/R0; the current mirror unit 12 composed of a P-type transistor M12 and a P-type transistor M13 outputs the generated current as a reference current for other modules.
  • the first pull-down resistor unit 10 is not a polycrystalline resistor, but is a resistor unit calibrated by the ZQ calibration circuit 100.
  • the first pull-down resistance unit 10 includes a plurality of transistors coupled in parallel.
  • the pull-up unit and the pull-down unit are calibrated through the ZQ calibration circuit, so that the equivalent resistance value of the pull-up unit and the pull-down unit meets the accuracy requirements. That is, the equivalent resistance values of the calibrated pull-up unit and pull-down unit are not sensitive to changes in process, voltage, and temperature.
  • the ZQ calibration circuit 100 includes a first pull-up resistor unit 110, a second pull-up resistor unit 120, a second pull-down resistor unit 130, a reference voltage generator 102, a first comparator 103, and a second Two comparators 104 and a P code counter 105 and an N code counter 106.
  • ZQ calibration includes pull-up calibration and pull-down calibration.
  • the specific method of the pull-up calibration is as follows: the power supply voltage VDDQ is divided by the first pull-up resistor unit 110 and the reference resistor 101, so as to provide a voltage to the node ZQ.
  • the reference resistor 101 connected to the pin coupled to the node ZQ generally has a resistance of 240 ⁇ .
  • the first comparator 103 compares the voltage at the node ZQ with the reference voltage Vref2 output from the bandgap voltage generator 102, thereby generating an up/down signal UP/DN.
  • the reference voltage Vre2f is generally set to half of the supply voltage, that is, VDDQ/2.
  • the P code counter 105 receives the uplink/downlink signal UP/DN, thereby generating the binary code PCODE ⁇ 0:N> as the pull-up calibration code.
  • the binary code PCODE ⁇ 0:N> turns on/off the MOS transistors coupled in parallel in the first pull-up resistance unit 110, thereby calibrating the resistance of the first pull-up resistance unit 110.
  • the calibrated resistance of the first pull-up resistance unit 110 has an influence on the voltage at the node ZQ. Repeat the above operation. That is, the pull-up calibration is performed in the first pull-up resistance unit 110 so that the resistance of the first pull-up resistance unit 110 becomes equal to the resistance of the reference resistor 101.
  • the binary code PCODE ⁇ 0:N> generated during the pull-up calibration is also input to the second pull-up resistance unit 120 and its resistance is determined.
  • the binary code NCODE ⁇ 0:N> generated by the second comparator 104 and the N code counter 106 is used as the pull-down calibration code.
  • the pull-down calibration code By applying the pull-down calibration code, the voltage at the node NODE becomes equal to the reference voltage Vref2; perform pull-down calibration, The resistance of the second pull-down resistance unit 130 becomes equal to the resistance of the second pull-up resistance unit 120.
  • the binary codes PCODE ⁇ 0:N> and NCODE ⁇ 0:N> generated by the ZQ calibration to the input or output circuit to calibrate the resistors of the resistance unit.
  • the binary codes PCODE ⁇ 0:N> and NCODE ⁇ 0:N> determine the resistance of the pull-up and pull-down resistors connected to the DQ pad.
  • the pull-up and pull-down resistors have a similar layout to the above-mentioned pull-up and pull-down resistor units.
  • the ZQ calibration also uses the ZQ calibration controller 107 and the time counter 108 to control the ZQ calibration.
  • the equivalent resistance values of the first pull-up resistance unit 110 and the second pull-down resistance unit 130 meet the accuracy requirements, that is, the first pull-up resistance unit 110 and the second pull-down resistance unit 130 after being calibrated
  • the equivalent resistance value is not sensitive to changes in process, voltage and temperature.
  • the on-chip reference current generation circuit of the present invention multiplexes the pull-down calibration code NCODE ⁇ 0:N> of the ZQ calibration circuit, and duplicates the second pull-down resistance unit 130 of the ZQ calibration circuit as the chip of the present invention.
  • the first pull-down resistance unit 10 of the internal reference current generating circuit is a resistance unit calibrated by a ZQ calibration circuit, and its equivalent resistance value is not sensitive to changes in process, voltage, and temperature.
  • the first pull-down resistor unit 10 and the second pull-down resistor unit 130 are strictly matched in layout and layout, and the corresponding MOS transistors of the two adopt the same size and arrangement direction.
  • the control of both The signals are also the same, all are pull-down calibration codes NCODE ⁇ 0:N>.
  • the first pull-down resistance unit 10 and the second pull-down resistance unit 130 are arranged adjacent to each other to avoid the influence of other factors that cause the ZQ calibration circuit to interfere with the first pull-down resistance unit 10 and the The calibration of the second pull-down resistor unit 130 is different, thereby reducing the sensitivity of the equivalent resistance of the first pull-down resistor unit 10 to changes in process, voltage, and temperature.
  • the voltage value of the reference voltage Vref1 of the on-chip reference current generating circuit of the present invention cannot be too large.
  • the voltage value of the reference voltage Vref1 of the on-chip reference current generating circuit of the present invention is less than 2 (V GS -V TH ), so that the MOS tube in the first pull-down resistor unit 10 is in the triode region, Among them, V GS is the gate-source voltage of the MOS tube in the first pull-down resistance unit 10, and V TH is the breakdown voltage of the MOS tube in the first pull-down resistance unit 10.
  • the voltage value of the reference voltage Vref1 is much smaller than 2 (V GS -V TH ), for example, the voltage value of the reference voltage Vref1 is 1/100 to 1/10 of 2 (V GS -V TH ), so that The MOS transistor in the first pull-down resistance unit 10 is in a deep triode region, and the first pull-down resistance unit 10 is closer to a real resistance.
  • the on-chip reference current generation circuit of the present invention uses the first pull-down resistance unit 10 calibrated by the ZQ calibration circuit to replace the traditional on-chip resistance.
  • the equivalent resistance of the first pull-down resistance unit 10 after calibration by the ZQ calibration circuit is The value will not change significantly with changes in temperature or process tolerances, and the reference current output by the current mirror unit 12 will not change significantly with changes in temperature or process tolerances.
  • the reference current generating circuit can provide a stable reference current.
  • Fig. 4 is a circuit diagram of the second embodiment of the on-chip reference current generating circuit of the present invention. Please refer to FIG. 4, in order to avoid that the first pull-down resistor unit 10 is fully turned off and cannot generate current when the ZQ calibration circuit is initialized, thereby affecting the generation of the reference current, the on-chip reference current generation circuit further includes The resistance unit 10 is connected in parallel to the shunt resistance unit 13.
  • the shunt resistor unit 13 Before the first pull-down resistor unit 10 is not calibrated by the ZQ calibration circuit 100, the shunt resistor unit 13 is turned on to ensure that there is still a current path; After the calibration circuit 100 is calibrated, the shunt resistance unit 13 is turned off, which does not affect the normal operation of the reference current generating circuit.
  • the shunt resistance unit 13 includes at least one transistor.
  • the transistor is an NMOS transistor.
  • the source of the transistor is grounded, and the gate is input with a control signal Ctrl.
  • the control signal Ctrl can be generated by the controller of the integrated circuit.

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Abstract

一种片内参考电流产生电路，用以供应至少一参考电流给至少一负载，片内参考电流产生电路包括：晶体管（M1）；运算放大单元（opamp），其正输入端输入一参考电压（Vref1），负输入端耦接晶体管（M1）的源极，输出端耦接晶体管（M1）的栅极；第一下拉电阻单元（10），耦接于晶体管（M1）的源极与接地之间，第一下拉电阻单元（10）为经过ZQ校准电路（100）校准的电阻单元；电流镜单元（12），耦接于晶体管（M1）的漏极与电源电压之间，用于将产生的电流输出供负载使用，片内参考电流产生电路能够提供稳定的参考电流。

Description

片内参考电流产生电路
相关申请引用说明
本申请要求于2019年10月16日递交的中国专利申请号201910981700.6，申请名为“片内参考电流产生电路”的优先权，其全部内容以引用的形式附录于此。
技术领域
本发明涉及集成电路领域，尤其涉及一种片内参考电流产生电路。
背景技术
参考电流是对温度、电压、工艺等因素变化不敏感的电流，其被广泛应用在集成电路设计中。例如，通过参考电流对电容充放电形成的振荡器电路可以应用在DRAM中的电荷泵电路。请参阅图1，其为振荡器电路图，通过参考电流I ch1和I ch2对电容C 1和C 2进行充电，当电容C 1和C 2上的电压被充到与参考电压V bg相同的时候，比较器comp 1和comp 2翻转，对DFF进行置位或者复位动作；输出信号S 1或S 2发生翻转并对相应的电容进行放电，循环往复，产生时钟信号。其中，工艺偏差、温度变化等因素会导致参考电流变化，参考电流的变化会影响电容的充电时间，进而影响该时钟信号的频率，导致振荡器频率的精度不够高。
图2是一个芯片内部常用的参考电流产生电路。请参阅图2，通过运放opamp的钳位使得电阻R0上的电压也为Vref，这样流过电阻上的电流为Vref/R0。通过晶体管M12和晶体管M13组成的电流镜即可将所产生的电流输出供其它模块使用。Vref可以由内部带隙电压分压得到，并且通常会对Vref进行调整(Trimming)以获得精度较高的参考电压Vref，由此得到的Vref对工艺、电压和温度的变化不敏感。而R0是片上电阻，通常由多晶电阻实现， 其阻值会随温度或工艺容差的变化而产生较大的变化，这导致最终输出的电流(即参考电流)也会随温度或者工艺容差的变化而发生较大的变化。若是将R0通过片外电阻来实现，其会占用额外的管脚资源，不利于元器件的小型化，且必定耗费大量空间，增加生产成本，不符合经济效益。
因此，如何使片内参考电流产生电路输出稳定的参考电流成为目前亟需解决的技术。
发明内容
本发明所要解决的技术问题是，提供一种片内参考电流产生电路，其能够输出稳定的参考电流。
为了解决上述问题，本发明提供了一种片内参考电流产生电路，用以供应至少一参考电流给至少一负载，所述片内参考电流产生电路包括：晶体管；运算放大单元，其正输入端输入一参考电压，负输入端耦接所述晶体管的源极，输出端耦接所述晶体管的栅极；第一下拉电阻单元，耦接于所述晶体管的源极与接地之间，所述第一下拉电阻单元为经过ZQ校准电路校准的电阻单元；电流镜单元，耦接于所述晶体管的漏极与电源电压之间，用于将产生的电流输出供所述负载使用。
进一步，所述ZQ校准电路具有一第二下拉电阻单元及校准所述第二下拉电阻单元的下拉校准码，所述第一下拉电阻单元复制所述第二下拉电阻单元，并使用所述下拉校准码作为所述第一下拉电阻单元的下拉校准码。
进一步，所述第一下拉电阻单元与所述第二下拉电阻单元相邻设置。
进一步，所述参考电压远小于2(V GS-V TH)。
进一步，所述参考电压为2(V GS-V TH)的1/100～1/10。
进一步，所述片内参考电流产生电路还包括与所述第一下拉电阻单元并联 的旁路电阻单元，在所述第一下拉电阻单元未被所述ZQ校准电路校准之前，所述旁路电阻单元开启，在所述第一下拉电阻单元被所述ZQ校准电路校准后，所述旁路电阻单元关断。
进一步，所述旁路电阻单元包括至少一晶体管。
进一步，所述旁路电阻单元中的所述晶体管的源极接地。
进一步，所述第一下拉电阻单元包括多个并行耦合的晶体管。
进一步，所述片内参考电流产生电路还包括带隙电压产生器，所述带隙电压产生器耦接所述运算放大单元的正输入端，用于产生所述参考电压。
进一步，所述晶体管为N型晶体管。
本发明的优点在于，所述片内参考电流产生电路的第一下拉电阻单元经过ZQ校准电路校准，其等效阻值随工艺、电压以及温度的变化不敏感，则经电流镜单元输出的参考电流也不会随工艺、电压以及温度的变化而发生较大的变化，本发明片内参考电流产生电路能够提供稳定的参考电流。
附图说明
图1是现有的振荡器电路图；
图2是现有的芯片内部常用的参考电流产生电路；
图3是本发明片内参考电流产生电路的第一具体实施方式的电路图；
图4是本发明片内参考电流产生电路的第二具体实施方式的电路图。
具体实施方式
下面结合附图对本发明提供的片内参考电流产生电路的具体实施方式做详细说明。
本发明片内参考电流产生电路设置在芯片1内，用以供应至少一参考电流给至少一负载。图3是本发明片内参考电流产生电路的第一具体实施方式的电 路图。请参阅图3，所述片内参考电流产生电路包括晶体管M1、运算放大单元opamp、电流镜单元12及第一下拉电阻单元10。其中，在本具体实施方式中，所述晶体管M1为N型晶体管。
所述运算放大单元opamp的正输入端输入一参考电压Vref1，负输入端耦接所述晶体管M1的源极，输出端耦接所述晶体管M1的栅极。其中，在本具体实施方式中，所述参考电压由带隙电压产生器102产生。所述带隙电压产生器13耦接所述运算放大单元opamp的正输入端，用于将产生的参考电压传输至所述运算放大单元opamp的正输入端。
电流镜单元12耦接于所述晶体管M1的漏极与电源电压之间，用于将所述片内参考电流产生电路产生的电流输出供所述负载使用。在本具体实施方式中，所述电流镜单元12由P型晶体管M12及P型晶体管M13组成。其中，P型晶体管M12具有与电源电位连接的源极、以及与晶体管M1的漏极连接的栅极和漏极；P型晶体管M13具有与电源电位连接的源极、以及与P型晶体管M12的栅极以及漏极连接的栅极，P型晶体管M13的漏极输出参考电流。在本发明其他具体实施方式中，也可采用其他形式的电路作为电流镜单元。所述电流镜单元12能够实现电流信号的复制或倍乘，具体地说，在本具体实施方式中，所述电流镜单元12复制流经所述第一下拉电阻单元10的电流，并将其作为参考电流输出。
所述第一下拉电阻单元10耦接于所述晶体管M1的源极与接地之间，其等效阻值为R0。所述片内参考电流产生电路通过运算放大单元11的钳位使得所述第一下拉电阻单元10上的电压与参考电压Vref1相同，其大小也为Vref1，则流过所述第一下拉电阻单元10上的电流为Vref1/R0；通过P型晶体管M12和P型晶体管M13组成的电流镜单元12将所产生的电流作为参考电流输出供 其它模块使用。
如背景技术所述，若所述第一下拉电阻单元10为一电阻，则其阻值会随温度或工艺容差的变化而产生较大的变化，这导致最终输出的参考电流也会随温度或者工艺容差的变化而发生较大的变化。因此，为了克服上述技术问题，在本发明的具体实施方式中，所述第一下拉电阻单元10并不是一多晶电阻，其为经过ZQ校准电路100校准的电阻单元。例如，所述第一下拉电阻单元10包括多个并行耦合的晶体管。
在存储芯片中，例如DDR4中，通常会有ZQ校准(ZQ calibration)功能，通过ZQ校准电路对上拉单元和下拉单元进行校准，使得上拉单元和下拉单元的等效电阻值满足精度要求，即经过校准后的上拉单元和下拉单元的等效电阻值随工艺、电压以及温度的变化不敏感。
具体地说，请参阅图3，ZQ校准电路100包括第一上拉电阻单元110、第二上拉电阻单元120、第二下拉电阻单元130、参考电压发生器102、第一比较器103、第二比较器104以及P码计数器105和N码计数器106。ZQ校准包括上拉校准和下拉校准。
上拉校准的具体方法为：电源电压VDDQ被第一上拉电阻单元110和参考电阻器101划分，从而向节点ZQ提供电压。连接到耦合到节点ZQ的引脚的参考电阻器101一般具有240Q的电阻。第一比较器103比较节点ZQ处的电压与从带隙电压产生器102输出的参考电压Vref2，从而生成上行/下行信号(up/down signal)UP/DN。参考电压Vre2f一般被设置成供应电压的一半，即VDDQ/2。P码计数器105接收上行/下行信号UP/DN，从而生成二进制码PCODE<0:N>作为上拉校准码。该二进制码PCODE<0:N>导通/关断在第一上拉电阻单元110中并行耦合的MOS晶体管，从而校准第一上拉电阻单元110 的电阻。第一上拉电阻单元110的被校准的电阻对节点ZQ处的电压有影响。重复上述操作。也就是说，在第一上拉电阻单元110中进行上拉校准，使得第一上拉电阻单元110的电阻变得与参考电阻器101的电阻相等。在上拉校准期间生成的二进制码PCODE<0:N>还被输入到第二上拉电阻单元120并确定其电阻。
与上拉校准类似地进行下拉校准。由第二比较器104和N码计数器106生成的二进制码NCODE<0:N>作为下拉校准码，通过应用该下拉校准码在节点NODE处的电压变得与参考电压Vref2相等；进行下拉校准，使得第二下拉电阻单元130的电阻变得与第二上拉电阻单元120的电阻相等。
将由ZQ校准产生的二进制码PCODE<0:N>和NCODE<0:N>输入到输入或输出电路以校准电阻单元的各电阻器。在半导体存储器件的情况下，二进制码PCODE<0:N>和NCODE<0:N>确定连接到DQ衬垫的上拉和下拉电阻器的电阻。上拉和下拉电阻器具有与上述上拉和下拉电阻单元相似的布局。进一步，ZQ校准还采用ZQ校准控制器107和时间计数器108来控制ZQ校准。
经过ZQ校准电路100校准后，第一上拉电阻单元110和第二下拉电阻单元130的等效电阻值满足精度要求，即经过校准后的第一上拉电阻单元110和第二下拉电阻单元130的等效电阻值随工艺、电压以及温度的变化不敏感。
鉴于ZQ校准电路的上述优点，本发明片内参考电流产生电路复用ZQ校准电路的下拉校准码NCODE<0:N>，并复制所述ZQ校准电路的第二下拉电阻单元130作为本发明片内参考电流产生电路的第一下拉电阻单元10，则所述第一下拉电阻单元10为经过ZQ校准电路校准的电阻单元，其等效电阻值随工艺、电压以及温度的变化不敏感。在本具体实施方式中，第一下拉电阻单元10与所述第二下拉电阻单元130在版图布局布线上严格匹配，两者对应的MOS 管采用相同的尺寸和排布方向，两者的控制信号也相同，均为下拉校准码NCODE<0:N>。
优选地，在版图布局中，所述第一下拉电阻单元10与所述第二下拉电阻单元130相邻设置，避免其他因素影响而造成ZQ校准电路对第一下拉电阻单元10与所述第二下拉电阻单元130的校准不同，从而降低所述第一下拉电阻单元10的等效阻值随工艺、电压以及温度的变化的敏感性。
进一步，为了使所述第一下拉电阻单元10更接近真实电阻，本发明片内参考电流产生电路的所述参考电压Vref1的电压值不能太大。优选地，本发明片内参考电流产生电路的所述参考电压Vref1的电压值小于2(V GS-V TH)，使得第一下拉电阻单元10中的MOS管处于三极管区(triode region)，其中，V GS是第一下拉电阻单元10中的MOS管的栅源电压，V TH是第一下拉电阻单元10中的MOS管的击穿电压。更优选地，所述参考电压Vref1的电压值远小于2(V GS-V TH)，例如，参考电压Vref1的电压值为2(V GS-V TH)的1/100～1/10，使得第一下拉电阻单元10中的MOS管处于深三极管区(deep triode region)，所述第一下拉电阻单元10更接近真实的电阻。
本发明片内参考电流产生电路采用经ZQ校准电路校准的第一下拉电阻单元10代替传统的片内电阻，经所述ZQ校准电路校准后所述第一下拉电阻单元10的等效阻值不会随温度或工艺容差的变化而产生较大的变化，则经电流镜单元12输出的参考电流也不会随温度或者工艺容差的变化而发生较大的变化，本发明片内参考电流产生电路能够提供稳定的参考电流。
另外，发明人发现，在ZQ校准电路初始化时，第一下拉电阻单元10全关断无法产生电流，其会影响参考电流的产生。为了避免上述问题，本发明还提供了片内参考电流产生电路的一第二具体实施方式。图4是本发明片内参考 电流产生电路的第二具体实施方式的电路图。请参阅图4，为了避免在ZQ校准电路初始化时，第一下拉电阻单元10全关断无法产生电流，而影响参考电流产生，所述片内参考电流产生电路还包括与所述第一下拉电阻单元10并联的旁路电阻单元13。在所述第一下拉电阻单元10未被所述ZQ校准电路100校准之前，所述旁路电阻单元13开启，保证仍有电流通路；在所述第一下拉电阻单元10被所述ZQ校准电路100校准后，所述旁路电阻单元13关断，不影响参考电流产生电路正常工作。
其中，在本具体实施方式中，所述旁路电阻单元13包括至少一晶体管。在本具体实施方式中，所述晶体管为NMOS管。所述晶体管的源极接地，栅极被输入控制信号Ctrl。当第一下拉电阻单元10的晶体管没有开启的时候，控制信号Ctrl为高，晶体管导通，所述旁路电阻单元13接地，保证片内参考电流产生电路中仍有电流通路；在ZQ校准功能起作用之后将该旁路电阻关断，不影响正常的参考电流产生电路工作。其中，所述控制信号Ctrl可由集成电路的控制器产生。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (11)

  1. 一种片内参考电流产生电路，用以供应至少一参考电流给至少一负载，其特征在于，所述片内参考电流产生电路包括：
    晶体管；
    运算放大单元，其正输入端输入一参考电压，负输入端耦接所述晶体管的源极，输出端耦接所述晶体管的栅极；
    第一下拉电阻单元，耦接于所述晶体管的源极与接地之间，所述第一下拉电阻单元为经过ZQ校准电路校准的电阻单元；
    电流镜单元，耦接于所述晶体管的漏极与电源电压之间，用于将产生的电流输出供所述负载使用。
  2. 根据权利要求1所述的片内参考电流产生电路，其特征在于，所述ZQ校准电路具有一第二下拉电阻单元及校准所述第二下拉电阻单元的下拉校准码，所述第一下拉电阻单元复制所述第二下拉电阻单元，并使用所述下拉校准码作为所述第一下拉电阻单元的下拉校准码。
  3. 根据权利要求2所述的片内参考电流产生电路，其特征在于，所述第一下拉电阻单元与所述第二下拉电阻单元相邻设置。
  4. 根据权利要求1所述的片内参考电流产生电路，其特征在于，所述参考电压小于2(V GS-V TH)。
  5. 根据权利要求4所述的片内参考电流产生电路，其特征在于，所述参考电压为2(V GS-V TH)的1/100～1/10。
  6. 根据权利要求1所述的片内参考电流产生电路，其特征在于，所述片内参考电流产生电路还包括与所述第一下拉电阻单元并联的旁路电阻单元，在所述第一下拉电阻单元未被所述ZQ校准电路校准之前，所述旁路电阻单元开启，在所述第一下拉电阻单元被所述ZQ校准电路校准后，所述旁路 电阻单元关断。
  7. 根据权利要求6所述的片内参考电流产生电路，其特征在于，所述旁路电阻单元包括至少一晶体管。
  8. 根据权利要求7所述的片内参考电流产生电路，其特征在于，所述旁路电阻单元中的所述晶体管的源极接地。
  9. 根据权利要求1所述的片内参考电流产生电路，其特征在于，所述第一下拉电阻单元包括多个并行耦合的晶体管。
  10. 根据权利要求1所述的片内参考电流产生电路，其特征在于，所述片内参考电流产生电路还包括带隙电压产生器，所述带隙电压产生器耦接所述运算放大单元的正输入端，用于产生所述参考电压。
  11. 根据权利要求1所述的片内参考电流产生电路，其特征在于，所述晶体管为N型晶体管。
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