WO2021068672A1 - Igzo薄膜晶体管及其制造方法 - Google Patents

Igzo薄膜晶体管及其制造方法 Download PDF

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WO2021068672A1
WO2021068672A1 PCT/CN2020/111426 CN2020111426W WO2021068672A1 WO 2021068672 A1 WO2021068672 A1 WO 2021068672A1 CN 2020111426 W CN2020111426 W CN 2020111426W WO 2021068672 A1 WO2021068672 A1 WO 2021068672A1
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igzo
layer
substrate
spin
igzo layer
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PCT/CN2020/111426
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English (en)
French (fr)
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吴汪然
杨光安
林峰
孙贵鹏
王耀辉
孙伟锋
时龙兴
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东南大学
无锡华润上华科技有限公司
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Priority to US17/767,333 priority Critical patent/US20220367722A1/en
Publication of WO2021068672A1 publication Critical patent/WO2021068672A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
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    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02623—Liquid deposition
    • H01L21/02628—Liquid deposition using solutions
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials

Definitions

  • the invention relates to the field of semiconductor manufacturing, in particular to an IGZO thin film transistor and a manufacturing method thereof.
  • Flexible electronics is an emerging electronic technology that uses organic or inorganic material electronic devices on flexible substrates. It has the characteristics of flexibility and high-efficiency and low-cost manufacturing processes. It has a wide range of application prospects in the fields of information, energy, medical care, and national defense.
  • indium gallium zinc oxide (IGZO) thin film transistors have the advantages of high mobility and high switching current ratio.
  • High-mobility IGZO thin-film transistors are one of the key technologies for generating high-resolution displays, and they have been commercially applied.
  • a method for manufacturing an IGZO thin film transistor includes: obtaining a substrate; forming an IGZO layer on the substrate by a solution process; doping group V impurities on the surface of the IGZO layer by a spin doping process; A source is formed on one side and a drain is formed on the other side, and a gate dielectric layer is formed on the doped IGZO layer; and a gate is formed on the gate dielectric layer.
  • An IGZO thin film transistor includes: a substrate; an IGZO layer is provided on the substrate, the IGZO layer is formed by a solution process, the IGZO layer includes a channel region, and the surface of the channel region is spin-doped The doping process is doped with group V impurities; a source electrode is formed on one side of the IGZO layer; a drain electrode is formed on the other side of the IGZO layer; a gate dielectric layer is formed on the IGZO layer; and The gate is formed on the gate dielectric layer.
  • FIG. 1 is a schematic diagram of an IGZO thin film transistor in an embodiment
  • FIG. 2 is a flowchart of a manufacturing method of an IGZO thin film transistor in an embodiment
  • FIG. 3 is a flowchart of sub-steps of step S220 in an embodiment
  • FIG. 4 is a graph of drain current of IGZO thin film transistors according to an embodiment of the present application and a comparative example.
  • first element, component, region, layer or section discussed below may be represented as a second element, component, region, layer or section.
  • Spatial relationship terms such as “under”, “below”, “below”, “below”, “above”, “above”, etc., in It can be used here for the convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatial relationship terms are intended to include different orientations of devices in use and operation. For example, if the device in the figure is turned over, then elements or features described as “under” or “below” or “under” other elements will be oriented “on” the other elements or features. Therefore, the exemplary terms “below” and “below” can include both an orientation of above and below. The device can be otherwise oriented (rotated by 90 degrees or other orientations) and the spatial descriptors used here are interpreted accordingly.
  • the embodiments of the invention are described here with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention.
  • changes from the shown shape due to, for example, manufacturing technology and/or tolerances can be expected. Therefore, the embodiments of the present invention should not be limited to the specific shapes of the regions shown here, but include shape deviations due to, for example, manufacturing.
  • the implanted region shown as a rectangle usually has round or curved features and/or implant concentration gradients at its edges, rather than a binary change from an implanted region to a non-implanted region.
  • the buried region formed by the implantation may result in some implantation in the region between the buried region and the surface through which the implantation proceeds. Therefore, the regions shown in the figure are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the present invention.
  • P-type and N-type impurities in order to distinguish the doping concentration, simply P+ type represents the heavy doping concentration of P type, and P type represents middle P-type doping concentration, P-type represents P-type with light doping concentration, N+-type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents light-doping concentration N type.
  • controlling the composition ratio of the precursor solution to adjust the composition ratio of ions can increase the mobility and current density of the thin film.
  • increasing the ratio of In ions means reducing the ratio of Ga and Zn ions, which leads to an increase in oxygen vacancies and a decrease in the stability of the film structure.
  • To achieve a joint improvement between current density and structural stability has become a difficult problem in the IGZO thin film solution process.
  • the inventor believes that the carrier transport of ⁇ -IGZO thin films is mainly concentrated on the surface of the thin film, which requires extremely high properties on the surface of the thin film.
  • the common disadvantage of the above methods is that it is easy to cause damage to the surface of the thin film (such as interface defects and the generation of interface states). It severely restricted the improvement of ⁇ -IGZO film performance.
  • FIG. 1 is a schematic diagram of an IGZO thin film transistor in an embodiment
  • FIG. 2 is a flowchart of a manufacturing method of an IGZO thin film transistor in an embodiment. The method can be used to manufacture the IGZO thin film transistor shown in FIG. 1, and includes the following steps:
  • the substrate may be a rigid substrate (for example, glass) or a flexible substrate known in the art.
  • the base is a semiconductor substrate, such as a silicon substrate.
  • a silicon dioxide layer may be formed by oxidation on the silicon substrate, and then an IGZO layer may be formed on the silicon dioxide layer.
  • step S230 is doping on the entire IGZO surface. Doping of group V impurities can increase the channel carrier concentration, thereby increasing the operating current density of the device. For the embodiment in which only a part of the IGZO layer is used as the conductive channel, it is also possible to dope only the surface of the channel region of the IGZO layer if the process permits.
  • step S230 an ITO (tin-doped indium oxide) source and an ITO drain are respectively formed on both sides of the IGZO layer, and the ITO source and ITO drain extend from both sides of the IGZO layer to the substrate On (in this embodiment, it extends to the silicon dioxide layer of the substrate).
  • ITO indium oxide
  • ITO drain extend from both sides of the IGZO layer to the substrate On (in this embodiment, it extends to the silicon dioxide layer of the substrate).
  • other source and drain materials/structures known in the art can also be used as the source and drain.
  • step S240 may be performed first after step S220, and then step S230 is performed.
  • the gate dielectric layer covers the surface of the channel region of the IGZO layer and extends to the ITO source and ITO drain on both sides. In other embodiments, the gate dielectric layer may not extend to the source and drain. In one embodiment, the material of the gate dielectric layer is aluminum oxide (Al 2 O 3 ).
  • steps S250 and S260 are performed after step S240. In other embodiments, step S240 may also be performed after step S260.
  • the gate is an ITO gate; in other embodiments, other gate materials known in the art can also be used as the gate.
  • the IGZO layer is formed by a solution process, and the surface of the channel region of the IGZO layer is doped with group V impurities by a spin doping process. Therefore, the entire IGZO layer is prepared by a solution process, which is simple and easy to operate. Low cost, combined with roll-to-roll (roll-to-roll process) technology and printed electronics technology can achieve mass production. Doping of group V impurities on the surface of the channel region can increase the channel carrier concentration, thereby increasing the device operating current density (channel current density). And since the doping adopts a solution process, it will not cause damage to the surface of the IGZO layer compared to processes such as ion implantation.
  • this solution can significantly reduce the on-resistance of the ⁇ -IGZO thin film transistor and improve Thin film channel carrier mobility.
  • the IGZO layer formed by the above method is an ⁇ -IGZO (amorphous IGZO) film.
  • steps S240, S250, and S260 are also prepared by a solution process, so that the ⁇ -IGZO thin film transistor can be prepared by a full solution process, with simple operation and low cost, combined with roll-to-roll process and printed electronics technology Large-scale production can be achieved.
  • the dopant used in step S230 contains phosphorus element.
  • the dopant may also contain other group V elements, such as arsenic.
  • the step of drying the IGZO layer and an ultraviolet light annealing treatment is further included.
  • the substrate on which the IGZO layer is formed can be dried on a heating stage.
  • the temperature of the heating stage can be set to 200° C., and the doped impurities can be ion-activated by combining with UV-Light low temperature annealing technology.
  • step S220 includes:
  • indium (III) nitrate hydrate In(NO 3 ) 3 ⁇ xH 2 O
  • zinc nitrate hydrate Zn(NO 3 ) 3 ⁇ xH 2 O
  • gallium (III) nitrate The hydrate (Ga(NO 3 ) 3 ⁇ xH 2 O) was dissolved in 2-methoxyethanol (CH 3 OCH 2 CH 2 OH) solvent and stirred, and then the stirred liquid was filtered to obtain the IGZO precursor solution .
  • step S222 specifically includes indium (III) nitrate hydrate (In(NO 3 ) 3 ⁇ xH 2 O) and zinc nitrate hydrate (Zn(NO 3 ) 3 ⁇ xH 2 O) in an indoor environment.
  • gallium nitrate (III) hydrate (Ga(NO 3 ) 3 ⁇ xH 2 O) is dissolved in 2-methoxyethanol (CH 3 OCH 2 CH 2 OH) solvent at a molar ratio of 6:1:1, Use a blender to quickly stir for more than 12 hours, and filter through a 0.2 ⁇ m thick polytetrafluoroethylene (PTFE) filter to complete the preparation of the ⁇ -IGZO precursor solution.
  • PTFE polytetrafluoroethylene
  • the ⁇ -IGZO precursor solution is spin-coated on the substrate and rotated at a speed of 3500 RPM (revolutions per minute) for 60 seconds.
  • the substrate spin-coated with the IGZO precursor solution is annealed at a temperature of 300° C. for 30 minutes.
  • the present application also provides an IGZO thin film transistor, which can be prepared by the manufacturing method of any of the above embodiments.
  • the IGZO thin film transistor includes a substrate 10, an IGZO layer 20, a source electrode 22, a drain electrode 24, a gate dielectric layer 30 and a gate electrode 40.
  • the substrate 10 may be a rigid substrate (such as glass) or a flexible substrate known in the art.
  • the base is a semiconductor substrate, such as a silicon substrate.
  • the IGZO thin film transistor adopts a top-gate/top-contact structure. It should be pointed out that the size of each film layer in FIG. 1 is only an illustration, and does not represent its actual size.
  • the IGZO layer 20 is provided on the substrate.
  • the IGZO layer 20 includes a channel region a.
  • the IGZO layer 20 is formed through a solution process, and the surface of the channel region a is doped with group V impurities through a spin doping process.
  • the source electrode 22 is formed on one side of the IGZO layer 20 and the drain electrode 24 is formed on the other side of the IGZO layer 20.
  • the source 22 is an ITO source and the drain 24 is an ITO drain.
  • other source and drain materials/structures known in the art can also be used as the source and drain.
  • the gate dielectric layer 30 is formed on the IGZO layer 20.
  • the source electrode 22 and the drain electrode 24 both extend from the substrate surface on both sides of the IGZO layer 20 to the IGZO layer 20.
  • the gate dielectric layer 30 covers the channel region a and extends to the source electrode 22 and the drain electrode 24.
  • the gate 40 is formed on the gate dielectric layer 30.
  • the material of the gate dielectric layer 30 is aluminum oxide (Al 2 O 3 ).
  • the gate 40 is an ITO gate.
  • the IGZO layer 20 is an ⁇ -IGZO film.
  • the gate 40 is connected to a positive voltage to accumulate negative charges in the channel of the ⁇ -IGZO thin film, and the drain 24 is energized for carrier transport to form a current.
  • the IGZO thin film transistor further includes an insulating oxide layer 12 provided on the substrate 10.
  • the material of the insulating oxide layer 12 is silicon dioxide.
  • the thickness of the IGZO layer 20 is 100 nm
  • the thickness of the source 22 and the drain 24 is 40 nm (the thickness of the source/drain on the IGZO layer 20)
  • the thickness of the gate dielectric layer 30 The thickness of the gate electrode 40 is 200 nm
  • the thickness of the gate electrode 40 is 40 nm
  • the length of the channel region a is 100 ⁇ m.
  • the group V impurity doped in the channel region a is phosphorous ions.
  • the concentration of doped phosphorus ions may be 1e16 cm -3 .
  • FIG. 4 is a graph of drain current of IGZO thin film transistors according to an embodiment of the present application and a comparative example.
  • the comparative example is an IGZO thin film transistor without doping the channel region of the IGZO layer with group V impurities.
  • the abscissa is the drain voltage
  • the ordinate is the drain current.
  • Curve C1 is the drain current curve of the comparative example when the gate voltage is 2 volts
  • curve C2 is the drain current curve of the embodiment of the application when the gate voltage is 2 volts
  • curve D1 is the comparative example when the gate voltage is 4 volts
  • the drain current curve of the curve D2 is the drain current curve of the embodiment of the present application when the gate voltage is 4 volts. It can be seen that the output performance (drain current) of the ⁇ -IGZO thin film transistor is significantly improved after spin coating doping.

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Abstract

一种IGZO薄膜晶体管及其制造方法，所述方法包括：获取基底；通过溶液工艺在所述基底上形成IGZO层；通过自旋掺杂工艺在所述IGZO层表面掺杂V族杂质；在所述IGZO层的一侧形成源极、另一侧形成漏极，并在所述掺杂后的IGZO层上形成栅介电层；在所述栅介电层上形成栅极。

Description

IGZO薄膜晶体管及其制造方法 技术领域
本发明涉及半导体制造领域，特别是涉及一种IGZO薄膜晶体管及其制造方法。
背景技术
柔性电子是将有机或无机材料电子器件制作在柔性基板上的新兴电子技术，其具有柔性以及高效、低成本制造工艺等特点，在信息、能源、医疗、国防领域具有广泛的应用前景。柔性薄膜材料中，氧化铟镓锌氧化物(IGZO)薄膜晶体管具有高迁移率、高开关电流比等优点。高迁移率IGZO薄膜晶体管是生成高分辨率显示器关键技术之一，已经得到商业应用。
发明内容
基于此，有必要提供一种工作电流密度高的IGZO薄膜晶体管及其制造方法。
一种IGZO薄膜晶体管的制造方法，包括：获取基底；通过溶液工艺在所述基底上形成IGZO层；通过自旋掺杂工艺在所述IGZO层表面掺杂V族杂质；在所述IGZO层的一侧形成源极、另一侧形成漏极，并在所述掺杂后的IGZO层上形成栅介电层；及在所述栅介电层上形成栅极。
一种IGZO薄膜晶体管，包括：基底；IGZO层，设于所述基底上，所述IGZO层是通过溶液工艺形成，所述IGZO层包括沟道区，所述沟道区的表面通过自旋掺杂工艺掺杂有V族杂质；源极，形成于所述IGZO层的一侧；漏极，形成于所述IGZO层的另一侧；栅介电层，形成于所述IGZO层上；及栅极，形成于所述栅介电层上。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1是一实施例中IGZO薄膜晶体管的示意图；
图2是一实施例中IGZO薄膜晶体管的制造方法的流程图；
图3是一实施例中步骤S220的子步骤流程图；
图4是本申请实施例与对比例的IGZO薄膜晶体管漏极电流曲线图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第 一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本发明的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此，本发明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意 性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本发明的范围。
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇，例如对于P型和N型杂质，为区分掺杂浓度，简易的将P+型代表重掺杂浓度的P型，P型代表中掺杂浓度的P型，P-型代表轻掺杂浓度的P型，N+型代表重掺杂浓度的N型，N型代表中掺杂浓度的N型，N-型代表轻掺杂浓度的N型。
对于示例性的IGZO薄膜溶液制备工艺，控制前体溶液的组成比来调节离子的组成比例，如提高In离子的含量，可提高薄膜的迁移率、电流密度。但是提升In离子的比例意味着降低Ga及Zn离子的比例，从而导致氧空缺的增加及薄膜结构稳定性降低。在电流密度与结构稳定性之间达到共同提升成为IGZO薄膜溶液工艺的一个难题。
随着学术界与产业界的不断发展，提出了多种方法来提升α-IGZO薄膜的电流密度。主要包括：1)NH 3等离子体处理提高氢(H)离子浓度、氟(F)离子注入增加核外自由电子数等提高α-IGZO薄膜载流子浓度的方法；2)氮气(N 2)氛围下溅射生成α-IGZO薄膜，使用N离子填充氧空缺，且Ga-N键更稳定，从而提高α-IGZO薄膜结构稳定性。但上述方法存在工艺复杂、操作困难、成本较高、容易造成薄膜界面损伤等缺点。发明人认为α-IGZO薄膜载流子输运主要集中在薄膜表面，对薄膜表面的性质要求极高，而上述方法共同缺点就是易造成薄膜表面损伤(例如界面缺陷、界面态的产生)，这严重制约了α-IGZO薄膜性能的提升。
图1是一实施例中IGZO薄膜晶体管的示意图，图2是一实施例中IGZO薄膜晶体管的制造方法的流程图，该方法可以用于制造图1所示的IGZO薄膜晶体管，包括如下步骤：
S210，获取基底。
基底可以是本领域习知的刚性基底(例如玻璃)或柔性基底。在一个实施例中，基底为半导体衬底，例如硅衬底。
S220，通过溶液工艺在基底上形成IGZO层。
在一个实施例中，可以在硅衬底上氧化形成二氧化硅层，然后再于二氧化硅层上形成IGZO层。
S230，通过自旋掺杂工艺在IGZO层表面掺杂V族杂质。
自旋掺杂(Spin-on dopant，SOD)工艺也是一种溶液工艺，因此与离子注入、溅射、等离子体处理等高能量的工艺相比，其不会造成IGZO层表面损伤。在本实施例中，步骤S230是在整块IGZO表面进行掺杂。掺杂V族杂质能够提高沟道载流子浓度，从而提高器件工作电流密度。对于只有部分面积的IGZO层作为导电沟道的实施例，在使用的工艺允许的前提下也可以只对IGZO层的沟道区表面进行掺杂。
S240，在IGZO层的一侧形成源极、另一侧形成漏极。
在本实施例中，是在步骤S230后于IGZO层两侧分别形成ITO(锡掺杂氧化铟)源极、ITO漏极，ITO源极和ITO漏极从IGZO层两侧之上延伸至基底上(在本实施例中为延伸至基底的二氧化硅层上)。在其他实施例中，也可以采用本领域习知的其他源漏材质/结构作为源极和漏极。在一个实施例中，也可以在步骤S220后先执行步骤S240，再执行步骤S230。
S250，在IGZO层上形成栅介电层。
在本实施例中，栅介电层覆盖IGZO层的沟道区表面并延伸至两侧的ITO源极和ITO漏极上。在其他实施例中，栅介电层也可以不延伸至源极和漏极上。在一个实施例中，栅介电层的材质为氧化铝(Al 2O 3)。
S260，在栅介电层上形成栅极。
在本实施例中，步骤S250和S260是在步骤S240后进行。在其他实施例中，步骤S240也可以在步骤S260后进行。在一个实施例中，栅极为ITO栅极；在其他实施例中，也可以采用其他本领域习知的栅极材质作为栅极。
上述IGZO薄膜晶体管的制造方法，IGZO层通过溶液工艺形成，并通过自旋掺杂工艺在IGZO层的沟道区表面掺杂V族杂质，因此整个IGZO层的制备是采用溶液工艺，操作简单、成本低，结合roll-to-roll(卷对卷制程)工艺与印刷电子技术可实现大规模生产。在沟道区表面掺杂V族杂质能够提高 沟道载流子浓度，从而提高器件工作电流密度(沟道电流密度)。且由于掺杂采用溶液工艺，相比于离子注入等工艺不会造成IGZO层表面损伤。而由于α-IGZO薄膜载流子输运主要集中在薄膜表面，故与离子注入等工艺进行沟道区掺杂的方案相比，本方案能够显著降低α-IGZO薄膜晶体管的导通电阻，提升薄膜沟道载流子迁移率。
在一个实施例中，上述方法形成的IGZO层为α-IGZO(非晶IGZO)薄膜。
在一个实施例中，步骤S240、S250及S260也是采用溶液工艺进行制备，从而使得α-IGZO薄膜晶体管可实现全溶液工艺制备，操作简单、成本低，结合roll-to-roll工艺与印刷电子技术可实现大规模生产。
在一个实施例中，步骤S230使用的掺杂剂含有磷元素。在其他实施例中，掺杂剂也可以含有其他V族元素，比如砷元素。
在一个实施例中，步骤230之后还包括对IGZO层进行烘干处理及紫外光退火处理的步骤。具体地，可以将形成有IGZO层的基底在加热台上烘干，加热台的温度可以设置为200℃，并结合紫外光(UV-Light)低温退火技术对掺杂的杂质进行离子激活。
参见图3，在一个实施例中，步骤S220包括：
S222，制作IGZO前体溶液。
在一个实施例中，是将硝酸铟(III)水合物(In(NO 3) 3·xH 2O)、硝酸锌水合物(Zn(NO 3) 3·xH 2O)、硝酸镓(III)水合物(Ga(NO 3) 3·xH 2O)溶解于2-甲氧基乙醇(CH 3OCH 2CH 2OH)溶剂中并进行搅拌，再将搅拌后的液体进行过滤得到IGZO前体溶液。
在一个实施例中，步骤S222具体是在室内环境下将硝酸铟(III)水合物(In(NO 3) 3·xH 2O)、硝酸锌水合物(Zn(NO 3) 3·xH 2O)、硝酸镓(III)水合物(Ga(NO 3) 3·xH 2O)按照6:1:1的摩尔比溶解于2-甲氧基乙醇(CH 3OCH 2CH 2OH)溶剂中，使用搅拌机快速搅拌12小时以上，并通过0.2μm厚的聚四氟乙烯(PTFE)过滤器过滤以此完成α-IGZO前体溶液的制备。
S224，将IGZO前体溶液旋涂于基底上。
在一个实施例中，是将α-IGZO前体溶液旋涂于基底上并以3500RPM(转/分)的速度旋转60秒。
S226，进行热退火处理。
在一个实施例中，是将旋涂有IGZO前体溶液的基底在300℃温度条件下退火30分钟。
本申请还提供一种IGZO薄膜晶体管，该IGZO薄膜晶体管可以通过以上任一实施例的制造方法进行制备。如图1所示，IGZO薄膜晶体管包括基底10、IGZO层20、源极22、漏极24、栅介电层30以及栅极40。基底10可以是本领域习知的刚性基底(例如玻璃)或柔性基底。在一个实施例中，基底为半导体衬底，例如硅衬底。在图1所示的实施例中，IGZO薄膜晶体管采用顶栅共面(Top-gate/Top-contact)结构。需要指出的是，各膜层在图1中的尺寸只是一个示意，并不代表其实际尺寸。
IGZO层20设于基底之上。在图1所示的实施例中，IGZO层20包括沟道区a。IGZO层20是通过溶液工艺形成，沟道区a的表面通过自旋掺杂工艺掺杂有V族杂质。
源极22形成于IGZO层20的一侧、漏极24形成于IGZO层20的另一侧。在图1所示的实施例中，源极22为ITO源极、漏极24为ITO漏极。在其他实施例中，也可以采用本领域习知的其他源漏材质/结构作为源极和漏极。
栅介电层30形成于IGZO层20上。在图1所示的实施例中，源极22和漏极24均是从IGZO层20两侧的基底表面延伸至IGZO层20上。栅介电层30覆盖沟道区a，并延伸至源极22和漏极24上。栅极40形成于栅介电层30上。在一个实施例中，栅介电层30材质为氧化铝(Al 2O 3)。在一个实施例中，栅极40为ITO栅极。
在一个实施例中，IGZO层20为α-IGZO薄膜。在IGZO薄膜晶体管工作时，栅极40接正电压，在α-IGZO薄膜沟道中积累形成负电荷，漏极24加电进行载流子输运形成电流。
在图1所示的实施例中，IGZO薄膜晶体管还包括设于基底10上的绝缘 氧化层12。在一个实施例中，绝缘氧化层12的材质为二氧化硅。
在图1所示的实施例中，IGZO层20的厚度为100nm,源极22和漏极24的厚度为40纳米(IGZO层20上的源/漏极厚度)，栅介电层30的厚度为200纳米，栅极40的厚度为40纳米，沟道区a的长度为100微米。
在一个实施例中，沟道区a掺杂的V族杂质为磷离子。具体地，掺杂的磷离子浓度可以为1e16cm -3。
图4是本申请实施例与对比例的IGZO薄膜晶体管漏极电流曲线图，其中对比例为未对IGZO层的沟道区掺杂V族杂质的IGZO薄膜晶体管。图4中横坐标为漏极电压、纵坐标为漏极电流。曲线C1为栅极电压为2伏时对比例的漏极电流曲线，曲线C2为栅极电压为2伏时本申请实施例的漏极电流曲线；曲线D1为栅极电压为4伏时对比例的漏极电流曲线，曲线D2为栅极电压为4伏时本申请实施例的漏极电流曲线。可以看到旋涂掺杂后α-IGZO薄膜晶体管输出性能(漏极电流)明显提升。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种IGZO薄膜晶体管的制造方法，包括：
    获取基底；
    通过溶液工艺在所述基底上形成IGZO层；
    通过自旋掺杂工艺在所述IGZO层表面掺杂V族杂质；
    在所述IGZO层的一侧形成源极、另一侧形成漏极，并在所述掺杂后的IGZO层上形成栅介电层；及
    在所述栅介电层上形成栅极。
  2. 根据权利要求1所述的方法，其特征在于，所述通过自旋掺杂工艺在所述IGZO层表面掺杂V族杂质的步骤使用的掺杂剂含有磷元素。
  3. 根据权利要求1所述的方法，其特征在于，所述通过溶液工艺在所述基底上形成IGZO层的步骤包括：
    制作IGZO前体溶液；
    将所述IGZO前体溶液旋涂于所述基底上。
  4. 根据权利要求3所述的方法，其特征在于，还包括对旋涂了所述IGZO前体溶液的基底进行热退火处理的步骤。
  5. 根据权利要求3所述的方法，其特征在于，所述制作IGZO前体溶液的步骤包括：
    将硝酸铟水合物、硝酸锌水合物、硝酸镓水合物溶解于2-甲氧基乙醇溶剂中并进行搅拌；
    将搅拌后的液体进行过滤得到所述IGZO前体溶液。
  6. 根据权利要求5所述的方法，其特征在于，所述过滤是使用0.2微米厚的聚四氟乙烯滤膜进行。
  7. 根据权利要求5所述的方法，其特征在于，所述将硝酸铟水合物、硝酸锌水合物、硝酸镓水合物溶解于2-甲氧基乙醇溶剂中的步骤中，硝酸铟水合物、硝酸锌水合物、硝酸镓水合物的摩尔比是6：1：1。
  8. 根据权利要求1-7中任一项所述的方法，其特征在于，所述通过自旋掺杂工艺在所述IGZO层表面掺杂V族杂质的步骤后还包括对所述IGZO层进行烘干处理及紫外光退火处理的步骤。
  9. 根据权利要求1所述的方法，其特征在于，所述在所述IGZO层的一侧形成源极、另一侧形成漏极，并在所述掺杂后的IGZO层上形成栅介电层的步骤，及在所述栅介电层上形成栅极的步骤是采用溶液工艺进行制备。
  10. 根据权利要求3所述的方法，其特征在于，将所述IGZO前体溶液旋涂于所述基底上的步骤包括：将α-IGZO前体溶液旋涂于基底上并以3500转/分的速度旋转60秒。
  11. 根据权利要求4所述的方法，其特征在于，所述对旋涂了所述IGZO前体溶液的基底进行热退火处理的步骤包括：将旋涂有IGZO前体溶液的基底在300℃温度条件下退火30分钟。
  12. 一种IGZO薄膜晶体管，包括：
    基底；
    IGZO层，设于所述基底上，所述IGZO层是通过溶液工艺形成，所述IGZO层包括沟道区，所述沟道区的表面通过自旋掺杂工艺掺杂有V族杂质；
    源极，形成于所述IGZO层的一侧；
    漏极，形成于所述IGZO层的另一侧；
    栅介电层，形成于所述IGZO层上；及
    栅极，形成于所述栅介电层上。
  13. 根据权利要求12所述的IGZO薄膜晶体管，其特征在于，所述基底包括半导体衬底和所述半导体衬底上的绝缘氧化层。
  14. 根据权利要求12所述的IGZO薄膜晶体管，其特征在于，所述源极包括覆盖所述IGZO层的一侧边缘的ITO源极，所述漏极包括部分覆盖所述IGZO层的另一侧边缘的ITO漏极，所述栅介电层从所述IGZO层的沟道区表面延伸至所述ITO源极上和ITO漏极上，所述栅介电层的材质包括氧化铝，所述栅极包括ITO栅极。
  15. 根据权利要求12所述的IGZO薄膜晶体管，其特征在于，所述IGZO层为α-IGZO薄膜。
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