WO2021062982A1 - Procédé et appareil de gestion de la mémoire hmb, dispositif informatique et support d'enregistrement - Google Patents

Procédé et appareil de gestion de la mémoire hmb, dispositif informatique et support d'enregistrement Download PDF

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Publication number
WO2021062982A1
WO2021062982A1 PCT/CN2020/076957 CN2020076957W WO2021062982A1 WO 2021062982 A1 WO2021062982 A1 WO 2021062982A1 CN 2020076957 W CN2020076957 W CN 2020076957W WO 2021062982 A1 WO2021062982 A1 WO 2021062982A1
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Prior art keywords
unit
management
mapping
hmb
mapping unit
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PCT/CN2020/076957
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English (en)
Chinese (zh)
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吴娴
韩道静
王庆
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深圳忆联信息系统有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0868—Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0873—Mapping of cache memory to specific storage devices or parts thereof

Definitions

  • This application relates to the technical field of solid-state hard disks, and in particular to a method, device, computer equipment, and storage medium for managing HMB memory.
  • the NVMe (Non Volatile Memory Express) protocol defines the HMB (Host Memory Buffer, host memory buffer) function, which means that the solid state drive (SSD) that supports the NVMe protocol can use the host memory (DRAM) specially allocated to the solid state drive by the host. Solid-state hard drives do not need to be equipped with DRAM, which can greatly reduce cost and power consumption.
  • HMB High Memory Buffer, host memory buffer
  • the solid-state drive master control that supports the HMB function can obtain the right to use part of the host memory.
  • the size of the host’s memory is negotiated between the host and the solid-state drive according to their respective capabilities, and is not fixed.
  • the HMB size is 256MB, which is used to cache the temporary mapping table.
  • this part of the memory can only cache part of the mapping table.
  • the complete mapping table still needs to be stored in the flash memory, and the SSD master is responsible for management.
  • the temporary mapping table in the HMB, and the solid-state drive firmware is responsible for managing the complete mapping table in the flash memory.
  • the master When the host initiates a read command, the master first judges whether the mapping information of each LBA is in the HMB according to the management information. If so, it reads the mapping information (data) from the HMB to the SSD master through the PCIe bus.
  • the third-generation PCIe bus can provide a bus bandwidth of 1GB/s. It only takes 4us to transfer 4KB of data. The speed is quite fast. If the mapping information is not in the HMB, the SSD master can only read the mapping information from the SSD flash memory, and read a physical The page time is about 80us, which is relatively slow. After that, the mapping information needs to be cached in the HMB because it is Hot (frequently updated data).
  • the existing master control design has proposed a method to manage the HMB memory.
  • n complete mapping table size/HMB size
  • the master cache SRAM allocates management information for each 4KB memory in HMB.
  • Those 4KB mapping units with the same offset in different segments in the complete mapping table compete for the management unit with offset of offset in master SRAM and 4KB with offset of offset in HMB.
  • Memory and the implementation of the competition principle of new data overwriting old data.
  • the maximum offset is 3(0 ⁇ 3).
  • the controller stores the segment_idx and offset_idx of the 4KB mapping unit provided by the firmware in the management information with an offset equal to offset_idx, and transfers the 4KB mapping unit data to the offset in the HMB 4KB of host memory for offset_idx, and then set the valid position as valid.
  • the prior art method for managing HMB memory allows the mapping units of the same offset in all segments to compete for a management unit in the master control (corresponding to the 4KB memory space in a HMB), which is easy to lose heat. data.
  • the five hot data written [segment0, offset0], [segment0, offset2], [segment1, offset0], [segment2, offset0], [segment1, offset2], finally cached in the HMB only [segment2, offset0] With [segment1, offset2], the other three pieces of data are lost, and the utilization rate of HMB is low, which causes a waste of HMB resources.
  • One of the objectives of the embodiments of the present application is to provide a method, device, computer equipment, and storage medium for managing HMB memory, so as to solve the problem of low utilization rate of HMB.
  • a method for managing HMB memory including:
  • mapping unit Acquiring the mapping unit to be written in the complete mapping table to obtain attribute information of the mapping unit
  • the management unit with the largest Age value is acquired as the target management unit;
  • the mapping unit is written into the segmented memory space with the same offset in the HMB.
  • a device for managing HMB memory including:
  • the attribute obtaining unit is used to obtain the mapping unit to be written in the complete mapping table to obtain the attribute information of the mapping unit;
  • the idle judging unit is used to judge whether there are idle management units in the initial set. If there are idle management units, select the idle management units to obtain the target management unit. If there are no idle management units, get the maximum Age value The management unit as the target management unit;
  • the information writing unit is used to write the attribute information of the mapping unit into the target management unit to form management information
  • the assignment unit is used to set the Valid value of the target management unit to 1, and the Age value to 0, and to set the Age value of other management units in the initial set except the target management unit plus 1;
  • the mapping writing unit is used to write the mapping unit into the segmented memory space with the same offset in the HMB according to the management information.
  • a computer device including a memory, a processor, and a computer program stored in the memory and capable of running on the processor.
  • the processor implements the management HMB described in the first aspect when the processor executes the computer program. The steps of the memory method.
  • a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the method for managing HMB memory in the first aspect.
  • this application divides the HMB into multiple segments, corresponding to the mapping unit storing the same offset, greatly increasing the HMB Hot data hit rate, thereby increasing the utilization rate of HMB; mapping the management unit with the same offset in the main control to the continuous physical address segment of SRAM, with the parallel implementation of the hardware circuit, shortening the query time and improving the efficiency of data query.
  • Figure 1 is an application schematic diagram of the existing method for managing HMB memory
  • FIG. 2 is a schematic flowchart of a method for managing HMB memory provided by an embodiment of the application
  • FIG. 3 is a schematic diagram of the HMB setting sub-flow of a method for managing HMB memory provided by an embodiment of the application;
  • mapping unit reading sub-process of a method for managing HMB memory provided by an embodiment of the application
  • FIG. 5 is a schematic flowchart of a method for managing HMB memory according to another embodiment of the application.
  • FIG. 6 is an application principle diagram of a method for managing HMB memory provided by an embodiment of the application.
  • FIG. 7 is an application principle diagram of a method for managing HMB memory provided by an embodiment of the application.
  • FIG. 8 is a schematic block diagram of a device for managing HMB memory provided by an embodiment of the application.
  • FIG. 9 is a schematic block diagram of an HMB setting unit of an apparatus for managing HMB memory provided by an embodiment of the application.
  • FIG. 10 is a schematic block diagram of a device for managing HMB memory provided by another embodiment of this application.
  • FIG. 11 is a schematic block diagram of a data reading unit of a device for managing HMB memory provided by another embodiment of the application.
  • FIG. 12 is a schematic block diagram of a computer device provided by an embodiment of this application.
  • FIG. 2 is a schematic flowchart of a method for managing HMB memory provided by an embodiment of the application.
  • the method for managing HMB memory is applied to SSD, and the SSD performs data interaction with the host.
  • FIG. 2 is a schematic flowchart of a method for managing HMB memory provided by an embodiment of the present application. As shown in Figure 2, the method includes the following steps S110 to S180.
  • the complete mapping table can be divided into multiple mapping units.
  • Each mapping unit has a size of KB, and each mapping unit is written with corresponding attribute information.
  • the attribute information includes offset information and subdivision information.
  • the mapping unit [segment_x, offset_y] represents the offset information as offset_y, and the subordinate segment information is segment_x.
  • the attribute information of the mapping unit includes offset information offset_y and subordinate segment information as segment_x.
  • FIG. 3 is a schematic flowchart of the HMB setting sub-process.
  • a method for managing HMB memory in this embodiment further includes an HMB setting process before step S110, and the HMB setting process includes steps S210-S250.
  • the SSD initially applies for a part of the memory space from the host to be used as HMB (Host Memory Buffer), so that the SSD (Solid State Drive) that supports the NVMe protocol can use the host memory (DRAM) requested from the host.
  • Solid-state hard drives do not need to be equipped with DRAM by themselves, which can greatly reduce cost and power consumption.
  • S220 Divide the HMB into N segments to obtain the segment size.
  • the complete mapping table in the flash memory is equally divided into M segments, and the sizes of the segments and the segments are equal.
  • the segment is divided into S segmented memory spaces, and the segment is divided into S mapping units, and the size of the segmented memory space and the mapping unit are equal.
  • This application first divides the entire HMB into N segments (SET), and then divides the complete mapping table according to the segment size to obtain M segments, and further divides the segments into S segments.
  • the memory space is divided into S mapping units.
  • the segmented memory space and the mapping unit have the same size. In this embodiment, the segmented memory space and the mapping unit are both 4KB in size.
  • the SRAM of the SSD master control has 6 management units corresponding to the associated management of 6 segmented memory spaces.
  • the management unit is used to store the attribute information of the mapping unit written into the segmented memory space as Management information, including segment value and offset value.
  • mapping unit is stored in the segmented memory space with the same offset, and the attribute information of the mapping unit is stored as management information in the target management unit with the same offset.
  • the size of the mapping unit and the segmented memory space are both 4KB, and this application defines that mapping units with the same offset can be stored in the segmented memory space with the same offset.
  • This solution can store multiple mapping units with the same offset at the same time, making better use of HMB memory space and improving the hit rate of HMB usage.
  • the aforementioned N, M, and S all represent natural numbers greater than zero.
  • the offset information in the attribute information is obtained, all management units with the same offset are filtered out according to the offset information, and all the management units are used as the initial set for further checking
  • the management unit in the initial set judges and determines the target management unit for writing management information.
  • S140 If there are idle management units, select the idle management units to obtain the target management unit.
  • the initial set contains management units with the same offset attribute.
  • the mapping unit Before the mapping unit writes the segmented memory space corresponding to the offset according to the offset, it needs to determine whether there is free segmented memory space. It is available for writing, so it is necessary to determine whether there is an idle management unit in the initial set. There are two situations at this time. One is that there is an idle management unit, which means there is a segmented memory space that has not been written into the mapping unit. The mapping unit can be directly written into the corresponding segmented memory space, and the idle management unit needs to be further selected to obtain Target management unit; the other is that there is no idle management unit, and a segmented memory space that has been written with a mapping unit needs to be eliminated and written into a new mapping unit. At this time, the management unit with the largest Age value needs to be obtained as the target Management unit.
  • this application adopts the LRU (Least Recently Used) algorithm to introduce the Age value in the management unit, and the Age value represents the new and old data in the corresponding segmented memory space, and the value is 0, 1...N -1, the smaller the value, the newer the data.
  • Each management unit carries the Age value.
  • the management unit with the largest Age value (N-1) in the initial set is the oldest management unit, which is used as The target management unit eliminates data and writes it into a new mapping unit.
  • the attribute information is written into the target management unit to form management information, which is used to subsequently query the corresponding mapping unit according to the attribute information and download the corresponding mapping data.
  • S170 Set the Valid value of the target management unit to 1, and the Age value to 0, and set the Age value of other management units in the initial set except the target management unit plus 1.
  • Valid indicates whether the management information is valid, a Valid value of 1 represents that the management information of the management unit is valid, a Valid value of 0 represents that the management information of the management unit is invalid, and the Valid value of the target management unit is set to 1. It means that the management information in the management unit is effective.
  • the Age value in the eliminated management unit is correspondingly increased by 1, ensuring that the Age value corresponding to the management unit corresponding to the mapping unit written first is always greater than the Age value corresponding to the management unit corresponding to the mapping unit written later, so that the Age value can be passed To filter out the oldest management unit and eliminate it.
  • the firmware writes [segment0, offset0], [segment0, offset1], [segment1, offset0], [segment2, offset0], [segment1, offset1] five mapping units, according to the above write and elimination rules, finally
  • the management unit #1 will be eliminated according to the elimination rule, as shown in Figure 6.
  • mapping unit into the segmented memory space with the same offset in the HMB according to the management information.
  • step S190 is further included after step S180.
  • S190 Store the management units belonging to the same initial collection in an SRAM segment with consecutive physical addresses.
  • the main control needs to query multiple SRAM address segments when querying the management unit, which will slightly increase the query time.
  • this application stores the management units belonging to the same initial collection in the SRAM segment with continuous physical addresses.
  • the SRAM query can be started only once (start address Add the query length), which can effectively shorten the query time and improve the query efficiency.
  • Figure 4 is a schematic flow chart of the mapping unit reading sub-process, referring to Figure 4, a method for managing HMB memory in this embodiment, after step S180, also includes a mapping information (data) reading process, mapping information (data) reading
  • the fetching process includes steps S310-S340.
  • S330 Query the management unit according to the attribute information to obtain management units with the same attribute information.
  • S340 Read the mapping unit data of the corresponding position on the HMB according to the management information of the management unit.
  • mapping unit read command when reading the mapping unit data, the mapping unit read command is obtained, the mapping unit read command is parsed to obtain the attribute information of the mapping unit to be read, and the management unit is queried according to the attribute information to obtain The management unit with the same attribute information reads the mapping unit data of the corresponding position on the HMB according to the management information of the management unit.
  • FIG. 8 is a schematic block diagram of a device for managing HMB memory provided by an embodiment of the present application. As shown in FIG. 8, corresponding to the above method for managing HMB memory, this application also provides a device for managing HMB memory.
  • the device for managing HMB memory includes a unit for executing the above method for managing HMB memory, and the device can be configured in a desktop computer, a tablet computer, a laptop computer, and other terminals.
  • the device for managing HMB memory includes an attribute acquisition unit 10, a screening collection unit 20, an idle determination unit 30, an information writing unit 40, an assignment unit 50, a mapping writing unit 60, and an HMB setting unit 70.
  • the attribute obtaining unit 10 is used to obtain the mapping unit to be written in the complete mapping table to obtain the attribute information of the mapping unit.
  • the screening collection unit 20 screens management units with the same offset as the mapping unit according to the attribute information to obtain the initial collection.
  • the idle judging unit 30 is used to judge whether there are idle management units in the initial set. If there are idle management units, select the idle management units to obtain the target management unit; if there are no idle management units, obtain the Age value The largest management unit is used as the target management unit.
  • the information writing unit 40 is used to write the attribute information of the mapping unit into the target management unit to form management information.
  • the assignment unit 50 is used to set the Valid value of the target management unit to 1, and the Age value to 0, and to set the Age value of other management units in the initial set except the target management unit plus 1.
  • the mapping writing unit 60 is configured to write the mapping unit into the segmented memory space with the same offset in the HMB according to the management information.
  • an apparatus for managing HMB memory of the present application further includes an HMB setting unit 70.
  • the HMB setting unit 70 includes a memory application subunit 71, a segmentation subunit 72, a segmentation subunit 73, and a switch.
  • the molecular unit 74 and the definition subunit 75 are included in an apparatus for managing HMB memory of the present application.
  • the memory application subunit 71 is used to apply to the host to allocate a memory space as an HMB for storing the mapping unit.
  • the segmentation subunit 72 is used to divide the HMB into N segments to obtain the segment size.
  • the division subunit 73 is configured to divide the complete mapping table in the flash memory into M divisions according to the size of the division, and the divisions and divisions have the same size.
  • the molecular cutting unit 74 divides the segment into S segmented memory spaces, and divides the segment into S mapping units, and the size of the segmented memory space and the mapping unit are equal.
  • the definition subunit 75 is used to define that the mapping unit is stored in the segmented memory space with the same offset, and the attribute information of the mapping unit is stored as management information in the target management unit with the same offset.
  • N, M, and S all represent natural numbers greater than zero.
  • FIG. 10 is a schematic block diagram of a device for managing HMB memory provided by another embodiment of the present application. As shown in FIG. 10, the device for managing HMB memory in this embodiment is based on the above embodiment with an address adjustment unit 80 and a data reading unit 90 added.
  • the address adjustment unit 80 is used to store the management units belonging to the same initial collection in an SRAM segment with consecutive physical addresses.
  • the data reading unit 90 includes a command acquisition subunit 91, an attribute analysis subunit 92, an attribute query subunit 93 and a data reading subunit 94.
  • the command obtaining subunit 91 is used to obtain a reading command of the mapping unit.
  • the attribute analysis subunit 92 is used to parse the mapping unit read command to obtain the attribute information of the mapping unit to be read.
  • the attribute query subunit 93 is used to query the management units according to the attribute information to obtain management units with the same attribute information.
  • the data reading subunit 94 is used to read the mapping unit data of the corresponding position on the HMB according to the management information of the management unit.
  • the computer device 500 may be a terminal or a server, where the terminal may be an electronic device with communication functions such as a smart phone, a tablet computer, a notebook computer, a desktop computer, a personal digital assistant, and a wearable device.
  • the server can be an independent server or a server cluster composed of multiple servers.
  • the computer device 500 includes a processor 502, a memory, and a network interface 505 connected through a system bus 501, where the memory may include a non-volatile storage medium 503 and an internal memory 504.
  • the non-volatile storage medium 503 can store an operating system 5031 and a computer program 5032.
  • the computer program 5032 includes program instructions.
  • the processor 502 can execute a method for managing HMB memory.
  • the processor 502 is used to provide calculation and control capabilities to support the operation of the entire computer device 500.
  • the internal memory 504 provides an environment for the operation of the computer program 5032 in the non-volatile storage medium 503.
  • the processor 502 can execute a method for managing HMB memory.
  • the network interface 505 is used for network communication with other devices.
  • the specific computer device 500 may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.
  • the processor 502 is configured to run a computer program 5032 stored in the memory.
  • the processor 502 may be a central processing unit (Central Processing Unit, CPU), and the processor 502 may also be other general-purpose processors, digital signal processors (Digital Signal Processors, DSPs), Application Specific Integrated Circuit (ASIC), Field-Programmable Gate Array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc.
  • the general-purpose processor may be a microprocessor or the processor may also be any conventional processor.
  • the computer program includes program instructions, and the computer program can be stored in a storage medium, which is a computer-readable storage medium.
  • the program instructions are executed by at least one processor in the computer system to implement the process steps of the foregoing method embodiments.
  • the storage medium may be a computer-readable storage medium.
  • the storage medium may be a U disk, a mobile hard disk, a read-only memory (Read-Only Memory, ROM), a magnetic disk or an optical disk, and other computer-readable storage media that can store program codes.

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Abstract

L'invention concerne un procédé et un appareil de gestion d'une mémoire HMB, ainsi qu'un dispositif informatique et un support d'enregistrement. Le procédé comprend : l'acquisition d'une unité de mappage à écrire dans une table de mappage complète, de façon à obtenir des informations d'attribut de l'unité de mappage (S110) ; en fonction des informations d'attribut, le criblage d'une unité de gestion ayant le même décalage que l'unité de mappage, de façon à obtenir un ensemble initial (S120) ; la détermination de l'existence d'une unité de gestion au repos dans l'ensemble initial (S130) ; si tel est le cas, la sélection de l'unité de gestion au repos, de façon à obtenir une unité de gestion de cible (S140) ; dans le cas contraire, l'acquisition d'une unité de gestion ayant la valeur Âge maximale pour servir d'unité de gestion de cible (S150) ; l'écriture d'informations d'attribut de l'unité de mappage dans l'unité de gestion de cible, de façon à former des informations de gestion (S160) ; et selon les informations de gestion, l'écriture de l'unité de mappage dans un espace de mémoire de segment, ayant le même décalage, dans un HMB (S180). Un HMB est divisé en une pluralité de segments pour stocker de manière correspondante des unités de mappage ayant le même décalage, de sorte que le taux de réussite des données chaudes du HMB est fortement augmenté, ce qui permet également d'augmenter le taux d'utilisation du HMB.
PCT/CN2020/076957 2019-09-30 2020-02-27 Procédé et appareil de gestion de la mémoire hmb, dispositif informatique et support d'enregistrement WO2021062982A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023103495A1 (fr) * 2021-12-08 2023-06-15 深圳忆联信息系统有限公司 Procédé et appareil de mise à jour retardée pour table de mappage de disque électronique, et dispositif informatique et support de stockage

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110737607B (zh) * 2019-09-30 2021-09-14 深圳忆联信息系统有限公司 管理hmb内存的方法、装置、计算机设备及存储介质
CN113867641B (zh) * 2021-09-29 2023-06-02 杭州海康存储科技有限公司 主机内存缓冲管理方法、装置、以及固态硬盘

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160026406A1 (en) * 2014-06-05 2016-01-28 Sandisk Technologies Inc. Methods, systems, and computer readable media for providing flexible host memory buffer
CN108021511A (zh) * 2017-11-22 2018-05-11 深圳忆联信息系统有限公司 一种ssd性能提升的方法及ssd
CN108885584A (zh) * 2016-04-01 2018-11-23 桑迪士克科技有限责任公司 使用主机存储器缓冲区的无序读取传输
CN110109851A (zh) * 2018-02-01 2019-08-09 爱思开海力士有限公司 具有主机和存储器控制器的电子系统及其操作方法
CN110109845A (zh) * 2019-04-26 2019-08-09 深圳忆联信息系统有限公司 缓存数据管理方法、装置、计算机设备及存储介质
CN110737607A (zh) * 2019-09-30 2020-01-31 深圳忆联信息系统有限公司 管理hmb内存的方法、装置、计算机设备及存储介质

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103049397B (zh) * 2012-12-20 2015-09-16 中国科学院上海微系统与信息技术研究所 一种基于相变存储器的固态硬盘内部缓存管理方法及系统
US10268584B2 (en) * 2014-08-20 2019-04-23 Sandisk Technologies Llc Adaptive host memory buffer (HMB) caching using unassisted hinting
CN105005536B (zh) * 2015-07-01 2019-08-06 忆正科技（武汉）有限公司 固态存储设备、主机的工作方法及固态存储设备、主机
US10360156B2 (en) * 2016-08-04 2019-07-23 Samsung Electronics Co., Ltd. Data storage device using host memory and method of operating same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160026406A1 (en) * 2014-06-05 2016-01-28 Sandisk Technologies Inc. Methods, systems, and computer readable media for providing flexible host memory buffer
CN108885584A (zh) * 2016-04-01 2018-11-23 桑迪士克科技有限责任公司 使用主机存储器缓冲区的无序读取传输
CN108021511A (zh) * 2017-11-22 2018-05-11 深圳忆联信息系统有限公司 一种ssd性能提升的方法及ssd
CN110109851A (zh) * 2018-02-01 2019-08-09 爱思开海力士有限公司 具有主机和存储器控制器的电子系统及其操作方法
CN110109845A (zh) * 2019-04-26 2019-08-09 深圳忆联信息系统有限公司 缓存数据管理方法、装置、计算机设备及存储介质
CN110737607A (zh) * 2019-09-30 2020-01-31 深圳忆联信息系统有限公司 管理hmb内存的方法、装置、计算机设备及存储介质

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023103495A1 (fr) * 2021-12-08 2023-06-15 深圳忆联信息系统有限公司 Procédé et appareil de mise à jour retardée pour table de mappage de disque électronique, et dispositif informatique et support de stockage

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