WO2021056458A1 - Procédé et appareil de traitement de données basés sur un bus pcie, et plateforme mobile - Google Patents

Procédé et appareil de traitement de données basés sur un bus pcie, et plateforme mobile Download PDF

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Publication number
WO2021056458A1
WO2021056458A1 PCT/CN2019/108693 CN2019108693W WO2021056458A1 WO 2021056458 A1 WO2021056458 A1 WO 2021056458A1 CN 2019108693 W CN2019108693 W CN 2019108693W WO 2021056458 A1 WO2021056458 A1 WO 2021056458A1
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Prior art keywords
data
address
description file
root complex
destination address
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PCT/CN2019/108693
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English (en)
Chinese (zh)
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董培方
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深圳市大疆创新科技有限公司
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Priority to PCT/CN2019/108693 priority Critical patent/WO2021056458A1/fr
Priority to CN201980033883.7A priority patent/CN112189191A/zh
Publication of WO2021056458A1 publication Critical patent/WO2021056458A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Definitions

  • the present disclosure relates to the field of data processing technology, and in particular to a data processing method and device based on PCIe bus, and a movable platform.
  • the processor of the embedded system often needs to process a large amount of sensor data. Due to the limited processing speed and computing resources of a single processor, multiple processors are often required to be interconnected in this case, and data can be shared between multiple processors to meet the real-time requirements for sensor data processing.
  • USB universal serial bus
  • the present disclosure provides a data processing method based on PCIe bus, including:
  • One of the root complex device and the terminal device transmits data and description files to the other through the PCIe bus;
  • the root complex device After the root complex device transmits the first data and its first description file to the terminal device, the root complex device triggers an interrupt generator so that the interrupt generator sends a first interrupt to the terminal device signal;
  • the terminal device After receiving the first interrupt signal, the terminal device processes the first data according to the first description file.
  • the present disclosure also provides a data processing device based on PCIe bus, including: root complex device, terminal device and interrupt generator;
  • One of the root complex device and the terminal device can transmit data and description files to the other through the PCIe bus;
  • the root complex device After the root complex device transmits the first data and its first description file to the terminal device, the root complex device can trigger an interrupt generator, and the interrupt generator can send the first data to the terminal device. Interrupt signal
  • the terminal device may process the first data according to the first description file.
  • the present disclosure also provides a movable platform, including: the above-mentioned data processing device.
  • the PCIe bus is used for data transmission between processors, which improves the data transmission rate and ensures the real-time transmission of large data volumes.
  • the root complex device and the terminal device can perform two-way data transmission, which improves the utilization of computing resources and is beneficial to the The reasonable allocation of computing resources improves the computing power of the processor.
  • FIG. 1 is a flowchart of a data processing method based on PCIe bus according to an embodiment of the disclosure.
  • Fig. 2 is a schematic diagram of the structure of a data processing device for executing a data processing method.
  • Figure 3 shows the storage space of the root complex device and the terminal device when the first data and the first description file are transmitted.
  • Figure 4 shows the outbound and inbound process when transmitting the first data.
  • Figure 5 shows the outbound and inbound process when transmitting the first description file.
  • Fig. 6 is another schematic diagram of the structure of the data processing device for executing the data processing method.
  • Figure 7 shows the storage space of the root complex device and the terminal device when the second data and the second description file are transmitted.
  • Figure 8 shows the outbound and inbound process when transmitting the second data.
  • Figure 9 shows the outbound and inbound process when transmitting the second description file.
  • Fig. 10 is a schematic diagram of another structure of a data processing device for executing a data processing method.
  • FIG. 11 is a schematic structural diagram of a data processing device based on a PCIe bus according to an embodiment of the disclosure.
  • Fig. 12 is a schematic structural diagram of an unmanned aerial vehicle according to an embodiment of the disclosure.
  • An embodiment of the present disclosure provides a data processing method based on PCIe bus, as shown in FIG. 1, including the following steps:
  • Step S101 One of the root complex device and the terminal device transmits data and description files to the other through the PCIe bus;
  • Step S102 After the root complex device transmits the first data and its first description file to the terminal device, the root complex device triggers an interrupt generator to cause the interrupt generator to send to the terminal device The first interrupt signal;
  • Step S103 After receiving the first interrupt signal, the terminal device processes the first data according to the first description file.
  • the application scenario of the data processing method of this embodiment is a dual-processor data processing device interconnected by a Peripheral Component Interconnect Express (PCIe) bus.
  • PCIe Peripheral Component Interconnect Express
  • the PCIe bus is a point-to-point communication protocol.
  • One processor is used as a root complex device (RC, Root Complex), and the other processor is used as a terminal device (EP, End Point).
  • RC equipment and EP equipment The RC device and the EP device exchange data through the PCIe bus.
  • the data processing device is also provided with an interrupt generator.
  • step S101 one of the RC device and the EP device transmits data and a description file (Description) to the other through the PCIe bus. That is, not only the EP device can transmit data to the RC device, but the RC device can also transmit data to the EP device.
  • the data processing method of this embodiment can realize two-way data transmission between the RC device and the EP device. The data transmission process will be described in detail below.
  • the RC device includes: a central processing unit (CPU) and a first enhanced direct memory access (EDMA) module. Both the CPU and the first EDMA module can obtain the control right of the PCIe bus and transmit the device to the EP device at the opposite end through the PCIe bus. In order to improve the data transmission efficiency, this embodiment uses the first EDMA module to transmit data to the EP device.
  • CPU central processing unit
  • EDMA enhanced direct memory access
  • the CPU needs to configure the parameters of the first EDMA module. After the parameters are configured, the first EDMA module can transmit the data and the description file.
  • the first EDMA module has multiple parameters that need to be configured, including at least: a transmission mode, a first source address, and a first destination address.
  • the first source address refers to the address of the first data in the storage space of the RC device.
  • the first destination address refers to the address of the first data in the storage space of the EP device.
  • the first source address may refer to one address or multiple addresses.
  • the first data can be stored in a whole block in the memory of the RC device, that is, the first data occupies consecutive addresses in the storage space of the RC device.
  • the first source address may be the first address of the first data in the storage space of the RC device.
  • the first data may also be stored in blocks in the memory of the RC device, that is, the addresses of the data blocks of the first data in the storage space of the RC device are not continuous.
  • the first source address may be the first address of each data block in the storage space of the RC device.
  • the first destination address is similar to this.
  • the first data When the first data occupies consecutive addresses in the storage space of the RC device, the first data can be stored in a whole block in the memory of the EP device.
  • the first destination address can be the first address of the first data in the storage space of the EP device. ;
  • the first data can also be stored in blocks in the memory of the EP device.
  • the first destination address can be the first address of each data block in the storage space of the EP device.
  • the first destination address may be the first address of the first data in the storage space of the EP device, or the first address of each data block in the storage space of the EP device.
  • the transmission modes include: linked list mode and non-linked list mode.
  • the choice of transmission mode depends on the address continuity of the data to be transmitted.
  • the first EDMA module uses a linked list Mode; otherwise, when the first data is stored in one block in the memories of the RC device and the EP device, the first EDMA module adopts the non-linked list mode.
  • the CPU transfers the control right of the PCIe bus to the first EDMA module.
  • the first EDMA module transmits the first data to the EP device according to the configured parameters. For example, the first EDMA module reads the first source address in the memory of the RC device, adopts linked list mode or non-linked list mode, and transmits the first data stored in the first source address to the EP device, and the EP device stores the first data in its memory The first destination address.
  • the storage space of the RC device and the EP device mentioned above refers to their respective internal address spaces.
  • the PCIe bus also defines a PCIe address space, and the memory of the RC device and the EP device is addressed in the PCIe address space. That is, there is a mapping relationship between the storage space of the RC device and the EP device and the PCIe address space, and the address in the storage space of the RC device and the EP device has a corresponding PCIe space address. Therefore, when the RC device transmits data to the EP device, address conversion is required.
  • the RC device Before the first EDMA module transmits the first data to the EP device, the RC device first converts the first destination address into the corresponding first PCIe space address. Then, the first EDMA module uses the first PCIe space address as a destination address, and sends the first data to the first PCIe space address. After receiving the first data, the EP device converts the first PCIe space address into the first destination address, and stores the first data in the first destination address.
  • the process of converting the first destination address into the corresponding first PCIe space address is generally called outbound.
  • An outbound register is provided in the RC device, and the mapping relationship between the storage space of the RC device and the PCIe address space is stored in the outbound register.
  • the RC device converts the first destination address into the corresponding first PCIe space address according to the mapping relationship stored in the outbound register.
  • the process of converting the first PCIe space address into the first destination address is generally called inbound.
  • the EP device is provided with an inbound register, and the inbound register stores the mapping relationship between the storage space of the EP device and the PCIe address space.
  • the EP device converts the first PCIe space address into the first destination address according to the mapping relationship stored in the inbound register.
  • the RC device In addition to transmitting data to the EP device, the RC device also needs to transmit a description file of the data to the EP device.
  • This description file is used to record the parameters of the transmitted data, and is used to notify the EP device of the address and size of the data transmitted, otherwise the EP The device does not know whether the data has been transferred, and the storage address of the data, and cannot read and further process the data.
  • the first description file corresponding to the first data records the following parameters: the first destination address and the size of the first data.
  • the first description file itself is also a kind of data that needs to be transmitted. Similar to the first data, the first description file itself has a storage address in the storage space of the RC device. After it is transmitted to the EP device, it will be stored in the storage space of the EP device. A storage address is also required. Therefore, the parameters configured by the CPU for the first EDMA module also include: a second source address and a second destination address.
  • the second source address refers to the address of the first description file in the storage space of the RC device
  • the second destination address refers to the address of the first description file in the storage space of the EP device.
  • the first EDMA module transmits the first description file to the EP device according to the configured parameters. For example, the first EDMA module reads the second source address in the memory of the RC device, and transmits the first description file stored in the second source address to the EP device, and the EP device stores the first description file in the second destination address of its memory.
  • the RC device before the first EDMA module transmits the first description file to the EP device, the RC device first converts the second destination address into the corresponding second PCIe space address. Then the first EDMA module uses the second PCIe space address as the destination address, and sends the first description file to the second PCIe space address. After receiving the first description file, the EP device converts the second PCIe space address into a second destination address, and stores the first description file at the second destination address.
  • the second source address and the second destination address of the first description file are determined by means of dynamic configuration.
  • the RC device and the EP device can open up a storage space in their respective memories, which is specifically used to store the first description file.
  • the EP device knows in advance the second destination address where the first description file is stored. After the first description file is transmitted to the EP device, the EP device can read and retrieve the first description file from the second destination address.
  • the second destination address can be converted into the corresponding one according to the mapping relationship between the storage space of the RC device and the PCIe address space stored in the Outbound register of the RC device
  • the second PCIe space address converts the second PCIe space address into a second destination address according to the mapping relationship between the storage space of the EP device stored in the inbound register of the EP device and the PCIe address space.
  • the size of the first data recorded in the first description file corresponds to the storage mode of the first data.
  • the size of the first data refers to the size of the whole block of first data.
  • the size of the first data includes the size of each block of the first data.
  • step S102 and step S103 after the RC device transmits the first data and its first description file to the EP device, the RC device configures the interrupt generator so that the interrupt generator sends the interrupt generator to the EP device.
  • the device sends the first interrupt signal; after receiving the first interrupt signal, the EP device processes the first data according to the first description file.
  • the interrupt generator may be a General Purpose Input Output (GPIO, General Purpose Input Output) interrupt generator.
  • GPIO General Purpose Input Output
  • the first EDMA module sends a trigger signal to the GPIO interrupt generator.
  • the GPIO interrupt generator After receiving the trigger signal, the GPIO interrupt generator generates a GPIO interrupt signal and sends it to the CPU of the EP device. After the EP device receives the GPIO interrupt signal, it knows that the RC device has transmitted the first data to itself.
  • GPIO General Purpose Input Output
  • the CPU of the EP device reads the first description file from the second destination address from the EP device, and obtains the first destination address and size of the first data from the first description file, which can be read from the first destination address The first data, so that subsequent operations are performed on the first data.
  • the RC device can respectively transfer the first data and the first description file to the EP device during the two EDMA transfer processes.
  • the first EDMA module can also transmit the first data and the first description file to the EP device during one EDMA transmission process. By simultaneously transmitting the first data and the first description file in an EDMA transmission process, the data transmission efficiency can be improved.
  • the first EDMA module After the RC device transmits the first data to the EP device, the first EDMA module also sends a second interrupt signal to the CPU of the RC device.
  • the second interrupt signal may be an EDMA DONE/ABORT interrupt signal, which is used to notify the RC device that the first data has been transmitted.
  • the CPU of the RC device After receiving the second interrupt signal, the CPU of the RC device can take back control of the PCIe bus and perform subsequent processing.
  • the PCIe bus is used for data transmission between processors, which improves the data transmission rate and ensures the real-time transmission of a large amount of data.
  • the RC device transmits the first data and its first description file to the EP device, it notifies the EP device through the interrupt generator so that the EP device can process the first data according to the first description file, realizing the active data transmission of the RC device , That is, data transmission can also be carried out in the direction of RC equipment ⁇ EP equipment.
  • the data of RC equipment can be shared in EP equipment.
  • the calculations originally undertaken by RC equipment can be transferred to EP equipment for completion, which improves the utilization of computing resources. Conducive to the reasonable allocation of computing resources.
  • the EDMA method is adopted for data transmission, which has high data transmission speed and low delay, which improves the efficiency of data interaction between processors.
  • the GPIO interrupt generator is taken as an example to describe this embodiment above, but this is only exemplary and not a limitation of the present disclosure. Except for the GPIO interrupt generator, any interrupt generator that can generate an interrupt signal under the excitation of an external trigger signal falls within the protection scope of the present disclosure.
  • the EP device can transmit data to the RC device.
  • the EP device includes: a central processing unit (CPU) and a second enhanced direct memory access (EDMA) module. Both the CPU and the second EDMA module can obtain the control right of the PCIe bus and transmit the device to the opposite RC device through the PCIe bus. In order to improve the efficiency of data transmission, this embodiment uses the second EDMA module to transmit data to the EP device.
  • CPU central processing unit
  • EDMA enhanced direct memory access
  • the CPU of the EP device configures the parameters of the second EDMA module. After the parameters are configured, the second EDMA module can transfer the data and the description file. .
  • the second EDMA module has multiple parameters that need to be configured, including at least: a transmission mode, a third source address, and a third destination address.
  • the third source address refers to the address of the second data in the storage space of the EP device. After the second data is transmitted to the RC device, it is stored in the memory of the RC device, and the third destination address refers to an address in the storage space of the second data RC device.
  • the third source address may refer to one address or multiple addresses.
  • the second data can be stored in a whole block in the memory of the EP device, that is, the second data occupies consecutive addresses in the storage space of the EP device.
  • the third source address may be the first address of the second data in the storage space of the EP device.
  • the second data may also be stored in blocks in the memory of the EP device, that is, the addresses of the data blocks of the second data in the storage space of the EP device are not continuous.
  • the third source address may be the first address of each data block in the storage space of the EP device.
  • the third destination address is similar to this.
  • the second data When the second data occupies consecutive addresses in the storage space of the EP device, the second data can be stored in one block in the memory of the RC device.
  • the third destination address can be the first address of the second data in the storage space of the RC device. ;
  • the second data can also be stored in blocks in the memory of the RC device.
  • the third destination address can be the first address of each data block in the storage space of the EP device.
  • the second data in the storage space of the EP device is not continuous, the second data can be stored in a block in the memory of the RC device, or can be stored in blocks in the memory of the RC device.
  • the third destination address may be the first address of the second data in the storage space of the RC device, or the first address of each data block in the storage space of the RC device.
  • the transmission modes include: linked list mode and non-linked list mode.
  • the choice of transmission mode depends on the address continuity of the data to be transmitted.
  • the second EDMA module uses a linked list Mode; otherwise, when the second data is stored in one block in the memories of the RC device and the EP device, the second EDMA module adopts the non-linked list mode.
  • the CPU of the EP device transfers the control right of the PCIe bus to the second EDMA module.
  • the second EDMA module transmits the second data to the RC device according to the configured parameters.
  • the EP device Before the second EDMA module transmits the second data to the RC device, the EP device first converts the third destination address into the corresponding third PCIe space address. Then the second EDMA module uses the third PCIe space address as the destination address, and sends the second data to the third PCIe space address. After receiving the second data, the RC device converts the third PCIe space address into a third destination address, and stores the second data in the third destination address.
  • the process of converting the third destination address into the corresponding third PCIe space address is called outbound.
  • the EP device is provided with an outbound register, and the outbound register stores the mapping relationship between the storage space of the EP device and the PCIe address space.
  • the EP device converts the third destination address into a corresponding third PCIe space address according to the mapping relationship stored in the outbound register.
  • the process of converting the third PCIe space address to the third destination address is called inbound.
  • An inbound register is provided in the RC device, and the inbound register stores the mapping relationship between the storage space of the RC device and the PCIe address space.
  • the RC device converts the third PCIe space address into the third destination address according to the mapping relationship stored in the inbound register.
  • the EP device Similar to the transmission of the first data, in addition to transmitting data to the RC device, the EP device also needs to transmit a data description file to the RC device.
  • This description file is used to record the parameters of the transmitted data and is used to notify the RC device of the transmitted data. The address and size of the data, otherwise the RC device does not know whether the data has been transferred, and the storage address of the data, and cannot read and further process the data.
  • the second description file corresponding to the second data records the following parameters: the third destination address and the size of the second data.
  • the second description file itself is also a kind of data that needs to be transmitted. Similar to the second data, the second description file itself has a storage address in the storage space of the EP device. After it is transmitted to the RC device, it is stored in the storage space of the RC device. A storage address is also required. Therefore, the parameters configured by the CPU of the EP device on the second EDMA module also include: a fourth source address and a fourth destination address.
  • the fourth source address refers to the address of the second description file in the storage space of the EP device
  • the fourth destination address refers to the address of the second description file in the storage space of the RC device.
  • the second EDMA module transmits the second description file to the RC device according to the configured parameters. For example, the second EDMA module reads the fourth source address in the EP device memory, and transmits the second description file stored in the fourth source address to the RC device, and the RC device stores the second description file in the fourth destination address of its memory.
  • the EP device before the second EDMA module transmits the second description file to the RC device, the EP device first converts the fourth destination address into the corresponding fourth PCIe space address. Then the second EDMA module uses the fourth PCIe space address as the destination address, and sends the second description file to the fourth PCIe space address. After receiving the second description file, the RC device converts the fourth PCIe space address into a fourth destination address, and stores the second description file at the fourth destination address.
  • the fourth source address and the fourth destination address of the second description file are also determined by means of dynamic configuration.
  • the RC device and the EP device can open up a storage space in their respective memories, specifically for storing the second description file.
  • the RC device knows in advance the fourth destination address where the second description file is stored. After the second description file is transferred to the RC device, the RC device can read the second description file from the fourth destination address.
  • the fourth destination address can be converted to the corresponding mapping relationship between the storage space of the EP device stored in the outbound register of the EP device and the PCIe address space.
  • the fourth PCIe space address converts the fourth PCIe space address into a fourth destination address according to the mapping relationship between the storage space of the RC device and the PCIe address space stored in the inbound register of the RC device.
  • the size of the second data recorded in the second description file corresponds to the storage mode of the second data.
  • the size of the second data refers to the size of the whole block of second data.
  • the size of the second data includes the size of each block of the second data.
  • the EP device sends a third interrupt signal to the RC device through the PCIe bus.
  • the third interrupt signal may be a message signal interrupt (MSI, Message Signaled Interrupt) interrupt signal in the PCIe protocol.
  • MSI message signal interrupt
  • the RC device processes the second data according to the second description file.
  • the second EDMA module also sends a fourth interrupt signal to the CPU of the EP device.
  • the fourth interrupt signal may be an EDMA DONE/ABORT interrupt signal, which is used to notify the EP device that the second data has been transmitted.
  • the CPU of the EP device receives the fourth interrupt signal, it can take back control of the PCIe bus and perform subsequent processing.
  • the EP device can respectively transfer the second data and the second description file to the RC device during the two EDMA transfer processes.
  • the second EDMA module can also transmit the second data and the second description file to the RC device during one EDMA transmission process. By simultaneously transmitting the second data and the second description file in an EDMA transmission process, the data transmission efficiency can be improved.
  • the EP device in addition to the active data transmission of the RC device, the EP device can also actively initiate data transmission, that is, the two-way data transmission between the RC device and the EP device is realized, and the utilization rate of computing resources is improved. Conducive to the reasonable allocation of computing resources.
  • the EDMA method is adopted for data transmission, and the data transmission speed is high and the delay is low, which improves the efficiency of data interaction between processors.
  • FIG. 11 Another embodiment of the present disclosure provides a PCIe bus-based data processing device, as shown in FIG. 11, including: an RC device, an EP device, and an interrupt generator.
  • One of the RC device and the EP device can transmit data and description files to the other through the PCIe bus.
  • the RC device After the RC device transmits the first data and its first description file to the EP device, the RC device can configure the interrupt generator so that the interrupt generator sends the first interrupt signal to the EP device.
  • the EP device After receiving the first interrupt signal, the EP device can process the first data according to the first description file.
  • the interrupt generator may be a GPIO interrupt generator; the first interrupt signal is: a GPIO interrupt signal.
  • the RC device includes: a first EDMA module and a CPU.
  • the first EDMA module can transmit the first data and the first description file to the EP device through the PCIe bus.
  • the RC device can configure the parameters of the first EDMA module, and the first EDMA module can transmit the first data and the first description file to the EP device according to the configured parameters.
  • the parameters include: transmission mode, first source address, and first destination address.
  • the first source address is the storage address of the first data in the RC device
  • the first destination address is the storage address of the first data in the EP device after the RC device transmits the first data to the EP device.
  • the transmission modes include: linked list mode and non-linked list mode.
  • the RC device may configure the transmission mode of the first EDMA module as a linked list mode; otherwise, configure it as a non-linked list mode.
  • the transmission mode is the linked list mode, the first EDMA module can transmit the first data and the first description file to the EP device in one EDMA transmission process.
  • the RC device can convert the first destination address into the corresponding first PCIe space address, and the first EDMA module can send the first data to the first PCIe space address; the EP device can transfer the first destination address to the first PCIe space address.
  • the PCIe space address is converted to the first destination address, and the first data is stored in the first destination address.
  • the first description file records the following parameters: the first destination address and the size of the first data.
  • the configuration parameters according to the first EDMA module also include: a second source address and a second destination address; the second source address is the storage address of the first description file in the RC device, and the second destination address is the RC device transmitting the first description file After arriving at the EP device, the storage address of the first description file in the EP device.
  • the RC device can convert the second destination address to the corresponding second PCIe space address, the first EDMA module can send the first description file to the second PCIe space address; the EP device can convert the second PCIe space address to the second destination Address, and store the first description file at the second destination address.
  • the EP device After receiving the first interrupt signal, the EP device can read the first description file of the second destination address, obtain the first destination address recorded in the first description file, and read the first data of the first destination address.
  • the first EDMA module can send a second interrupt signal to the CPU of the RC device.
  • the EP device includes: a second EDMA module and a CPU.
  • the second EDMA module can transmit the second data and the second description file to the RC device through the PCIe bus.
  • the EP device After the EP device transmits the second data and its second description file to the RC device, the EP device can send a third interrupt signal to the RC device; after the RC device receives the third interrupt signal, it can compare the second data according to the second description file. To process.
  • the EP device can configure the parameters of the second EDMA module, and the second EDMA module can transmit the second data and the second description file to the RC device according to the configured parameters.
  • the parameters include: transmission mode, third source address, and third destination address.
  • the third source address is the storage address of the second data in the EP device
  • the third destination address is the storage address of the second data in the RC device after the EP device transmits the second data to the RC device.
  • the transmission modes include: linked list mode and non-linked list mode.
  • the EP device may configure the transmission mode of the second EDMA module as a linked list mode; otherwise, configure it as a non-linked list mode.
  • the transmission mode is the linked list mode
  • the second EDMA module transmits the second data and the second description file to the RC device in one EDMA transmission process.
  • the EP device converts the third destination address into the corresponding third PCIe space address
  • the second EDMA module can send the second data to the third PCIe space address
  • the RC device converts the third PCIe space
  • the address is converted into a third destination address, and the second data is stored in the third destination address.
  • the second description file records the following parameters: the third destination address and the size of the second data.
  • the EP device's configuration parameters for the second EDMA module also include: a fourth source address and a fourth destination address; the fourth source address is the storage address of the second description file in the EP device, and the fourth destination address is the second description of the EP device After the file is transferred to the RC device, the storage address of the second description file in the RC device.
  • the EP device can convert the fourth destination address to the corresponding fourth PCIe space address, the second EDMA module can send the second description file to the fourth PCIe space address; the RC device can convert the fourth PCIe space address to the fourth destination Address, and store the second description file in the fourth destination address.
  • the RC device After receiving the third interrupt signal, the RC device can read the second description file of the fourth destination address, obtain the third destination address recorded by the second description file, and read the second data of the third destination address.
  • the second EDMA module After the EP device transmits the second data and the second description file to the RC device, the second EDMA module sends a fourth interrupt signal to the EP device.
  • Another embodiment of the present disclosure provides a movable platform including: at least one sensor and the data processing device described in the previous embodiment.
  • the data processing device is connected with the sensor, and is used for receiving the sensing data of the sensor and processing the sensing data.
  • the movable platform may be a movable carrier in any environment such as ground, air, water surface, underwater, etc., such as a vehicle, a drone, and other aircraft.
  • the movable platform may also be a mobile terminal or a handheld pan/tilt.
  • the data processing device can be installed in the fuselage of the drone.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

Procédé et appareil de traitement de données basés sur un bus PCIe, et plateforme mobile. Le procédé de traitement de données comprend : l'un parmi un dispositif complexe racine et un équipement terminal utilise un bus PCIe pour transmettre des données et un fichier de description à l'autre ; après que le dispositif complexe racine transmet des premières données et un premier fichier de description associé à l'équipement terminal, le dispositif complexe racine déclenche un générateur d'interruption de telle sorte que le générateur d'interruption transmet un premier signal d'interruption à l'équipement terminal ; et après réception du premier signal d'interruption, l'équipement terminal traite les premières données selon le premier fichier de description.
PCT/CN2019/108693 2019-09-27 2019-09-27 Procédé et appareil de traitement de données basés sur un bus pcie, et plateforme mobile WO2021056458A1 (fr)

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PCT/CN2019/108693 WO2021056458A1 (fr) 2019-09-27 2019-09-27 Procédé et appareil de traitement de données basés sur un bus pcie, et plateforme mobile
CN201980033883.7A CN112189191A (zh) 2019-09-27 2019-09-27 基于PCIe总线的数据处理方法及装置、可移动平台

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