WO2021051119A2

WO2021051119A2 - Apparatus and method of layer 2 data processing using flexible layer 2 circuits

Info

Publication number: WO2021051119A2
Application number: PCT/US2020/065428
Authority: WO
Inventors: Su-Lin Low; Tianan MA; Hong Kui Yang
Original assignee: Zeku, Inc.
Priority date: 2020-12-16
Filing date: 2020-12-16
Publication date: 2021-03-18
Also published as: WO2021051119A8; CN116420346A; WO2021051119A3

Abstract

According to one aspect of the present disclosure, a baseband chip may include a plurality of Layer 2 circuits that are each configured to perform Layer 2 data processing operations associated with a first radio access technology (RAT) and a second RAT. In certain aspects, the first RAT and the second RAT may be different. The baseband chip may also include a microcontroller unit (MCU) configured to program the plurality of Layer 2 circuits to perform the Layer 2 data processing operations associated with the first RAT or the second RAT.

Description

APPARATUS AND METHOD OF LAYER 2 DATA PROCESSING USING

FLEXIBLE LAYER 2 CIRCUITS

BACKGROUND

[0001] Embodiments of the present disclosure relate to apparatus and method for wireless communication.

[0002] Wireless communication systems are widely deployed to provide various telecommunication services such as telephony, video, data, messaging, and broadcasts. A radio access technology (RAT) is the underlying physical connection method for a radio-based communication network. Many modern terminal devices, such as mobile devices, support several RATs in one device. In cellular communication, such as the 4th-generation (4G) Long Term Evolution (LTE) and the 5th-generation (5G) New Radio (NR), the 3rd Generation Partnership Project (3 GPP) defines a Radio Layer 2 (referred to here as “Layer 2”) as part of the cellular protocol stack structure corresponding to the data plane (DP) (also referred to as the “user plane”), which includes a Packet Data Convergence Protocol (PDCP) layer, a Radio Link Control (RLC) layer, and a Medium Access Control (MAC), from higher to lower in the stack. In certain wireless communication, such as Wi-Fi, the Institute of Electronics and Electrical Engineers (IEEE) Standards Committee (802.11) defines a Layer 2 as part of the Wi Fi protocol stack structure corresponding to the data plane, which includes a MAC Packet Data Unit (MPDU), a Block Acknowledgement (BA), and an Aggregate MAC Packet Data Unit (AMPDU), from higher to lower in the stack.

SUMMARY

[0003] Embodiments of apparatus and method for Layer 2 data processing are disclosed herein.

[0004] According to one aspect of the present disclosure, a baseband chip may include a plurality of Layer 2 circuits that are each configured to perform Layer 2 data processing operations associated with a first RAT and a second RAT. In certain aspects, the first RAT and the second RAT may be different. The baseband chip may also include a microcontroller unit (MCU) configured to program the plurality of Layer 2 circuits to perform the Layer 2 data processing operations associated with the first RAT or the second RAT. [0005] According to another aspect of the present disclosure, a baseband chip includes a first Layer 2 circuit configured to control MAC operations associated with a first RAT and AMPDU operations associated with a second RAT. The baseband chip may also include a second Layer 2 circuit configured to perform RLC operations associated with the first RAT and BA operations associated with the second RAT. The baseband chip may further include a third Layer 2 circuit configured to perform PDCP operations associated with the first RAT and MPDU operations associated with the second RAT.

[0006] According to another aspect of the present disclosure, a method of Layer 2 data processing may include identifying whether a data packet is associated with a first RAT or a second RAT. The method may also include programming a plurality of Layer 2 circuits to perform the Layer 2 data processing associated with the first RAT in response to determining that the data packet is associated with the first RAT. The method may further include programming the plurality of Layer 2 circuits to perform the Layer 2 data processing associated with the second RAT in response to determining that the data packet is associated with the second RAT.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

[0008] FIG. 1 illustrates an exemplary wireless network, according to some embodiments of the present disclosure.

[0009] FIG. 2 illustrates a block diagram of an apparatus including a baseband chip, a radio frequency (RF) chip, and a host chip, according to some embodiments of the present disclosure.

[0010] FIG. 3 illustrates a block diagram of an exemplary baseband chip, according to some embodiments of the present disclosure.

[0011] FIGs. 4A-4C illustrate a data flow of uplink (UL) Layer 2 data processing using the baseband chip of FIG. 3, according to some embodiments of the present disclosure.

[0012] FIGs. 5 A-5C illustrate a data flow of downlink (DL) Layer 2 data processing using the baseband chip of FIG. 3, according to some embodiments of the present disclosure. [0013] FIG. 6 illustrates a flow chart of an exemplary method for Layer 2 data processing, according to some embodiments of the present disclosure.

[0014] FIG. 7 illustrates a block diagram of an exemplary node, according to some embodiments of the present disclosure.

[0015] FIG. 8 illustrates a block diagram of a conventional baseband chip.

[0016] Embodiments of the present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

[0017] Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

[0018] It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” “certain embodiments,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

[0019] In general, terminology may be understood at least in part from usage in context.

For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context. [0020] Various aspects of wireless communication systems will now be described with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, units, components, circuits, steps, operations, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using electronic hardware, firmware, computer software, or any combination thereof. Whether such elements are implemented as hardware, firmware, or software depends upon the particular application and design constraints imposed on the overall system.

[0021] The techniques described herein may be used for various wireless communication networks, such as code division multiple access (CDMA) system, time division multiple access (TDMA) system, frequency division multiple access (FDMA) system, orthogonal frequency division multiple access (OFDMA) system, single-carrier frequency division multiple access (SC-FDMA) system, wireless local area network (WLAN) system, and other networks. The terms “network” and “system” are often used interchangeably. A CDMA network may implement a radio access technology (RAT), such as Universal Terrestrial Radio Access (UTRA), evolved UTRA (E-UTRA), CDMA 2000, etc. A TDMA network may implement a RAT, such as GSM. An OFDMA network may implement a first RAT, such as LTE or NR. A WLAN system may implement a second RAT, such as Wi-Fi. The techniques described herein may be used for the wireless networks and RATs mentioned above, as well as other wireless networks and RATs.

[0022] In cellular and/or Wi-Fi communication, Layer 2 is the protocol stack layer responsible for ensuring a reliable, error-free datalink for the wireless modem (referred to herein as a “baseband chip”) of a UE. More specifically, Layer 2 interfaces with Radio Layer 1 (also referred to as “Layer 1” or the “physical (PHY) layer”) and Radio Layer 3 (also referred to as “Layer 3” or the “Internet Protocol (IP) layer”), passing data packets up or down the protocol stack structure, depending on whether the data packets are associated with uplink (UL) or downlink (DL) transmissions.

[0023] Furthermore, Layer 2 may perform de-multiplexing / multiplexing, segmentation / reassembly, aggregation / de-aggregation, and sliding window automatic repeat request (ARQ) techniques, among others, to ensure reliable end-to-end data integrity and in-order error-free delivery of data packets. For a UL data packet, L3 data packets (e.g., IP data packets) may be input into the L2 protocol stack, and encoded into MAC layer packets (e.g., 5GNR) or AMPDU layer packets (e.g., Wi-Fi) for transporting to the PHY layer. For a DL data packet, Layer 1 data packets (e.g., PHY layer data packets) may be input into the L2 protocol stack, where Layer 2 data processing operations are performed on the data packets before being passed up to Layer 3.

[0024] Conventionally, a baseband chip may be either designed in standalone mode or multi-mode. A standalone baseband chip may be designed with a single RAT-specific protocol data stack. On the other hand, a multi-mode baseband chip may be designed with multiple RAT-specific protocol stacks. That is, a multi-mode baseband chip includes different protocol stacks, one for each RAT supported by the baseband chip.

[0025] FIG. 8 illustrates a block diagram of a conventional baseband chip 800. As seen in

FIG. 8, a conventional baseband chip 800 may include PHY subsystem 802 configured to transmit and/or receive data packets over an air interface, an L2 buffer 808 that is configured to buffer data packets between Layer 1 and Layer 2, a Layer 2 subsystem 804 that includes a limited number of Layer 2 hardware (HW) accelerators 806, a generic main processor 828 that includes Layer 2 processors and/or Layer 2 software (SW) 836 for multiple RATs, a control plane device 826 external to the Layer 2 main processor 828, Layer 3 (L3) external DDR memory 830, Layer 3 and/or Layer 4 subsystems 832, and an application processor (AP) host 834.

[0026] The conventional baseband chip 800 illustrated in FIG. 8 uses a software-centric

Layer 2 protocol data stack. Namely, the data stack processing resides on the Layer 2 main processor 828 and uses a limited number of HW accelerators 806. Using the conventional baseband chip 800, the Layer 2 main processor 828 may access a data packet by direct memory access (DMA) from a PHY layer memory at the PHY subsystem(s) 802. Furthermore, the HW accelerators 806 may DMA a UL data packet to the Layer 3 external DDR memory 830.

[0027] In conventional baseband chip 800, Layer 2 data processing, for example, processing the transport blocks received from Layer 1 (e.g., PHY subsystem 802) in the DL user plane or processing data packets received from Layer 3 in the UL user plane, is usually implemented using software modules executed on a generic baseband processor, such as a central processing unit (CPU) or a digital signal processor (DSP). During processing, data may be frequency transferred between the generic main processor 828 and external memory (e.g., Layer 3 external DDR memory or Layer 2 buffer 808), e.g., for buffering between each layer. As a result, the known solutions for Layer 2 data processing suffer from high power consumption, large data buffer, and long process delays. Furthermore, the conventional baseband chip 800 may occupy an undesirable amount of area due to the increased number of processors and/or HW accelerators 806 that are dedicated to different RATs. Still further, the different Layer 2 protocol data stacks in the conventional baseband chip 800 may be inflexible in that they may not be adaptable to changes in the 3GPP and/or IEEE 802.11 standards.

[0028] Thus, there exists an unmet need for a baseband chip that includes a single set of

Layer 2 protocol data stack components that are configurable to perform data processing operations associated with a first RAT and a second RAT.

[0029] The baseband chip of the present invention provides a solution using the same set of Layer 2 circuits, which are dynamically configurable to perform high performance, low latency Layer 2 data processing associated with multiple RATs. Furthermore, using one or more microcontroller units (MCUs), the sequence and timing trigger for each Layer 2 data processing pipeline stage can be crafted for each use case, technology, and mode using a single set of Layer 2 circuits. Using the same set of Layer 2 circuits, the baseband chip of the present disclosure uses a reduced amount of power and occupies a smaller amount of area as compared with conventional baseband chips, e.g., as described below in connection with FIGs. 1-7.

[0030] FIG. 1 illustrates an exemplary wireless network 100, in which certain aspects of the present disclosure may be implemented, according to some embodiments of the present disclosure. As shown in FIG. 1, wireless network 100 may include a network of nodes, such as a UE 102, an access node 104, and a core network element 106. User equipment 102 may be any terminal device, such as a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, or any other device capable of receiving, processing, and transmitting information, such as any member of a vehicle to everything (V2X) network, a cluster network, a smart grid node, or an Internet-of-Things (IoT) node. It is understood that user equipment 102 is illustrated as a mobile phone simply by way of illustration and not by way of limitation.

[0031] Access node 104 may be a device that communicates with user equipment 102, such as a wireless access point, a base station (BS), a Node B, an enhanced Node B (eNodeB or eNB), a next-generation NodeB (gNodeB or gNB), a cluster master node, or the like. Access node 104 may have a wired connection to user equipment 102, a wireless connection to user equipment 102, or any combination thereof. Access node 104 may be connected to user equipment 102 by multiple connections, and user equipment 102 may be connected to other access nodes in addition to access node 104. Access node 104 may also be connected to other user equipments. It is understood that access node 104 is illustrated by a radio tower by way of illustration and not by way of limitation.

[0032] Core network element 106 may serve access node 104 and user equipment 102 to provide core network services. Examples of core network element 106 may include a home subscriber server (HSS), a mobility management entity (MME), a serving gateway (SGW), or a packet data network gateway (PGW). These are examples of core network elements of an evolved packet core (EPC) system, which is a core network for the LTE system. Other core network elements may be used in LTE and in other communication systems. In some embodiments, core network element 106 includes an access and mobility management function (AMF) device, a session management function (SMF) device, or a user plane function (UPF) device, of a core network for the NR system. It is understood that core network element 106 is shown as a set of rack-mounted servers by way of illustration and not by way of limitation.

[0033] Core network element 106 may connect with a large network, such as the Internet

108, or another Internet Protocol (IP) network, to communicate packet data over any distance. In this way, data from user equipment 102 may be communicated to other user equipments connected to other access points, including, for example, a computer 110 connected to Internet 108, for example, using a wired connection or a wireless connection, or to a tablet 112 wirelessly connected to Internet 108 via a router 114. Thus, computer 110 and tablet 112 provide additional examples of possible user equipments, and router 114 provides an example of another possible access node.

[0034] A generic example of a rack-mounted server is provided as an illustration of core network element 106. However, there may be multiple elements in the core network including database servers, such as a database 116, and security and authentication servers, such as an authentication server 118. Database 116 may, for example, manage data related to user subscription to network services. A home location register (HLR) is an example of a standardized database of subscriber information for a cellular network. Likewise, authentication server 118 may handle authentication of users, sessions, and so on. In the NR system, an authentication server function (AUSF) device may be the specific entity to perform user equipment authentication. In some embodiments, a single server rack may handle multiple such functions, such that the connections between core network element 106, authentication server 118, and database 116, may be local connections within a single rack.

[0035] Each element in FIG. 1 may be considered a node of wireless network 100. More detail regarding the possible implementation of a node is provided by way of example in the description of a node 700 in FIG. 7. Node 700 may be configured as user equipment 102, access node 104, or core network element 106 in FIG. 1. Similarly, node 700 may also be configured as computer 110, router 114, tablet 112, database 116, or authentication server 118 in FIG. 1. As shown in FIG. 7, node 700 may include a processor 702, a memory 704, and a transceiver 706. These components are shown as connected to one another by a bus, but other connection types are also permitted. When node 700 is user equipment 102, additional components may also be included, such as a user interface (UI), sensors, and the like. Similarly, node 700 may be implemented as a blade in a server system when node 700 is configured as core network element 106. Other implementations are also possible.

[0036] Transceiver 706 may include any suitable device for sending and/or receiving data.

Node 700 may include one or more transceivers, although only one transceiver 706 is shown for simplicity of illustration. An antenna 708 is shown as a possible communication mechanism for node 700. Multiple antennas and/or arrays of antennas may be utilized. Additionally, examples of node 700 may communicate using wired techniques rather than (or in addition to) wireless techniques. For example, access node 104 may communicate wirelessly to user equipment 102 and may communicate by a wired connection (for example, by optical or coaxial cable) to core network element 106. Other communication hardware, such as a network interface card (NIC), may be included as well.

[0037] As shown in FIG. 7, node 700 may include processor 702. Although only one processor is shown, it is understood that multiple processors can be included. Processor 702 may include microprocessors, MCUs, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout the present disclosure. Processor 702 may be a hardware device having one or more processing cores. Processor 702 may execute software. Software shall be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software modules, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Software can include computer instructions written in an interpreted language, a compiled language, or machine code. Other techniques for instructing hardware are also permitted under the broad category of software.

[0038] As shown in FIG. 7, node 700 may also include memory 704. Although only one memory is shown, it is understood that multiple memories can be included. Memory 704 can broadly include both memory and storage. For example, memory 704 may include random- access memory (RAM), read-only memory (ROM), static RAM (SRAM), dynamic RAM (DRAM), ferro-electric RAM (FRAM), electrically erasable programmable ROM (EEPROM), CD-ROM or other optical disk storage, hard disk drive (HDD), such as magnetic disk storage or other magnetic storage devices, Flash drive, solid-state drive (SSD), or any other medium that can be used to carry or store desired program code in the form of instructions that can be accessed and executed by processor 702. Broadly, memory 704 may be embodied by any computer-readable medium, such as a non-transitory computer-readable medium.

[0039] Processor 702, memory 704, and transceiver 706 may be implemented in various forms in node 700 for performing wireless communication functions. In some embodiments, processor 702, memory 704, and transceiver 706 of node 700 are implemented (e.g., integrated) on one or more system-on-chips (SoCs). In one example, processor 702 and memory 704 may be integrated on an application processor (AP) SoC (sometimes known as a “host,” referred to herein as a “host chip”) that handles application processing in an operating system (OS) environment, including generating raw data to be transmitted. In another example, processor 702 and memory 704 may be integrated on a baseband processor (BP) SoC (sometimes known as a “modem,” referred to herein as a “baseband chip”) that converts the raw data, e.g., from the host chip, to signals that can be used to modulate the carrier frequency for transmission, and vice versa, which can run a real-time operating system (RTOS). In still another example, processor 702 and transceiver 706 (and memory 704 in some cases) may be integrated on an RF SoC (sometimes known as a “transceiver,” referred to herein as an “RF chip”) that transmits and receives RF signals with antenna 708. It is understood that in some examples, some or all of the host chip, baseband chip, and RF chip may be integrated as a single SoC. For example, a baseband chip and an RF chip may be integrated into a single SoC that manages all the radio functions for cellular communication. [0040] Referring back to FIG. 1, in some embodiments, any suitable node of wireless network 100 (e.g., user equipment 102 or access node 104) in transmitting signals to another node, for example, from user equipment 102 to access node 104 via, or vice versa, may process Layer 2 data packets for a first RAT and a second RAT using the same set of Layer 2 circuits (sometimes controlled by an MCU) on a baseband chip, as described below in detail. As a result, compared with known solutions in which Layer 2 data is processed using software modules implemented on a generic processor in conjunction with the system memory, the data speed can be improved due to hardware acceleration, the chip cost can be reduced by reducing memory usage, and the power consumption can be decreased as well.

[0041] FIG. 2 illustrates a block diagram of an apparatus 200 including a baseband chip

202, an RF chip 204, and a host chip 206, according to some embodiments of the present disclosure. Apparatus 200 may be an example of any suitable node of wireless network 100 in FIG. 1, such as user equipment 102 or access node 104. As shown in FIG. 2, apparatus 200 may include baseband chip 202, RF chip 204, host chip 206, and one or more antennas 210. In some embodiments, baseband chip 202 is implemented by processor 702 and memory 704, and RF chip 204 is implemented by processor 702, memory 704, and transceiver 706, as described above with respect to FIG. 7. Besides the on-chip memory (also known as “internal memory,” e.g., registers, buffers, or caches) on each chip 202, 204, or 206, apparatus 200 may further include an external memory 208 (e.g., the system memory or main memory) that can be shared by each chip 202, 204, or 206 through the system/main bus. Although baseband chip 202 is illustrated as a standalone SoC in FIG. 2, it is understood that in one example, baseband chip 202 and RF chip 204 may be integrated as one SoC; in another example, baseband chip 202 and host chip 206 may be integrated as one SoC; in still another example, baseband chip 202, RF chip 204, and host chip 206 may be integrated as one SoC, as described above.

[0042] In the uplink, host chip 206 may generate raw data and send it to baseband chip 202 for encoding, modulation, and mapping. Baseband chip 202 may also access the raw data generated by host chip 206 and stored in external memory 208, for example, using the direct memory access (DMA). Baseband chip 202 may first encode (e.g., by source coding and/or channel coding) the raw data and modulate the coded data using any suitable modulation techniques, such as multi-phase pre-shared key (MPSK) modulation or quadrature amplitude modulation (QAM). Baseband chip 202 may perform any other functions, such as symbol or layer mapping, to convert the raw data into a signal that can be used to modulate the carrier frequency for transmission. In the uplink, baseband chip 202 may send the modulated signal to RF chip 204. RF chip 204, through the transmitter (Tx), may convert the modulated signal in the digital form into analog signals, i.e., RF signals, and perform any suitable front-end RF functions, such as filtering, up-conversion, or sample-rate conversion. Antenna 210 (e.g., an antenna array) may transmit the RF signals provided by the transmitter of RF chip 204.

[0043] In the downlink, antenna 210 may receive RF signals and pass the RF signals to the receiver (Rx) of RF chip 204. RF chip 204 may perform any suitable front-end RF functions, such as filtering, down-conversion, or sample-rate conversion, and convert the RF signals into low-frequency digital signals (baseband signals) that can be processed by baseband chip 202. In the downlink, baseband chip 202 may demodulate and decode the baseband signals to extract raw data that can be processed by host chip 206. Baseband chip 202 may perform additional functions, such as error checking, de-mapping, channel estimation, descrambling, etc. The raw data provided by baseband chip 202 may be sent to host chip 206 directly or stored in external memory 208.

[0044] In some embodiments, one or more of the component of apparatus 200 (e.g., baseband chip 202, RF chip 204, host chip 206, external memory 208, etc.) may process Layer 2 data packets for a first RAT and a second RAT using the same set of Layer 2 circuits (sometimes controlled by an MCU) on a baseband chip, as described below in detail. As a result, compared with known solutions in which Layer 2 data is processed using software modules implemented on a generic processor in conjunction with the system memory, the data speed can be improved due to hardware acceleration, the chip cost can be reduced by reducing memory usage, and the power consumption can be decreased as well.

[0045] FIG. 3 illustrates a block diagram of an exemplary baseband chip 300, according to some embodiments of the present disclosure. Baseband chip 300 may be of a node, either UE 102 or access node 104, that implements a protocol stack defined in the standards, for example, by the 3GPP or by IEEE 802.11, which includes a set of network protocol layers that work together to provide networking capabilities.

[0046] In certain implementations, the baseband chip 300 may be dynamically programmed to perform operations associated with Layer 2 data processing for a first RAT and a second RAT using the same set of Layer 2 circuits 312 and/or Layer 2 engines 316. In certain implementations, a plurality of MCUs (uC) 306 may program the Layer 2 circuits 312 and/or the Layer 2 engines 316 to perform Layer 2 data processing of a first RAT data path (e.g., 5G NR) and a second RAT data path (e.g., Wi-Fi 5, Wi-Fi 6, Wi-Fi 7, Wi-Fi 8, and beyond). Moreover, the baseband chip 300 may support concurrent 5G + Wi-Fi mode, or 5G / Wi-Fi selective mode with dynamic command interfaces and stateless processing. In certain other implementations, the baseband chip 300 may be configured to operate as standalone 5G only mode or Wi-Fi only mode.

[0047] Referring to FIG. 3, the baseband chip 300 may include, among others, a first PHY subsystem 302a associated with a first RAT (e.g., 5G NR), a second PHY subsystem 302b associated with a second RAT (e.g., Wi-Fi), a Layer 2 subsystem 304, a control plane circuit 326, a main processor 328, a DDR memory 330, a Layer 2 quality of service (QoS) queue(s) 336, Layer 3 and Layer 4 circuit(s) 332, and an application processor (AP) host 334. The Layer 2 subsystem 304 may include, among others, a plurality of MCUs (e.g., uC), a plurality of Layer 2 circuits 312, and a plurality of Layer 2 engines 316.

[0048] The plurality of MCUs 306 (hereinafter, “MCUs” or “uC”) may include, among others, an MCU cluster, a UL scheduler, and a DL director. More specifically, the MCUs 306 may include a UL uC cluster 308a and a DL uC cluster 308b. The MCUs 306 may include a set of functions (e.g., UL functions and DL functions), which may configure the Layer 2 circuits 312, as well as a UL scheduler (see FIGs. 4A-4C), a DL director (see FIGs. 5A-5C), and routing tasks. These UL and DL functions may control the Layer 2 circuits 312 and Layer 2 engine(s) 316 through Command / Status queues 310a and 310b, respectively. Each command may contain a command descriptor with specific parameters or instructions for a data packet. When a Layer 2 circuit 312 completes the processing a data packet, the Layer 2 circuit may output the status of the data packet in the Command / Status queue 310a and 310b. The MCUs 306 may process the status descriptor and decide how to continue to the next pipeline stage of the Layer 2 processing of the data packet. The Layer 2 pipeline stages in 5G NR include, e.g., a MAC layer stage, an RLC layer stage, and a PDCP layer stage. The Layer 2 pipeline stages in Wi-Fi including, e.g., an AMPDU layer stage, a BA layer stage, and an MPDU layer stage. In response to determining how to continue to the next pipeline stage, the MCUs 306 may send a signal to one or more of, e.g., the UL Command / Status queue 310a, the DL Command / Status queue 310b, one or more of the Layer 2 circuits 312, and/or one or more of the Layer 2 engines 316.

[0049] The MAC AMPDU circuit 314a may perform Layer 2 data processing operations associated with the lower layer in the Layer 2 protocol stack for both the first RAT and the second RAT. More specifically, the MAC_AMPDU circuit 314a may perform MAC layer processing of the Layer 2 protocol, which may include multiplexing / de-multiplexing, header extraction or generation of the MAC layer packet data units (PDUs) for both the first RAT and the second RAT. Moreover, the MAC AMPDU circuit 314a may interface with the PHY subsystems 302a, 302b to send / receive data packets (e.g., data byte streams). Furthermore, the MAC AMPDU circuit 314a may coordinate operations associated with a first set of the Layer 2 engines 316.

[0050] The RLC BA circuit 314b may perform Layer 2 data processing operations associated with the middle layer of the Layer 2 protocol stack for both the first RAT and the second RAT. More specifically, the RLC BA circuit 314b may be responsible for RLC or BA layer processing of the Layer 2 protocols for 5GNR and Wi-Fi, respectively. For example, the RLC BA circuit 314b may perform functions to ensure reliable data delivery such as ARQ, window checking, sliding window movement, duplicate, and out-of-window discards using bitmaps to track the data packets deliveries. Additionally and/or alternatively, the RLC BA circuit 314b may also perform segmentation and reassembly of segmented radio frames, subframes, data packets, etc. In certain implementations, the RLC BA circuit 314b may perform aggregation and de-aggregation of radio frames, subframes, PDUs, service data units (SDUs), data packets, etc. Namely, the RLC BA circuit 314b may coordinate operations associated with a second set of the Layer 2 engines 316.

[0051] The PDCP MDPU circuit 314c may perform Layer 2 data processing operations associated with the upper layer of the Layer 2 protocol stack associated with both the first RAT and the second RAT. More specifically, the PDCP MPDU circuit 314c may perform PDU packet processing of the extracted user data packet, which may include an IP Layer 3 data packet. The functions of the PDCP MPDU circuit 314b may include, among others, ciphering / deciphering, integrity / de-integrity, data compression, Robust Header Compression (ROHC), and re-ordering operations before delivery to Layer 3 for DL cases or to the RLC B A circuit 314b for UL cases. Depending on whether the operations are related to the first RAT or the second RAT, as well as the mode (e.g., 5G standalone mode, Wi-Fi standalone mode, concurrent 5G and Wi-Fi multi-mode, dynamic 5G or Wi-Fi mode), the PDCP MPDU circuit 314c may perform second level aggregation / de-aggregation of service data units (SDUs), where the SDUs may be aggregated for optimal high throughput. Namely, the PDCP MDPU 314c may coordinate operations associated with a third set of the Layer 2 engines 316. [0052] The Layer 2 engines 316 may include a plurality of hardware engines, which may be dynamically triggered in any order by the Layer 2 circuits 314a, 314b, 314c or by the MCUs 306, depending on the mode of operation. More specifically, the Layer 2 engine 316 may include, among others, a multiplexing engine 318a, a de-multiplexing engine 318b, a header generation engine 318c, a header extraction engine 318d, a segmentation engine 320a, a reassembly 320b, a window operation engine 320c, a decipher / de-integrity engine 322a, a cipher / integrity engine 322b, a ROHC engine 322c, a re-ordering engine 322d, a data compression engine 322e, an aggregation engine 322f, and a de-aggregation engine 322g. Each of the plurality of hardware engines may be a stateless, modular Layer 2 hardware unit block. Each of the Layer 2 engines 316 may be a packet processing engine that performs specific functions generic to a first RAT and a second RAT. The UL uC cluster 308a and/or the DL uC cluster 308b may link together the entire Layer 2 data packet processing pipeline chain, by commanding each of the plurality of Layer 2 engines 316 to run their specific per data packet operation in the packet processing pipeline. Additional details describing each of the plurality of Layer 2 engines 316 is set forth below.

[0053] The header extraction engine 318d may extract the header of one or more data packets from the PHY subsystem 302a or 302b. More specifically, the header extraction engine 318d may extract the header according to a lookup table with indices that include, among others, the RAT type (e.g., 5GNR, Wi-Fi, LTE, 3G, Bluetooth, etc.), the identity of the logical channel, the radio bearer identity, MAC subframe type, just to name a few. Using the extracted header and the lookup table, the header extraction engine 318d may identify, among others, a specific decode template associated with the received data packet. Upon extraction of the header, the header extraction engine 318d may update the UL Command / Status queue 310a to indicate the header is extracted.

[0054] The multiplex engine 318a may multiplex multiple PDUs together from different locations indicated by the input data buffer pointers, and triggers DMA engines (not shown) to move data packets to the inline buffer 324. In certain implementations, the multiplex engine 318a may interface with the PHY layer (e.g., PHY subsystem 302a or 302b) to transport packet data.

[0055] The de-multiplex engine 318b de-multiplexes incoming PHY code blocks, data packets, or data frames. Furthermore, de-multiplex engine 318b may perform inline buffer management to re-order the incoming PHY code blocks and stream the re-ordered PHY code blocks out for the next pipeline stage processing, or store the re-ordered PHY code blocks in an external memory.

[0056] The header generation engine 318c may accept input index parameters for the lookup table and header fields. Moreover, the header generation engine 318c may generate the header that is included in the UL data packet.

[0057] The segmentation engine 320a may segment an input data packet into one or more segment packets according to the grant size of the transport data packet. Moreover, the segmentation engine 320a may output the header fields of all segments after segmentation.

[0058] The reassembly engine 320b may check the corresponding packet sequence numbers and offsets for an incoming input segment packet and reassemble the original packet. In certain implementations, the reassembly engine 320b may look up the format of the segmented packet header may be looked up using input indexing parameters, e.g., such as the logical channel identification, the mode, and the type of RAT, for example.

[0059] The window operation engine 320c may perform sliding window ARQ procedures to ensure reliable data delivery. The sliding window ARQ procedures include, among others, duplicate packet check and discard, out-of-window check and discard, bitmap update when a packet is received, generating ARQ acknowledgements and status reports that may be sent to the communicating node (e.g., Wi-Fi node, base station, gNB, eNB, IoT device, etc.), processing ARQ acknowledgements and status reports received from the communicating node, performing a window sliding operation by updating the upper and lower bound variable of the sliding window, managing the abort timer, just to name a few.

[0060] The decipher / de-integrity engine 322a may decipher incoming data packets (e.g., incoming byte streams), according to input keys, sequence numbers, and any other decipher inputs. Additionally and/or optionally, the decipher / de-integrity engine 322a may perform an integrity check and output the status of the decipher / de-integrity procedures, e.g., to the DL Command / Status queue 310b.

[0061] The cipher / integrity engine 322b may cipher incoming data packets (e.g., incoming byte streams), according to input keys, sequence numbers, and any other cipher inputs. Additionally and/or optionally, cipher / integrity engine 322b may perform an integrity check, and output the status and integrity bits of the cipher / integrity operations to, e.g., the UL Command / Status queue 310a. [0062] The ROHC engine 322c may receive Layer 3 data packets as an input. Moreover, the ROHC engine 322c may perform IP header compression associated with ROHC operations defined by, e.g., the ROHC standard. The IP header parameters on which the ROHC engine 322c may perform IP header compression include, among others, one or more of a context identification (ID) (contextID) and/or the packet sequencelD, e.g., such as the packet count value in the 5G NR PDCP layer of the Layer 2 data protocol stack. Additionally and/or alternatively, the output compressed header may be written to a location buffer specified by the MCUs 306.

[0063] The re-ordering engine 322d may re-order DL data packets that have been received from a communicating node and checked in the bitmap such that the DL data packets are delivered to Layer 3 in order.

[0064] The data compression engine 322e may perform data compression on incoming data packets (e.g., incoming byte streams). Moreover, the data compression engine 322e may output compressed data packets (e.g., compressed bytes). For optimized high throughput performance, the incoming data packets may be routed to the data compression engine 322e from other engine(s) in the Layer 2 engine 316, e.g., such as the cipher / integrity engine 322b. Additionally and/or alternatively, the data compression engine 322e may route the compressed data to other engines(s) in the Layer 2 engine 316, e.g., such as the cipher / integrity engine 322b.

[0065] The aggregation engine 322f may aggregate PDUs according to operations associated with the first RAT and the second RAT. Furthermore, the aggregation engine 322f may aggregate PDUs based at least in part on the input grant size. Aggregation of PDUs may occur more than once in the packet processing pipeline chain. For example, when performing operations associated with Wi-Fi, two different levels of aggregation may occur for the MAC SDU (MSDU) and MPDU.

[0066] The de-aggregation engine 322g may perform de-aggregation of aggregated PDUs to extract each PDU in the aggregation. The extracted PDUs may be output one at a time to the DL Command / Status queue 310b.

[0067] FIGs. 4A-4C illustrate a data flow 400 that may be used to perform UL Layer 2 data processing for a first RAT and a second RAT, according to certain aspects of the disclosure. The data flow 400 illustrated in FIGs. 4A-4C may be performed by, e.g., the baseband chip 300 of FIG. 3. In FIGs. 4A-4C, operations 409-455 may be associated with UL Layer 2 data processing for the 5G NR (e.g., the first RAT), and operations 457-475 may be associated with UL Layer 2 data processing for Wi-Fi (e.g., the second RAT).

[0068] Referring to FIG. 4A, the control plane circuit 326 may perform (at 401) a RAT system selection process. Namely, the control plane circuit 326 may determine whether to perform UL Layer 2 data processing for 5G NR or Wi-Fi communication. The control plane circuit 326 may send (at 403) Layer 2 configuration information (L2_Config) that indicates to the configuration unit 340 of the UL uC cluster 308a. The UL uC cluster 308a may send (at 405a, 405b, 405c, respectively) a Layer 2 configuration command (L2_ConfigCmd) to each of the PDCP MPDU circuit 314c, the RLC BA 314b, and the MAC AMPDU 314a. The L2_ConfigCmd may program the MAC AMPDU circuit 314a, the RLC BA circuit 314b, and the PDCP MPDU circuit 314c to perform operations associated with Layer 2 data processing of the first RAT (e.g., 5G NR) or the second RAT (e.g., Wi-Fi).

[0069] The Layer 3 circuit 332 may send (at 407) a Layer 3 IP data packet to the Layer 2

QoS queue(s) 336, which may be located at the DDR memory 330 or remote from the DDR memory 330. The Layer 2 QoS queue(s) 336 may maintain and/or store incoming and/or outgoing data packet descriptors, between the Layer 2 and Layer 3 applications The Layer 3 IP data packet may undergo Layer 2 data processing prior to being sent to a PHY subsystem 302a, 302b.

5G UL Data Processing

[0070] When the L2_Config sent (at 403) indicates that the Layer 2 data processing is associated with 5G NR, the data flow 400 moves from operation 407 to operation 409 in FIG. 4A. The pipeline stages associated with 5G UL Layer 2 data processing includes a PDCP stage, an RLC stage, and a MAC stage, as set forth below.

[0071] Referring to FIG. 4A, a scheduler 342 of the UL uC cluster 308a may receive (at

409) a UL resource grant from the PHY subsystem 302a. Upon UL grant arrival from the base station through the Downlink Control Information (DCI) in the physical downlink control channel (PDCCH), the UL uC cluster 308a may process the grant information and performs Logical Channel Prioritization (LCP) priority scheduling of UL packets from the Layer 2 QoS queue(s) 336. Each logical channel may be allocated grant resources (e.g., bytes) based on the LCP algorithm until the UL resource grant is exhausted. The UL scheduler 342 may ensure that the low latency data packets are given the highest priority to proceed to the next pipeline stage first. The UL resource grant may also provide the time at which the UL packets may be sent to the PHY subsystem 302a for encoding and transmission over the air. Upon connection establishment with the base station, all necessary bearer, logical channels, ARQ mode configurations, and carrier channels parameters may be configured and stored in lookup tables accessible by each of the PDCP MPDU circuit 314c, the RLC BA 314b, and the MAC AMPDU 314a.

[0072] After dequeuing a data packet from the Layer 2 QoS queue(s) 336, the UL uC cluster 308a may prepare the data packet to be sent to the Layer 2 circuits 312 and/or Layer 2 engines 316 for 5G NR Layer 2 data processing. For example, the UL uC cluster 308a may decide if PDCP processing should be performed on the data packet. If so, the UL uC cluster may enqueue a PDCP command (PDCP Cmd) descriptor that may be sent (at 417) to the PDCP MPDU circuit 314c. The PDCP Cmd descriptor may include, among others, the data packet Sequence Number, ciphering / integrity algorithm and parameters, and ROHC or data compression parameters. The PDCP MPDU circuit 314c may process the PDCP Cmd and instruct the ROHC engine 322c, data compression engine 322e, and/or ciphering / integrity engine 322b to perform their respective operations on the data packet. Once this task is complete, the PDCP MPDU circuit 314c may send (at 419) the PDCP status complete (PDCP Status) to the UL Command / Status queue 310a and/or scheduler 342 in the UL uC cluster 308a for further processing. The PDCP MPDU circuit 314c may send the PDCP processed data packet to the RLC BA circuit 314b.

[0073] The UL uC cluster 308a may determine parameters and functions associated with the next pipeline stage, e.g., RLC stage. In certain implementations, such as Unacknowledgement (UACK) mode (UM), the UL uC cluster 308a may determine that segmentation may be relevant. In certain other implementations, such as acknowledgement (ACK) mode (AM), the UL uC clusters 308a may determine that one or more of sliding window operations, segmentation, and/or aggregation may be relevant. Status reporting using a bitmap may also be determined to be sent to the base station. The UL uC cluster 308a may send an RLC command descriptor (RLC Cmd) (at 421) to the RLC BA circuit 314b (e.g., via the UL Command / Status queue 310a), where the RLC Cmd may trigger the sequence of operations performed by, e.g., one or more of window operation engine 320c, aggregation engine 322f, and/or segmentation engine 320a. Referring to FIG. 4B, upon completion of the RLC operations, the RLC BA engine 314b may send (at 423) an RLC Status signal to UL Command / Status queue 310a and/or scheduler 342 in the UL uC cluster 308a. The RLC processed data packet may be sent to the MAC AMPDU circuit 314a.

[0074] Finally, at the last pipeline stage, the UL uC cluster 308a enqueue an RLC command descriptor (MAC Cmd) to the UL Command / Status queue 310a. The MAC AMPDU circuit 314a may receive and/or access (at 425) the MAC_Cmd from the UL Command / Status queue 310a. The MAC Cmd may command the MAC AMPDU circuit 314a to instruct, e.g., the multiplex engine 318a and/or header generation engine 318c to perform MAC layer operations on the data packets (e.g., MAC PDUs). The header parameters may be included in the MAC Cmd, or the MAC AMPDU circuit 314a may access a lookup table that indicates the header parameters based on given logical channel and radio bearer identities. After generating the headers and multiplexing the packet byte streams, the MAC AMPDU circuit 314a may send (at 427) the MAC_Status to the UL uC cluster 308a. Moreover, the MAC_AMPDU 314a may send (at 429) the Layer 2 data packets (e.g., data byte stream) to the PHY subsystem 302a via the inline buffer 324.

Wi-Fi UL Data Processing

[0075] When the L2_Config sent (at 403) indicates that the Layer 2 data processing is associated with Wi-Fi, the data flow 400 moves from operation 407 in FIG. 4A to operation 455 in FIG. 4B.

[0076] Referring to Fig. 4B, upon receiving (at 455) the UL resource grant from the Wi-Fi node, the UL uC cluster 308a may perform (at 457) transmission prioritized scheduling of UL data packets from the Layer 2 QoS queue(s) 336 until the grant is exhausted. The UL scheduler 342 ensures that the low latency packets are given the highest priority to proceed to the next pipeline stage first. The UL resource grant may also provide the time at which the UL Layer 2 data packets should be sent to the PHY subsystem 302b for encoding and transmission over the air. The Layer 3 circuit 332 may send (at 459) an IP data packet to the DDR memory 330. The IP data packet (hereinafter, “data packet”) may be sent (at 461) to the Layer 2 QoS queue(s) 336.

[0077] After dequeuing a data packet from the Layer 2 QoS queue(s) 336, the UL uC cluster 308a may prepare the data packet to be sent to the Layer 2 circuits 312 and/or Layer 2 engines 316 for Wi-Fi Layer 2 data processing. For example, the UL uC cluster 308a may determine whether cipher / integrity operations and/or data compression should be performed on the data packet. Additionally and/or optionally, the UL uC cluster 308a may determine whether to aggregate the data packet at the AMSDU layer. The UL uC cluster 308a may generate an MSDU command (MPDU Cmd) descriptor that is sent (at 463) to the PDCP MDPU circuit 314c. The MPDU Cmd descriptor may include, among others, the data packet Sequence Number, ciphering / integrity algorithm and parameters, ROHC parameters, data compression parameters. Optionally, the MPDU Cmd may include aggregation parameters when the UL uC cluster 308a determines that aggregation of the data packet at the MPDU level. The PDCP MPDU circuit 314c may process the MPDU Cmd and instruct one or more of, e.g., the ROHC engine 322c, data compression engine 322e, ciphering / integrity engine 322b, and/or the aggregation engine 322f to perform their respective operations on the data packet. Once this task is complete, the PDCP MPDU circuit 314c may send (at 465) the MPDU status complete (MPDU Status) to the UL Command / Status queue 310a and/or scheduler 342 in the UL uC cluster 308a. The PDCP MPDU circuit 314c may send the MDPU processed data packet to the RLC BA circuit 314b.

[0078] The UL uC cluster 308a may determine whether to perform BA on the data packet at the BA level. Upon determining to perform BA, the UL uC cluster 308a may generate a BA command descriptor (BA Cmd) to the RLC BA circuit 314b. The BA Cmd may include, among others, the data packet sequence number and/or window operation parameters. The RLC BA circuit 314b may process the BA Cmd and instruct, among others, the window operation engine 320c to perform its respective operations on the data packet. Additionally and/or alternatively, the RLC BA circuit 314b may update and/or generate a bitmap status of the data packets that will be sent to the Wi-Fi node. In either case, referring to FIG. 4C, the RLC BA circuit 314b may send (at 469) a BA status complete (BA Status) to the UL Command / Status queue 310a and/or the scheduler 342 in the UL uC cluster 308a.

[0079] The UL uC cluster 308a may determine whether to perform segmentation on the data packet at the AMPDU level. The UL uC cluster 308a may enqueue an AMPDU command descriptor (AMPDU Cmd) into the UL Command / Status queue 310a. The AMPDU Cmd may include, among others, header generate parameters, aggregation parameters, segmentation parameters, and/or multiplexing parameters. The AMPDU Cmd may be accessed and/or received (at 471) by the MAC_AMPDU circuit 314a. The MAC_AMPDU circuit 314a may process the AMPDU Cmd and instruct, among others, the header generation engine 318c, the aggregation engine 322f, the segmentation engine 320a, and the multiplex engine 318a to perform their respective functions on the data packet. The MAC AMPDU circuit 314a may send (at 473) an AMPDU status complete (AMPDU Status) to the UL Command / Status queue 310a and/or the scheduler 342 in the UL uC cluster 308a. The Layer 2 data packet may be sent (at 475) to the PHY subsystem 302b.

[0080] FIGs. 5 A-5C illustrate a data flow 500 that may be used to perform DL Layer 2 data processing for a first RAT and a second RAT, according to certain aspects of the disclosure. The data flow 500 illustrated in FIGs. 5A-5C may be performed by, e.g., the baseband chip 300 of FIG. 3. In FIGs. 5A-5C, operations 507-527 may be associated with DL Layer 2 data processing for the 5G NR. (e.g., the first RAT), and operations 529-549 may be associated with DL Layer 2 data processing for Wi-Fi (e.g., the second RAT).

[0081] Referring to FIG. 5A, the control plane circuit 326 may perform (at 501) a RAT system selection process. Namely, the control plane circuit 326 may determine whether to perform DL Layer 2 data processing for 5G NR or Wi-Fi communication. The control plane circuit 326 may send (at 503) Layer 2 configuration information (L2_Config) that indicates to the configuration unit 340 of the DL uC cluster 308b whether to perform DL Layer 2 data processing operations associated with 5G NR or Wi-Fi. The DL uC cluster 308b may send (at 505a, 505b, 505c, respectively) a Layer 2 configuration command (L2_ConfigCmd) to each of the PDCP MPDU circuit 314c, the RLC B A circuit 314b, and the MAC AMPDU circuit 314a.

5G DL Data Processing

[0082] The DL uC cluster 308b may generate a MAC command descriptor (MAC Cmd) that is sent (at 507) to the MAC_AMPDU circuit 314a. The MAC_Cmd may include, among others, relevant carrier and channel information that may enable the header extraction engine 318d to lookup the data packet format for decoding. The data packet (e.g., one or more code blocks (CBs) or data byte streams) may be sent (at 509) from the PHY subsystem 302a to the header extraction engine 318d via the inline buffer 324. The header extraction engine 318d may extract packet descriptors, e.g., header parameters, logical channel ID, lookup table- specific decode format for the subsequent layers (e.g., RLC and PDCP). The data packets may be sent from the header extraction engine 318d to the de-multiplex engine 318b, which de multiplexes the data packet(s). The de-multiplex engine 318b may send (at 511) the packet descriptors in a, e.g., MDPU control packet to the MAC AMPDU 314a. The MAC AMPDU circuit 314a may send (at 513) a MAC status complete (MAC Status) to the DL Command / Status queue 310b and/or the director 344 of the DL uC cluster 308b. The PHY subsystem 302a may send one or more data packets to the inline buffer 324, which may send (at 515) the data packet(s) to the MAC AMPDU circuit 314a.

[0083] The DL uC clusters 308b may send (at 517) an RLC command descriptor

(RLC Cmd) to the RLC BA circuit 314b. The RLC Cmd may include, among others, data packet sequence number, window operation parameters, de-aggregation parameters, and reassemble parameters. The RLC BA circuit 314b may instruct, among others, one or more of the de-aggregation engine 322g, the reassembly engine 320b, and/or the window operation engine 320c to perform their respective operations on the data packet. Upon completion, the RLC BA circuit 314b may send (at 519) an RLC status complete (RLC Status) to the DL Command / Status queue 310b and/or the director 344 of the DL uC cluster 308b. The RLC BA circuit 314b may send the data packet(s) to the PDCP MPDU circuit 314c.

[0084] Referring to FIG. 5B, the DL uC cluster 308b may enqueue a PDCP command descriptor (PDCP Cmd) in the DL Command / Status queue 310b. The PDCP Cmd may include, among others, a data packet sequence number, decipher parameters, de-integrity parameters, ROHC parameters, window operation parameters, and/or re-ordering parameters. The PDCP MPDU circuit 314c may access and/or receive the PDCP Cmd from the DL Command / Status queue 310b. The PDCP MPDU circuit 314c may instruct, among others, one or more of the decipher / de-integrity engine 322a, the ROHC engine 322c, the window operations engine 320c, and/or the re-ordering engine 322d to perform their respective operations. Upon completion, the PDCP MPDU circuit 314c may send (at 523) a PDCP status complete (PDCP Status) to the DL Command / Status queue 310b and/or the director 344 of the DL uC cluster 308b.

[0085] The DL uC cluster 308b may send the packet descriptors to the Layer 2 QoS queue(s) 336 for retrieval (at 525) by the Layer 3 circuit 332. The data packet payloads may be sent (at 527) from internal buffers at the L2 circuits 312 and L2 engines 316 to the DDR memory 330. The Layer 3 circuit 332 may retrieve the data packet payloads from the DDR memory 330.

Wi-Fi DL Data Processing

[0086] The DL uC cluster 308b may generate an AMPDU command descriptor

(AMPDU Cmd) that is sent (at 529) to the MAC AMPDU circuit 314a. The AMPDU Cmd may include, among others, relevant carrier and channel information that may enable the header extraction engine 318d to lookup the AMPDU frame format and/or AMPDU subframe format for decoding. The data packet (e.g., one or more code blocks (CBs) or data byte streams) may be sent (at 531) from the PHY subsystem 302b to the header extraction engine 318d via the inline buffer 324. The header extraction engine 318d may extract packet descriptors, e.g., header parameters, logical channel ID, lookup table-specific decode format for the subsequent layers (e.g., BA and MPDU), and to continue the process for the AMPDU, MPDU, AMSDU, and MSDU. The data packets may be sent from the header extraction engine 318d to the de multiplex engine 318b, which de-multiplexes the data packet(s). The de-multiplex engine 318b may send (at 533) the packet descriptors in a, e.g., MDPU control packet to the MAC AMPDU 314a. The MAC_AMPDU circuit 314a may send (at 535) an AMPDU status complete (AMPDU Status) to the DL Command / Status queue 310b and/or the director 344 of the DL uC cluster 308b. The PHY subsystem 302a may send one or more data packets to the inline buffer 324, which may send (at 537) the data packet(s) to the MAC_AMPDU circuit 314a.

[0087] The DL uC clusters 308b may send (at 539) a BA command descriptor (BA Cmd) to the RLC BA circuit 314b. The BA Cmd may include, among others, data packet sequence number and window operation parameters. The RLC BA circuit 314b may instruct, among others, the window operation engine 320c to perform its respective operations on the data packet. Upon completion, referring to FIG. 5C, the RLC BA circuit 314b may send (at 519) a BA status complete (BA Status) to the DL Command / Status queue 310b and/or the director 344 of the DL uC cluster 308b. The RLC BA circuit 314b may send the data packet(s) to the PDCP MPDU circuit 314c.

[0088] The DL uC cluster 308b may enqueue an MDPU command descriptor

(MPDU Cmd) in the DL Command / Status queue 310b. The MPDU Cmd may include, among others, a data packet sequence number, decipher parameters, de-integrity parameters, de-aggregate parameters, and/or re-ordering parameters. The PDCP MPDU circuit 314c may access and/or receive the MPDU Cmd from the DL Command / Status queue 310b. The PDCP MPDU circuit 314c may instruct, among others, one or more of the decipher / de integrity engine 322a, the de-aggregation engine 322g, the reassembly engine 320b, and/or the re-ordering engine 322d to perform their respective operations. Upon completion, the PDCP MPDU circuit 314c may send (at 545) an MPDU status complete (MPDU Status) to the DL Command / Status queue 310b and/or the director 344 of the DL uC cluster 308b.

[0089] The DL uC cluster 308b may send the packet descriptors to the Layer 2 QoS queue(s) 336 for retrieval (at 547) by the Layer 3 circuit 332. The data packet payloads may be sent (at 549) from internal buffers at the L2 circuits 312 and L2 engines 316 to the DDR memory 330. The Layer 3 circuit 332 may retrieve the data packet payloads from the DDR memory 330.

[0090] FIG. 6 illustrates a flow chart of an exemplary method 600 for Layer 2 data processing, according to some embodiments of the present disclosure. Examples of the apparatus that can perform operations of method 600 include, for example, baseband chip 300 depicted in FIG. 3 in the interactive mode or any other suitable apparatus disclosed herein. It is understood that the operations shown in method 600 are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in FIG. 6.

[0091] Referring to FIG. 6, at 602, the baseband chip may identify whether a data packet is associated with a first RAT or a second RAT. For example, referring to FIG. 4A, the control plane circuit 326 may perform (at 401) a RAT system selection process. Namely, the control plane circuit 326 may determine whether to perform UL Layer 2 data processing for 5G NR or Wi-Fi communication.

[0092] At 604, the baseband chip may program a plurality of Layer 2 circuits to perform the Layer 2 data processing associated with the first RAT in response to determining that the data packet is associated with the first RAT. For example, referring to FIG. 4A, the UL uC cluster 308a may send (at 405a, 405b, 405c, respectively) a Layer 2 configuration command (L2_ConfigCmd) to each of the PDCP MPDU circuit 314c, the RLC BA 314b, and the MAC_AMPDU 314a. The L2_ConfigCmd may program the MAC_AMPDU circuit 314a, the RLC BA circuit 314b, and the PDCP MPDU circuit 314c to perform operations associated with Layer 2 data processing of the first RAT (e.g., 5G NR).

[0093] At 606, the baseband chip may program the plurality of Layer 2 circuits to perform the Layer 2 data processing associated with the second RAT in response to determining that the data packet is associated with the second RAT. For example, referring to FIG. 4A, the UL uC cluster 308a may send (at 405a, 405b, 405c, respectively) a Layer 2 configuration command (L2_ConfigCmd) to each of the PDCP MPDU circuit 314c, the RLC BA 314b, and the MAC_AMPDU 314a. The L2_ConfigCmd may program the MAC_AMPDU circuit 314a, the RLC BA circuit 314b, and the PDCP MPDU circuit 314c to perform operations associated with Layer 2 data processing of the second RAT (e.g., Wi-Fi). [0094] In various aspects of the present disclosure, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or encoded as instructions or code on a non-transitory computer-readable medium. Computer-readable media includes computer storage media. Storage media may be any available media that can be accessed by a computing device, such as node 700 in FIG. 7. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, HDD, such as magnetic disk storage or other magnetic storage devices, Flash drive, SSD, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a processing system, such as a mobile device or a computer. Disk and disc, as used herein, includes CD, laser disc, optical disc, DVD, and floppy disk where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer- readable media.

[0095] According to one aspect of the present disclosure, a baseband chip may include a plurality of Layer 2 circuits that are each configured to perform Layer 2 data processing operations associated with a first RAT and a second RAT. In certain aspects, the first RAT and the second RAT may be different. The baseband chip may also include an MCU configured to program the plurality of Layer 2 circuits to perform the Layer 2 data processing operations associated with the first RAT or the second RAT.

[0096] In certain aspects, the baseband chip may further include a buffer configured to receive a Layer 1 transport block from a first Layer 1 circuit associated with the first RAT or from a second Layer 1 circuit associated with the second RAT.

[0097] In certain other aspects, in response to the buffer receiving the Layer 1 transport block, the MCU may be configured to identify whether the Layer 1 transport block is received from the first Layer 1 circuit associated with the first RAT or the second Layer 1 circuit associated with the second RAT.

[0098] In certain other aspects, in response to identifying that the Layer 1 transport block is received from the first Layer 1 circuit, the MCU may be further configured to program the plurality of Layer 2 circuits to perform the Layer 2 data processing operations associated with the first RAT on the Layer 1 transport block. [0099] In certain other aspects, in response to identifying that the Layer 1 transport block is received from the second Layer 1 circuit, the MCU may be further configured to program the plurality of Layer 2 circuits to perform the Layer 2 data processing operations associated with the second RAT on the Layer 1 transport block.

[0100] In certain other aspects, the plurality of Layer 2 circuits may comprise a first Layer

2 circuit configured to control MAC operations associated with the first RAT and AMPDU operations associated with the second RAT.

[0101] In certain other aspects, the plurality of Layer 2 circuits may comprise a second

Layer 2 circuit configured to perform RLC operations associated with the first RAT and BA operations associated with the second RAT.

[0102] In certain other aspects, the plurality of Layer 2 circuits may comprise a third Layer

2 circuit configured to perform PDCP operations associated with the first RAT and MPDU operations associated with the second RAT.

[0103] In certain other aspects, the first Layer 2 circuit may be configured to control the

MAC operations and the AMPDU operations performed by a first set of Layer 2 engines associated with the first Layer 2 circuit.

[0104] In certain other aspects, the second Layer 2 circuit may be configured to control the

RLC operations and the BA operations performed by a second set of Layer 2 engines associated with the second Layer 2 circuit.

[0105] In certain other aspects, the third Layer 2 circuit may be configured to control PDCP operations and MPDU operations performed by a third set of Layer 2 engines associated with the third Layer 2 circuit.

[0106] In certain other aspects, the first set of Layer 2 engines may include one or more of a multiplexing engine, a de-multiplexing engine, a header extraction engine, or a header generation engine.

[0107] In certain other aspects, the second set of Layer 2 engines may include one or more of a segmentation engine, a reassembly engine, or a window operation engine.

[0108] In certain other aspects, the third set of Layer 2 engines may include one or more of a ciphering / integrity engine, a deciphering / de-integrity engine, a data compression engine, a ROHC engine, a re-ordering operation engine, an aggregation engine, or a de-aggregation engine. [0109] In certain other aspects, the baseband chip may further comprise a memory operatively coupled to the MCU and the plurality of Layer 2 circuits and configured to store a plurality sets of commands into a plurality of command queues to be fetched by at least one of the plurality of Layer 2 circuits.

[0110] In certain other aspects, the memory may be further configured to receive a plurality sets of result statuses from the at least one of the Layer 2 circuits and store the plurality sets of result statuses in a plurality of status queues, respectively.

[0111] In certain other aspects, the MCU may be further configured to retrieve the plurality sets of result statuses from the memory. The MCU may be further configured to generate each set of the commands for controlling a respective one of the Layer 2 circuits based on a corresponding set of the result statuses.

[0112] In certain aspects, the corresponding set of the result status may be from another one of the Layer 2 circuits at a lower layer in Layer 2 protocol stack than the respective one of the Layer 2 circuits.

[0113] According to another aspect of the present disclosure, a baseband chip includes a first Layer 2 circuit configured to control MAC operations associated with a first RAT and AMPDU operations associated with a second RAT. The baseband chip may also include a second Layer 2 circuit configured to perform RLC operations associated with the first RAT and BA operations associated with the second RAT. The baseband chip may further include a third Layer 2 circuit configured to perform PDCP operations associated with the first RAT and MPDU operations associated with the second RAT.

[0114] In certain aspects, the first Layer 2 circuit may be configured to control the MAC operations and the AMPDU operations by controlling a first set of Layer 2 engines associated with the first Layer 2 circuit.

[0115] In certain other aspects, the second Layer 2 circuit may be configured to control the

RLC operations and the BA operations by controlling a second set of Layer 2 engines associated with the second Layer 2 circuit.

[0116] In certain other aspects, the third Layer 2 circuit may be configured to control PDCP operations and MPDU operations by controlling a third set of Layer 2 engines associated with the third Layer 2 circuit. [0117] In certain other aspects, the first set of Layer 2 engines may include one or more of a multiplexing engine, a de-multiplexing engine, a header extraction engine, or a header generation engine.

[0118] In certain other aspects, the second set of Layer 2 engines may include one or more of a segmentation engine, a reassembly engine, or a window operation engine.

[0119] In certain other aspects, the third set of Layer 2 engines may include one or more of a ciphering / integrity engine, a deciphering / de-integrity engine, a data compression engine, a ROHC engine, a re-ordering operation engine, an aggregation engine, or a de-aggregation engine.

[0120] According to another aspect of the present disclosure, a method of Layer 2 data processing may include identifying whether a data packet is associated with a first RAT or a second RAT. The method may also include programming a plurality of Layer 2 circuits to perform the Layer 2 data processing associated with the first RAT in response to determining that the data packet is associated with the first RAT. The method may further include programming the plurality of Layer 2 circuits to perform the Layer 2 data processing associated with the second RAT in response to determining that the data packet is associated with the second RAT.

[0121] In certain other aspects, the plurality of Layer 2 circuits may comprise a first Layer

[0122] In certain other aspects, the plurality of Layer 2 circuits may comprise a second

[0123] In certain other aspects, the plurality of Layer 2 circuits may comprise a third Layer

[0124] In certain other aspects, the first Layer 2 circuit may be configured to control the

[0125] In certain other aspects, the second Layer 2 circuit may be configured to control the

RLC operations and the BA operations performed by a second set of Layer 2 engines associated with the second Layer 2 circuit. [0126] In certain other aspects, the third Layer 2 circuit may be configured to control PDCP operations and MPDU operations performed by a third set of Layer 2 engines associated with the third Layer 2 circuit.

[0127] In certain other aspects, the programming a plurality of Layer 2 circuits to perform the Layer 2 data processing associated with the first RAT may include programming the first Layer 2 circuit to control the MAC operations performed by the first set of Layer 2 engines. In certain other aspects, the programming a plurality of Layer 2 circuits to perform the Layer 2 data processing associated with the first RAT may include programming the second Layer 2 circuit to control the RLC operations performed by the second set of Layer 2 engines. In certain other aspects, the programming a plurality of Layer 2 circuits to perform the Layer 2 data processing associated with the first RAT may include programming the third Layer 2 circuit to control the PDCP operations performed by the third set of Layer 2 engines.

[0128] In certain other aspects, the programming a plurality of Layer 2 circuits to perform the Layer 2 data processing associated with the second RAT may include programming the first Layer 2 circuit to control the AMPDU operations performed by the first set of Layer 2 engines. In certain other aspects, the programming a plurality of Layer 2 circuits to perform the Layer 2 data processing associated with the second RAT may include programming the second Layer 2 circuit to control the BA operations performed by the second set of Layer 2 engines. In certain other aspects, the programming a plurality of Layer 2 circuits to perform the Layer 2 data processing associated with the second RAT may include programming the third Layer 2 circuit to control the MPDU operations performed by the third set of Layer 2 engines.

[0129] In certain other aspects, the first set of Layer 2 engines may include one or more of a multiplexing engine, a de-multiplexing engine, a header extraction engine, or a header generation engine.

[0130] In certain other aspects, the second set of Layer 2 engines may include one or more of a segmentation engine, a reassembly engine, or a window operation engine.

[0131] In certain other aspects, the third set of Layer 2 engines may include one or more of a ciphering / integrity engine, a deciphering / de-integrity engine, a data compression engine, a ROHC engine, a re-ordering operation engine, an aggregation engine, or a de-aggregation engine. [0132] The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

[0133] Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

[0134] The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0135] Various functional blocks, modules, and steps are disclosed above. The particular arrangements provided are illustrative and without limitation. Accordingly, the functional blocks, modules, and steps may be re-ordered or combined in different ways than in the examples provided above. Likewise, certain embodiments include only a subset of the functional blocks, modules, and steps, and any such subset is permitted.

[0136] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

WHAT IS CLAIMED IS:

1. A baseband chip, comprising: a plurality of Layer 2 circuits that are each configured to perform Layer 2 data processing operations associated with a first radio access technology (RAT) and a second radio access technology (RAT), the first RAT and the second RAT being different; and a microcontroller unit (MCU) configured to program the plurality of Layer 2 circuits to perform the Layer 2 data processing operations associated with the first RAT or the second RAT.

2. The baseband chip of claim 1, further comprising: a buffer configured to receive a Layer 1 transport block from a first Layer 1 circuit associated with the first RAT or from a second Layer 1 circuit associated with the second RAT.

3. The baseband chip of claim 2, wherein, in response to the buffer receiving the Layer 1 transport block, the MCU is configured to: identify whether the Layer 1 transport block is received from the first Layer 1 circuit associated with the first RAT or the second Layer 1 circuit associated with the second RAT.

4. The baseband chip of claim 3, wherein, in response to identifying that the Layer 1 transport block is received from the first Layer 1 circuit, the MCU is further configured to: program the plurality of Layer 2 circuits to perform the Layer 2 data processing operations associated with the first RAT on the Layer 1 transport block.

5. The baseband chip of claim 3, wherein, in response to identifying that the Layer 1 transport block is received from the second Layer 1 circuit, the MCU is further configured to: program the plurality of Layer 2 circuits to perform the Layer 2 data processing operations associated with the second RAT on the Layer 1 transport block.

6. The baseband chip of claim 1, wherein the plurality of Layer 2 circuits comprises: a first Layer 2 circuit configured to control Media Access Control (MAC) operations associated with the first RAT and Aggregate MAC Packet Data Unit (AMPDU) operations associated with the second RAT, a second Layer 2 circuit configured to perform Radio Link Control (RLC) operations associated with the first RAT and Block Acknowledgement (BA) operations associated with the second RAT, and a third Layer 2 circuit configured to perform Packet Data Convergence Protocol (PDCP) operations associated with the first RAT and MAC Packet Data Unit (MPDU) operations associated with the second RAT.

7. The baseband chip of claim 6, wherein: the first Layer 2 circuit is configured to control the MAC operations and the AMPDU operations performed by a first set of Layer 2 engines associated with the first Layer 2 circuit, the second Layer 2 circuit is configured to control the RLC operations and the BA operations performed by a second set of Layer 2 engines associated with the second Layer 2 circuit, and the third Layer 2 circuit is configured to control PDCP operations and MPDU operations performed by a third set of Layer 2 engines associated with the third Layer 2 circuit.

8. The baseband chip of claim 7, wherein: the first set of Layer 2 engines includes one or more of a multiplexing engine, a de multiplexing engine, a header extraction engine, or a header generation engine, the second set of Layer 2 engines includes one or more of a segmentation engine, a reassembly engine, or a window operation engine, and the third set of Layer 2 engines includes one or more of a ciphering / integrity engine, a deciphering / de-integrity engine, a data compression engine, a robust header compression (ROHC) engine, a re-ordering operation engine, an aggregation engine, or a de-aggregation engine.

9. The baseband chip of claim 1, further comprising a memory operatively coupled to the MCU and the plurality of Layer 2 circuits and configured to store a plurality sets of commands into a plurality of command queues to be fetched by at least one of the plurality of Layer 2 circuits.

10. The baseband chip of claim 9, wherein the memory is further configured to receive a plurality sets of result statuses from the at least one of the Layer 2 circuits and store the plurality sets of result statuses in a plurality of status queues, respectively.

11. The baseband chip of claim 10, wherein the MCU is further configured to: retrieve the plurality sets of result statuses from the memory; and generate each set of the commands for controlling a respective one of the Layer 2 circuits based on a corresponding set of the result statuses, wherein the corresponding set of the result status are from another one of the Layer 2 circuits at a lower layer in Layer 2 protocol stack than the respective one of the Layer 2 circuits.

12. A baseband chip, comprising: a first Layer 2 circuit configured to control Media Access Control (MAC) operations associated with a first radio access technology (RAT) and Aggregate MAC Packet Data Unit (AMPDU) operations associated with a second RAT; a second Layer 2 circuit configured to perform Radio Link Control (RLC) operations associated with the first RAT and Block Acknowledgement (BA) operations associated with the second RAT; and a third Layer 2 circuit configured to perform Packet Data Convergence Protocol (PDCP) operations associated with the first RAT and MAC Packet Data Unit (MPDU) operations associated with the second RAT.

13. The baseband chip of claim 12, wherein: the first Layer 2 circuit is configured to control the MAC operations and the AMPDU operations by controlling a first set of Layer 2 engines associated with the first Layer 2 circuit, the second Layer 2 circuit is configured to control the RLC operations and the BA operations by controlling a second set of Layer 2 engines associated with the second Layer 2 circuit, and the third Layer 2 circuit is configured to control PDCP operations and MPDU operations by controlling a third set of Layer 2 engines associated with the third Layer 2 circuit.

14. The baseband chip of claim 13, wherein: the first set of Layer 2 engines includes one or more of a multiplexing engine, a de multiplexing engine, a header extraction engine, or a header generation engine, the second set of Layer 2 engines includes one or more of a segmentation engine, a reassembly engine, or a window operation engine, and the third set of Layer 2 engines includes one or more of a ciphering / integrity engine, a deciphering / de-integrity engine, a data compression engine, a robust header compression (ROHC) engine, a re-ordering operation engine, an aggregation engine, or a de-aggregation engine.

15. A method of Layer 2 data processing, comprising: identifying whether a data packet is associated with a first radio access technology (RAT) or a second RAT; programming a plurality of Layer 2 circuits to perform the Layer 2 data processing associated with the first RAT in response to determining that the data packet is associated with the first RAT; and programming the plurality of Layer 2 circuits to perform the Layer 2 data processing associated with the second RAT in response to determining that the data packet is associated with the second RAT.

16. The method of claim 15, wherein the plurality of Layer 2 circuits comprises: a first Layer 2 circuit configured to control Media Access Control (MAC) operations associated with a first radio access technology (RAT) and Aggregate MAC Packet Data Unit (AMPDU) operations associated with a second RAT; a second Layer 2 circuit configured to perform Radio Link Control (RLC) operations associated with the first RAT and Block Acknowledgement (BA) operations associated with the second RAT; and a third Layer 2 circuit configured to perform Packet Data Convergence Protocol (PDCP) operations associated with the first RAT and MAC Packet Data Unit (MPDU) operations associated with the second RAT.

17. The method of claim 16, wherein: the first Layer 2 circuit is configured to control the MAC operations and the AMPDU operations performed by a first set of Layer 2 engines associated with the first Layer 2 circuit, the second Layer 2 circuit is configured to control the RLC operations and the BA operations performed by a second set of Layer 2 engines associated with the second Layer 2 circuit, and the third Layer 2 circuit is configured to control PDCP operations and MPDU operations performed by a third set of Layer 2 engines associated with the third Layer 2 circuit.

18. The method of claim 17, wherein the programming a plurality of Layer 2 circuits to perform the Layer 2 data processing associated with the first RAT comprises: programming the first Layer 2 circuit to control the MAC operations performed by the first set of Layer 2 engines, programming the second Layer 2 circuit to control the RLC operations performed by the second set of Layer 2 engines, and programming the third Layer 2 circuit to control the PDCP operations performed by the third set of Layer 2 engines.

19. The method of claim 18, wherein the programming a plurality of Layer 2 circuits to perform the Layer 2 data processing associated with the second RAT comprises: programming the first Layer 2 circuit to control the AMPDU operations performed by the first set of Layer 2 engines, programming the second Layer 2 circuit to control the BA operations performed by the second set of Layer 2 engines, and programming the third Layer 2 circuit to control the MPDU operations performed by the third set of Layer 2 engines.

20. The method of claim 19, wherein: the first set of Layer 2 engines includes one or more of a multiplexing engine, a de multiplexing engine, a header extraction engine, or a header generation engine, the second set of Layer 2 engines includes one or more of a segmentation engine, a reassembly engine, or a window operation engine, and the third set of Layer 2 engines includes one or more of a ciphering / integrity engine, a deciphering / de-integrity engine, a data compression engine, a robust header compression (ROHC) engine, a re-ordering operation engine, an aggregation engine, or a de-aggregation engine.