WO2021042882A1

WO2021042882A1 - Downlink control information scheduling method and apparatus, and storage medium

Info

Publication number: WO2021042882A1
Application number: PCT/CN2020/102631
Authority: WO
Inventors: 钟庆新
Original assignee: 中兴通讯股份有限公司
Priority date: 2019-09-04
Filing date: 2020-07-17
Publication date: 2021-03-11
Also published as: CN112449437A

Abstract

Provided are a downlink control information scheduling method and apparatus, and a storage medium. Said method comprises: storing, in a DCI buffer, DCI outputted by a PDCCH detector; transferring, to a cyclic buffer scheduler, a parameter group corresponding to the DCI; and the cyclic buffer scheduler updating a cyclic buffer scheduler node according to the received parameter group, so that a control scheduler performs DCI scheduling processing according to the updated cyclic buffer scheduler node.

Description

Downlink control information scheduling method, device and storage medium

This article claims the priority of the Chinese patent application CN201910832425.1 entitled "Downlink control information scheduling method, device and storage medium" filed on September 4, 2019, the entire content of which is incorporated herein by reference.

Technical field

This article relates to the field of communication technology, and specifically to a method, device and storage medium for scheduling downlink control information.

Background technique

Mobile broadband enhancements (enhanced Mobile Broadband, eMBB), Ultra Reliable Low Latency Communications (URLLC) and massive machines planned in the 5th-Generation mobile communication technology (5G) In the three major application scenarios of Massive Machine Type Communications (mMTC), through a parameter set (Numerologies) concept, different parameters μ are specified for low frequency bands and high frequency bands. As shown in Table 1, this parameter μ defines sub The basic resource parameters of time domain and frequency domain such as carrier interval, frame and time slot structure, among them, the time slot structure corresponding to different parameters μ is shown in Figure 1.

Table 1 Parameter set μ and symbol and time slot structure parameters

As the 5G New Radio (NR) system defines a flexible time slot structure, it can support two formats: Frequency Division Duplex (FDD) and Time Division Duplex (TDD). At the same time, the 5G TDD standard no longer uses the certain TDD uplink and downlink subframe ratio modes defined by the 4G Long Term Evolution (LTE) technology, but can flexibly configure the uplink through semi-static signaling and dynamic signaling. , Downlink time slot structure.

For example, for the physical downlink shared channel (Physical Downlink Shared Channel, PDSCH), the time-domain resource allocation domain parameters in the downlink control information (Downlink Control Information, DCI) format (Format) 1_0 and DCI Format 1_1 determine the time slot offset parameter K0, time domain symbol resource allocation parameter (Start and length indicator, SLIV) 0, to flexibly control the time slot and symbol resources where PDSCH scheduling is located; for the physical uplink shared channel (Physical Uplink Shared Channel, PUSCH), through DCI Format 0_0 , The time domain resource allocation domain parameter in DCI Format0_1 determines the time slot offset parameter K2 and the time domain symbol resource allocation parameter SLIV2, so as to flexibly control the time slot and its symbol resources where PUSCH is scheduled. Among them, the value range of the time slot offset parameters K0 and K2 can be 0 to 32, and flexible time-domain scheduling can be realized through the time-domain resource allocation parameter in the DCI to meet different requirements in various application scenarios. For the mini-slot scheduling mode, the system can allocate part of the symbols in a time slot for PUSCH and PDSCH time domain resources (for example, the number of symbols can be 2, 4, 7), and the same time slot can also be time division multiplexed and scheduled A PUSCH, PDSCH.

However, according to the technical specification requirements of the 3rd Generation Partnership Project (3rd Generation Partnership Project, 3GPP), the scheduling of 5G NR mobile terminals on the physical layer and downlink traffic channels requires the following support: (1), available at any time Simultaneously store a maximum of 16 DCI Format 1_0 or DCI Format 1_1, 16 DCI Format 0_0 or DCI Format 0_1 to schedule the PDSCH and PUSCH in the current and subsequent multiple time slots; in any time slot, it is necessary to check the number of current possible detections. For a DCI, determine the corresponding PDSCH and PUSCH scheduling time slots according to its time domain resource allocation parameters, and control the reception of PDSCH and the transmission of PUSCH according to the determined time slot number; (2), support the time slot offset parameters K0 and K2. Possible values, and support different uplink and downlink parameters μ, where the parameter μ is related to the time slot structure and time slot offset parameters K0, K2; (3) According to the terminal capability level, it needs to support the same time slot Time division multiplexing schedules one or more PUSCH and PDSCH transmission blocks, and the time domain symbol resources of multiple PUSCH and PDSCH in one slot can be flexibly allocated according to the configured SLIV value. As shown in Figure 2, for PUSCH and PDSCH scheduling, one or more uplink (Uplink, UL) DCI and downlink (Downlink, DL) DCI can be allocated in one time slot, and subsequent PUSCH and PDSCH in different time slots can be scheduled, or , Multiple UL DCI, DL DCI can be allocated in one time slot, multiple PUSCH, PDSCH in the subsequent time slot can be scheduled, or multiple UL DCI, DL DCI can be allocated in multiple time slots, and the next time slot can be scheduled Multiple PUSCH and PDSCH in the slot.

Therefore, from the existing conventional implementation technology, the above implementation has at least the following problems: first, the method of constructing a processing queue based on the scheduling time slot number, queue maintenance and access is more complicated; second, based on hybrid automatic The method for maintaining DCI scheduling by the Hybrid Automatic Repeat Request (HARQ) process number must be planned according to the time slot number for the HARQ process number to simplify the processing of each scheduled time slot, and there are also problems with complex queue maintenance, and It is difficult to deal with the situation of DCI misdetection; third, the method of directly constructing the processing queue based on the time slot offset parameters K0, K2 and the corresponding DCI load information also has the problem of complex queue maintenance and large buffer space consumed by the queue .

Summary of the invention

This article provides a downlink control information scheduling method, device and storage medium, which can implement downlink control information scheduling with a simple circular buffer scheduler, so as to efficiently and flexibly realize the scheduling processing of the physical layer uplink and downlink traffic channels by the mobile terminal .

The embodiment of this document provides a downlink control information scheduling method, including: a DCI buffer stores the DCI output by a Physical Downlink Control Channel (PDCCH) detector; the DCI buffer transfers the parameter group corresponding to the DCI to the loop Cache scheduler; the cyclic cache scheduler updates the cyclic cache scheduler node according to the received parameter group; controls the scheduler to perform DCI scheduling processing according to the updated cyclic cache scheduler node.

On the other hand, the embodiment of this document also provides a downlink control information scheduling device, including: a PDCCH detector configured to detect and output DCI; a DCI buffer configured to store DCI output by the PDCCH detector; a DCI buffer, and It is set to pass the parameter group corresponding to DCI to the circular buffer scheduler; the circular buffer scheduler is set to update the circular buffer scheduler node according to the received parameter group; the control scheduler is set to be based on the updated circular buffer scheduler The node performs DCI scheduling processing.

In addition, the embodiments herein also provide a computer-readable storage medium that stores a computer program, and when the computer program is executed by a processor, any one of the downlink control information scheduling methods in the embodiments of this document is implemented.

With regard to the above embodiments and other aspects of this document and their implementation, more descriptions are provided in the description of the drawings, the specific implementation and the claims.

Description of the drawings

Figure 1 is a schematic diagram of the time slot structure of the 5G NR system;

Figure 2 is a schematic diagram of PUSCH and PDSCH scheduling in 5G NR system;

FIG. 3 is a flowchart of a method for scheduling downlink control information according to an embodiment;

FIG. 4 is a schematic structural diagram of a downlink control information device provided by an embodiment;

FIG. 5 is a schematic structural diagram of another downlink control information device provided by an embodiment;

Fig. 6 is a schematic structural diagram of a terminal provided by an embodiment.

detailed description

In order to make the purpose, technical solutions and advantages of this document clearer, the embodiments of this document will be described in detail below with reference to the accompanying drawings. It should be noted that, in the case of no conflict, the embodiments herein and the features in the embodiments can be combined with each other arbitrarily.

In addition, in the examples herein, words such as "in an embodiment" are used as examples, illustrations, or illustrations. In the examples herein, it is described as "any embodiment or design in one embodiment should not be construed as being more preferable or advantageous than other embodiments or design. To be precise, the use of "in an implementation" Words such as "in the way" are intended to present related concepts in a specific way.

For ease of understanding, some explanations of concepts related to this article are given as examples for reference. As follows.

DCI buffer parameters: (1) MaxNumberOfReceivedDci: used to set the maximum number of DCI buffers; 5G NR technical specifications stipulate that the maximum number of DCI buffers that need to be buffered is 16. Considering that DCI misdetection may occupy part of the effective buffer, this The parameter value is set to be greater than 16. This parameter needs to be set separately for UL DCI buffer and DL DCI buffer. (2) ReceivedDciTagBitmap: Used to set the occupancy identifier and buffer index of the DCI detected and output by the PDCCH detector in the DCI buffer, where the buffer index can be directly derived from the bit position in the DCI buffer bitmap, and the bitmap valid bit The range is determined according to the above parameter MaxNumberOfReceivedDci. This parameter needs to be set separately for UL DCI buffer and DL DCI buffer. (3) ReceivedDciPayloadBuffer: used to buffer a list of DCI related information (for example, load information), and the size of the list is determined according to the parameter MaxNumberOfReceivedDci. Similarly, this parameter needs to be set separately for the UL DCI buffer and the DL DCI buffer.

DCI circular buffer scheduler parameters: (1) MaxNumberOfRingBufferNode (NNode): used to set the maximum number of nodes of the circular buffer scheduler, this parameter is determined according to the value range of the time slot offset parameters K0 and K2. (2) MaxNumberOfNodeToDoDci: used to set the maximum number of DCI to be processed in the cyclic buffer scheduler node. This parameter needs to be set according to the terminal capability level and terminal protection measures (DCI misdetection may occupy the effective buffer). Among them, the terminal capability level and The number of PDSCHs and PUSCHs processed by time division within a time slot is related; terminal protection measures take into account that DCI misdetection may occupy effective buffers, so the maximum number of DCIs to be processed in the node can be expanded. This parameter needs to be set separately for the UL DCI cyclic buffer scheduler and the DL DCI cyclic buffer scheduler. (3) PointerRingBufferSchedulingNode (PNode): A pointer used to instruct the circular buffer scheduler to process the current scheduling node. This parameter needs to be set separately for the UL DCI cyclic buffer scheduler and the DL DCI cyclic buffer scheduler. (4) T_RingBufferNodeInfo: used to store the control information of the circular buffer scheduler node. This parameter is a structure type, including: the time slot number information of the node to be processed, the number of DCI to be processed, the list of to be processed DCI ToDoDci[], the list of to be processed DCI order identification ToDoDciOrder[] and other parameters. Among them, the list ToDoDci[] is established according to the storage index value of the DCI in its corresponding buffer, and the list ToDoDciOrder[] determines the processing order of the DCI to be processed according to the starting symbol calculated by the SLIV. The sizes of these two lists are set according to MaxNumberOfNodeToDoDci . This parameter needs to be set separately for the UL DCI cyclic buffer scheduler and the DL DCI cyclic buffer scheduler.

Based on the above concept, Figure 3 is a flowchart of a method for scheduling downlink control information provided by an embodiment. The method can be applied to scenarios where 5G NR terminals configure various parameters to meet the requirements of 5G NR terminal support. This method specifically includes the following steps: a set of frame structure parameters, scheduling time sequence parameters established by technical specifications, time slot and mini-slot scheduling, etc.

S301. The DCI buffer stores the DCI output by the PDCCH detector.

When the PDCCH detector detects the DCI, it can output the detected DCI to the DCI buffer for storage.

In an implementation manner, the DCI buffer may be a UL DCI buffer or a DL DCI buffer, as shown in FIG. 4.

For the DL DCI buffer, when the PDCCH detector detects DCI Format 1_0 or DCI Format 1_1, it can access the DL DCI buffer in a polling manner, and look for the DL DCI buffer by querying the bitmap variable ReceivedDciTagBitmap of the DL DCI buffer. Bits.

Suppose that 1 means that there is a corresponding DL DCI stored, and 0 means that DL DCI has not been stored yet. Then, you can query ReceivedDciTagBitmap to find a bit with a value of 0, and use the bit index value with a bit of 0 as the list index. The list index can be marked as IndexOfDLDci, and the DL DCI output by the PDCCH detector is stored in the DL DCI buffer definition In the ReceivedDciPayloadBuffer list, set the bit position of the bitmap variable to 1.

For the UL DCI buffer, when the PDCCH detector detects DCI Format 0_0 or DCI Format 0_1, the UL DCI buffer can also be accessed in a polling manner.

For example, query the bitmap variable ReceivedDciTagBitmap of the UL DCI buffer to find the bits where DL DCI is not stored.

In one embodiment, when the value of the bit is 1, it means that the corresponding bit is stored in UL DCI, and when the value of the bit is 0, it means that the corresponding bit is not stored in UL DCI.

In an implementation manner, a bit index value with a bit value of 0 may be used as a list index, the list index is recorded as IndexOfULDci, and the UL DCI output by the PDCCH detector is stored in the ReceivedDciPayloadBuffer list defined by the UL DCI buffer , And the bit is set to 1.

S302. The DCI buffer transfers the parameter group corresponding to the DCI to the circular buffer scheduler.

After the DCI buffer stores the acquired DCI in corresponding bits, it can parse the DCI to obtain the time domain resource scheduling parameter group in the DCI.

For example, the time domain resource scheduling parameter group in DL DCI can be {IndexOfDLDci, nDL, K0, SLIV, μPDCCH, μPDSCH}, where nDL represents the number of the time slot in which DL DCI is detected by the PDCCH detector, and μPDCCH represents the parameters of the PDCCH channel μ, μPDSCH represents the parameter μ of the PDSCH channel. The time domain resource scheduling parameter group in UL DCI can be {IndexOfULDci, nDL, K2, SLIV, μPDCCH, μPUSCH}, where nDL represents the number of the time slot in which UL DCI is detected, μPDCCH represents the parameter μ of the PDCCH channel, and μPUSCH represents PUSCH The parameter μ of the channel.

After obtaining the parameter group of the DCI, the parameter group corresponding to the DCI can be passed to the circular buffer scheduler.

In the embodiments herein, the DL DCI cyclic buffer scheduler can be separated from the UL DCI cyclic buffer scheduler. Then, in one embodiment, the time domain resource scheduling parameter group {IndexOfDLDci, nDL, K0, SLIV, μPDCCH, μPDSCH} in DL DCI can be passed to the DL DCI circular buffer scheduler, and the time domain in UL DCI The resource scheduling parameter group {IndexOfULDci, nDL, K2, SLIV, μPDCCH, μPUSCH} is passed to the UL DCI cyclic buffer scheduler.

S303. The circular buffer scheduler updates the circular buffer scheduler node according to the received parameter group.

After the circular buffer scheduler receives the time domain resource scheduling parameter group in the DCI, it can update the circular buffer scheduler node based on the parameter group.

For example, the circular buffer scheduler may update the control information of the circular buffer scheduler node according to the received parameter group.

In an implementation manner, the embodiment of this document provides an alternative implementation manner in which the circular buffer scheduler determines the to-be-updated circular buffer scheduler node corresponding to the currently received DCI according to the received parameter group, and according to the received The received parameter group updates the determined control information of the to-be-updated cyclic buffer scheduler node.

It can be understood that the above-mentioned currently received DCI is also the DCI output by the PDCCH detector stored in the DCI buffer.

For example, for the DL DCI cyclic buffer scheduler, it is assumed that the node pointed to by the pointer PNode of the DL DCI cyclic buffer scheduler processing the current scheduling node is NDL, the current downlink time slot number is nDL, and the current downlink time slot number is the same as the detected The PDCCH slot numbers are the same. Then, the DL DCI cyclic buffer scheduler can calculate the currently received DL DCI based on the received parameters nDL, K0, μPDCCH, and μPDSCH. In the DL DCI cyclic buffer scheduler, the cyclic buffer scheduler node MDL and PDSCH receive time slots are to be updated. Number mDL.

In an embodiment, determining that the currently received DL DCI is in the DL DCI cyclic buffer scheduler to be updated, the cyclic buffer scheduler node MDL can be calculated by using the following formula:

M _DL ＝(N _DL +K ₀ )%N _Node (1)

In an implementation manner, determining the PDSCH receiving slot number mDL can be calculated by using the following formula:

In an implementation manner, information such as the determined PDSCH receiving slot number mDL and the list index IndexOfDLDci may be used as the control information, and the MDL is used as the index value to be stored in the structure parameter T_RingBufferNodeInfo of the DL and DCI cyclic buffer scheduler.

At the same time, the start symbol SPDSCH of the scheduled PDSCH in the time slot can be determined according to the SLIV in the parameter group, and combined with the to-be-processed DL DCI list ToDoDci[] and the to-be-processed DL DCI order identification list ToDoDciOrder[] in the T_RingBufferNodeInfo structure parameter, The sequence identifier of the currently received DL DCI is determined, and the sequence identifier of the DL DCI is updated to the ToDoDciOrder[] list.

In an implementation manner, the DL DCI cyclic buffer scheduler may also count and update the number of DL DCI to be processed stored in each node, so as to update the determined control information of the cyclic buffer scheduler node to be updated.

For the UL DCI cyclic buffer scheduler, suppose that the node pointer PNode pointed to by the UL DCI cyclic buffer scheduler to process the current schedule is NUL, the current downlink slot number is nUL, and the current downlink slot number is nUL and uplink time slot parameters The μ value is related. Then, the UL DCI cyclic buffer scheduler can calculate the current received UL DCI based on the received parameters nDL, K2, μPDCCH, and μPUSCH when the cyclic buffer scheduler node MUL and PUSCH are to be updated in the UL DCI cyclic buffer scheduler. Slot number mUL.

In an implementation manner, determining that the currently received UL DCI is in the UL DCI cyclic buffer scheduler to be updated cyclic buffer scheduler node MUL can be implemented in the following manner:

IfμPUSCH≤μPDCCH

M _UL ＝(N _UL +K ₂ )%N _Node

Else if μPUSCH> μPDCCH

End

In an implementation manner, the PDSCH receiving slot number mUL can be determined by calculation using the following formula:

In an implementation manner, information such as the determined PUSCH transmission slot number mUL and the list index IndexOfULDci may be used as control information, and MUL is used as the index value to be stored in the structure parameter T_RingBufferNodeInfo of the UL DCI cyclic buffer scheduler.

At the same time, the start symbol SPUSCH of the scheduled PUSCH in the time slot can be determined according to the SLIV in the parameter group, and combined with the to-be-processed UL DCI list ToDoDci[] and the to-be-processed UL DCI order identification list ToDoDciOrder[] in the T_RingBufferNodeInfo structure parameter, Determine the sequence identifier of the UL DCI currently received, and update the UL DCI sequence identifier to the ToDoDciOrder[] list.

In an implementation manner, the UL DCI cyclic buffer scheduler may also count and update the number of UL DCI to be processed stored by each node.

Through the foregoing implementation manners, it is possible to update the control information of the DL DCI cyclic buffer scheduler or the cyclic buffer scheduler node in the UL DCI cyclic buffer scheduler.

S304. Control the scheduler to perform DCI scheduling processing according to the updated circular buffer scheduler node.

When the control scheduler is the DL PDSCH reception control scheduler, the DL PDSCH reception control scheduler may determine the target cyclic buffer scheduler node according to the updated cyclic buffer scheduler node.

It should be noted that the above-mentioned target circular buffer scheduler node is the DL DCI circular buffer scheduler node that the DL PDSCH receiving control scheduler should currently process.

In an implementation manner, the embodiment of this document provides an implementation manner for determining the target cyclic buffer scheduler node, which is based on the current node indicated by the pointer PNode of the current scheduling node of the DL DCI cyclic buffer scheduler and the downlink current slot number nDL, Determine the target circular cache scheduler node.

The DL PDSCH receives the control scheduler to access and obtains the control information of the target cyclic buffer scheduler node, and obtains the DL DCI processing order identifier from the ToDoDciOrder[] list according to the number of DL DCI to be processed in the node control information, and then obtains the DL DCI processing order identifier from the corresponding ToDoDci[ ] Obtain the corresponding DL DCI buffer list index IndexOfDLDci from the list, and then obtain DL DCI related information (for example, load information) from the DL DCI buffer according to the list index IndexOfDLDci, and schedule the DL DCI by the PDSCH receiving control scheduler deal with.

Conversely, when the control scheduler is the UL PUSCH transmission control scheduler, the UL PUSCH transmission control scheduler can also determine the current DL DCI cyclic buffer scheduler node that should be processed according to the updated cyclic buffer scheduler node, that is, the target cyclic buffer scheduler.器Node.

In an implementation manner, the UL PUSCH transmission control scheduler may determine the target cyclic buffer scheduler node according to the current node indicated by the pointer PNode of the current scheduling node of the UL DCI cyclic buffer scheduler and the uplink current time slot number nUL.

In one embodiment, the UL PUSCH transmission control scheduler can access and obtain the control information of the target cyclic buffer scheduler node, and obtain the UL DCI processing from the ToDoDciOrder[] list according to the number of UL DCI to be processed in the node control information. Order identification, and then obtain the UL DCI buffer list index IndexOfDLDci from the corresponding ToDoDci[] list, and then obtain UL UCI related information from the UL DCI buffer according to the list index IndexOfDLDci, and then the UL PUSCH transmission control scheduler according to the obtained The related information performs scheduling processing on the UL UCI.

The foregoing implementation process has excellent scalability for diversified uplink and downlink time slot structure configurations, different time slot offset values, and the processing of one or more transmission block scheduling in one time slot.

In an implementation manner, in the above-mentioned DCI scheduling process, the embodiment of this document also provides an implementation manner for maintaining the DCI circular buffer scheduler node, which specifically includes the following situations.

(1) Under the circumstance that the value of the downlink parameter set Numerologiesμ does not change, the maintenance of the DL DCI circular buffer scheduler can be implemented in the following manner.

If the DL DCI in the pending DCI list of the current DL DCI cyclic buffer scheduler node has been processed, the control information of the node is cleared, and the following operations are performed in each time slot according to the downlink time slot structure:

PNode=(PNode+1)%NNode (4)

In order to realize that the node pointer PNode indicating the current processing and scheduling of the DL DCI cyclic buffer scheduler is cyclically moved to the next node.

(2) Under the circumstance that the value of the uplink parameter set Numerologiesμ does not change, the maintenance of the UL DCI cyclic buffer scheduler can be implemented in the following manner.

If the DL DCI in the pending DCI list of the current UL DCI cyclic buffer scheduler node has been processed, the control information of the node is cleared, and the following operations are performed in each time slot according to the uplink time slot structure:

PNode=(PNode+1)%NNode (5)

In order to realize that the node pointer PNode indicating the current processing and scheduling of the UL DCI cyclic buffer scheduler is cyclically moved to the next node.

(3) When the value of the downlink parameter set Numerologiesμ changes, the maintenance of the DL DCI circular buffer scheduler can be implemented in the following manner.

The DL DCI cyclic buffer scheduler requests the timing management module module to update the time slot structure according to the downstream μ value after switching, and performs the following operations in each time slot according to the time slot structure after switching:

PNode=(PNode+1)%NNode (6)

(4) In the case where the value of the uplink parameter set Numerologiesμ changes, the maintenance of the UL DCI cyclic buffer scheduler can be implemented in the following manner.

The UL DCI cyclic buffer scheduler requests the timing management module module to update the time slot structure according to the uplink μ value after the switch, and performs the following operations in each time slot according to the time slot structure after the switch:

PNode=(PNode+1)%NNode (7)

In the downlink control information scheduling method provided by the embodiments of this document, the DCI output by the PDCCH detector is stored in the DCI buffer, and the parameter group corresponding to the DCI is transferred to the circular buffer scheduler, and the circular buffer scheduler according to the received parameter group Update the circular buffer scheduler node so that the control scheduler performs DCI scheduling processing according to the updated circular buffer scheduler node. In this way, a simple circular buffer scheduler is used to implement downlink control information scheduling, which can efficiently and flexibly implement the scheduling processing of the physical layer uplink and downlink traffic channels by the mobile terminal.

Fig. 5 is a schematic structural diagram of a downlink control information scheduling apparatus provided by an embodiment. As shown in Fig. 5, the apparatus provided in this embodiment includes: a PDCCH detector 501, a DCI buffer 502, a circular buffer scheduler 503, and a control Scheduler 504.

Among them, the PDCCH detector is set to detect and output DCI; the DCI buffer is set to store the DCI output by the PDCCH detector, and the parameter group corresponding to the DCI is passed to the circular buffer scheduler; the circular buffer scheduler is set to receive The received parameter group updates the cyclic buffer scheduler node; the control scheduler is set to perform DCI scheduling processing according to the updated cyclic buffer scheduler node.

In an implementation manner, the DCI buffer is configured to parse the DCI, obtain the time domain resource scheduling parameter group in the DCI, and pass the parameter group to the circular buffer scheduler.

The circular buffer scheduler is set to update the control information of the circular buffer scheduler node according to the received parameter group.

In an embodiment, the circular buffer scheduler may determine the circular buffer scheduler node to be updated corresponding to the DCI according to the received parameter group, and update the control information of the circular buffer scheduler node to be updated according to the received parameter group .

The control scheduler is configured to determine the target cyclic buffer scheduler node according to the updated cyclic buffer scheduler node, and determine the DCI from the DCI buffer according to the control information of the target cyclic buffer scheduler node, and perform scheduling processing on the DCI.

In an embodiment, the downlink control information scheduling device further includes: a timing management module.

The circular buffer scheduler is also set to clear the control information of the current circular buffer scheduler node when the pending DCI list of the current circular buffer scheduler node has been processed, and loop the pointer of the current processing scheduling node to the next node; or According to the parameter value after the switch, the timing management module is requested to update the time slot structure, and according to the time slot structure after the switch, the current processing scheduling node pointer is cyclically pointed to the next node.

The downlink control information scheduling apparatus provided in this embodiment is used to implement the downlink control information scheduling method of the embodiment shown in FIG. 3. The implementation principles and technical effects of the downlink control information scheduling apparatus provided in this embodiment are similar, and will not be repeated here.

Fig. 6 is a schematic structural diagram of a terminal provided by an embodiment. As shown in Fig. 6, the terminal includes a processor 601 and a memory 602; the number of processors 601 in the terminal can be one or more. The processor 601 is taken as an example; the processor 601 and the memory 602 in the terminal may be connected by a bus or in other ways. In FIG. 6, a bus connection is taken as an example.

As a computer-readable storage medium, the memory 602 can be used to store software programs, computer-executable programs, and modules, such as program instructions/modules corresponding to the downlink control information scheduling method in the embodiment of FIG. 3 herein (for example, downlink control information scheduling PDCCH detector 501, DCI buffer 502, circular buffer scheduler 503, and control scheduler 504 in the device). The processor 601 implements the aforementioned downlink control information scheduling method by running software programs, instructions, and modules stored in the memory 602.

The memory 602 may mainly include a program storage area and a data storage area. The program storage area may store an operating system and an application program required by at least one function; the data storage area may store data created according to the use of the device, and the like. In addition, the memory 602 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices.

The embodiments herein also provide a storage medium containing computer-executable instructions. The computer-executable instructions are used to perform a downlink control information scheduling method when executed by a computer processor. The method includes: a DCI buffer storing the PDCCH detector output DCI; the DCI buffer transfers the parameter group corresponding to the DCI to the circular buffer scheduler; the circular buffer scheduler updates the circular buffer scheduler node according to the received parameter group; controls the scheduler according to the updated circular buffer scheduler node DCI scheduling processing.

In this way, a simple circular buffer scheduler is used to implement downlink control information scheduling, which can efficiently and flexibly implement the scheduling processing of the physical layer uplink and downlink traffic channels by the mobile terminal.

The above are only exemplary embodiments of this document, and are not used to limit the protection scope of this document.

Those skilled in the art should understand that the term terminal encompasses any suitable type of wireless user equipment, such as mobile phones, portable data processing devices, portable web browsers, or vehicle-mounted mobile stations.

In general, the various embodiments herein can be implemented in hardware or dedicated circuits, software, logic or any combination thereof. For example, some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software that may be executed by a controller, microprocessor, or other computing device, although this document is not limited thereto.

The embodiments herein may be implemented by executing computer program instructions by a data processor of the downlink control information scheduling device, for example, in the processor entity, or by hardware, or by a combination of software and hardware. Computer program instructions can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code written in any combination of one or more programming languages or Object code.

The block diagram of any logic flow in the drawings herein may represent program steps, or may represent interconnected logic circuits, modules, and functions, or may represent a combination of program steps and logic circuits, modules, and functions. The computer program can be stored on the memory. The memory can be of any type suitable for the local technical environment and can be implemented using any suitable data storage technology, such as but not limited to read only memory (ROM), random access memory (RAM), optical storage devices and systems (digital multi-function optical discs) DVD or CD) etc. Computer-readable media may include non-transitory storage media. The data processor can be any type suitable for the local technical environment, such as but not limited to general-purpose computers, special-purpose computers, microprocessors, digital signal processors (DSP), application-specific integrated circuits (ASIC), programmable logic devices (FGPA) And processors based on multi-core processor architecture.

By way of exemplary and non-limiting examples, a detailed description of the exemplary embodiments herein has been provided above. However, considering the accompanying drawings and claims, various modifications and adjustments to the above embodiments are obvious to those skilled in the art, but do not deviate from the scope of this document. Therefore, the proper scope of this document will be determined according to the claims.

Claims

A method for scheduling downlink control information, which includes:

The downlink control information DCI buffer stores the DCI output by the physical downlink control channel PDCCH detector;

The DCI buffer transfers the parameter group corresponding to the DCI to the circular buffer scheduler;

The circular buffer scheduler updates the circular buffer scheduler node according to the received parameter group;

The control scheduler performs DCI scheduling processing according to the updated circular buffer scheduler node.
The method according to claim 1, wherein the DCI buffer transferring the parameter group corresponding to the DCI to a circular buffer scheduler comprises:

The DCI buffer parses the DCI, and obtains the time domain resource scheduling parameter group in the DCI;

The DCI buffer transfers the parameter group to a circular buffer scheduler.
The method according to claim 1, wherein the cyclic buffer scheduler updating the cyclic buffer scheduler node according to the received parameter group comprises:

The circular buffer scheduler updates the control information of the circular buffer scheduler node according to the received parameter group.
The method according to claim 3, wherein the cyclic buffer scheduler updating the control information of the cyclic buffer scheduler node according to the received parameter group comprises:

Determining, by the circular buffer scheduler, the to-be-updated circular buffer scheduler node corresponding to the DCI according to the received parameter group;

The circular buffer scheduler updates the control information of the to-be-updated circular buffer scheduler node according to the received parameter group.
The method according to any one of claims 1 to 4, wherein controlling the scheduler to perform DCI scheduling processing according to the updated circular buffer scheduler node comprises:

The control scheduler determines the target cyclic cache scheduler node according to the updated cyclic cache scheduler node;

The control scheduler determines the DCI from the DCI buffer according to the control information of the target circular buffer scheduler node;

The control scheduler performs scheduling processing on the DCI.
The method according to claim 1, wherein the method further comprises:

If the DCI list to be processed of the current circular buffer scheduler node has been processed, the circular buffer scheduler clears the control information of the current circular buffer scheduler node, and circularly points the pointer of the current processing scheduling node to the next node;

Alternatively, the circular buffer scheduler requests the timing management module to update the time slot structure according to the parameter value after the switch, and circularly points the current processing scheduling node pointer to the next node according to the time slot structure after the switch.
A downlink control information scheduling device, which includes:

Physical downlink control channel PDCCH detector, set to detect and output downlink control information DCI;

The DCI buffer is set to store the DCI output by the PDCCH detector;

The DCI buffer is further configured to transfer the parameter group corresponding to the DCI to the circular buffer scheduler;

A circular buffer scheduler, configured to update the circular buffer scheduler node according to the received parameter group;

The control scheduler is set to perform DCI scheduling processing according to the updated circular buffer scheduler node.
7. The apparatus according to claim 7, wherein the DCI buffer is configured to parse the DCI, obtain a time domain resource scheduling parameter group in the DCI, and pass the parameter group to a circular buffer scheduler.
8. The apparatus according to claim 7, wherein the circular buffer scheduler is configured to update the control information of the circular buffer scheduler node according to the received parameter group.
The apparatus according to claim 9, wherein the cyclic buffer scheduler is configured to determine the to-be-updated cyclic buffer scheduler node corresponding to the DCI according to the received parameter group, and according to the received The parameter group updates the control information of the cyclic buffer scheduler node to be updated.
The apparatus according to any one of claims 7-10, wherein the control scheduler is configured to determine a target circular buffer scheduler node according to the updated circular buffer scheduler node, and according to the target circular buffer scheduler node The control information of the node determines the DCI from the DCI buffer, and performs scheduling processing on the DCI.
The device according to claim 7, wherein the device further comprises a timing management module;

The circular buffer scheduler is further configured to clear the control information of the current circular buffer scheduler node if the DCI list to be processed of the current circular buffer scheduler node has been processed, and loop the pointer of the current processing scheduling node to point downward One node

Or, according to the parameter value after the switch, the timing management module is requested to update the time slot structure, and according to the time slot structure after the switch, the current processing scheduling node pointer is cyclically pointed to the next node.
A computer-readable storage medium, wherein the computer-readable storage medium stores a computer program that, when executed by a processor, implements the downlink control information scheduling method of any one of claims 1-6.