WO2021042618A1

WO2021042618A1 - Display panel and display apparatus

Info

Publication number: WO2021042618A1
Application number: PCT/CN2019/124728
Authority: WO
Inventors: 周志伟
Original assignee: 武汉华星光电半导体显示技术有限公司
Priority date: 2019-09-02
Filing date: 2019-12-12
Publication date: 2021-03-11
Also published as: CN110707127A

Abstract

A display panel and a display apparatus. The method for introducing a power supply voltage signal is changed, and the power supply voltage signal is simultaneously supplied to different positions, so that the problem of voltage drop of a display panel is solved, thereby ameliorating the problem of the brightness of an image not being uniform.

Description

Display panel and display device

This application claims the priority of a Chinese patent application filed with the Chinese Patent Office with the application number 201910823792.5 and the application name "Display Panel and Display Device" on September 02, 2019, the entire content of which is incorporated into this application by reference.

Technical field

This application belongs to the field of display technology, and in particular relates to a display panel and a display device.

Background technique

When the organic light emitting diode emits light, the driving current is related to the power supply voltage, and the driving current needs to be supplied through the power supply voltage VDD. Considering the impedance of the power supply voltage VDD trace, under the action of the resistance drop (IR Drop), the actual VDD voltage obtained by the pixel unit is smaller than the VDD voltage supplied by the power supply, that is, VDDpixel=VDD-Ioled*RVDD. As shown in Figure 1, compared with the lower end of the display panel, the upper end of the display panel is relatively farther away from the power supply voltage VDD, and the resistance is relatively larger. Therefore, the power supply voltage VDD at this position drops more drastically, resulting in the upper end of the display panel. It is dark and bright at the bottom, and it seriously affects the brightness uniformity of the display panel.

How to effectively solve the problem of dark top and bright bottom of the display panel and improve the brightness uniformity of the display panel is an important issue in the display technology.

technical problem

The purpose of this application is to provide a display panel and a display device, which can solve the problems in the prior art.

Technical solutions

In order to solve the above-mentioned problems, the present application provides a display panel and a display device.

According to an aspect of the present application, the present application provides a display panel, which includes: a display area and a non-display area, the non-display area is located at the periphery of the display area; In the non-display area, and the first wiring forms a closed loop, the first wiring is arranged around the display area, the first wiring is a source-drain wiring; a plurality of second wirings, Pass through the display area along the longitudinal direction of the display panel, and the plurality of second traces are electrically connected to the first trace; a driving chip is electrically connected to the first trace, the The driving chip is used to generate a power terminal voltage signal of the display panel, and is provided to the second wiring through the first wiring.

According to another aspect of the present application, the present application provides a display panel, which includes: a display area and a non-display area, the non-display area is located at the periphery of the display area; In the non-display area, and the first wiring forms a closed loop; a plurality of second wirings pass through the display area along the longitudinal direction of the display panel, and the plurality of second wirings are all connected with The first wiring is electrically connected; a driving chip is electrically connected to the first wiring, and the driving chip is used to generate the power terminal voltage signal of the display panel, and is provided to The second wiring.

Further, the first wiring is arranged around the display area.

Further, the first wiring is a source-drain wiring.

Further, the driving chip is arranged at one end of the non-display area along the longitudinal direction of the display panel.

Further, the display panel further includes at least one third wiring, the third wiring passing through the display area along the lateral direction of the display panel, the third wiring and the first wiring respectively It is electrically connected to the second wiring, and is used to receive the power terminal voltage signal transmitted by the first wiring and generated from the driving chip, and transmit it to the second wiring.

Further, the third wiring and the first wiring are arranged in the same layer.

Further, when the third wire is a single wire, the third wire passes through the display area along the central axis of the display area.

Further, when there are multiple third wires, the third wires are arranged at equal intervals.

Further, the third wiring is communicated with the second wiring through a via structure.

According to another aspect of the present application, the present application provides a display device including the display panel as described above.

Beneficial effect

Compared with the prior art, the embodiment of the present application changes the way of introducing the power supply voltage (VDD) signal and uses different positions to provide the VDD signal at the same time to solve the voltage drop problem of the display panel, thereby improving the problem of uneven brightness of the picture.

Description of the drawings

FIG. 1 is a schematic diagram of the structure of a display panel provided by the prior art.

FIG. 2 is a schematic structural diagram of a display panel provided by an embodiment of the present application.

FIG. 3 is a schematic diagram of the structure of a via provided by an embodiment of the present application.

FIG. 4 is a schematic diagram of the structure of the line change processing provided by an embodiment of the present application.

FIG. 5 is a schematic structural diagram of another display panel provided by an embodiment of the present application.

FIG. 6 is a schematic flowchart of another display panel provided by an embodiment of the present application.

FIG. 7 is a schematic structural diagram of a display device provided by an embodiment of the present application.

Embodiments of the present invention

The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative work shall fall within the protection scope of this application.

The terms "first", "second", "third", etc. (if any) in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and not necessarily used to describe a specific order Or precedence. It should be understood that the objects described in this way can be interchanged under appropriate circumstances. In addition, the terms "including" and "having" and any variations of them are intended to cover non-exclusive inclusions.

In the description of this application, the drawings discussed below and various embodiments used to describe the principles disclosed in this application are for illustration only, and should not be construed as limiting the scope of the disclosure of this application. Those skilled in the art will understand that the principles of the present application can be implemented in any suitably arranged system. Exemplary embodiments will be described in detail, and examples of these embodiments are shown in the drawings. In addition, a terminal according to an exemplary embodiment will be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings refer to the same elements.

The terms used in the specification of this application are only used to describe specific implementations, and are not intended to show the concept of this application. Unless there is a clearly different meaning in the context, the expression used in the singular form encompasses the expression in the plural form. In the specification of this application, it should be understood that terms such as "including", "having" and "containing" are intended to indicate the possibility of the features, numbers, steps, actions, or combinations thereof disclosed in the specification of this application, but not The possibility that one or more other features, numbers, steps, actions or combinations thereof may exist or may be added is excluded. The same reference numerals in the drawings refer to the same parts.

As shown in FIG. 2, an embodiment of the present application provides a display panel 1 including a display area 10, a non-display area 20, a first wiring 30, a second wiring 40 and a driving chip 50.

Specifically, the non-display area 20 is located at the periphery of the display area 10.

The first wiring 30 is provided on the non-display area 20, and in this embodiment, the first wiring 30 is formed around the display area 10 to close a loop, so that the first wiring 30 provides the same at both ends of the display panel 1. Therefore, the voltage drop caused by a single VDD signal provided from the driving chip 50 can be reduced, so as to reduce the problem of uneven brightness of the display panel 1. Among them, the first wiring 30 is a source-drain (SD) wiring.

The plurality of second wires 40 penetrate the display area 10 along the longitudinal direction of the display panel 1, and the plurality of second wires 40 are electrically connected to the first wires 30. The second wiring 40 is used to provide voltage to the thin film transistor.

The driving chip 50 is disposed at one end of the non-display area 20 along the longitudinal direction of the display panel 1 and is electrically connected to the first wiring 30. The driving chip 50 is used to generate the VDD signal of the display panel 1 and is provided to the second wiring 40 through the first wiring 30.

As shown in Figs. 3 and 4, due to the design of the first circuit 30, there are more longitudinal SD traces 320 arranged along the longitudinal direction of the display panel 1 than in the prior art, which will be different from the original arrangement along the lateral direction of the display panel 1. The horizontal SD traces 330 on the same layer are short-circuited, so the insulating layer 200 needs to be replaced by CNT (contact) vias 310 at the intersections, so that the vertical SD traces 320 at the intersections are replaced with different layers of metal. Route 100 to prevent the risk of short circuit.

As shown in FIG. 5, an embodiment of the present application provides another display panel 1, which includes a display area 10, a non-display area 20, a first wiring 30, a second wiring 40, a driving chip 50, and a third wiring 60 .

The first wiring 30 is provided on the non-display area 20, and in this embodiment, the first wiring 30 is formed around the display area 10 to close a loop. Among them, the first wiring 30 is a source-drain (SD) wiring.

The plurality of second wires 40 penetrate the display area 10 along the longitudinal direction of the display panel, and the plurality of second wires 40 are electrically connected to the third wires 60. The second wiring 40 is used to provide voltage to the thin film transistor.

The driving chip 50 is disposed at one end of the non-display area 20 along the longitudinal direction of the display panel 1 and is electrically connected to the first wiring 30. The driving chip 50 is used to generate the VDD signal of the display panel 1.

The third wiring 60 penetrates the display area 10 along the central axis of the display panel 1 in the transverse direction, and the third wiring 60 is electrically connected to the first wiring 30 and the second wiring 40 respectively. The third wiring 60 is used to receive the VDD signal transmitted by the first wiring 30 and generated by the driving chip 50 and transmit it to the second wiring 40. Wherein, the third wiring 60 is provided on the same layer as the first wiring 30, and the third wiring 60 is connected to the second wiring 40 through the via structure.

The third wiring 60 provides the VDD signal to both ends of the display panel 1 from the central position at the same time, reducing the number of thin film transistors in the VDD signal path, reducing the voltage drop, and reducing the problem of uneven brightness of the display panel 1.

As shown in FIGS. 3 and 4, due to the design of the first circuit 30, there are more vertical SD traces 320 arranged along the longitudinal direction of the display panel 1 than in the prior art. The horizontal SD traces 330 on the same layer are short-circuited, so the insulating layer 200 needs to be replaced by CNT (contact) vias 310 at the intersections, so that the vertical SD traces 320 at the intersections are replaced with different layers of metal. Route 100 to prevent the risk of short circuit.

As shown in FIG. 6, an embodiment of the present application provides yet another display panel 1, including a display area 10, a non-display area 20, a first wiring 30, a second wiring 40, a driving chip 50 and a third wiring 60.

The plurality of second wirings 40 penetrate the display area 10 along the longitudinal direction of the display panel 1, and the plurality of second wirings 40 are all electrically connected to the third wiring 60. The second wiring 40 is used to provide voltage to the thin film transistor.

The third wiring 60 runs through the display area 10 along the lateral direction of the display panel 1. In this embodiment, there are three third wires 60, which are arranged at equal intervals. The third wiring 60 is electrically connected to the first wiring 30 and the second wiring 40, and is used to receive the VDD signal transmitted by the first wiring 30 and generated by the driving chip 50, and transmit the VDD signal to the second wiring 40. Wherein, the third wiring 60 is provided on the same layer as the first wiring 30, and the third wiring 60 is connected to the second wiring 40 through the via structure.

The third wiring 60 provides VDD signals to both ends of the display panel 1 from three positions at the same time, further reducing the number of thin film transistors in the VDD signal path, reducing voltage drop, and reducing the problem of uneven brightness of the display panel 1.

As shown in FIGS. 3 and 4, due to the design of the first circuit 30, there are more vertical SD traces 320 arranged along the longitudinal direction of the display panel 1 than in the prior art, which will be different from those originally arranged along the horizontal direction of the display panel 1. The horizontal SD traces 330 on the same layer are short-circuited, so the insulating layer 200 needs to be replaced by CNT (contact) vias 310 at the intersections, so that the vertical SD traces 320 at the intersections are replaced with different layers of metal. Route 100 to prevent the risk of short circuit. The three third wirings 60 provided will compress the size space of the pixels. Therefore, the relevant wiring of the display area 10 needs to be modified accordingly.

As shown in FIG. 7, an embodiment of the present application also provides a display device 100 including the display panel 1 as described above, so as to improve the problem of uneven brightness of the picture caused by the voltage drop problem.

The embodiment of the present application changes the way of introducing the power supply voltage (VDD) signal and uses different positions to provide the VDD signal at the same time to solve the voltage drop problem of the display panel, thereby improving the problem of uneven brightness of the picture.

The above is a detailed introduction to a display panel and a display device provided by the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementations of the present application. The descriptions of the above embodiments are only used to help understand the present application. At the same time, for those skilled in the art, according to the ideas of this application, there will be changes in the specific implementation and the scope of application. In summary, the content of this specification should not be construed as a reference to this Application restrictions.

Industrial applicability

The subject of this application can be manufactured and used in industry and has industrial applicability.

Claims

A display panel, which includes:

A display area and a non-display area, the non-display area being located at the periphery of the display area;

A first wiring is arranged in the non-display area, and the first wiring forms a closed loop, the first wiring is arranged around the display area, and the first wiring is source and drain Traces;

A plurality of second wiring lines passing through the display area along the longitudinal direction of the display panel, and the plurality of second wiring lines are electrically connected to the first wiring lines; and

A driving chip is electrically connected to the first wiring, and the driving chip is used to generate a power supply terminal voltage signal of the display panel, which is provided to the second wiring through the first wiring.
A display panel, which includes:

A display area and a non-display area, the non-display area being located at the periphery of the display area;

A first wiring arranged in the non-display area, and the first wiring forming a closed loop;

A plurality of second wiring lines passing through the display area along the longitudinal direction of the display panel, and the plurality of second wiring lines are electrically connected to the first wiring lines; and

A driving chip is electrically connected to the first wiring, and the driving chip is used to generate a power supply terminal voltage signal of the display panel, which is provided to the second wiring through the first wiring.
3. The display panel according to claim 2, wherein the first wiring is arranged around the display area.
3. The display panel of claim 2, wherein the first wiring is a source-drain wiring.
3. The display panel according to claim 2, wherein the driving chip is disposed at one end of the non-display area along the longitudinal direction of the display panel.
3. The display panel according to claim 2, wherein the display panel further comprises at least one third wiring, the third wiring passing through the display area along a lateral direction of the display panel, the third wiring Are electrically connected to the first wiring and the second wiring, respectively, for receiving the power terminal voltage signal transmitted by the first wiring and generated from the driving chip, and transmitting to the first wiring Two routing.
3. The display panel according to claim 2, wherein the third wiring and the first wiring are arranged in the same layer.
7. The display panel according to claim 6, wherein when the third wire is a single wire, the third wire passes through the display area along the central axis of the display area.
7. The display panel according to claim 6, wherein when there are multiple third wires, the third wires are arranged at equal intervals.
8. The display panel of claim 8, wherein the third wiring is connected to the second wiring through a via structure.
A display device comprising the display panel according to claim 1.