WO2021039542A1 - Drive device - Google Patents

Abstract

Provided is a drive device (A1) for controlling the driving of a laser diode (LD). The drive device (A1) comprises: a switching element (Q1) for switching a conduction state and a cut-off state; a capacitor (C1), a first diode (D1), and an input terminal (T1) that receives a power supply voltage (VLD). The capacitor (C1) has a first end (C11) connected to the cathode of the laser diode (LD) and a second end (C12) connected to the switching element (Q1). The anode of the first diode (D1) is connected to a junction point between the first end (C11) of the capacitor (C1) and the cathode of the laser diode (LD). The input terminal (T1) is connected to a junction point between the second end (C12) of the capacitor (C1) and the switching element (Q1).

Description

Drive device

The present disclosure relates to a drive device, and more particularly to a laser diode drive device that controls the drive of a laser diode. The present disclosure also relates to a laser device, a laser radar device, and a vehicle provided with a laser diode driving device.

Laser diodes are used in optical pickups of optical drives, OA equipment (copiers, printers, etc.), communication equipment using optical fibers, and optical ranging devices. Patent Document 1 discloses a drive device for a laser diode. This drive device includes a switching element and a pulse generation circuit. The switching element switches between a conductive state and a cutoff state by a drive pulse from a pulse generation circuit. The switching element is connected to the laser diode, and when the switching element becomes conductive, a forward current flows through the laser diode and the laser diode emits light.

Patent Document 2 discloses a laser diode driving device that enables short pulse laser light output. In this drive, the switching element is turned off to charge the capacitor, and then the switching element is turned on to discharge the capacitor. The discharge current at this time causes the laser diode to emit light. After the laser diode stops emitting light, the switching element is turned off and the capacitor is charged again. As is well known, the pulse width of the laser beam (the time from when the switching element is turned on until the discharge current of the capacitor becomes 0) is determined by the circuit constant of the LCR resonance circuit. In the disclosure of the same document, the LCR resonant circuit includes a capacitor, a laser diode, a switching element (in the on state), a diode connected in parallel with the laser diode, and a parasitic inductance.

Patent Document 3 also discloses an example of a laser diode driving device (driving circuit). The drive device described in the document includes a resistor connected in series with a laser diode.

Japanese Unexamined Patent Publication No. 2016-161533 Japanese Unexamined Patent Publication No. 2016-152336 JP-A-2002-16314

In the drive device of Patent Document 1, when the switching element is in a conductive state, a current flows through the laser diode and a current also flows through the switching element. In this configuration, the amount of current flowing through the laser diode is reduced by the parasitic inductance component and the parasitic resistance component of the switching element.

According to Patent Document 2, the discharge current becomes 0 when the electric charge accumulated in the capacitor disappears, and the light emission of the laser diode stops. In the laser diode driving device of the same document, the shortening of the output period of the laser beam is limited by the parasitic inductance, and the output period of the laser beam may not be sufficiently shortened. Further, in the laser diode driving device of the same document, the on-time of the switching element is set to 1000 times or more the output period of the laser beam. Therefore, unnecessary laser light is intermittently output until the resonance of the LCR resonance circuit is sufficiently attenuated.

According to Patent Document 3, when a drive current flows through a laser diode, a drive current also flows through a resistor connected in series with the laser diode. At this time, the driving current of the laser diode decreases due to the parasitic inductance of the resistor. In particular, the more the laser diode is driven with a large current and a short pulse, the more remarkable the decrease in the drive current due to the parasitic inductance becomes.

In view of the above circumstances, one object of the present disclosure is to provide a laser diode driving device capable of efficiently emitting a laser diode.

Another object of the present disclosure is to provide a laser diode driving device capable of shortening the output period of the laser beam and suppressing unnecessary laser beam output.

Another object of the present disclosure is to provide various products (for example, a laser device, a laser radar device, a vehicle, etc.) including the laser diode driving device as described above.

According to the first aspect of the present disclosure, a drive device for driving and controlling a laser diode is provided. The drive device includes a switching element that switches between a conduction state and a cutoff state, a capacitor, a first diode, and an input terminal to which a power supply voltage is supplied. The first end of the capacitor is connected to the cathode of the laser diode, and the second end is connected to the switching element. In the first diode, the anode is connected to the connection point between the first end of the capacitor and the cathode of the laser diode. The input terminal is connected to a connection point between the second end of the capacitor and the switching element.

According to the second aspect of the present disclosure, a drive device that controls the drive of the laser diode is provided. The drive device has a switching element, a control unit that controls on / off of the switching element, a rectifying element in which an anode and a cathode are connected in parallel to the laser diode in opposite directions, and the switching element is off. A capacitor that is sometimes charged and that forms a closed circuit with the switching element, the laser diode, and the rectifying element when the switching element is on. The control unit is configured to make the on-time of the switching element shorter than half of the resonance period of the closed circuit.

According to the third aspect of the present disclosure, there is provided a drive device including a plurality of electronic components for supplying a drive current to the laser diode and a circuit board on which the plurality of electronic components are mounted. The plurality of electronic components include a switching element that switches between a conduction state and a cutoff state, a plurality of resistors connected in parallel with each other and each connected in series with the anode of the laser diode, and a cathode of the laser diode. It includes a capacitor connected to the switching element. The plurality of resistors are arranged in a first direction orthogonal to the thickness direction of the circuit board. Of the plurality of resistors, two resistors adjacent to each other in the first direction have a separation distance in the first direction equal to or larger than the dimension of any one of the plurality of resistors in the first direction.

Further features and advantages of this disclosure will be further clarified by the following detailed description based on the accompanying drawings.

It is a figure which shows the circuit structure of the drive device based on the embodiment of the 1st aspect. It is a figure which shows the operation example of a drive device. It is a figure which shows the operation example of a drive device. It is a top view which shows the module structure of a drive device, and shows a component layout and a land pattern. It is a top view which shows the wiring layer (first layer) of a circuit board. It is a top view which shows the wiring layer (second layer) of a circuit board. It is a top view which shows the wiring layer (third layer) of a circuit board. It is a top view which shows the wiring layer (fourth layer) of a circuit board. It is a top view which shows the solder layer formed on the wiring layer (first layer). It is a top view which shows the solder layer formed under the wiring layer (fourth layer). It is a top view which shows the switching element. It is a top view which shows the module structure of the drive device which concerns on the modification based on 1st side surface. It is a top view which shows the module structure of the drive device which concerns on the modification based on 1st side surface. It is a figure which shows the schematic structure of the laser apparatus based on the embodiment of the 2nd aspect. It is a figure which shows the time chart of a resonance current and a gate signal. It is a figure which shows the path through which a positive resonance current flows. It is a figure which shows the path through which a negative resonance current flows. It is a figure which shows one configuration example of a control part. It is a figure which shows the specific example of the control part of the configuration example shown in FIG. It is a figure which shows the time chart of each signal of the control part shown in FIG. 19A. It is a figure which shows the other specific example of the control part of the configuration example shown in FIG. It is a figure which shows still more specific example of the control part of the configuration example shown in FIG. It is a figure which shows the modification of the control part shown in FIG. 19A. It is a figure which shows the time chart of each signal of the control part shown in FIG. 19E. It is a figure which shows the modification of the control part shown in FIG. 19E. It is a figure which shows the structural example of a shunt resistor. It is a top view of the substrate. It is a schematic diagram which shows the cross section of a substrate. It is a figure which shows the schematic structure of the laser radar apparatus. It is an external view of a vehicle. It is a figure which shows the circuit structure of the drive device based on the embodiment of the 3rd aspect. It is a figure which shows the operation example of a drive device. It is a figure which shows the operation example of a drive device. It is a top view which shows the module structure of a drive device, and shows a component layout and a land pattern. It is a partially enlarged view which is a part of FIG. 28 enlarged. It is a top view which shows the wiring layer (first layer) of a circuit board. It is a top view which shows the wiring layer (second layer) of a circuit board. It is a top view which shows the wiring layer (third layer) of a circuit board. It is a top view which shows the wiring layer (fourth layer) of a circuit board. It is a top view which shows the switching element. It is a figure which showed the time change of the voltage applied to a shunt resistor. It is a top view (layout view) which shows the driving device which concerns on a modification. It is a circuit block diagram of the drive device of FIG. It is a top view (layout view) which shows the driving device which concerns on a modification. It is a circuit block diagram of the drive device of FIG. 38. It is a top view (layout view) which shows the driving device which concerns on a modification. It is a circuit block diagram of the drive device of FIG. 40. It is a top view (layout view) which shows the driving device which concerns on a modification. It is a circuit block diagram of the drive device of FIG. 42.

An embodiment based on the first aspect of the present disclosure will be described below with reference to FIGS. 1 to 13. In FIGS. 1 to 13, the same or similar components are designated by the same reference numerals and the description thereof will be omitted.

1 to 11 show the drive device A1 based on the embodiment of the first aspect. The drive device A1 controls the drive of the laser diode LD (for example, irradiation of laser light). The drive device A1 supplies a drive current to the laser diode LD, and causes the laser diode LD to emit light with a brightness corresponding to the drive current. The laser diode LD connected to the drive device A1 may be a TO-Can package type or a surface mount type.

An example of the circuit configuration of the drive device A1 will be described with reference to FIG. As shown in FIG. 1, the drive device A1 includes a switching element Q1, a plurality of capacitors C1, a plurality of shunt resistors R1, a feedback diode (rectifier element) D1, a discharge diode D2, a drive circuit DR, a pulse generation circuit PG, and a plurality of shunt resistors R1. It includes connector terminals T1 to T3, socket terminals T4, connection terminals T5, and two power supply units PS1 and PS2. In FIG. 1, the connection of the laser diode LD is shown by an imaginary line (dashed line).

The switching element Q1 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The switching element Q1 is not limited to the MOSFET, and may be another transistor. The switching element Q1 is made of a semiconductor material. The semiconductor material is, for example, GaN (gallium nitride). The semiconductor material is not limited to GaN, and may be Si (silicon), SiC (silicon carbide), GaAs (gallium arsenide), Ga ₂ O ₃ (gallium oxide), or the like.

As shown in FIG. 1, in the switching element Q1, the drain is connected to each capacitor C1, the source is connected to the ground end GND, and the gate is connected to the drive circuit DR. The ground terminal GND gives a reference potential. A drive signal is input to the gate of the switching element Q1 from the drive circuit DR, and the conduction state and the cutoff state are switched according to the drive signal. In the following, an operation of switching between a conduction state (on state) and a cutoff state (off state) may be referred to as a “switching operation”. The conductive state is a state in which a current flows between the drain and the source, and the cutoff state is a state in which no current flows between the drain and the source. The drive signal is, for example, a pulse wave in which an on signal and an off signal are alternately switched. The switching element Q1 is in a conductive state when the drive signal is an on signal, and is in a cutoff state when the drive signal is an off signal, for example.

As shown in FIG. 1, a plurality of capacitors C1 are connected in parallel with each other. In each capacitor C1, the first end C11 is connected to the cathode of the laser diode LD, and the second end C12 is connected to the drain of the switching element Q1. Further, the first end C11 of each capacitor C1 is also connected to the anode of the feedback diode D1 and the anode of the discharge diode D2, respectively. Each capacitor C1 is connected to the power supply unit PS1, and the power supply voltage VLD is applied from the power supply unit PS1.

As shown in FIG. 1, a plurality of shunt resistors R1 are connected in parallel with each other. In each shunt resistor R1, the first end R11 is connected to the cathode of the feedback diode D1 and the anode of the laser diode LD, and the second end R12 is connected to the ground end GND.

As shown in FIG. 1, the feedback diode D1 has an anode connected to the cathode of the laser diode LD and a cathode connected to the anode of the laser diode LD. Further, in the feedback diode D1, the anode is connected to the second end C12 of each capacitor C1, and the cathode is connected to the first end R11 of each shunt resistor R1. As shown in FIG. 1, the feedback diode D1 has an anode connected to a connection point between the second end C12 of each capacitor C1 and the cathode of the laser diode LD. In the example shown in FIG. 1, the feedback diode D1 is a Schottky barrier diode.

As shown in FIG. 1, the discharge diode D2 has an anode connected to the second end C12 of the capacitor C1 and a cathode connected to the ground end GND via a resistor. In the example shown in FIG. 1, the discharge diode D2 is a Schottky barrier diode.

The pulse generation circuit PG generates a pulse signal for controlling the switching operation of the switching element Q1. The pulse generation circuit PG receives a control signal from the connector terminal T1 and generates a pulse signal based on the control signal. The pulse generation circuit PG outputs the generated pulse signal to the drive circuit DR. The pulse signal in the present embodiment is, for example, a square wave having a frequency of 20 kHz (period of 50,000 nsec) and an on-time of 50 nsec. The duty ratio of this pulse signal is 0.1%.

The drive circuit DR generates a drive signal for driving (switching operation) the switching element Q1. In the drive circuit DR, a pulse signal is input from the pulse generation circuit PG, and a drive signal is generated based on the pulse signal. The drive signal is, for example, a signal obtained by boosting the pulse signal to a voltage required for driving the switching element Q1. The drive circuit DR includes a drive IC 9, and a drive signal is generated by the drive IC 9. The drive circuit DR outputs the generated drive signal to the gate of the switching element Q1 via the gate resistor R2. The gate resistor R2 may not be provided in some cases.

The connector terminal T1 is an input terminal for the power supply voltage VLD. A DC power supply (external power supply) provided outside the drive device A1 is connected to the connector terminal T1, and a power supply voltage VLD is supplied from this external power supply. The power supply voltage VLD is used for driving the laser diode LD, and is, for example, 3 V or more and 100 V or less. The connector terminal T1 is also an input terminal for a control signal. The connector terminal T1 is, for example, a plug-type terminal.

Each connector terminal T2 and T3 is a jack type terminal to which a coaxial cable can be connected, for example.

The socket terminal T4 is a terminal for connecting a TO-Can package type laser diode. When the laser diode LD is a TO-Can package type, the laser diode LD is connected to the socket terminal T4.

The connection terminal T5 is a terminal for connecting a surface-mounted laser diode. When the laser diode LD is a surface mount type, the laser diode LD is connected to the connection terminal T5.

As shown in FIG. 1, the power supply unit PS1 is connected between the connector terminal T1 and the plurality of capacitors C1. The power supply unit PS1 includes an electrolytic capacitor C2, a backflow prevention diode D3, a reactor L1, a charging resistor R3, and the like. The electrolytic capacitor C2 is a bypass capacitor and stabilizes the input voltage (power supply voltage VLD). The backflow prevention diode D3 prevents current from flowing from each capacitor C1 side to the external power supply (connector terminal T1) side. The reactor L1 boosts the input voltage. The charging resistor R3 adjusts the amount of current of the current from the external power supply (connector terminal T1) side toward each capacitor C1.

The power supply unit PS2 generates an operating voltage V1. The operating voltage V1 is mainly used for driving each electronic component constituting the pulse generation circuit PG. The operating voltage V1 is, for example, 3.3 V, but is not limited thereto.

As shown in FIG. 1, the drive device A1 includes two test points TP1 and TP2. Each test point TP1 and TP2 is a terminal for signal detection.

The drive control (light emission operation) of the laser diode LD by the drive device A1 will be described with reference to FIGS. 2 and 3. 2 and 3 are diagrams in which the main electronic components in the light emitting operation of the laser diode LD are extracted from the circuit configuration of the drive device A1 shown in FIG. In FIGS. 2 and 3, a plurality of capacitors C1 and a plurality of shunt resistors R1 are shown one by one. The DC power supply shown in FIGS. 2 and 3 corresponds to the external power supply connected to the connector terminal T1 shown in FIG. 1 and the power supply unit PS1. FIG. 2 shows the case where the switching element Q1 is in the cutoff state, and FIG. 3 shows the case where the switching element Q1 is in the conductive state.

When the switching element Q1 is cut off, a current flows from the DC power supply to each capacitor C1 as shown in FIG. 2 (see the current path shown by the broken line). Due to this current, electric charge is accumulated in the second end C12 of each capacitor C1 and each capacitor C1 is charged. At this time, assuming that the power supply voltage of the DC power supply is VLD, the potential of the second end C12 of each capacitor C1 is the power supply voltage VLD. When each capacitor C1 is fully charged, this current stops flowing. When the switching element Q1 is in the cutoff state, no voltage is applied to the laser diode LD and the laser diode LD does not emit light.

When the switching element Q1 is brought into a conductive state, as shown in FIG. 3, the second end C12 of each capacitor C1 conducts to the ground end GND via the switching element Q1. As a result, the second end C12 is grounded to the reference potential, and the potential of the second end C12 of each capacitor C1 fluctuates (decreases) to the reference potential. At this time, since the potential difference between the first end C11 and the second end C12 of each capacitor C1 is constant, the potential of the first end C11 of each capacitor C1 also fluctuates (decreases) by the potential fluctuation of the second end C12. To do). That is, as shown in FIG. 3, the potential of the first end C11 of the capacitor C1 becomes the reference potential (GND), and the potential of the second end C12 becomes the difference (GND-VLD) between the reference potential and the power supply voltage VLD. As a result, the anode side of the laser diode LD has a higher potential than the cathode side, a forward current flows through the laser diode LD, and the laser diode LD emits light. In the present embodiment, as shown in FIG. 3, a current path passing through the laser diode LD and the discharge diode D2 and a current path passing through the laser diode LD and the feedback diode D1 are generated from the shunt resistor R1 (each shown by a broken line). See current path).

An example of the module configuration of the drive device A1 will be described with reference to FIGS. 4 to 11. For convenience, the three directions orthogonal to each other (x direction, y direction and z direction) are appropriately referred to. The z direction corresponds to the thickness direction of the drive device A1 (or the circuit board 10).

The drive device A1 includes a circuit board 10 and a plurality of electronic components. The plurality of electronic components correspond to the plurality of electronic components in the circuit configuration shown in FIG. 1, and are mounted on the circuit board 10.

FIG. 4 shows the component layout and land pattern on the circuit board 10. In FIG. 4, a plurality of electronic components are shown by imaginary lines (dashed-dotted lines).

As shown in FIG. 4, the circuit board 10 has a substantially rectangular shape in a plan view. The circuit board 10 has, for example, a dimension of 70.0 mm in the x direction and a dimension of 45.0 mm in the y direction. The plan view dimensions of the circuit board 10 are not limited to this, and can be changed as appropriate.

The circuit board 10 is, for example, a laminated board, and includes a plurality of wiring layers Ly1 to Ly4 that are laminated to each other. The wiring layers Ly1 to Ly4 are separated from each other via an insulating layer. 5 to 8 are plan views showing each wiring layer Ly1 to Ly4, respectively. As shown in FIGS. 5 to 8, wiring patterns 20 (parts painted in black) are arranged in the wiring layers Ly1 to Ly4.

The wiring layer Ly1 is the first layer (top layer) of the circuit board 10. Each electronic component is mounted on the wiring layer Ly1. The solder layer 21 shown in FIG. 9 is formed on the upper surface of the wiring layer Ly1. In FIG. 9, the region where the solder 210 is formed is painted in black. The solder layer 21 is partially covered with a resist film (not shown). The solder 210 exposed from the resist film corresponds to the land pattern shown in FIG. The wiring layer Ly4 is a fourth layer (bottom layer) in the circuit board 10. The solder layer 22 shown in FIG. 10 is formed on the lower surface of the wiring layer Ly4. In FIG. 10, the region where the solder 220 is formed is painted in black. The solder layer 22 is partially covered with a resist film (not shown). The wiring layers Ly2 and Ly3 are intermediate layers in the circuit board 10. The wiring layer Ly2 is a second layer in the circuit board 10, and is sandwiched between the wiring layer Ly1 and the wiring layer Ly3 in the z direction. The wiring layer Ly3 is a third layer in the circuit board 10, and is sandwiched between the wiring layer Ly2 and the wiring layer Ly4 in the z direction. As shown in FIGS. 6 and 7, each wiring layer Ly2 and Ly3 has a wiring pattern 20 grounded at a reference potential formed along the outer peripheral edge in a plan view. The plurality of wiring layers Ly1 to Ly4 are electrically connected to each other by the penetrating vias penetrating the insulating layer.

As shown in FIGS. 4 to 10, the circuit board 10 is formed with through holes HL at its four corners, respectively. Each through hole HL penetrates the circuit board 10 in the z direction. Each through hole HL is provided to fix the drive device A1 to the support member, and a fastener such as a bolt can be inserted therethrough. In a plan view, wiring patterns 20 grounded at a reference potential are arranged in each of the wiring layers Ly1 to Ly4 around each through hole HL, and are used as a grounding end GND. Each through hole HL is arranged so that the center in a plan view overlaps with each of the four corners of the circuit board 10 at positions of, for example, 3.5 mm in the x direction and 3.5 mm in the y direction.

Each electronic component mounted on the circuit board 10 will be described with reference to FIG.

As can be seen from FIG. 4, a plurality of capacitors C1 are arranged side by side in the x direction (adjacent to each other in the x direction at predetermined intervals in the illustrated example) to form the capacitor group C0. ing. That is, the plurality of capacitors C1 are adjacent to each other with a sufficiently short separation distance, and other elements (for example, functional elements) are configured not to be arranged between the plurality of capacitors C1. As shown in the figure, the two terminals (C11 and C12) of each capacitor C1 are arranged so as to be arranged in the y direction. Each capacitor C1 is, for example, a chip type, but may be a lead type.

As shown in FIG. 4, a plurality of shunt resistors R1 are arranged side by side in the x direction to form a shunt resistor group R0. In each shunt resistor R1, two terminals (first end R11 and second end R12) are arranged in the y direction. Each shunt resistor R1 is, for example, a chip type, but may be a lead type.

The capacitor group C0 and the shunt resistor group R0 are aligned in the y direction as shown in FIG. In the y direction, a socket terminal T4 and a feedback diode D1 are arranged between the capacitor group C0 and the shunt resistor group R0. The socket terminal T4 and the feedback diode D1 are adjacent to each other in the y direction.

As shown in FIG. 4, the switching element Q1 is aligned with the capacitor group C0 in the y direction. In the example shown in FIG. 4, the switching element Q1 is adjacent to the capacitor group C0 in the y direction. The switching element Q1 is located on the side opposite to the shunt resistance group R0 with respect to the capacitor group C0 in the y direction.

As shown in FIG. 4, the drive IC 9 and the switching element Q1 are adjacent to each other in the y direction. As shown in FIG. 11, the switching element Q1 has a plurality of electrodes Q11, Q12, and Q13 formed on the lower surface in the z direction. The plurality of electrodes Q11 are gate terminals in the switching element Q1. The plurality of electrodes Q12 are drain terminals in the switching element Q1. The plurality of electrodes Q13 are source terminals in the switching element Q1. In the present embodiment, the switching element Q1 is mounted on the circuit board 10 so that a plurality of electrodes Q11 (gate terminals) are arranged near the drive IC 9 in the y direction. The arrangement of the electrodes Q11, Q12, and Q13 is not limited to the example shown in FIG.

As shown in FIG. 4, each electronic component (see FIG. 1) constituting the drive circuit DR is arranged in the capacitor group C0 in the y direction, and is on the opposite side of the shunt resistor group R0 with reference to the capacitor group C0. Located in. Each electronic component constituting the drive circuit DR and the switching element Q1 are covered with an electromagnetic shield 28. The land pattern shown in FIG. 4 shows a pattern 29 to which the electromagnetic shield 28 is joined. The electromagnetic shield 28 suppresses noise from being superimposed on each electronic component or switching element Q1 constituting the drive circuit DR. As a result, it is possible to prevent each electronic component (for example, drive IC9) and the switching element Q1 constituting the drive circuit DR from malfunctioning due to noise.

As shown in FIG. 4, switching element Q1, drive circuit DR, capacitor group C0 (plurality of capacitors C1), shunt resistance group R0 (plurality of shunt resistors R1), feedback diode D1, discharge diode D2, socket terminal T4, and , The connection terminal T5 is arranged on one side of the center of the circuit board 10 in the x direction.

As shown in FIG. 4, the connection terminal T5 is arranged along the edge of the circuit board 10 in a plan view. As shown in FIG. 4, the connection terminal T5 has a solid pattern. In FIG. 4, the connection terminal T5 has the cathode of the laser diode connected to the upper side in the y direction and the anode of the laser diode connected to the lower side in the y direction. It is also possible to connect a TO-Can package type laser diode LD to the connection terminal T5. For example, in a TO-Can package type laser diode, the TO-Can package type laser diode is connected to the connection terminal T5 by joining the anode and cathode pin terminals to the direct connection terminal T5 with solder or the like. it can.

As shown in FIG. 4, the discharge diode D2 is arranged next to the drive circuit DR and the switching element Q1 in the x direction, and is arranged along the edge of the circuit board 10 in a plan view. The discharge diode D2 and the connection terminal T5 are aligned in the y direction. The discharge diode D2 is arranged between the capacitor group C0 and the grounding end GND (through hole HL on the upper right) in the y direction.

The actions and effects of the drive device A1 are as follows.

The drive device A1 includes a switching element Q1 and a capacitor C1. In the capacitor C1, the first end C11 is connected to the cathode of the laser diode LD, and the second end C12 is connected to the switching element Q1. The connector terminal T1 to which the power supply voltage VLD is input is connected to the connection point between the second end C12 of the capacitor C1 and the switching element Q1, whereby the power supply voltage VLD is connected to the second end C12 of the capacitor C1. It is applied to the connection point with the switching element Q1. According to this configuration, the charge of the capacitor C1 is fluctuated by the switching operation of the switching element Q1, and the forward current flows through the laser diode LD (the laser diode LD emits light) due to this charge fluctuation. At this time, as shown in FIGS. 2 and 3, since the switching element Q1 is not on the current path flowing through the laser diode LD, the current flowing through the switching element Q1 can be suppressed. Therefore, the drive device A1 can suppress a decrease in the amount of current flowing through the laser diode LD due to the parasitic inductance component and the parasitic resistance component of the switching element Q1. That is, the drive device A1 can efficiently make the laser diode LD emit light.

In the drive device A1, each capacitor C1 is connected between the DC power supply and the laser diode LD (see FIGS. 1 to 3). According to this configuration, the power supply voltage VLD from the DC power supply is not directly applied to the laser diode LD. Therefore, the load applied to the laser diode LD is reduced, and the failure of the laser diode LD is suppressed.

In the drive device A1, the capacitor group C0 and the shunt resistor group R0 are aligned in the y direction, and include a socket terminal T4 and a connection terminal T5 to which the laser diode LD is connected between them (see FIG. 4). Further, the discharge diode D2 is arranged between the grounding end GND (through hole HL in the upper right of FIG. 4) and the socket terminal T4 or the connection terminal T5. According to this configuration, in the drive device A1, the current path (see FIG. 3) flowing from the shunt resistor R1 to the grounding end GND via the laser diode LD and the discharge diode D2 can be shortened. As a result, the parasitic inductance component and the parasitic resistance component inside the drive device A1 are reduced.

In the drive device A1, the feedback diode D1 is arranged in the immediate vicinity of the socket terminal T4 (see FIG. 4). According to this configuration, the resonance phenomenon due to the capacitance component of each capacitor C1 and the parasitic inductance component such as the feedback diode D1 and the wiring can be suppressed. Further, since the loop path (see FIG. 3) circulating between the laser diode LD and the feedback diode D1 can be shortened, the parasitic inductance component and the parasitic resistance component in this loop path are suppressed. In the drive device A1, the feedback diode D1 may be arranged between the socket terminal T4 and the connection terminal T5. In this case, the resonance phenomenon can be suppressed regardless of whether the laser diode LD is connected to the socket terminal T4 or the connection terminal T5.

The drive device A1 includes a plurality of capacitors C1 connected in parallel to each other. According to this configuration, the parasitic inductance component inside the drive device A1 can be reduced. As a result, it is possible to suppress a decrease in the amount of current due to the parasitic inductance component inside the drive device A1 and an increase in the pulse width input to the laser diode LD. Further, the drive device A1 includes a plurality of shunt resistors R1 connected in parallel with each other. According to this configuration, the parasitic inductance component inside the drive device A1 can be reduced as in the case of the plurality of capacitors C1.

In the present embodiment, the drive device A1 is provided with both the socket terminal T4 and the connection terminal T5, but may be configured to include only one of them. For example, when the socket terminal T4 is provided and the connection terminal T5 is not provided, it can be configured as shown in FIG. On the other hand, when the socket terminal T4 is not provided and the connection terminal T5 is provided, it can be configured as shown in FIG. In the configuration shown in FIG. 13, the capacitor group C0 and the shunt resistor group R0 are adjacent to each other in the y direction, and the feedback diode D1 and the connection terminal T5 are adjacent to each other in the x direction.

In the present embodiment, the drive device A1 is provided with the discharge diode D2 (and the resistor between the discharge diode D2 and the grounding end GND), but it may not be provided. However, when the discharge diode D2 is provided, the forward current of the laser diode LD can be improved and the measurement stabilization of the current-voltage characteristic of the laser diode LD can be improved as compared with the case where the discharge diode D2 is provided.

The drive device based on the first aspect is not limited to the above-described embodiment. The specific configuration of each part of the drive device can be freely redesigned.

The configuration provided based on the first aspect includes the embodiments described in Appendix 1A-20A below.
Appendix 1 A. A drive device that controls the drive of a laser diode.
A switching element that switches between a conductive state and a cutoff state,
With a capacitor
With the first diode
The input terminal to which the power supply voltage is supplied and
Is equipped with
The capacitor has a first end connected to the cathode of the laser diode and a second end connected to the switching element.
In the first diode, the anode is connected to the connection point between the first end of the capacitor and the cathode of the laser diode.
The input terminal is a drive device connected to a connection point between the second end of the capacitor and the switching element.
Appendix 2 A. The drive device according to Appendix 1A, further comprising a resistor whose first end is connected to the anode of the laser diode.
Appendix 3A. The driving device according to Appendix 2A, wherein the resistor has a second end grounded to a reference potential.
Appendix 4 A. The drive according to Appendix 2A or Appendix 3A, further comprising a second diode whose anode is connected to the first end of the capacitor.
Appendix 5A. The driving device according to Appendix 4A, wherein the second diode has a cathode grounded to a reference potential.
Appendix 6 A. The driving device according to any one of Supplementary A2 to Appendix 5A, wherein the switching element is a field effect transistor.
Appendix 7A. The drain of the switching element is connected to the second end of the capacitor.
The source of the switching element is grounded to the reference potential.
The drive device according to Appendix 6A, wherein a drive signal for switching between the conduction state and the cutoff state is input to the gate of the switching element.
Appendix 8A. The drive device according to Appendix 7A, further comprising a drive circuit for generating the drive signal.
Appendix 9A. The drive device according to any one of Supplementary note 6A to Supplementary note 8A, wherein the switching element is made of a semiconductor material.
Appendix 10 A. The drive device according to any one of Appendix 2A to Appendix 9A, further comprising a circuit board on which the capacitor, the first diode, the input terminal, and the resistor are mounted.
Appendix 11A. It also has an additional capacitor connected in parallel with the capacitor.
The driving device according to Appendix 10A, wherein the capacitor and the additional capacitor are arranged side by side in a first direction orthogonal to the thickness direction of the circuit board to form a capacitor group.
Appendix 12 A. It also has an additional resistor connected in parallel with the resistor.
The driving device according to Appendix 11A, wherein the resistor and the additional resistor are arranged side by side in the first direction to form a group of resistors.
Appendix 13 A. The driving device according to Appendix 12A, wherein the capacitor group and the resistor group are arranged in the thickness direction and the second direction orthogonal to the first direction.
Appendix 14 A. The driving device according to Appendix 13A, wherein the first diode is sandwiched between the capacitor group and the resistor group in the second direction.
Appendix 15 A. The driving device according to Appendix 13A or Appendix 14A, wherein the switching element is located on the opposite side of the resistor group with respect to the capacitor group in the second direction.
Appendix 16 A. The driving device according to Appendix 15A, wherein the switching element is adjacent to the capacitor group in the second direction.
Appendix 17 A. It also has a first terminal to which a TO-Can package type laser diode can be connected.
The drive device according to any one of Supplementary note 13A to Supplementary note 16A, wherein the first terminal is mounted on the circuit board.
Appendix 18 A. The drive device according to Appendix 17A, wherein the first terminal is arranged between the capacitor group and the resistor group in the second direction.
Appendix 19 A. It also has a second terminal to which a surface-mounted laser diode can be connected.
The drive device according to any one of Supplementary note 10A to Supplementary note 18A, wherein the second terminal is mounted on the circuit board.
Appendix 20 A. The driving device according to Appendix 19A, wherein the second terminal is arranged along an edge of the circuit board when viewed in the thickness direction of the circuit board.

<Code in FIGS. 1 to 13>
A1: Drive device 10: Circuit board 20: Wiring pattern 29: Patterns 21 and 22: Solder layer 210, 220: Solder 28: Electromagnetic shield C0: Capacitor group C1: Capacitor C11: First end C12: Second end C2: Electrolytic Capacitor D1: Feedback diode D2: Discharge diode D3: Backflow prevention diode DR: Drive circuit 9: Drive IC
GND: Grounding end HL: Through hole L1: Reactor LD: Laser diode Ly1 to Ly4: Wiring layer PG: Pulse generation circuit PS1, PS2: Power supply unit Q1: Switching element Q11, Q12, Q13: Electrode R0: Shunt resistor group R1: Shunt resistance R11: 1st end R12: 2nd end R2: Gate resistance R3: Charging resistance T1, T2, T3: Connector terminal T4: Socket terminal T5: Connection terminal

Next, an embodiment based on the second aspect of the present disclosure will be described with reference to FIGS. 14 to 24. The reference numerals in FIGS. 14 to 24 are attached independently of the reference numerals in FIGS. 1 to 13 (first side surface). Therefore, in FIGS. 14 to 24 and FIGS. 1 to 13, the same reference numerals may refer to different elements, or the same (or similar) elements may be referred to.

FIG. 14 is a diagram showing a schematic configuration of a laser device based on the embodiment of the second aspect. The illustrated laser device 1 includes a laser diode LD1 and a laser diode driving device 2.

The laser diode drive device 2 includes an NMOS (N-channel Metal Oxide Semiconductor) transistor Q1, a control unit CNT1, a capacitor C1, a diode D1, and a shunt resistor R1. In the present embodiment, the NMOS transistor Q1 is used as the switching element, but a switching element other than the NMOS transistor Q1 may be used instead of the NMOS transistor Q1. Further, in the present embodiment, the diode D1 is used as the rectifying element, but a rectifying element other than the diode D1 may be used instead of the diode D1. The configuration shown in FIG. 14 also has the same characteristics as the configuration according to the first aspect described above. That is, the laser diode driving device 2 shown in FIG. 14 has a switching element (Q1) that switches between a conduction state and a cutoff state, a capacitor (C1), a first diode (D1), and an input terminal to which a power supply voltage is supplied. (Upper end of PS1) and. The first end (lower end) of the capacitor (C1) is connected to the cathode of the laser diode (LD1), and the second end (upper end) is connected to the switching element (Q1). The anode of the first diode (D1) is connected to a connection point between the first end (lower end) of the capacitor (C1) and the cathode of the laser diode (LD1). The input terminal (upper end of PS1) is connected to a connection point between the second end (upper end) of the capacitor (C1) and the switching element (Q1). Therefore, the above-mentioned technical effect regarding the first aspect is also exhibited in the configuration (second aspect) shown in FIG. On the contrary, it is also possible to apply the configuration according to the second aspect described below to the drive device according to the first aspect. In particular, those skilled in the art will understand that the configuration of the control unit CNT1 according to the second aspect and the control mode thereof can be applied to the drive device according to the first aspect.

The gate signal G1 output from the control unit CNT1 is supplied to the gate of the NMOS transistor Q1. One end of the capacitor C1 and the drain of the NMOS transistor Q1 are connected to the positive electrode of the DC power supply PS1. The other end of the capacitor C1 is connected to the anode of the diode D1 and the cathode of the laser diode LD1. The cathode of the diode D1 and the anode of the laser diode LD1 are connected to one end of the shunt resistor R1. The other end of the shunt resistor R1, the source of the NMOS transistor Q1, and the negative electrode of the DC power supply PS1 are connected to the ground potential.

The control unit CNT1 controls the NMOS transistor Q1 on / off by the gate signal G1.

When the NMOS transistor Q1 is off, a current flows from the positive electrode of the DC power supply PS1 to the negative electrode of the DC power supply PS1 via the capacitor C1, the diode D1 and the shunt resistor R1 in this order, and the capacitor C1 is charged. When the output voltage of the DC power supply PS1 and the potential difference across the capacitor C1 are substantially balanced, the current stops flowing and the charging of the capacitor C1 stops.

When the NMOS transistor Q1 is on, a closed circuit is formed by the NMOS transistor Q1, the capacitor C1, the diode D1, the laser diode LD1, and the shunt resistor R1. The closed circuit contains parasitic inductance. Therefore, the closed circuit becomes an LCR resonant circuit. When the NMOS transistor Q1 is switched from off to on while the electric charge is stored in the capacitor C1, the LCR resonance circuit starts resonance.

When the NMOS transistor Q1 is continuously turned on, the resonance current Ires of the LCR resonance circuit is attenuated with the passage of time as shown by the thick dotted line shown in FIG. The path through which the resonant current Ires flows when the resonant current Ires is positive includes the laser diode LD1 as shown in FIG. Therefore, when the positive resonance current Ires flows, the laser diode LD1 emits light. The path through which the resonance current Ires flows when the resonance current Ires is negative does not include the laser diode LD1 as shown in FIG. Therefore, the laser diode LD1 does not emit light even when a negative resonance current Ires flows. In the present embodiment, the direction from the drain to the source of the NMOS transistor Q1 is defined as the positive direction of the resonance current Ires, and the direction from the source to the drain of the NMOS transistor Q1 is defined as the negative direction of the resonance current Ires.

In the present embodiment, the high level period of the gate signal G1, that is, the on-time of the NMOS transistor Q1 is shorter than half of the resonance period T of the LCR resonance circuit. The on-time of the NMOS transistor Q1 means the time during which the NMOS transistor Q1 is continuously on. Specifically, the period from the time t1 to the time t2 shown in FIG. 15 is the on-time of the NMOS transistor Q1 in the present embodiment.

For a while after the NMOS transistor Q1 is turned off, the resonance current Ires flows through the parasitic capacitance between the drain and source of the NMOS transistor Q1. Therefore, the output period of the laser beam does not completely match the on-time of the NMOS transistor Q1, and is a little longer than the on-time of the NMOS transistor Q1. Specifically, the period from time t1 to time t3 is the output period of the laser beam in the present embodiment.

Since the resonance current Ires becomes substantially zero after the time t3, the laser device 1 does not output the laser light until the next high level period of the gate signal G1 arrives after the time t3.

In the reference example (see the graph at the bottom in FIG. 15), similarly to the laser diode driving device disclosed in Patent Document 2, the high level period of the gate signal G1 is maintained even after the resonance attenuation of the LCR resonance circuit is completed. Followed. Therefore, in the reference example, the high level period of the gate signal G1, that is, the on-time of the NMOS transistor Q1 is longer than half of the resonance period T of the LCR resonance circuit. Since the high level period of the gate signal G1 continues even after the attenuation of the resonance of the LCR resonance circuit is completed, the period in which the resonance current Ires is positive (the period from time t1 to time t4, the period from time t5 to time t6, The laser beam is output in the period from time t7 to time t8). That is, the period from time t1 to time t4 is the output period of the laser beam in the reference example. Further, in the reference example, unnecessary laser light output is generated in the period from the time t5 to the time t6 and the period from the time t7 to the time t8. Unwanted light output during these periods can lead to malfunction of the laser radar device, for example in a vehicle.

As is clear from the above description, the laser diode driving device 2 and the laser device 1 can shorten the output period of the laser beam and suppress unnecessary laser beam output.

In order to prevent the laser light from harming the human eye, it is required that the higher the power of the laser light, the shorter the output period of the laser light. For example, in laser radar devices, development is underway to increase the power of laser light to improve the distance that can be measured, and the output period of laser light can be shortened from the viewpoint of ensuring safety for the human eye. The laser diode driving device 2 and the laser device 1 are very useful. Further, for example, in a laser radar device, an unnecessary laser light output can cause erroneous detection, so that the laser diode driving device 2 and the laser device 1 capable of suppressing the unnecessary laser light output are very useful. ..

The on-time of the NMOS transistor Q1 is preferably shorter than the period from the time t1 to the second timing TM2 in which the resonance current Ires becomes half of the maximum value MAX. In FIG. 15, for ease of understanding, the first timing TM1 in which the resonance current Ires becomes half of the maximum value MAX is also shown.

The pulse width of the laser beam emitted from the laser diode LD1 is usually defined by the full width at half maximum of the current flowing through the laser diode LD1. Therefore, by making the on-time of the NMOS transistor Q1 shorter than the period from the time t1 to the second timing TM2 in which the resonance current Ires becomes half of the maximum value MAX, the pulse width of the laser beam is made larger than that of the above-mentioned reference example. It can be shortened.

The on-time of the NMOS transistor Q1 is preferably one-fourth or more of the resonance period T of the LCR resonance circuit. Since it is possible to prevent the NMOS transistor Q1 from turning off before the resonance current Ires reaches the maximum value MAX, it is possible to suppress a decrease in the power of the laser beam.

FIG. 18 is a diagram showing a configuration example of the control unit CNT1. The control unit CNT1 of the configuration example shown in FIG. 18 includes an input terminal 11, a delay unit 12, a waveform shaping unit 13, a calculation unit 14, and a driver unit 15. The arithmetic unit 14 and the driver unit 15 may be configured by a single IC (Integrated Circuit), or may be separate components.

The input terminal 11 inputs the first pulse signal P1.

The delay unit 12 delays the signal based on the first pulse signal P1 to generate the delay signal DL1. The signal based on the first pulse signal P1 may be the first pulse signal P1 itself.

The waveform shaping unit 13 shapes the waveform of the delay signal DL1 to generate the second pulse signal P2. The waveform shaping unit 13 may perform processing other than waveform shaping on the delay signal DL1.

The calculation unit 14 generates a third pulse signal P3 having a shorter pulse width than the first pulse signal P1 by calculation using the first pulse signal P1 and the second pulse signal P2.

The driver unit 15 amplifies the third pulse signal P3 to generate the gate signal G1. The driver unit 15 provides a current output (for example, 5 A or more) that has a small signal delay, can handle an input signal of a high frequency, ultrashort pulse (for example, a pulse width of 5 nex or less), and can further drive a high output laser. It is preferable that the driver portion has. Further, the smaller the self-inductance of the driver unit 15, the better so that high-speed switching operation is possible. When using an LSI-IC, it is preferable to select a CSP package or a bare chip product.

The NMOS transistor Q1 that receives the gate signal G1 from the driver unit 15 is preferably a transistor having a small input capacitance (for example, 500 pF or less) and a small input impedance (for example, 0.5 Ω or less) so that high-speed switching operation is possible. .. Since a large current flows through the NMOS transistor Q1, it is preferable to use a transistor having a small on-resistance (for example, 20 mΩ or less). Further, it is preferable to select a CSP package or a bare chip product having a small self-inductance of the NMOS transistor Q1.

According to the control unit CNT1 of the configuration example shown in FIG. 18, the pulse width W3 of the third pulse signal P3 and thus the pulse width of the gate signal G1 can be made shorter than the pulse width W1 of the first pulse signal P1 (for example, FIG. 19B described later). reference). As a result, even when the first pulse signal P1 is generated by an inexpensive pulse signal generator that cannot sufficiently shorten the pulse width of the pulse signal, the pulse width of the gate signal G1, that is, the high level period of the gate signal G1 can be set. It can be shorter than half of the resonance period T of the LCR resonance circuit.

Therefore, when the control unit CNT1 of the configuration example shown in FIG. 18 is used, it is preferable that the pulse width of the first pulse signal P1 is set to half or more of the resonance period T of the LCR resonance circuit. As a result, the cost of the pulse signal generator that generates the first pulse signal P1 can be reduced.

In the present embodiment, the pulse widths of the first pulse signal P1, the third pulse signal P3, and the gate signal G1 are each high level period of the first pulse signal P1, the third pulse signal P3, and the gate signal G1. The low level period may be the pulse width depending on the characteristics of the switching element, the use of the inverter, and the like.

FIG. 19A is a diagram showing a specific example of the control unit CNT1 of the configuration example shown in FIG. FIG. 19B is a time chart of each signal of the control unit CNT1 shown in FIG. 19A.

The control unit CNT1 shown in FIG. 19A includes a hysteresis inverter INV1 in addition to the input terminal 11, the delay unit 12, the waveform shaping unit 13, the calculation unit 14, and the driver unit 15. The hysteresis inverter INV1 inverts the first pulse signal P1 and supplies the inverted signal of the first pulse signal P1 to the delay unit 12. The delay unit 12 of the control unit CNT1 shown in FIG. 19A is configured by the resistor 12A and the capacitor 12B, and the waveform shaping unit 13 of the control unit CNT1 shown in FIG. 19A is composed of the hysteresis inverter INV2.

As shown in FIG. 19B, the hysteresis inverter INV2 shapes the waveform of the delay signal DL1 while inverting the delay signal DL1. Specifically, as shown in FIG. 19B, the hysteresis inverter INV2 shapes the waveform of the delay signal DL1 so that the switching between the high level and the low level becomes steep while inverting the delay signal DL1.

The waveform shaping unit 14 of the control unit CNT1 shown in FIG. 19A performs arithmetic processing for subtracting the second pulse signal G2 from the first pulse signal G1 to generate the third pulse signal P3.

FIG. 19C is a diagram showing another specific example of the control unit CNT1 of the configuration example shown in FIG. The control unit CNT1 shown in FIG. 19C is different from the control unit CNT1 shown in FIG. 19A in that the hysteresis inverter INV1 is provided between the delay unit 12 and the hysteresis inverter INV2. The waveform shaping unit 13 of the control unit CNT1 shown in FIG. 19C is composed of the hysteresis inverters INV1 and INV2. The waveform shaping unit 13 of the control unit CNT1 shown in FIG. 19C shapes the waveform of the delay signal DL1 while inverting the delay signal DL1 twice.

As in the control unit CNT1 of the configuration example shown in FIG. 19D, only one hysteresis inverter may be provided in the path from the input terminal 11 to the calculation unit 14 via the delay unit 12.

When the logic of the gate signal G1 may be inverted with respect to the control unit CNT1 shown in FIG. 19A and the control unit CNT1 shown in FIG. 19C, the calculation unit 14 of the control unit CNT1 of the configuration example shown in FIG. The third pulse signal P3 may be generated by performing arithmetic processing for subtracting the second pulse signal G2 from the first pulse signal G1.

On the other hand, when the logic of the gate signal G1 must not be inverted with respect to the control unit CNT1 shown in FIG. 19A and the control unit CNT1 shown in FIG. 19C, the calculation unit 14 of the control unit CNT1 of the configuration example shown in FIG. 19D , The second pulse signal G2 may be inverted inside the arithmetic unit 14, and then the arithmetic processing of subtracting the inverted signal of the second pulse signal G2 from the first pulse signal G1 may be performed to generate the third pulse signal P3. ..

If the performance of the pulse signal generator that generates the first pulse signal P1 is low, the slew rate of the rising edge and the falling edge of the first pulse signal P1 can be large. Therefore, the arrangement of the hysteresis inverter INV1 of the control unit CNT1 shown in FIG. 19A is changed to FIG. 19E so that the first pulse signal P1 having a large slew rate of the rising edge and the falling edge can be appropriately handled. The configuration shown may be used.

In the control unit CNT1 shown in FIG. 19E, the hysteresis inverter INV1 is used as the waveform shaping unit 13'that generates the waveform of the first pulse signal P1 and supplies the pulse signal P1'after the waveform shaping to the calculation unit 14. In FIG. 19B, the time chart of each signal of the control unit CNT1 shown in FIG. 19E is as shown in FIG. 19F. H1 in FIG. 19F shows the hysteresis amount of the hysteresis inverter INV1, and H2 in FIG. 19F shows the hysteresis amount of the hysteresis inverter INV2.

The control unit CNT1 shown in FIG. 19A, the control unit CNT1 shown in FIG. 19C, the control unit CNT1 shown in FIG. 19D, and the control unit CNT1 shown in FIG. 19E are configured to include a hysteresis inverter, but instead of the hysteresis inverter, for example, A hysteresis comparator may be used. For example, the control unit CNT1 shown in FIG. 19E may be configured as shown in FIG. 19G by using the hysteresis comparators COM1 and COM2 instead of the hysteresis inverters INV1 and INV2. The control unit CNT1 shown in FIG. 19G is different from the control unit CNT1 shown in FIG. 19E in that the waveform shaping units 13 and 13'do not invert signals. However, the signal may be inverted in the waveform shaping unit by exchanging the inverting input terminal and the non-inverting input terminal of the hysteresis comparator.

The control unit CNT1 shown in FIG. 19A, the control unit CNT1 shown in FIG. 19C, the control unit CNT1 shown in FIG. 19D, the control unit CNT1 shown in FIG. 19E, and the control unit CNT1 shown in FIG. 19G include a hysteresis inverter or a hysteresis comparator. Although it has a configuration, an inverter having no hysteresis characteristic may be used instead of the hysteresis inverter, and a comparator having no hysteresis characteristic may be used instead of the hysteresis comparator.

FIG. 20 is a diagram showing a configuration example of the shunt resistor R1. The shunt resistor R1 of the configuration example shown in FIG. 20 has a configuration in which a plurality of resistance elements RE1 are connected in parallel. By connecting a plurality of resistance elements RE1 in parallel, it becomes easy to reduce the resistance value of the shunt resistor R1. The plurality of resistance elements RE1 shown in the figure can correspond to the plurality of resistors R1 shown in FIG.

In the laser device 1 shown in FIG. 14, since the on-time of the NMOS transistor Q1 is shorter than half of the resonance period T of the LCR resonance circuit, the power of the laser light is reduced. In order to suppress the power decrease of the laser beam, it is necessary to increase the capacitance of the capacitor C1 and increase the current flowing through the laser diode LD1. When increasing the capacitance of the capacitor C1, it is necessary to decrease the resistance value of the shunt resistor R1 in order to suppress the increase in the resonance period T of the LCR resonance circuit. Therefore, in the laser apparatus 1 shown in FIG. 14, it is important to reduce the resistance value of the shunt resistor R1.

In the configuration example shown in FIG. 20, three resistance elements RE1 are connected in parallel, but the number of resistance elements RE1 connected in parallel is not limited to three, and may be a plurality. However, as the number of resistance elements RE1 connected in parallel increases, it becomes easier to reduce the resistance value of the shunt resistor R1, but the mounting area of the shunt resistor R1 increases. Therefore, the number of resistance elements RE1 connected in parallel may be determined in consideration of the balance between the required resistance value of the shunt resistor R1 and the required mounting area of the shunt resistor R1.

In order to suppress the long resonance period T of the LCR resonance circuit and increase the maximum value of the resonance current Ires of the LCR resonance circuit, the inductance component of the LCR resonance circuit should be small. In order to minimize the parasitic inductance formed by the shunt resistor R1 of the configuration example shown in FIG. 20, it is preferable to set the mutual inductance M of the adjacent resistance elements RE1 to zero.

The mutual inductance M of the adjacent resistance elements RE1 can be expressed by the following equation (1). However, LN is the length of the resistance element RE1, and d is the distance between the adjacent resistance elements RE1. The unit of the mutual inductance M is [H], the unit of the length LN and the unit of the interval d are [m], respectively.
M = 2LN (ln (2LN / d) -1) x 10-7 ... (1)

The condition for suppressing the mutual inductance M to zero can be expressed by the following equation (2). However, e is the number of Napiers.
ln (2LN / d) -1 ≤ 0
d ≧ 2LN / e ・ ・ ・ (2)
The interval d between the adjacent resistance elements RE1 is preferably a value or more obtained by dividing twice the length LN of the resistance element RE1 by the number of napiers.

The laser device 1 shown in FIG. 14 includes a substrate B1. FIG. 21 is a top view of the substrate B1, and FIG. 22 is a schematic view showing a cross section of the substrate B1. For convenience of explanation, in FIGS. 21 and 22, three directions (x direction, y direction, and z direction) orthogonal to each other are referred to. The z direction corresponds to the thickness direction of the substrate B1.

A plurality of electronic components in the circuit configuration shown in FIG. 14 are mounted on the substrate B1.

FIG. 21 shows the component layout and land pattern on the board B1. In FIG. 21, a plurality of electronic components are shown by imaginary lines (dashed-dotted lines).

The substrate B1 has a rectangular shape in the z-direction view (plan view).

The substrate B1 is a laminated substrate, and as shown in FIG. 22, includes four wiring layers Ly1 to Ly4 laminated with each other via an insulating layer Ly0. The number of wiring layers is not limited to four, and may be a plurality. Unlike this embodiment, it is also possible to use a single layer substrate.

The wiring layer Ly1 is the first layer and the uppermost layer in the substrate B1. A solder layer is formed on the upper surface of the wiring layer Ly1. This solder layer is partially covered with a resist film (not shown). The solder exposed from the resist film corresponds to the land pattern shown in FIG.

The wiring layer Ly4 is the fourth layer and the lowest layer in the substrate B1. The wiring layers Ly2 and Ly3 are intermediate layers in the substrate B1. The wiring layer Ly2 is a second layer on the substrate B1 and is sandwiched between the wiring layer Ly1 and the wiring layer Ly3 in the z direction. The wiring layer Ly3 is a third layer on the substrate B1 and is sandwiched between the wiring layer Ly2 and the wiring layer Ly4 in the z direction. The wiring layer Ly2 is a ground layer to which a ground potential is applied. In the wiring layer Ly2, the ground of the signal system and the ground of the power supply system are not separated, and the ground of the signal system and the ground of the power supply system are shared. As a result, it is possible to suppress the deviation of the reference potential between the signal system and the power supply system. The plurality of wiring layers Ly1 to Ly4 are electrically connected to each other by a penetrating via TV penetrating the insulating layer Ly0. In FIG. 21, the penetrating via TV is shown by a dotted line.

The thickness d0 of the insulating layer Ly0 sandwiched between the wiring layer Ly1 and the wiring layer Ly3 is preferably 200 μm or less. As a result, the length of the penetrating via TV between the wiring layer Ly1 and the wiring layer Ly3 becomes shorter than that of the normal laminated substrate, and the inductance of the penetrating via TV between the wiring layer Ly1 and the wiring layer Ly3 becomes smaller. , The inductance of the LCR resonant circuit can be reduced. In a normal laminated substrate, the length of the penetrating via TV between the wiring layer Ly1 and the wiring layer Ly3 is about 700 μm.

If there is a power supply layer for noise removal by high frequency drive, it is recommended to insert a ground layer between the wiring layer and the power supply layer. If it cannot be inserted, the distance between the wiring layer and the power supply layer should be as large as possible.

As shown in FIG. 21, through holes TH are formed in the four corners of the substrate B1. Each through hole TH penetrates the substrate B1 in the z direction. Each through hole TH is provided to fix the substrate B1 to the support member, and a fastener such as a bolt is inserted through the through hole TH.

Next, each electronic component mounted on the substrate B1 will be described with reference to FIG.

As shown in FIG. 21, the plurality of capacitors C0 are arranged side by side in the x direction. A plurality of capacitors C0 are connected in parallel by the wiring layer Ly1 to form the capacitor C1. In each capacitor C0, two terminals are arranged in the y direction. Each capacitor C0 is, for example, a chip type, but may be a lead type. It is very effective to connect a plurality of capacitors C0 in parallel to form the capacitor C1 in order to reduce the parasitic inductance of the capacitor C1.

As shown in FIG. 21, the plurality of resistance elements RE1 are arranged side by side in the x direction. The plurality of resistance elements RE1 are connected in parallel by the wiring layer Ly1 to form a shunt resistor R1. In each resistance element RE1, two terminals are arranged in the y direction. Each resistance element RE1 is, for example, a chip type, but may be a lead type. Further, according to the above equation (2), it is preferable to select a resistance element (long-side resistance element) having a length LN as short as possible with respect to the interval d, or a metal electrode resistance element.

As shown in FIG. 21, the capacitor C1 and the shunt resistor R1 are aligned in the y direction. In the y direction, a diode D1 and a laser diode LD1 are arranged between the capacitor C1 and the shunt resistor R1. The diode D1 and the laser diode LD1 are arranged in the y direction. Three mounting regions for the laser diode LD1 are provided so that different types of laser diode LD1 can be mounted.

The 1st pin (anode of the laser diode) of the TO-Can package type laser diode LD1 and the 3rd pin (cathode of the laser diode) of the TO-Can package type laser diode LD1 are aligned in the y direction. More specifically, the direction from the 1st pin of the TO-Can package type laser diode LD1 to the 3rd pin of the TO-Can package laser diode LD1 is substantially parallel to the y direction. Further, the direction from the cathode of the chip-type laser diode LD1 mounted on the right end of the substrate B1 to the anode of the laser diode LD1 on the chip side mounted on the right end of the substrate B1 is also substantially parallel to the y direction. As a result, the total length of the path length between the laser diode LD1 and the capacitor C1 and the path length between the laser diode LD1 and the shunt resistor R1 can be minimized. The second pin of the TO-Can package type laser diode LD1 is the cathode of the light receiving element built in the TO-Can package.

As shown in FIG. 21, the switching element Q1 is aligned with the capacitor C1 in the y direction. In the example shown in FIG. 21, the switching element Q1 is adjacent to the capacitor C1 in the y direction. In the y direction, the capacitor C1 is sandwiched between the switching element Q1 and the shunt resistor R1.

FIG. 21 shows an input terminal 11 which is a coaxial connector, an inverter INV1, a delay unit 12 composed of a resistor 12A and a capacitor 12B, an inverter INV2, and an IC package U1 including a calculation unit 14 and a drive unit 15. As shown above, they are arranged in the x direction. As a result, the wiring length in the control unit CNT1 can be shortened.

As shown in FIG. 21, the number of through vias provided in the right half region of the substrate B1 (the region on which the diode D1, the laser diode LD1, the switching element Q1 and the shunt resistor R1 are mounted) is the left of the substrate B1. More than the number of penetrating diodes provided in the half area. Thereby, the ground in the LCR resonance circuit can be particularly strengthened.

The laser device 1 shown in FIG. 14 described above is used, for example, as a part of the laser radar device X1 shown in FIG. 23. The laser radar device X1 shown in FIG. 23 is a scanning laser radar device, and includes a laser device 1, a light receiving device 3, an optical system 4, and an overall control unit 5. The overall control unit 5 controls the output of the laser device 1 and the direction of the mirror in the optical system 4, calculates the distance to the object based on the control content of the output of the laser device 1 and the output signal of the light receiving device 3, and optics. The direction of the object is calculated based on the control content of the direction of the mirror in the system 4.

The laser radar device X1 shown in FIG. 23 is provided at the front end of the vehicle Y1 shown in FIG. 24, for example, and detects an object located in front of the vehicle Y1.

The above embodiment should be considered as an example and not restrictive.

For example, the arrangement of the parallel circuit of the capacitor C1, the diode D1 and the laser diode LD1 and the shunt resistor R1 does not have to be the configuration shown in FIG.

For example, when it is not necessary to detect the current flowing through the laser diode LD1 or when the current flowing through the laser diode LD1 is detected by another method, the shunt resistor R1 may not be provided.

For example, a plurality of embodiments and modifications shown in the present specification may be combined and implemented to the extent possible. Further, the laser diode driving device according to the first side surface may be used for the laser device 1 shown in FIG. Further, the laser device 1 may be used for the laser radar device X1 shown in FIG. 23 (and by extension, the vehicle Y1 shown in FIG. 24).

The configuration provided based on the second aspect includes the embodiments described in Appendix 1B-16B below.
Appendix 1 B. A drive device that controls the drive of a laser diode.
Switching element and
A control unit that controls the switching element on / off,
A rectifying element in which the anode and cathode are connected in parallel to the laser diode in opposite directions,
A capacitor that is charged when the switching element is off, and a capacitor that forms a closed circuit with the switching element, the laser diode, and the rectifying element when the switching element is on.
With
The control unit is a drive device that shortens the on-time of the switching element to less than half of the resonance period of the closed circuit.
The parallel connection between the laser diode and the rectifying element is not limited to the parallel connection between the laser diode only and the rectifying element only, and the parallel connection between the circuit including the laser diode and the rectifying element only. It may be a parallel connection of only the laser diode and the circuit including the rectifying element, or a parallel connection of the circuit including the laser diode and the circuit including the rectifying element.
Appendix 2 B. The control unit makes the on-time of the switching element shorter than the period from the timing when the switching element is switched from off to on to the second timing when the resonance current of the closed circuit becomes half of the maximum value. The drive device described in.
Appendix 3B.
The driving device according to Appendix 1B or Appendix 2B, wherein the control unit sets the on-time of the switching element to one-fourth or more of the resonance period of the closed circuit.
Appendix 4 B. The control unit
A delay unit that delays a signal based on the first pulse signal to generate a delay signal,
A waveform shaping unit that shapes the waveform of the delay signal and generates a second pulse signal,
A calculation unit that generates a third pulse signal having a pulse width shorter than that of the first pulse signal by a calculation using the first pulse signal and the second pulse signal.
With
The drive device according to any one of Appendix 1B to 3B, which controls on / off of the switching element based on the third pulse signal.
Appendix 5 B. The driving device according to Appendix 4B, wherein the pulse width of the first pulse signal is at least half of the resonance period of the closed circuit.
Appendix 6 B. The drive device according to any one of Appendix 1B to 5B, further comprising a shunt resistor for detecting a current flowing through the laser diode, wherein the closed circuit includes the shunt resistor.
Appendix 7 B. The driving device according to Appendix 6B, wherein the shunt resistor includes a plurality of resistance elements connected in parallel.
Appendix 8 B. The plurality of resistance elements include a first resistance element and a second resistance element having the same length and adjacent to each other, and the distance between the first resistance element and the second resistance element is 2 having the same length. The drive device according to Appendix 7B, which is equal to or greater than the value obtained by dividing the multiple by the number of napiers.
Appendix 9B. The drive device according to any one of Appendix 1B to 8B, and
With the laser diode
A laser device.
Appendix 10 B.
With more boards
The laser device according to Appendix 9B, wherein the switching element, the parallel circuit including the rectifying element and the laser diode, and the capacitor are arranged side by side in the first direction orthogonal to the thickness direction of the substrate.
Appendix 11B. The laser apparatus according to Appendix 10B, wherein the direction from the anode of the laser diode to the cathode of the laser diode is substantially parallel to the first direction.
Appendix 12 B. The drive device is the drive device described in Appendix 4B.
The laser device according to Appendix 10B or Appendix 11B, wherein the delay unit, the waveform shaping unit, and the calculation unit are arranged in a second direction orthogonal to the thickness direction and the first direction.
Appendix 13B. The substrate is a laminated substrate including a first wiring layer and a second wiring layer, the second wiring layer functions as a ground layer, and the distance between the first wiring layer and the second wiring layer is 200 μm or less. The laser device according to any one of Supplementary note 10B to Supplementary note 12B.
Appendix 14B. The laser device according to Appendix 13B, wherein the ground of the signal system and the ground of the power supply system are shared in the second wiring layer.
Appendix 15 B. A laser radar device including the laser device according to any one of Appendix 9B to 14B.
Appendix 16 B. A vehicle comprising the laser radar device according to Appendix 15B.

<Code in FIGS. 14 to 24>
1 Laser device 2 Laser diode drive device 12 Delay section 13 Waveform shaping section 14 Calculation section C1 Capacitor CNT1 Control section D1 Diode LD1 Laser diode R1 Shunt resistance RE1 Resistor Q1 NMOS transistor X1 Laser radar device Y1 Vehicle

Next, an embodiment based on the third aspect of the present disclosure will be described with reference to FIGS. 25 to 43. The reference numerals in FIGS. 25 to 43 are attached independently of the reference numerals in FIGS. 1 to 13 (first side surface) and 14 to 24 (second side surface). Therefore, in FIGS. 25 to 43 and 1 to 24, the same reference numerals may refer to different elements, or the same (or similar) elements may be referred to.

25 to 34 show the drive device A1 based on the embodiment of the third aspect. The drive device A1 controls the drive (irradiation of laser light) of the laser diode LD. The drive device A1 causes the laser diode LD to emit light by supplying a drive current to the laser diode LD.

The laser diode LD may be built in a so-called TO-Can package type laser module, or may be built in a surface mount type laser module. The package structure of the laser module is not limited to these. In the TO-Can package type laser module, it is assumed that a photodiode is built in in addition to the laser diode LD, but the photodiode may not be built in. The TO-Can package type laser module is provided with three lead terminals, that is, a lead terminal that conducts to the anode of the laser diode LD, a lead terminal that conducts to the cathode of the photodiode, and a cathode and photo of the laser diode LD. There is a lead terminal that conducts to the anode of the diode. The photodiode connections (anode-cathode connections) may be reversed. In the TO-Can package type laser module, the number of lead terminals may be two or four instead of three.

An example of the circuit configuration of the drive device A1 will be described with reference to FIG. As shown in FIG. 25, the drive device A1 includes a switching element Q1, a plurality of capacitors C1, a plurality of shunt resistors R1, a feedback diode D1, a drive circuit DR, two resistors R2, a pulse generation circuit PG, and a plurality of connector terminals. It includes T1 to T3, a connection terminal T4, and two power supply units PS1 and PS2. FIG. 25 also shows a laser diode LD that is driven and controlled by the driving device A1. The configuration shown in FIG. 25 also has the same characteristics as the configuration according to the first aspect described above. That is, the laser diode driving device A1 shown in FIG. 25 has a switching element (Q1) that switches between a conduction state and a cutoff state, a capacitor (C1), a first diode (D1), and an input terminal to which a power supply voltage is supplied. (See VLD) and. The first end (lower end) of the capacitor (C1) is connected to the cathode of the laser diode (LD1), and the second end (upper end) is connected to the switching element (Q1). The anode of the first diode (D1) is connected to a connection point between the first end (lower end) of the capacitor (C1) and the cathode of the laser diode (LD1). The input terminal (see VLD) is connected to a connection point between the second end (upper end) of the capacitor (C1) and the switching element (Q1). Therefore, the above-mentioned technical effect on the first aspect is also exhibited in the configuration (third aspect) shown in FIG. On the contrary, it is also possible to apply the configuration according to the third aspect described below to the drive device according to the first aspect.

As shown in FIG. 25, the switching element Q1 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The switching element Q1 is not limited to the MOSFET, and may be another transistor. The switching element Q1 is made of a semiconductor material. The semiconductor material is, for example, GaN (gallium nitride). The semiconductor material is not limited to GaN, and may be Si (silicon), SiC (silicon carbide), GaAs (gallium arsenide), Ga ₂ O ₃ (gallium oxide), or the like.

As shown in FIG. 25, the switching element Q1 has a drain connected to each capacitor C1, a source connected to the ground terminal GND, and a gate connected to the drive circuit DR. The ground terminal GND gives a reference potential. A drive signal is input to the gate of the switching element Q1 from the drive circuit DR, and the conduction state and the cutoff state are switched according to the drive signal. In the following, an operation of switching between a conduction state and a cutoff state may be referred to as a “switching operation”. The conductive state is a state in which a current flows between the drain and the source, and the cutoff state is a state in which no current flows between the drain and the source. The drive signal is, for example, a pulse wave in which an on signal and an off signal are alternately switched. For example, the switching element Q1 is in a conductive state when the drive signal is an on signal, and is in a cutoff state when the drive signal is an off signal.

As shown in FIG. 25, the plurality of capacitors C1 are connected in parallel with each other. In each capacitor C1, the first end C11 is connected to the cathode of the laser diode LD, and the second end C12 is connected to the drain of the switching element Q1. Further, the first end C11 of each capacitor C1 is also connected to the anode of the feedback diode D1. Each capacitor C1 (second end C12) is connected to the power supply unit PS1, and the power supply voltage VLD is applied from the power supply unit PS1. In the present embodiment, the case where 10 capacitors C1 are connected in parallel will be described, but the number of capacitors C1 is not limited to this.

As shown in FIG. 25, the plurality of shunt resistors R1 are connected in parallel with each other. In each shunt resistor R1, the first end R11 is connected to the cathode of the feedback diode D1 and the anode of the laser diode LD, and the second end R12 is connected to the ground end GND. In the present embodiment, the case where three shunt resistors R1 are connected in parallel will be described, but the number of shunt resistors R1 is not limited to this. A plurality of shunt resistors R1 are connected to monitor the drive current of the laser diode LD. The current value monitored by the shunt resistor R1 can be detected from the connector terminal T3.

As shown in FIG. 25, the feedback diode D1 has an anode connected to the cathode of the laser diode LD and a cathode connected to the anode of the laser diode LD. Further, in the feedback diode D1, the anode is connected to the first end C11 of each capacitor C1, and the cathode is connected to the first end R11 of each shunt resistor R1. As shown in FIG. 25, in the feedback diode D1, the anode is connected to the connection point between the first end C11 of each capacitor C1 and the cathode of the laser diode LD, and the cathode is connected to the first end R11 of each shunt resistor R1. It is connected to the connection point of the anode of the laser diode LD. In the example shown in FIG. 25, a PN junction diode (for example, a fast recovery diode) is used as the feedback diode D1, but a Schottky barrier diode may be used.

The pulse generation circuit PG generates a pulse signal for controlling the switching operation of the switching element Q1. The pulse generation circuit PG receives a control signal from the connector terminal T1 and generates a pulse signal based on the control signal. The pulse generation circuit PG outputs the generated pulse signal to the drive circuit DR. The pulse signal in this embodiment is, for example, a square wave having a frequency of 10 kHz and a duty ratio of 0.005%. Further, this pulse signal has a pulse width of 5 nsec and a pulse rise time of 1 nsec. In the drive device A1, a pulse signal for driving the laser diode LD in 5 nsec or less is generated. It should be noted that each parameter of the pulse signal is an example and is not limited to this.

The drive circuit DR generates a drive signal for driving (switching operation) the switching element Q1. In the drive circuit DR, a pulse signal is input from the pulse generation circuit PG, and a drive signal is generated based on the pulse signal. The drive signal is, for example, a signal obtained by boosting the pulse signal to a voltage required for driving the switching element Q1. The drive circuit DR includes a drive IC 9, and a drive signal is generated by the drive IC 9.

As shown in FIG. 25, each of the two resistors R2 is connected between the drive IC 9 and the gate of the switching element Q1. The drive signal output from the drive IC is input to the gate of the switching element Q1 via either resistor R2. Each resistor R2 is a so-called gate resistor. The current value input to the switching element Q1 is set according to the resistance value of each resistor R2. Further, each resistor R2 controls the switching speed of the switching element Q1.

The connector terminal T1 is an input terminal for the power supply voltage VLD. A DC power supply (external power supply) provided outside the drive device A1 is connected to the connector terminal T1, and a power supply voltage VLD is supplied from this external power supply. The power supply voltage VLD is used to drive the laser diode LD, and is, for example, 3 V or more and 100 V or less. The connector terminal T1 is also an input terminal for a control signal. The connector terminal T1 is, for example, a plug-type terminal.

Each connector terminal T2 and T3 is a jack type terminal to which a coaxial cable can be connected, for example.

The connection terminal T4 is a terminal for connecting a laser module (laser diode LD).

As shown in FIG. 25, the power supply unit PS1 is connected between the connector terminal T1 and the plurality of capacitors C1. The power supply unit PS1 includes an electrolytic capacitor C2, a backflow prevention diode D3, a reactor L1, two charging resistors R3, and the like. The electrolytic capacitor C2 is a so-called bypass capacitor and stabilizes the input voltage (power supply voltage VLD). The backflow prevention diode D3 prevents current from flowing from each capacitor C1 side to the external power supply (connector terminal T1) side. The reactor L1 boosts the input voltage. Each charging resistor R3 adjusts the amount of current of the current from the external power supply (connector terminal T1) side toward each capacitor C1. These may be connected as needed.

The power supply unit PS2 generates an operating voltage V1. The operating voltage V1 is mainly used for driving each electronic component constituting the pulse generation circuit PG. The operating voltage V1 is, for example, 3.3 V, but is not limited thereto.

In addition, as shown in FIG. 25, the drive device A1 includes a plurality of test points TP1 to TP6 and a plurality of ground points GP1 to GP4 in its circuit configuration. Each test point TP1 to TP6 is a terminal for signal detection. Each ground point GP1 to GP4 is a terminal grounded to a reference potential.

The drive control (light emission operation) of the laser diode LD by the drive device A1 will be described with reference to FIGS. 26 and 27. 26 and 27 are diagrams in which main electronic components in the light emitting operation of the laser diode LD are extracted from the circuit configuration of the drive device A1 shown in FIG. 25. In FIGS. 26 and 27, a plurality of capacitors C1 and a plurality of shunt resistors R1 are shown one by one. The DC power supply shown in FIGS. 26 and 27 corresponds to the external power supply connected to the connector terminal T1 shown in FIG. 25 and the power supply unit PS1. FIG. 26 shows the case where the switching element Q1 is in the cutoff state, and FIG. 27 shows the case where the switching element Q1 is in the conductive state.

When the switching element Q1 is cut off, a current flows from the DC power supply to each capacitor C1 as shown in FIG. 26 (see the current path shown by the broken line). Due to this current, electric charge is accumulated in the second end C12 of each capacitor C1 and each capacitor C1 is charged. At this time, assuming that the power supply voltage of the DC power supply is VLD, the potential of the second end C12 of each capacitor C1 is the power supply voltage VLD. When each capacitor C1 is fully charged, this current stops flowing. When the switching element Q1 is in the cutoff state, no current flows through the laser diode LD and the laser diode LD does not emit light.

On the other hand, when the switching element Q1 is brought into a conductive state, as shown in FIG. 27, the second end C12 of each capacitor C1 conducts to the ground end GND via the switching element Q1. As a result, the electric charge accumulated in each capacitor C1 flows into the switching element Q1, and a current flows from each capacitor C1 to the ground terminal GND via the switching element Q1. Then, a forward current flows from the grounded end GND to the laser diode LD through each shunt resistor R1, and the laser diode LD emits light (see the current path LP shown by the broken line). When each capacitor C1 is completely discharged, this current stops flowing and the laser diode LD does not emit light.

The module configuration of the drive device A1 will be described with reference to FIGS. 28 to 35. For convenience of explanation, in FIGS. 28 to 35, three directions (x direction, y direction, and z direction) orthogonal to each other are appropriately referred to. The z direction is the thickness direction of the drive device A1.

The drive device A1 includes a circuit board 10, a plurality of electronic components, and a plurality of terminals. The plurality of electronic components and the plurality of terminals correspond to the plurality of electronic components and the plurality of terminals in the circuit configuration shown in FIG. 25, and are mounted on the circuit board 10.

FIG. 28 shows the component layout and land pattern on the circuit board 10. In FIG. 28, a plurality of electronic components and a plurality of terminals are shown by an imaginary line (dashed line). FIG. 29 is an enlarged view of a part of FIG. 28, and a main part is extracted. In the example shown in FIGS. 28 and 29, the drive device A1 is provided with two socket terminals T41 and T42 and a pad terminal T43 as the connection terminals T4 having the circuit configuration shown in FIG. 25. It is not necessary to provide all of the two socket terminals T41 and T42 and the pad terminal T43 as the connection terminal T4, and it is sufficient to provide any one of them.

As shown in FIG. 28, the circuit board 10 has a substantially rectangular shape in a plan view. The thickness direction of the circuit board 10 coincides with the z direction. The circuit board 10 has, for example, a dimension of 70.0 mm in the x direction and a dimension of 45.0 mm in the y direction. The plan view dimensions of the circuit board 10 are not limited to this, and can be changed as appropriate.

The circuit board 10 is, for example, a laminated board, and includes a plurality of wiring layers Ly1 to Ly4 that are laminated with each other via an insulating layer in the z direction. 30 to 33 are plan views showing the respective wiring layers Ly1 to Ly4, respectively. As shown in FIGS. 30 to 33, the wiring layer Ly1 is formed by the wiring pattern 21, the wiring layer Ly2 is formed by the wiring pattern 22, the wiring layer Ly3 is formed by the wiring pattern 23, and the wiring layer Ly4 is formed by the wiring pattern 24. Is formed of. In FIGS. 30 to 33, the wiring patterns 21 to 24 are painted in black.

The wiring layer Ly1 is the first layer and the uppermost layer in the circuit board 10. Each electronic component is mounted on the wiring layer Ly1. For example, a solder layer is formed on the upper surface of the wiring layer Ly1, and the solder layer is partially covered with a resist film (not shown). The solder layer exposed from the resist film forms the land pattern shown in FIG. 28. This land pattern includes five resistance lands 20 as shown in FIG. Each of the five resistor lands 20 may be joined with each shunt resistor R1. The wiring layer Ly4 is the fourth layer and the lowest layer in the circuit board 10. For example, a solder layer is formed on the lower surface of the wiring layer Ly4, and the solder layer is partially covered with a resist film (not shown). The wiring layers Ly2 and Ly3 are intermediate layers in the circuit board 10. The wiring layer Ly2 is the second layer on the circuit board 10, and the wiring layer Ly3 is the third layer on the circuit board 10. The wiring layer Ly2 is sandwiched between the wiring layer Ly1 and the wiring layer Ly3 in the z direction, and the wiring layer Ly3 is sandwiched between the wiring layer Ly2 and the wiring layer Ly4 in the z direction.

The wiring pattern 22 (wiring layer Ly2) is a GND (ground) pattern that is grounded to the reference potential. As shown in FIG. 31, the wiring pattern 22 is a solid pattern. The wiring pattern 23 (wiring layer Ly3) is a power supply pattern. As shown in FIG. 32, the wiring pattern 23 is divided into a plurality of regions, and the value of the voltage applied in each region is different. The wiring pattern 24 (wiring layer Ly4) is mainly a GND pattern grounded at a reference potential. However, a part of the wiring pattern 24 (pattern 241 in FIG. 33) is a power supply pattern.

In the circuit board 10, each thickness (dimension in the z direction) of the plurality of wiring layers Ly1 to Ly4 is, for example, about 115 μm. In a drive device different from the drive device A1, the thickness of the wiring layer is generally 350 μm or 700 μm, for example, so that the thickness of each wiring layer Ly1 to Ly4 in the drive device A1 is thin. Of the plurality of wiring layers Ly1 to Ly4, only the wiring layer Ly1 has a thickness of about 115 μm, and the other wiring layers Ly2 to Ly4 may have a general thickness of about 350 μm or 700 μm.

As shown in FIG. 28, a plurality of through electrodes 30 are formed on the circuit board 10. The plurality of through electrodes 30 penetrate the circuit board 10 in the z direction. The plurality of wiring layers Ly1 to Ly4 (plurality of wiring patterns 21 to 24) are electrically connected to each other by the plurality of through electrodes 30. In FIG. 28, only a part of the plurality of through electrodes 30 is designated.

As shown in FIG. 28, the circuit board 10 includes two aggregation regions AG1 and AG2 in which a plurality of through electrodes 30 are densely arranged in a plan view. Each through electrode 30 arranged in each of the gathering regions AG1 and AG2 conducts at least the wiring layer Ly1 and the wiring layer Ly2, and does not conduct to the wiring layer Ly3. The through silicon vias 30 arranged in the gathering regions AG1 and AG2 may or may not be electrically connected to the wiring layer Ly4. However, the wiring layer Ly4 has a GND pattern, and it is preferable that the wiring layer Ly4 is electrically connected to the wiring layer Ly4. The gathering region AG1 is located in the y2 direction with respect to the shunt resistance group R0 and is adjacent to the shunt resistance group R0. The collecting region AG2 is located in the y1 direction with respect to the switching element Q1 and is adjacent to the switching element Q1.

As shown in FIGS. 28 and 30 to 33, through holes HL are formed at each of the four corners in the plan view of the circuit board 10. Each through hole HL penetrates the circuit board 10 in the z direction. Each through hole HL is provided to fix the drive device A1 to the support member, and a fastener such as a bolt can be inserted therethrough. Each through hole HL is arranged so that the center in a plan view overlaps each of the four corners of the circuit board 10 at a position of, for example, 3.5 mm in the x direction and 3.5 mm in the y direction.

As shown in FIGS. 28 and 29, the circuit board 10 includes two mounting regions M1 and M2 in a plan view. A laser module (laser diode LD) can be mounted in each of the mounting regions M1 and M2. In the present embodiment, the socket terminals T41 and T42 are attached to the mounting areas M1 and M2, and the TO-Can package type laser module is mounted via the socket terminals T41 and T42.

As shown in FIG. 29, each mounting area M1 and M2 includes three terminal connection portions Ma, Mb, and Mc. Each lead terminal of the TO-Can package type laser module is connected to each terminal connection portion Ma, Mb, Mc. A lead terminal conducting to the anode of the laser diode LD is connected to the terminal connection portion Ma. A lead terminal conducting to the cathode of the photodiode is connected to the terminal connection portion Mb. Leads conducting to the cathode of the laser diode LD and the anode of the photodiode are connected to the terminal connection portion Mc. In the example shown in FIG. 29, the terminal connection portions Ma, Mb, Mc in the mounting area M1 and the terminal connection portions Ma, Mb, Mc in the mounting area M2 are different in plan view dimensions, but are the same. You may. In the TO-Can package type laser module, when the number of lead terminals is four, each mounting area M1 and M2 includes four terminal connection portions. When the number of lead terminals is two, each mounting area M1 and M2 may be configured to include two terminal connecting portions or may be configured to include three or more terminal connecting portions.

As shown in FIG. 29, in each mounting area M1 and M2, the terminal connection portion Ma and the terminal connection portion Mc are aligned in the y direction, and the terminal connection portion Ma is located in the y1 direction with respect to the terminal connection portion Mc. .. When the laser module is mounted in the mounting region M1 via the socket terminal T41, the lead terminal conducting to the anode of the laser diode LD and the lead terminal conducting to the cathode of the laser diode LD are aligned in the y direction, and the laser diode The lead terminal conducting to the anode of the LD is located in the y1 direction with respect to the lead terminal conducting to the cathode of the laser diode LD. This also applies when the laser module is mounted in the mounting area M2 via the socket terminal T42.

As shown in FIG. 29, in the mounting areas M1 and M2, the terminal connection portion Mb and the terminal connection portion Mc are aligned in the x direction, and the terminal connection portion Mc is located in the x1 direction with respect to the terminal connection portion Mb. To do. On the contrary, the terminal connection portion Mc may be located in the x2 direction with respect to the terminal connection portion Mb.

Next, a plurality of electronic components and a plurality of terminals in the module configuration of the drive device A1 will be described.

As shown in FIGS. 28 and 29, the plurality of capacitors C1 are arranged side by side in the x direction. In each capacitor C1, two terminals (first end C11 and second end C12) are arranged in the y direction. In the drive device A1, the second end C12 is located in the y2 direction with respect to the first end C11. The first ends C11 of the plurality of capacitors C1 are electrically connected to each other by the wiring pattern 21 of the wiring layer Ly1, and the second ends C12 of the plurality of capacitors C1 are electrically connected to each other by the wiring pattern 21 of the wiring layer Ly1. doing. Each capacitor C1 is, for example, a chip type, but may be a lead type. The capacitances of the plurality of capacitors C1 are substantially the same, and the plan-view dimensions are also substantially the same. In the module configuration of the drive device A1, the capacitor group C0 is formed by the plurality of capacitors C1.

As shown in FIGS. 28 and 29, the plurality of shunt resistors R1 are arranged side by side in the x direction. In each shunt resistor R1, two terminals (first end R11 and second end R12) are arranged in the y direction. In the drive device A1, the first end R11 is located in the y2 direction with respect to the second end R12. The first ends R11 of the plurality of shunt resistors R1 are electrically connected to each other by the wiring pattern 21 of the wiring layer Ly1, and the second ends R12 of the plurality of shunt resistors R1 are connected to each other by the wiring pattern 21 of the wiring layer Ly1. They are conducting with each other. Each shunt resistor R1 is, for example, a chip type, but may be a lead type. The plurality of shunt resistors R1 have substantially the same resistance value, and the plan view dimensions are also substantially the same. Each shunt resistor R1 has, for example, an x-direction dimension (dimension Dx in FIG. 29) of 3.2 mm and a y-direction dimension (dimension D in FIG. 29) of 6.4 mm. The plan view dimension of each shunt resistor R1 is not limited to this, and generally, the larger the resistance value, the larger the plan view area. In the module configuration of the drive device A1, the shunt resistor group R0 is formed by the plurality of shunt resistors R1.

As shown in FIG. 29, in the shunt resistance group R0, the separation distance SD1 between the two shunt resistors R1 adjacent to each other in the x direction is equal to or larger than a predetermined size. In the drive device A1, this predetermined size is the x-direction dimension Dx of one shunt resistor R1. That is, one shunt resistor having the same magnitude as each shunt resistor R1 can be arranged between two shunt resistors R1 adjacent to each other in the x direction. In the drive device A1, the separation distance SD1 is, for example, about 5.0 mm. In the example shown in FIG. 29, there is a region in which three shunt resistors R1 can be arranged between the two shunt resistors R1 arranged at both ends in the x direction in the shunt resistor group R0, and one in the center of this region in the x direction. A shunt resistor R1 is arranged.

As shown in FIG. 29, in the drive device A1, resistance lands 20 are formed under the three shunt resistors R1 and between the two shunt resistors R1 adjacent to each other in the x direction. Therefore, five resistance lands 20 arranged in the x direction are formed on the circuit board 10, and the shunt resistor R1 is mounted on the resistance lands 20 at both ends in the x direction and the resistance lands 20 in the center of the x direction. Has been done. In this way, the separation distance SD1 is set to be equal to or greater than the x-direction dimension Dx of one shunt resistor R1.

As shown in FIGS. 28 and 29, the capacitor group C0 and the shunt resistor group R0 are aligned in the y direction. In the y direction, mounting regions M1 and M2 (socket terminals T41 and T42) are arranged between the capacitor group C0 and the shunt resistor group R0. Further, as shown in FIG. 29, the edge of the capacitor group C0 on the x1 direction side overlaps with the shunt resistance R1 arranged in the x1 direction of the shunt resistance group R0 when viewed in the y direction, and the capacitor group C0 The edge on the x2 direction side overlaps with the shunt resistance R1 arranged in the x2 direction of the shunt resistance group R0 when viewed in the y direction.

As shown in FIG. 28, the switching element Q1 is aligned with the capacitor group C0 in the y direction. In the example shown in FIG. 28, the switching element Q1 is adjacent to the capacitor group C0 in the y direction. The switching element Q1 is located on the opposite side of the shunt resistance group R0 with respect to the capacitor group C0 in the y direction. That is, the switching element Q1 is located in the y2 direction with respect to the capacitor group C0. The switching element Q1 overlaps the center of the capacitor group C0 in the x direction when viewed in the y direction. As a result, the difference in the conduction path from the switching element Q1 to each capacitor C1 becomes small.

As shown in FIG. 34, the switching element Q1 has a plurality of electrodes Q11, Q12, and Q13 formed on the lower surface in the z direction in the module configuration of the drive device A1. The plurality of electrodes Q11 are gate electrodes in the switching element Q1. The plurality of electrodes Q12 are drain electrodes in the switching element Q1. The plurality of electrodes Q13 are source electrodes in the switching element Q1. In the state where the switching element Q1 is mounted on the circuit board 10, a plurality of electrodes Q11 (gate electrodes) are arranged along the edge on the x1 direction side in a plan view. This is because the drive IC 9 is located on the x1 direction side of the switching element Q1 and the distance between the drive IC 9 and the plurality of electrodes Q11 is shortened. The arrangement of the electrodes Q11, Q12, and Q13 is not limited to the example shown in FIG. 34.

Each resistor R2 is arranged between the drive IC 9 and the switching element Q1 in the x direction, and is adjacent to these. As a result, the transmission path of the drive signal output from the drive IC9 (drive circuit DR) and input to the gate of the switching element Q1 via the resistor R2 becomes linear. The drive IC9, the switching element Q1, and each resistor R2 overlap each other when viewed in the x direction.

The two socket terminals T41 and T42 are terminals for connecting a TO-Can package type (3 terminals) laser module, respectively. When the laser module to be connected is a TO-Can package type, the laser module is connected to either the socket terminal T41 or the socket terminal T42. Each of the socket terminals T41 and T42 can be inserted with each lead terminal of the TO-Can package type laser module. The two socket terminals T41 and T42 have different sizes, and one of them is selected according to the size of the laser module to be connected. The sizes of the two socket terminals T41 and T42 are not limited to different ones, and may be the same. A feedback diode D1 is arranged next to the socket terminal T41 in the y1 direction. As shown in FIGS. 28 and 29, the socket terminal T41 is attached to the mounting area M1, and the socket terminal T42 is attached to the mounting area M2.

The pad terminal T43 is a terminal for connecting a surface-mounted laser module. The pad terminal T43 includes two land patterns that are separated from each other, as shown in FIGS. 28 and 29. When the laser module to be connected is a surface mount type, the laser module is connected to each land pattern of the pad terminal T43. As shown in FIG. 28, the pad terminal T43 is arranged along the edge of the circuit board 10 in a plan view. In the pad terminal T43, the cathode of the laser diode is connected to the land pattern in the y2 direction, and the anode of the laser diode is connected to the land pattern in the y1 direction. It is also possible to connect a TO-Can package type laser module to the pad terminal T43. For example, in a TO-Can package type laser module, by joining the anode and cathode lead terminals of the laser diode LD directly to the pad terminal T43 with solder or the like, the pad terminal T43 can be connected to the TO-Can package type. A laser module can be connected.

As shown in FIG. 28, switching element Q1, drive circuit DR, capacitor group C0 (plurality of capacitors C1), shunt resistor group R0 (plurality of shunt resistors R1), feedback diode D1, socket terminals T41, T42, and pads. The terminal T43 is arranged on one side of the center of the circuit board 10 in the x direction.

By mounting the plurality of electronic components and the plurality of terminals on the circuit board 10, they are appropriately conductively connected by the wiring patterns 21 to 24, and the circuit configuration shown in FIG. 25 is obtained.

The actions and effects of the drive device A1 configured as described above are as follows.

The drive device A1 includes a plurality of shunt resistors R1. The plurality of shunt resistors R1 are connected in parallel with each other, and each is connected in series with the laser diode LD. According to this configuration, since the plurality of shunt resistors R1 are connected in parallel with each other, the drive current supplied to the laser diode LD is divided into the respective shunt resistors R1. In particular, when the resistance values of the shunt resistors R1 are the same, the drive current is evenly divided into the shunt resistors R1. As a result, the current flowing through one shunt resistor R1 is reduced, so that the current reduction due to the parasitic inductance component is suppressed in each shunt resistor R1. That is, the drive device A1 can efficiently make the laser diode LD emit light.

In the drive device A1, the plurality of shunt resistors R1 are arranged in the x direction, and the separation distance SD1 of the two shunt resistors R1 adjacent to each other in the x direction is equal to or larger than the x-direction dimension Dx of each shunt resistor R1. According to this configuration, mutual inductance in two shunt resistors R1 adjacent to each other in the x direction can be reduced. As a result, the inductance component in the drive device A1 can be reduced. Therefore, the drive device A1 can suppress a decrease in the drive current to the laser diode LD, and can make the laser diode LD emit light efficiently. The mutual inductance M generated in two adjacent shunt resistors R1 is calculated by M = 2L (ln (2L / d) -1) × 10 ^-7. In this equation, L is the length of each shunt resistor R1 (corresponding to the y-direction dimension Dy in FIG. 29), and d is the separation distance between two adjacent shunt resistors R1 (corresponding to the separation distance SD1 in FIG. 29). is there. Further, in this equation, the parasitic inductance of each shunt resistor R1 is set to 1 nH. From this equation, it can be seen that the larger the separation distance d (separation distance SD1), the smaller the mutual inductance M. Further, in order to suppress the mutual inductance M to 0, it is preferable to set the separation distance d such that ln (2L / d) -1 ≦ 0 based on the above equation. That is, the separation distance d is preferably set to d ≧ (2L / e) ≈0.74 × L. e is the number of Napiers, and e = 2.718 ....

FIG. 35 shows the result of simulating the time change of the voltage (shunt resistance voltage) applied to each shunt resistor R1. The solid line in FIG. 35 is the result when the drive device A1, that is, between two shunt resistors R1 adjacent to each other in the x direction is equal to or larger than the x-direction dimension Dx of each shunt resistor R1. The broken line in FIG. 35 is a drive device different from the drive device A1 (hereinafter referred to as “comparative drive device”), and a shunt similar to that of each shunt resistor R1 is also between two shunt resistors R1 adjacent to each other in the x direction. This is the result when a resistor is mounted. The simulation results shown in FIG. 35 are shown in a simplified manner.

In the comparison drive device, the shunt resistance voltage vibrates several times as shown in the waveform of the period Ta'in the broken line in FIG. 35. On the other hand, in the drive device A1, in the solid line of FIG. 35, the vibration of the shunt resistance voltage is suppressed as shown in the waveform of the period Ta. These vibrations are generated by each inductance in the drive device A1 and the comparison drive device, and the higher the inductance value, the higher the number of vibrations. Therefore, in the drive device A1, the vibration of the shunt resistance voltage is suppressed as compared with the comparison drive device, so that the inductance component is reduced. Further, since this vibration is a cause of flicker at the time of light emission of the laser diode LD, for example, the drive device A1 can suppress this flicker. Further, the period Tb from the rise to the fall of the first wave in the drive device A1 (see the waveform of the solid line in FIG. 35) is the period from the rise to the fall of the first wave in the comparative drive device. Shorter than Tb'(see the dashed waveform in FIG. 35). That is, the fluctuation cycle of the shunt voltage in the drive device A1 is smaller than the fluctuation cycle of the shunt voltage in the comparative drive device (the resonance frequency is larger). This is because the inductance component of the drive device A1 is smaller than the inductance component of the comparative drive device. Therefore, by reducing the inductance component, the drive current of the laser diode LD can be shortened and increased in current.

In the circuit configuration of the drive device A1 (see FIGS. 25 to 27), each capacitor C1 is connected between the DC power supply and the laser diode LD. According to this configuration, the power supply voltage from the DC power supply is not directly applied to the laser diode LD. Therefore, the load applied to the laser diode LD is reduced, and the failure of the laser diode LD is suppressed.

In the drive device A1, a plurality of capacitors C1, a socket terminal T41 (or a socket terminal T42), and a plurality of shunt resistors R1 are arranged in this order in the y direction. According to this configuration, the conduction path of the drive current flowing from each shunt resistor R1 through the laser diode LD to each capacitor C1 can be made linear. As a result, the parasitic inductance of the wiring in the current path LP (see FIG. 27) when the switching element Q1 is in the conductive state can be reduced. That is, since the inductance component in the drive device A1 can be reduced, the drive device A1 can suppress a decrease in the drive current to the laser diode LD, and the laser diode LD can efficiently emit light.

In the drive device A1, the circuit board 10 has a mounting region M1 for mounting a laser module (laser diode LD). The mounting region M1 includes a terminal connection portion Ma connected to the anode of the laser diode LD and a terminal connection portion Mc connected to the cathode of the laser diode LD. The terminal connection portion Ma and the terminal connection portion Mc are arranged in the y direction, and the terminal connection portion Mc is arranged on the capacitor group C0 side and the terminal connection portion Ma is arranged on the shunt resistance group R0 side in the y direction. According to this configuration, the conduction path of the drive current flowing from each shunt resistor R1 to each capacitor C1 via the laser diode LD can be further made linear. As a result, the parasitic inductance of the wiring in the current path LP (see FIG. 27) when the switching element Q1 is in the conductive state can be reduced. Therefore, since the inductance component in the drive device A1 can be reduced, the drive device A1 can improve the luminous efficiency of the laser diode LD. The same applies to the mounting area M2.

In the drive device A1, the switching element Q1 and the drive IC9 are arranged in the x direction, and only the resistor R2 is arranged between the switching element Q1 and the drive IC9. According to this configuration, the distance between the drive IC 9 and the switching element Q1 can be shortened, so that the transmission time of the drive signal output from the drive IC 9 and input to the switching element Q1 can be shortened. This shortening of drive signal transmission improves the responsiveness of the switching operation. That is, the drive device A1 can improve the responsiveness of the switching operation of the switching element Q1. When the switching characteristic (switching speed) of the switching element Q1 is required to be improved, the drive IC9 and the switching element Q1 are placed adjacent to each other without providing each resistor R2. The distance of may be further shortened.

In the drive device A1, the circuit board 10 includes the gathering regions AG1 and AG2 in which a plurality of through electrodes 30 are densely arranged. The plurality of through electrodes 30 arranged in the collecting regions AG1 and AG2 are electrically connected to the wiring pattern 21 of the wiring layer Ly1 and the wiring pattern 22 of the wiring layer Ly2. According to this configuration, the conductivity between the wiring layer Ly1 and the wiring layer Ly2 becomes good. In particular, the plurality of through electrodes 30 in the gathering region AG1 conduct the one end (second end R12) of each shunt resistor R1 and the GND pattern (wiring pattern 22), and the plurality of through electrodes 30 in the gathering region AG2 are The source of the switching element Q1 and the GND pattern (wiring pattern 22) are made conductive. Therefore, the grounding of one end of each shunt resistor R1 and the source of the switching element Q1 to the reference potential (GND) is strengthened, the quality of each signal in the drive device A1 is improved (for example, noise reduction), and the shunt resistance voltage is described. Vibration (fluctuation of reference potential) can be reduced.

In the drive device A1, the circuit board 10 includes a plurality of wiring layers Ly1 to Ly4. The z-direction dimensions (thickness) of the plurality of wiring layers Ly1 to Ly4 are thinner than the general thickness (about 700 μm). According to this configuration, the z-direction dimensions of the plurality of through electrodes 30 are reduced. Therefore, the parasitic inductance of each through electrode 30 can be reduced. For example, the wiring layer Ly1 passes through the wiring layer Ly2 via the plurality of through electrodes 30 arranged in the gathering region AG1, and returns to the wiring layer Ly1 by the plurality of penetrating electrodes 30 arranged in the gathering region AG2. Since the incoming current path (corresponding to the current path LP in FIG. 27) can be shortened, the parasitic inductance of the wiring in this current path can be reduced.

In the present embodiment, the case where the socket terminals T41 and T42 are attached to the mounting areas M1 and M2 is shown, but the present invention is not limited to this, and the socket terminals T41 and T42 may not be attached. In this case, the TO-Can package type laser module is directly mounted in each mounting area M1 and M2 by, for example, soldering.

In the present embodiment, the case where three shunt resistors R1 are arranged is shown, but the number of shunt resistors R1 is not limited to this. For example, as shown in FIG. 36, two shunt resistors R1 may be arranged. In the example shown in FIG. 36, one shunt resistor R1 is joined to each of the five resistor lands 20 located at both ends in the x direction. The circuit configuration of the drive device shown in FIG. 36 is shown in FIG. 37. In FIG. 37, a part of the circuit configuration shown in FIG. 25 is excerpted. Further, as shown in FIG. 38, the configuration may be such that two shunt resistors R1 are arranged. In the example shown in FIG. 38, one shunt resistor R1 is joined to each of the five resistor lands 20 on both sides of the resistor lands 20 located at the center in the x direction. The circuit configuration of the drive device shown in FIG. 38 is shown in FIG. 39. In FIG. 39, a part of the circuit configuration shown in FIG. 25 is excerpted. Each layout diagram of FIGS. 36 and 38 corresponds to FIG. 29. However, when there are two shunt resistors R1, the effect of suppressing the current decrease due to the parasitic inductance of each shunt resistor R1 is smaller than when the shunt resistors R1 are three, but the mounting area on the circuit board 10 is reduced. It becomes possible. The number of shunt resistors R1 is appropriately determined according to the specifications required for the drive device A1.

In the present embodiment, a case where the resistance land 20 is arranged between two shunt resistors R1 adjacent to each other in the x direction in a plan view is shown, but the present invention is not limited to this. For example, as shown in FIG. 40, the resistor land 20 may not be arranged between two shunt resistors R1 adjacent to each other in the x direction. The circuit configuration of the drive device shown in FIG. 40 is shown in FIG. In FIG. 41, a part of the circuit configuration shown in FIG. 25 is excerpted. Further, as shown in FIG. 42, a solid pattern 29 may be arranged instead of the resistance land 20 between two adjacent shunt resistors R1 in the x direction. In this case, the solid pattern 29 may be designed as a microstrip line or a coplanar line. The circuit configuration of the drive device shown in FIG. 42 is shown in FIG. 43. In FIG. 43, a part of the circuit configuration shown in FIG. 25 is excerpted. Each layout diagram of FIGS. 40 and 42 corresponds to FIG. 29.

The drive device according to the present disclosure is not limited to the above-described embodiment. The specific configuration of each part of the drive device of the present disclosure can be freely redesigned.

The configuration provided by the third aspect includes the embodiments described in Appendix 1C-17C below.
Appendix 1 C.I. With multiple electronic components that supply the drive current to the laser diode,
A circuit board on which the plurality of electronic components are mounted and
Is equipped with
The plurality of electronic components include a switching element that switches between a conduction state and a cutoff state, a plurality of resistors connected in parallel with each other and each connected in series with the anode of the laser diode, and a cathode of the laser diode. It includes a capacitor connected to the switching element and
The plurality of resistors are arranged in a first direction orthogonal to the thickness direction of the circuit board.
The plurality of resistors include two resistors adjacent to each other in the first direction, and the distance between the two resistors in the first direction is such that the distance between the two resistors in the first direction is one of the plurality of resistors in the first direction. A drive that is greater than or equal to the dimensions.
Appendix 2 C.I. The switching element is a transistor having a first terminal, a second terminal, and a third terminal, and the conduction state and the cutoff state are switched according to a control signal input to the third terminal. The drive device described.
Appendix 3C. The first end of any one of the plurality of resistors is connected to the anode of the laser diode.
The second end of any one of the plurality of resistors is grounded to a reference potential.
The first end of the capacitor is connected to the cathode of the laser diode and
The second end of the capacitor is connected to the first terminal of the switching element.
The driving device according to Appendix 2C, wherein the second terminal of the switching element is grounded to the reference potential.
Appendix 4 C. The plurality of electronic components further include a drive circuit that generates the control signal.
The drive device according to Appendix 3C, wherein the drive circuit and the switching element are arranged in the first direction.
Appendix 5C. The plurality of electronic components further include a current value setting element connected between the drive circuit and the third terminal.
The drive device according to Appendix 4C, wherein the current value setting element is arranged between the drive circuit and the switching element on the circuit board.
Appendix 6 C.I. It also has an input terminal to which the power supply voltage is supplied.
The drive device according to any one of Supplementary note 3C to Supplementary note 5C, wherein the capacitor is connected to the input terminal, and the power supply voltage is applied to the capacitor when the switching element is in the cutoff state.
Appendix 7 C.I. The driving device according to any one of Supplementary note 1C to Supplementary note 6C, wherein a land pattern is formed between the two resistors when viewed in the thickness direction of the circuit board.
Appendix 8C. The plurality of resistors form a group of resistors, and the plurality of resistors form a group of resistors.
The driving device according to any one of Supplementary note 1C to Supplementary note 7C, wherein the capacitor and the resistor group are arranged in the thickness direction and the second direction orthogonal to the first direction.
Appendix 9C. The circuit board includes a mounting area for mounting the laser diode.
The drive according to Appendix 8C, wherein the mounting region is located between the capacitor and the resistor group when viewed in the first direction, and is adjacent to the capacitor and the resistor group, respectively. apparatus.
Appendix 10 C.I. The mounting region includes an anode connection for connecting the anode of the laser diode and a cathode connection for connecting the cathode of the laser diode.
The driving device according to Appendix 9C, wherein the anode connecting portion and the cathode connecting portion are arranged in the second direction when viewed in the thickness direction.
Appendix 11 C.I. It is connected in parallel with the capacitor and further includes an additional capacitor aligned with the resistor group in the second direction.
The drive device according to any one of Supplementary note 8C to Supplementary note 10C, wherein a capacitor group is formed by the capacitor and the additional capacitor.
Appendix 12 C.I. The driving device according to Appendix 11C, wherein the switching element is arranged on the side opposite to the side where the resistor group is located with respect to the capacitor group in the second direction, and is adjacent to the capacitor group.
Appendix 13 C.I. The plurality of resistors include a first resistor and a second resistor.
The first resistor is arranged on the most one side of the plurality of resistors in the first direction.
The second resistor is arranged on the farthest side of the plurality of resistors in the first direction.
The one-sided edge of the capacitor group in the first direction overlaps the first resistor when viewed in the second direction, and the other-side edge of the first direction of the capacitor group is the first. The drive device according to Appendix 11C or Appendix 12C, which overlaps the second resistor when viewed in two directions.
Appendix 14C. The plurality of electronic components further include the first resistor and a third resistor connected in parallel with the second resistor.
The driving device according to Appendix 13C, wherein the third resistor is arranged between the first resistor and the second resistor in the first direction.
Appendix 15 C.I. The circuit board includes an insulating layer and a first wiring layer and a second wiring layer laminated in the thickness direction and insulated from each other via the insulating layer.
The drive device according to any one of Supplementary note 8C to Supplementary note 14C, wherein the second wiring layer is grounded to a reference potential.
Appendix 16 C.I. The circuit board includes an assembly region in which a plurality of through electrodes are arranged when viewed in the thickness direction.
The plurality of through electrodes penetrate the insulating layer and conduct the first wiring layer and the second wiring layer.
The driving device according to Appendix 15C, wherein the gathering region is arranged on the side opposite to the side where the capacitor is located with respect to the resistor group in the second direction.
Appendix 17 C.I. The circuit board is arranged on the side opposite to the first wiring layer in the thickness direction and includes a third wiring layer on which a power supply pattern is formed. The drive device according to Appendix 16C.

<Code in FIGS. 25 to 43>
A1: Drive device LD: Laser diode R0: Shunt resistance group R1: Shunt resistance R11: First end R12: Second end C0: Capacitor group C1: Capacitor C11: First end C12: Second end D1: Feedback diode Q1: Switching elements Q11, Q12, Q13: Electrode DR: Drive circuit 9: Drive IC
R2: Resistor GND: Ground terminal PG: Pulse generation circuit PS1: Power supply unit C2: Electrolytic capacitor L1: Reactor D3: Backflow prevention diode R3: Charging resistance PS2: Power supply unit T1 to T3: Connector terminal T4: Connection terminals T41, T42 : Socket terminal T43: Pad terminal LP: Current path 10: Circuit board Ly1 to Ly4: Wiring layer 20: Resistor land 21 to 24: Wiring pattern 29: Solid pattern 30: Through electrode 241: Pattern HL: Through hole AG1, AG2 : Assembly area M1, M2: Mounting area Ma, Mb, Mc: Terminal connection

As described above, the basic configuration based on the first aspect of the present disclosure can be applied to both the second aspect and the third aspect (see paragraphs 0068, 0140). Hereinafter, such embodiments will be described as appendices 1D to 16D (first side surface + second side surface) and appendices 1E to 17E (first side surface + third side surface).

Appendix 1D. A drive device that controls the drive of a laser diode.
A switching element that switches between a conductive state and a cutoff state,
With a capacitor
With the first diode
The input terminal to which the power supply voltage is supplied and
A control unit that controls the switching element on / off,
Is equipped with
The capacitor has a first end connected to the cathode of the laser diode and a second end connected to the switching element.
In the first diode, the anode is connected to the connection point between the first end of the capacitor and the cathode of the laser diode.
The input terminal is connected to a connection point between the second end of the capacitor and the switching element.
When the switching element is in the ON state, the switching element, the laser diode, the first diode, and the capacitor form a closed circuit.
The control unit is a drive device that shortens the on-time of the switching element to less than half of the resonance period of the closed circuit.
Appendix 2D. The control unit makes the on-time of the switching element shorter than the period from the timing when the switching element is switched from the off state to the on state to the second timing when the resonance current of the closed circuit becomes half of the maximum value. The drive device according to Appendix 1D.
Appendix 3D. The driving device according to Appendix 1D, wherein the control unit sets the on-time of the switching element to one-fourth or more of the resonance period of the closed circuit.
Appendix 4D. The control unit
A delay unit that delays a signal based on the first pulse signal to generate a delay signal,
A waveform shaping unit that shapes the waveform of the delay signal and generates a second pulse signal,
A calculation unit that generates a third pulse signal having a pulse width shorter than that of the first pulse signal by a calculation using the first pulse signal and the second pulse signal.
With
The drive device according to any one of Supplementary note 1D to 3D, wherein on / off control of the switching element is performed based on the third pulse signal.
Appendix 5D. The driving device according to Appendix 4D, wherein the pulse width of the first pulse signal is at least half of the resonance period of the closed circuit.
Appendix 6D. The drive device according to any one of Supplementary note 1D to 5D, further comprising a shunt resistor for detecting a current flowing through the laser diode, wherein the closed circuit includes the shunt resistor.
Appendix 7D. The driving device according to Appendix 6D, wherein the shunt resistor includes a plurality of resistance elements connected in parallel to each other.
Appendix 8D. The plurality of resistance elements include a first resistance element and a second resistance element having the same length and adjacent to each other, and the distance between the first resistance element and the second resistance element is 2 having the same length. The drive device according to Appendix 7D, which is greater than or equal to the value obtained by dividing the multiple by the number of napiers.
Appendix 9D. The drive device according to any one of Appendix 1D to 8D, and
With the laser diode
A laser device.
Appendix 10D. With more boards
The laser device according to Appendix 9D, wherein the switching element, the parallel circuit including the first diode and the laser diode, and the capacitor are arranged side by side in the first direction orthogonal to the thickness direction of the substrate. ..
Appendix 11D. The laser apparatus according to Appendix 10D, wherein the direction from the anode of the laser diode to the cathode of the laser diode is substantially parallel to the first direction.
Appendix 12D. The drive device is the drive device described in Appendix 4D.
The laser device according to Appendix 10D or 11D, wherein the delay unit, the waveform shaping unit, and the calculation unit are arranged in a second direction orthogonal to the thickness direction and the first direction.
Appendix 13D. The substrate is a laminated substrate including a first wiring layer and a second wiring layer, the second wiring layer functions as a ground layer, and the distance between the first wiring layer and the second wiring layer is 200 μm or less. The laser device according to any one of the appendices 10D to 12D.
Appendix 14D. The laser apparatus according to Appendix 13D, wherein the ground of the signal system and the ground of the power supply system are shared in the second wiring layer.
Appendix 15D.
A laser radar device including the laser device according to any one of Appendix 9D to 14D.
Appendix 16D. A vehicle comprising the laser radar device according to Appendix 15D.

Appendix 1 E. A drive device that controls the drive of a laser diode.
A switching element that switches between a conductive state and a cutoff state,
With a capacitor
With the first diode
The input terminal to which the power supply voltage is supplied and
A plurality of resistors connected in parallel with each other and each connected in series with the anode of the laser diode.
A circuit board on which the switching element, the capacitor, the first diode, and the plurality of resistors are mounted,
Is equipped with
The capacitor has a first end connected to the cathode of the laser diode and a second end connected to the switching element.
In the first diode, the anode is connected to the connection point between the first end of the capacitor and the cathode of the laser diode.
The input terminal is connected to a connection point between the second end of the capacitor and the switching element.
The plurality of resistors are arranged in a first direction orthogonal to the thickness direction of the circuit board.
The plurality of resistors include two resistors adjacent to each other in the first direction, and the distance between the two resistors in the first direction is the distance between the two resistors in the first direction of any one of the plurality of resistors. Drive device that is greater than or equal to the dimensions in.
Appendix 2 E. The switching element is a transistor having a first terminal, a second terminal, and a third terminal, and the conduction state and the cutoff state are switched according to a control signal input to the third terminal. The drive device described.
Appendix 3E.
The first end of any one of the plurality of resistors is connected to the anode of the laser diode, and the second end of any one of the plurality of resistors is grounded to a reference potential.
The driving device according to Appendix 2E, wherein the second terminal of the switching element is grounded to the reference potential.
Appendix 4 E.
It further includes a drive circuit that generates the control signal.
The drive device according to Appendix 2E, wherein the drive circuit and the switching element are arranged in the first direction.
Appendix 5E.
Further, a current value setting element connected between the drive circuit and the third terminal is provided.
The drive device according to Appendix 4E, wherein the current value setting element is arranged between the drive circuit and the switching element on the circuit board.
Appendix 6 E.
The drive device according to any one of Appendix 1E to 5E, wherein the capacitor is connected to the input terminal, and the power supply voltage is applied to the capacitor when the switching element is in the cutoff state.
Appendix 7E.
The drive device according to any one of Appendix 1E to 6E, wherein a land pattern is formed between the two resistors when viewed in the thickness direction of the circuit board.
Appendix 8 E.
The plurality of resistors form a group of resistors, and the plurality of resistors form a group of resistors.
The driving device according to any one of Supplementary note 1E to 7E, wherein the capacitor and the resistor group are arranged in the thickness direction and the second direction orthogonal to the first direction.
Appendix 9E.
The circuit board includes a mounting area for mounting the laser diode.
The drive according to Appendix 8E, wherein the mounting region is located between the capacitor and the resistor group when viewed in the first direction, and is adjacent to the capacitor and the resistor group, respectively. apparatus.
Appendix 10 E.
The mounting region includes an anode connection for connecting the anode of the laser diode and a cathode connection for connecting the cathode of the laser diode.
The driving device according to Appendix 9E, wherein the anode connecting portion and the cathode connecting portion are arranged in the second direction when viewed in the thickness direction.
Appendix 11 E.
It is connected in parallel with the capacitor and further includes an additional capacitor aligned with the resistor group in the second direction.
The drive device according to any one of Appendix 8E to 10E, wherein a capacitor group is formed by the capacitor and the additional capacitor.
Appendix 12 E.
The driving device according to Appendix 11E, wherein the switching element is arranged on the side opposite to the side where the resistor group is located with respect to the capacitor group in the second direction, and is adjacent to the capacitor group.
Appendix 13 E.
The plurality of resistors include a first resistor and a second resistor.
The first resistor is arranged on the most one side of the plurality of resistors in the first direction.
The second resistor is arranged on the farthest side of the plurality of resistors in the first direction.
The one-sided edge of the capacitor group in the first direction overlaps the first resistor when viewed in the second direction, and the other-side edge of the first direction of the capacitor group is the first. The drive device according to Appendix 11E or 12E, which overlaps the second resistor when viewed in two directions.
Appendix 14E.
The plurality of electronic components further include the first resistor and a third resistor connected in parallel with the second resistor.
The driving device according to Appendix 13E, wherein the third resistor is arranged between the first resistor and the second resistor in the first direction.
Appendix 15 E.
The circuit board includes an insulating layer and a first wiring layer and a second wiring layer laminated in the thickness direction and insulated from each other via the insulating layer.
The drive device according to any one of Appendix 8E to 14E, wherein the second wiring layer is grounded to a reference potential.
Appendix 16 E.
The circuit board includes an assembly region in which a plurality of through electrodes are arranged when viewed in the thickness direction.
The plurality of through electrodes penetrate the insulating layer and conduct the first wiring layer and the second wiring layer.
The driving device according to Appendix 15E, wherein the gathering region is arranged on the side opposite to the side where the capacitor is located with respect to the resistor group in the second direction.
Appendix 17 E.
The circuit board is arranged on the side opposite to the first wiring layer with respect to the second wiring layer in the thickness direction, and includes a third wiring layer in which a power supply pattern is formed. The drive device according to 16E.

Claims (20)

1. A drive device that controls the drive of a laser diode.
   A switching element that switches between a conductive state and a cutoff state,
   With a capacitor
   With the first diode
   The input terminal to which the power supply voltage is supplied and
   Is equipped with
   The capacitor has a first end connected to the cathode of the laser diode and a second end connected to the switching element.
   In the first diode, the anode is connected to the connection point between the first end of the capacitor and the cathode of the laser diode.
   The input terminal is a drive device connected to a connection point between the second end of the capacitor and the switching element.
2. The drive device according to claim 1, further comprising a resistor whose first end is connected to the anode of the laser diode.
3. The drive device according to claim 2, wherein the resistor has a second end grounded at a reference potential.
4. The drive device according to claim 2 or 3, further comprising a second diode whose anode is connected to the first end of the capacitor.
5. The driving device according to claim 4, wherein the second diode has a cathode grounded to a reference potential.
6. The drive device according to any one of claims 2 to 5, wherein the switching element is a field effect transistor.
7. The drain of the switching element is connected to the second end of the capacitor.
   The source of the switching element is grounded to the reference potential.
   The drive device according to claim 6, wherein a drive signal for switching between the conduction state and the cutoff state is input to the gate of the switching element.
8. The drive device according to claim 7, further comprising a drive circuit for generating the drive signal.
9. The drive device according to any one of claims 6 to 8, wherein the switching element is made of a semiconductor material.
10. The drive device according to any one of claims 2 to 9, further comprising a circuit board on which the capacitor, the first diode, the input terminal, and the resistor are mounted.
11. It also has an additional capacitor connected in parallel with the capacitor.
    The driving device according to claim 10, wherein the capacitor and the additional capacitor are arranged side by side in a first direction orthogonal to the thickness direction of the circuit board to form a capacitor group.
12. It also has an additional resistor connected in parallel with the resistor.
    The driving device according to claim 11, wherein the resistor and the additional resistor are arranged side by side in the first direction to form a group of resistors.
13. The drive device according to claim 12, wherein the capacitor group and the resistor group are arranged in the thickness direction and the second direction orthogonal to the first direction.
14. The drive device according to claim 13, wherein the first diode is sandwiched between the capacitor group and the resistor group in the second direction.
15. The drive device according to claim 13 or 14, wherein the switching element is located on the opposite side of the resistor group with respect to the capacitor group in the second direction.
16. The driving device according to claim 15, wherein the switching element is adjacent to the capacitor group in the second direction.
17. It also has a first terminal to which a TO-Can package type laser diode can be connected.
    The drive device according to any one of claims 13 to 16, wherein the first terminal is mounted on the circuit board.
18. The drive device according to claim 17, wherein the first terminal is arranged between the capacitor group and the resistor group in the second direction.
19. It also has a second terminal to which a surface-mounted laser diode can be connected.
    The drive device according to any one of claims 10 to 18, wherein the second terminal is mounted on the circuit board.
20. The drive device according to claim 19, wherein the second terminal is arranged along an edge of the circuit board when viewed in the thickness direction of the circuit board.

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