WO2021039542A1 - Drive device - Google Patents

Drive device Download PDF

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Publication number
WO2021039542A1
WO2021039542A1 PCT/JP2020/031298 JP2020031298W WO2021039542A1 WO 2021039542 A1 WO2021039542 A1 WO 2021039542A1 JP 2020031298 W JP2020031298 W JP 2020031298W WO 2021039542 A1 WO2021039542 A1 WO 2021039542A1
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WO
WIPO (PCT)
Prior art keywords
capacitor
drive device
switching element
laser diode
resistor
Prior art date
Application number
PCT/JP2020/031298
Other languages
French (fr)
Japanese (ja)
Inventor
大志 木村
賢司 酒井
ニャット タン ホアン
佑輔 中小原
Original Assignee
ローム株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2019152844A external-priority patent/JP2022177325A/en
Priority claimed from JP2019172267A external-priority patent/JP2022177329A/en
Priority claimed from JP2019173043A external-priority patent/JP2022177330A/en
Application filed by ローム株式会社 filed Critical ローム株式会社
Publication of WO2021039542A1 publication Critical patent/WO2021039542A1/en

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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01SRADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/48Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
    • G01S7/483Details of pulse systems
    • G01S7/484Transmitters
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/04Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
    • H01S5/042Electrical excitation ; Circuits therefor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details

Definitions

  • the present disclosure relates to a drive device, and more particularly to a laser diode drive device that controls the drive of a laser diode.
  • the present disclosure also relates to a laser device, a laser radar device, and a vehicle provided with a laser diode driving device.
  • Patent Document 1 discloses a drive device for a laser diode.
  • This drive device includes a switching element and a pulse generation circuit.
  • the switching element switches between a conductive state and a cutoff state by a drive pulse from a pulse generation circuit.
  • the switching element is connected to the laser diode, and when the switching element becomes conductive, a forward current flows through the laser diode and the laser diode emits light.
  • Patent Document 2 discloses a laser diode driving device that enables short pulse laser light output.
  • the switching element is turned off to charge the capacitor, and then the switching element is turned on to discharge the capacitor.
  • the discharge current at this time causes the laser diode to emit light.
  • the switching element is turned off and the capacitor is charged again.
  • the pulse width of the laser beam (the time from when the switching element is turned on until the discharge current of the capacitor becomes 0) is determined by the circuit constant of the LCR resonance circuit.
  • the LCR resonant circuit includes a capacitor, a laser diode, a switching element (in the on state), a diode connected in parallel with the laser diode, and a parasitic inductance.
  • Patent Document 3 also discloses an example of a laser diode driving device (driving circuit).
  • the drive device described in the document includes a resistor connected in series with a laser diode.
  • the discharge current becomes 0 when the electric charge accumulated in the capacitor disappears, and the light emission of the laser diode stops.
  • the shortening of the output period of the laser beam is limited by the parasitic inductance, and the output period of the laser beam may not be sufficiently shortened.
  • the on-time of the switching element is set to 1000 times or more the output period of the laser beam. Therefore, unnecessary laser light is intermittently output until the resonance of the LCR resonance circuit is sufficiently attenuated.
  • Patent Document 3 when a drive current flows through a laser diode, a drive current also flows through a resistor connected in series with the laser diode. At this time, the driving current of the laser diode decreases due to the parasitic inductance of the resistor. In particular, the more the laser diode is driven with a large current and a short pulse, the more remarkable the decrease in the drive current due to the parasitic inductance becomes.
  • one object of the present disclosure is to provide a laser diode driving device capable of efficiently emitting a laser diode.
  • Another object of the present disclosure is to provide a laser diode driving device capable of shortening the output period of the laser beam and suppressing unnecessary laser beam output.
  • Another object of the present disclosure is to provide various products (for example, a laser device, a laser radar device, a vehicle, etc.) including the laser diode driving device as described above.
  • a drive device for driving and controlling a laser diode.
  • the drive device includes a switching element that switches between a conduction state and a cutoff state, a capacitor, a first diode, and an input terminal to which a power supply voltage is supplied.
  • the first end of the capacitor is connected to the cathode of the laser diode, and the second end is connected to the switching element.
  • the anode is connected to the connection point between the first end of the capacitor and the cathode of the laser diode.
  • the input terminal is connected to a connection point between the second end of the capacitor and the switching element.
  • a drive device that controls the drive of the laser diode.
  • the drive device has a switching element, a control unit that controls on / off of the switching element, a rectifying element in which an anode and a cathode are connected in parallel to the laser diode in opposite directions, and the switching element is off.
  • a capacitor that is sometimes charged and that forms a closed circuit with the switching element, the laser diode, and the rectifying element when the switching element is on.
  • the control unit is configured to make the on-time of the switching element shorter than half of the resonance period of the closed circuit.
  • a drive device including a plurality of electronic components for supplying a drive current to the laser diode and a circuit board on which the plurality of electronic components are mounted.
  • the plurality of electronic components include a switching element that switches between a conduction state and a cutoff state, a plurality of resistors connected in parallel with each other and each connected in series with the anode of the laser diode, and a cathode of the laser diode. It includes a capacitor connected to the switching element.
  • the plurality of resistors are arranged in a first direction orthogonal to the thickness direction of the circuit board. Of the plurality of resistors, two resistors adjacent to each other in the first direction have a separation distance in the first direction equal to or larger than the dimension of any one of the plurality of resistors in the first direction.
  • FIG. 19A It is a figure which shows the path through which a negative resonance current flows. It is a figure which shows one configuration example of a control part. It is a figure which shows the specific example of the control part of the configuration example shown in FIG. It is a figure which shows the time chart of each signal of the control part shown in FIG. 19A. It is a figure which shows the other specific example of the control part of the configuration example shown in FIG. It is a figure which shows still more specific example of the control part of the configuration example shown in FIG. It is a figure which shows the modification of the control part shown in FIG. 19A. It is a figure which shows the time chart of each signal of the control part shown in FIG. 19E. It is a figure which shows the modification of the control part shown in FIG. 19E.
  • FIG. 28 It is a figure which shows the structural example of a shunt resistor. It is a top view of the substrate. It is a schematic diagram which shows the cross section of a substrate. It is a figure which shows the schematic structure of the laser radar apparatus. It is an external view of a vehicle. It is a figure which shows the circuit structure of the drive device based on the embodiment of the 3rd aspect. It is a figure which shows the operation example of a drive device. It is a figure which shows the operation example of a drive device. It is a top view which shows the module structure of a drive device, and shows a component layout and a land pattern. It is a partially enlarged view which is a part of FIG. 28 enlarged.
  • FIGS. 1 to 13 An embodiment based on the first aspect of the present disclosure will be described below with reference to FIGS. 1 to 13.
  • the same or similar components are designated by the same reference numerals and the description thereof will be omitted.
  • the drive device A1 controls the drive of the laser diode LD (for example, irradiation of laser light).
  • the drive device A1 supplies a drive current to the laser diode LD, and causes the laser diode LD to emit light with a brightness corresponding to the drive current.
  • the laser diode LD connected to the drive device A1 may be a TO-Can package type or a surface mount type.
  • the drive device A1 includes a switching element Q1, a plurality of capacitors C1, a plurality of shunt resistors R1, a feedback diode (rectifier element) D1, a discharge diode D2, a drive circuit DR, a pulse generation circuit PG, and a plurality of shunt resistors R1. It includes connector terminals T1 to T3, socket terminals T4, connection terminals T5, and two power supply units PS1 and PS2.
  • the connection of the laser diode LD is shown by an imaginary line (dashed line).
  • the switching element Q1 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
  • the switching element Q1 is not limited to the MOSFET, and may be another transistor.
  • the switching element Q1 is made of a semiconductor material.
  • the semiconductor material is, for example, GaN (gallium nitride).
  • the semiconductor material is not limited to GaN, and may be Si (silicon), SiC (silicon carbide), GaAs (gallium arsenide), Ga 2 O 3 (gallium oxide), or the like.
  • the drain is connected to each capacitor C1
  • the source is connected to the ground end GND
  • the gate is connected to the drive circuit DR.
  • the ground terminal GND gives a reference potential.
  • a drive signal is input to the gate of the switching element Q1 from the drive circuit DR, and the conduction state and the cutoff state are switched according to the drive signal.
  • an operation of switching between a conduction state (on state) and a cutoff state (off state) may be referred to as a “switching operation”.
  • the conductive state is a state in which a current flows between the drain and the source
  • the cutoff state is a state in which no current flows between the drain and the source.
  • the drive signal is, for example, a pulse wave in which an on signal and an off signal are alternately switched.
  • the switching element Q1 is in a conductive state when the drive signal is an on signal, and is in a cutoff state when the drive signal is an off signal, for example.
  • each capacitor C1 is connected in parallel with each other.
  • the first end C11 is connected to the cathode of the laser diode LD, and the second end C12 is connected to the drain of the switching element Q1. Further, the first end C11 of each capacitor C1 is also connected to the anode of the feedback diode D1 and the anode of the discharge diode D2, respectively.
  • Each capacitor C1 is connected to the power supply unit PS1, and the power supply voltage VLD is applied from the power supply unit PS1.
  • a plurality of shunt resistors R1 are connected in parallel with each other.
  • the first end R11 is connected to the cathode of the feedback diode D1 and the anode of the laser diode LD, and the second end R12 is connected to the ground end GND.
  • the feedback diode D1 has an anode connected to the cathode of the laser diode LD and a cathode connected to the anode of the laser diode LD. Further, in the feedback diode D1, the anode is connected to the second end C12 of each capacitor C1, and the cathode is connected to the first end R11 of each shunt resistor R1. As shown in FIG. 1, the feedback diode D1 has an anode connected to a connection point between the second end C12 of each capacitor C1 and the cathode of the laser diode LD. In the example shown in FIG. 1, the feedback diode D1 is a Schottky barrier diode.
  • the discharge diode D2 has an anode connected to the second end C12 of the capacitor C1 and a cathode connected to the ground end GND via a resistor.
  • the discharge diode D2 is a Schottky barrier diode.
  • the pulse generation circuit PG generates a pulse signal for controlling the switching operation of the switching element Q1.
  • the pulse generation circuit PG receives a control signal from the connector terminal T1 and generates a pulse signal based on the control signal.
  • the pulse generation circuit PG outputs the generated pulse signal to the drive circuit DR.
  • the pulse signal in the present embodiment is, for example, a square wave having a frequency of 20 kHz (period of 50,000 nsec) and an on-time of 50 nsec.
  • the duty ratio of this pulse signal is 0.1%.
  • the drive circuit DR generates a drive signal for driving (switching operation) the switching element Q1.
  • a pulse signal is input from the pulse generation circuit PG, and a drive signal is generated based on the pulse signal.
  • the drive signal is, for example, a signal obtained by boosting the pulse signal to a voltage required for driving the switching element Q1.
  • the drive circuit DR includes a drive IC 9, and a drive signal is generated by the drive IC 9.
  • the drive circuit DR outputs the generated drive signal to the gate of the switching element Q1 via the gate resistor R2.
  • the gate resistor R2 may not be provided in some cases.
  • the connector terminal T1 is an input terminal for the power supply voltage VLD.
  • a DC power supply (external power supply) provided outside the drive device A1 is connected to the connector terminal T1, and a power supply voltage VLD is supplied from this external power supply.
  • the power supply voltage VLD is used for driving the laser diode LD, and is, for example, 3 V or more and 100 V or less.
  • the connector terminal T1 is also an input terminal for a control signal.
  • the connector terminal T1 is, for example, a plug-type terminal.
  • Each connector terminal T2 and T3 is a jack type terminal to which a coaxial cable can be connected, for example.
  • the socket terminal T4 is a terminal for connecting a TO-Can package type laser diode.
  • the laser diode LD is a TO-Can package type
  • the laser diode LD is connected to the socket terminal T4.
  • connection terminal T5 is a terminal for connecting a surface-mounted laser diode.
  • the laser diode LD is a surface mount type, the laser diode LD is connected to the connection terminal T5.
  • the power supply unit PS1 is connected between the connector terminal T1 and the plurality of capacitors C1.
  • the power supply unit PS1 includes an electrolytic capacitor C2, a backflow prevention diode D3, a reactor L1, a charging resistor R3, and the like.
  • the electrolytic capacitor C2 is a bypass capacitor and stabilizes the input voltage (power supply voltage VLD).
  • the backflow prevention diode D3 prevents current from flowing from each capacitor C1 side to the external power supply (connector terminal T1) side.
  • the reactor L1 boosts the input voltage.
  • the charging resistor R3 adjusts the amount of current of the current from the external power supply (connector terminal T1) side toward each capacitor C1.
  • the power supply unit PS2 generates an operating voltage V1.
  • the operating voltage V1 is mainly used for driving each electronic component constituting the pulse generation circuit PG.
  • the operating voltage V1 is, for example, 3.3 V, but is not limited thereto.
  • the drive device A1 includes two test points TP1 and TP2. Each test point TP1 and TP2 is a terminal for signal detection.
  • FIGS. 2 and 3 are diagrams in which the main electronic components in the light emitting operation of the laser diode LD are extracted from the circuit configuration of the drive device A1 shown in FIG.
  • a plurality of capacitors C1 and a plurality of shunt resistors R1 are shown one by one.
  • the DC power supply shown in FIGS. 2 and 3 corresponds to the external power supply connected to the connector terminal T1 shown in FIG. 1 and the power supply unit PS1.
  • FIG. 2 shows the case where the switching element Q1 is in the cutoff state
  • FIG. 3 shows the case where the switching element Q1 is in the conductive state.
  • the potential of the first end C11 of the capacitor C1 becomes the reference potential (GND), and the potential of the second end C12 becomes the difference (GND-VLD) between the reference potential and the power supply voltage VLD.
  • the anode side of the laser diode LD has a higher potential than the cathode side, a forward current flows through the laser diode LD, and the laser diode LD emits light.
  • a current path passing through the laser diode LD and the discharge diode D2 and a current path passing through the laser diode LD and the feedback diode D1 are generated from the shunt resistor R1 (each shown by a broken line). See current path).
  • the module configuration of the drive device A1 will be described with reference to FIGS. 4 to 11.
  • the three directions orthogonal to each other (x direction, y direction and z direction) are appropriately referred to.
  • the z direction corresponds to the thickness direction of the drive device A1 (or the circuit board 10).
  • the drive device A1 includes a circuit board 10 and a plurality of electronic components.
  • the plurality of electronic components correspond to the plurality of electronic components in the circuit configuration shown in FIG. 1, and are mounted on the circuit board 10.
  • FIG. 4 shows the component layout and land pattern on the circuit board 10.
  • a plurality of electronic components are shown by imaginary lines (dashed-dotted lines).
  • the circuit board 10 has a substantially rectangular shape in a plan view.
  • the circuit board 10 has, for example, a dimension of 70.0 mm in the x direction and a dimension of 45.0 mm in the y direction.
  • the plan view dimensions of the circuit board 10 are not limited to this, and can be changed as appropriate.
  • the circuit board 10 is, for example, a laminated board, and includes a plurality of wiring layers Ly1 to Ly4 that are laminated to each other.
  • the wiring layers Ly1 to Ly4 are separated from each other via an insulating layer.
  • 5 to 8 are plan views showing each wiring layer Ly1 to Ly4, respectively. As shown in FIGS. 5 to 8, wiring patterns 20 (parts painted in black) are arranged in the wiring layers Ly1 to Ly4.
  • the wiring layer Ly1 is the first layer (top layer) of the circuit board 10. Each electronic component is mounted on the wiring layer Ly1.
  • the solder layer 21 shown in FIG. 9 is formed on the upper surface of the wiring layer Ly1. In FIG. 9, the region where the solder 210 is formed is painted in black. The solder layer 21 is partially covered with a resist film (not shown). The solder 210 exposed from the resist film corresponds to the land pattern shown in FIG.
  • the wiring layer Ly4 is a fourth layer (bottom layer) in the circuit board 10.
  • the solder layer 22 shown in FIG. 10 is formed on the lower surface of the wiring layer Ly4. In FIG. 10, the region where the solder 220 is formed is painted in black. The solder layer 22 is partially covered with a resist film (not shown).
  • the wiring layers Ly2 and Ly3 are intermediate layers in the circuit board 10.
  • the wiring layer Ly2 is a second layer in the circuit board 10, and is sandwiched between the wiring layer Ly1 and the wiring layer Ly3 in the z direction.
  • the wiring layer Ly3 is a third layer in the circuit board 10, and is sandwiched between the wiring layer Ly2 and the wiring layer Ly4 in the z direction.
  • each wiring layer Ly2 and Ly3 has a wiring pattern 20 grounded at a reference potential formed along the outer peripheral edge in a plan view.
  • the plurality of wiring layers Ly1 to Ly4 are electrically connected to each other by the penetrating vias penetrating the insulating layer.
  • the circuit board 10 is formed with through holes HL at its four corners, respectively.
  • Each through hole HL penetrates the circuit board 10 in the z direction.
  • Each through hole HL is provided to fix the drive device A1 to the support member, and a fastener such as a bolt can be inserted therethrough.
  • wiring patterns 20 grounded at a reference potential are arranged in each of the wiring layers Ly1 to Ly4 around each through hole HL, and are used as a grounding end GND.
  • Each through hole HL is arranged so that the center in a plan view overlaps with each of the four corners of the circuit board 10 at positions of, for example, 3.5 mm in the x direction and 3.5 mm in the y direction.
  • a plurality of capacitors C1 are arranged side by side in the x direction (adjacent to each other in the x direction at predetermined intervals in the illustrated example) to form the capacitor group C0. ing. That is, the plurality of capacitors C1 are adjacent to each other with a sufficiently short separation distance, and other elements (for example, functional elements) are configured not to be arranged between the plurality of capacitors C1. As shown in the figure, the two terminals (C11 and C12) of each capacitor C1 are arranged so as to be arranged in the y direction.
  • Each capacitor C1 is, for example, a chip type, but may be a lead type.
  • a plurality of shunt resistors R1 are arranged side by side in the x direction to form a shunt resistor group R0.
  • a shunt resistor group R0 In each shunt resistor R1, two terminals (first end R11 and second end R12) are arranged in the y direction.
  • Each shunt resistor R1 is, for example, a chip type, but may be a lead type.
  • the capacitor group C0 and the shunt resistor group R0 are aligned in the y direction as shown in FIG.
  • a socket terminal T4 and a feedback diode D1 are arranged between the capacitor group C0 and the shunt resistor group R0.
  • the socket terminal T4 and the feedback diode D1 are adjacent to each other in the y direction.
  • the switching element Q1 is aligned with the capacitor group C0 in the y direction.
  • the switching element Q1 is adjacent to the capacitor group C0 in the y direction.
  • the switching element Q1 is located on the side opposite to the shunt resistance group R0 with respect to the capacitor group C0 in the y direction.
  • the drive IC 9 and the switching element Q1 are adjacent to each other in the y direction.
  • the switching element Q1 has a plurality of electrodes Q11, Q12, and Q13 formed on the lower surface in the z direction.
  • the plurality of electrodes Q11 are gate terminals in the switching element Q1.
  • the plurality of electrodes Q12 are drain terminals in the switching element Q1.
  • the plurality of electrodes Q13 are source terminals in the switching element Q1.
  • the switching element Q1 is mounted on the circuit board 10 so that a plurality of electrodes Q11 (gate terminals) are arranged near the drive IC 9 in the y direction.
  • the arrangement of the electrodes Q11, Q12, and Q13 is not limited to the example shown in FIG.
  • each electronic component (see FIG. 1) constituting the drive circuit DR is arranged in the capacitor group C0 in the y direction, and is on the opposite side of the shunt resistor group R0 with reference to the capacitor group C0.
  • Each electronic component constituting the drive circuit DR and the switching element Q1 are covered with an electromagnetic shield 28.
  • the land pattern shown in FIG. 4 shows a pattern 29 to which the electromagnetic shield 28 is joined.
  • the electromagnetic shield 28 suppresses noise from being superimposed on each electronic component or switching element Q1 constituting the drive circuit DR. As a result, it is possible to prevent each electronic component (for example, drive IC9) and the switching element Q1 constituting the drive circuit DR from malfunctioning due to noise.
  • connection terminal T5 is arranged on one side of the center of the circuit board 10 in the x direction.
  • connection terminal T5 is arranged along the edge of the circuit board 10 in a plan view. As shown in FIG. 4, the connection terminal T5 has a solid pattern. In FIG. 4, the connection terminal T5 has the cathode of the laser diode connected to the upper side in the y direction and the anode of the laser diode connected to the lower side in the y direction. It is also possible to connect a TO-Can package type laser diode LD to the connection terminal T5. For example, in a TO-Can package type laser diode, the TO-Can package type laser diode is connected to the connection terminal T5 by joining the anode and cathode pin terminals to the direct connection terminal T5 with solder or the like. it can.
  • the discharge diode D2 is arranged next to the drive circuit DR and the switching element Q1 in the x direction, and is arranged along the edge of the circuit board 10 in a plan view.
  • the discharge diode D2 and the connection terminal T5 are aligned in the y direction.
  • the discharge diode D2 is arranged between the capacitor group C0 and the grounding end GND (through hole HL on the upper right) in the y direction.
  • the drive device A1 includes a switching element Q1 and a capacitor C1.
  • the first end C11 is connected to the cathode of the laser diode LD, and the second end C12 is connected to the switching element Q1.
  • the connector terminal T1 to which the power supply voltage VLD is input is connected to the connection point between the second end C12 of the capacitor C1 and the switching element Q1, whereby the power supply voltage VLD is connected to the second end C12 of the capacitor C1. It is applied to the connection point with the switching element Q1.
  • the charge of the capacitor C1 is fluctuated by the switching operation of the switching element Q1, and the forward current flows through the laser diode LD (the laser diode LD emits light) due to this charge fluctuation.
  • the drive device A1 can suppress a decrease in the amount of current flowing through the laser diode LD due to the parasitic inductance component and the parasitic resistance component of the switching element Q1. That is, the drive device A1 can efficiently make the laser diode LD emit light.
  • each capacitor C1 is connected between the DC power supply and the laser diode LD (see FIGS. 1 to 3). According to this configuration, the power supply voltage VLD from the DC power supply is not directly applied to the laser diode LD. Therefore, the load applied to the laser diode LD is reduced, and the failure of the laser diode LD is suppressed.
  • the capacitor group C0 and the shunt resistor group R0 are aligned in the y direction, and include a socket terminal T4 and a connection terminal T5 to which the laser diode LD is connected between them (see FIG. 4).
  • the discharge diode D2 is arranged between the grounding end GND (through hole HL in the upper right of FIG. 4) and the socket terminal T4 or the connection terminal T5. According to this configuration, in the drive device A1, the current path (see FIG. 3) flowing from the shunt resistor R1 to the grounding end GND via the laser diode LD and the discharge diode D2 can be shortened. As a result, the parasitic inductance component and the parasitic resistance component inside the drive device A1 are reduced.
  • the feedback diode D1 is arranged in the immediate vicinity of the socket terminal T4 (see FIG. 4). According to this configuration, the resonance phenomenon due to the capacitance component of each capacitor C1 and the parasitic inductance component such as the feedback diode D1 and the wiring can be suppressed. Further, since the loop path (see FIG. 3) circulating between the laser diode LD and the feedback diode D1 can be shortened, the parasitic inductance component and the parasitic resistance component in this loop path are suppressed.
  • the feedback diode D1 may be arranged between the socket terminal T4 and the connection terminal T5. In this case, the resonance phenomenon can be suppressed regardless of whether the laser diode LD is connected to the socket terminal T4 or the connection terminal T5.
  • the drive device A1 includes a plurality of capacitors C1 connected in parallel to each other. According to this configuration, the parasitic inductance component inside the drive device A1 can be reduced. As a result, it is possible to suppress a decrease in the amount of current due to the parasitic inductance component inside the drive device A1 and an increase in the pulse width input to the laser diode LD. Further, the drive device A1 includes a plurality of shunt resistors R1 connected in parallel with each other. According to this configuration, the parasitic inductance component inside the drive device A1 can be reduced as in the case of the plurality of capacitors C1.
  • the drive device A1 is provided with both the socket terminal T4 and the connection terminal T5, but may be configured to include only one of them.
  • the socket terminal T4 when the socket terminal T4 is provided and the connection terminal T5 is not provided, it can be configured as shown in FIG.
  • the socket terminal T4 when the socket terminal T4 is not provided and the connection terminal T5 is provided, it can be configured as shown in FIG.
  • the capacitor group C0 and the shunt resistor group R0 are adjacent to each other in the y direction
  • the feedback diode D1 and the connection terminal T5 are adjacent to each other in the x direction.
  • the drive device A1 is provided with the discharge diode D2 (and the resistor between the discharge diode D2 and the grounding end GND), but it may not be provided.
  • the discharge diode D2 when the discharge diode D2 is provided, the forward current of the laser diode LD can be improved and the measurement stabilization of the current-voltage characteristic of the laser diode LD can be improved as compared with the case where the discharge diode D2 is provided.
  • the drive device based on the first aspect is not limited to the above-described embodiment.
  • the specific configuration of each part of the drive device can be freely redesigned.
  • Appendix 1 A A drive device that controls the drive of a laser diode.
  • a switching element that switches between a conductive state and a cutoff state, With a capacitor
  • the input terminal to which the power supply voltage is supplied and Is equipped with The capacitor has a first end connected to the cathode of the laser diode and a second end connected to the switching element.
  • the anode is connected to the connection point between the first end of the capacitor and the cathode of the laser diode.
  • the input terminal is a drive device connected to a connection point between the second end of the capacitor and the switching element.
  • Appendix 2 A A drive device that controls the drive of a laser diode.
  • the drive device according to Appendix 1A, further comprising a resistor whose first end is connected to the anode of the laser diode.
  • Appendix 3A The driving device according to Appendix 2A, wherein the resistor has a second end grounded to a reference potential.
  • Appendix 4 A The drive according to Appendix 2A or Appendix 3A, further comprising a second diode whose anode is connected to the first end of the capacitor.
  • Appendix 5A The driving device according to Appendix 4A, wherein the second diode has a cathode grounded to a reference potential.
  • Appendix 6 A The driving device according to any one of Supplementary A2 to Appendix 5A, wherein the switching element is a field effect transistor.
  • Appendix 7A The drain of the switching element is connected to the second end of the capacitor. The source of the switching element is grounded to the reference potential.
  • the drive device according to Appendix 6A wherein a drive signal for switching between the conduction state and the cutoff state is input to the gate of the switching element.
  • Appendix 8A The drive device according to Appendix 7A, further comprising a drive circuit for generating the drive signal.
  • Appendix 9A The drive device according to any one of Supplementary note 6A to Supplementary note 8A, wherein the switching element is made of a semiconductor material.
  • Appendix 10 A The drive device according to any one of Supplementary note 6A to Supplementary note 8A, wherein the switching element is made of a semiconductor material.
  • the drive device according to any one of Appendix 2A to Appendix 9A, further comprising a circuit board on which the capacitor, the first diode, the input terminal, and the resistor are mounted.
  • Appendix 11A It also has an additional capacitor connected in parallel with the capacitor.
  • the driving device according to Appendix 10A, wherein the capacitor and the additional capacitor are arranged side by side in a first direction orthogonal to the thickness direction of the circuit board to form a capacitor group.
  • Appendix 12 A It also has an additional resistor connected in parallel with the resistor.
  • the driving device according to Appendix 11A, wherein the resistor and the additional resistor are arranged side by side in the first direction to form a group of resistors.
  • Appendix 13 A Appendix 13 A.
  • the driving device according to Appendix 12A wherein the capacitor group and the resistor group are arranged in the thickness direction and the second direction orthogonal to the first direction.
  • Appendix 14 A The driving device according to Appendix 13A, wherein the first diode is sandwiched between the capacitor group and the resistor group in the second direction.
  • Appendix 15 A The driving device according to Appendix 13A or Appendix 14A, wherein the switching element is located on the opposite side of the resistor group with respect to the capacitor group in the second direction.
  • Appendix 16 A The driving device according to Appendix 15A, wherein the switching element is adjacent to the capacitor group in the second direction.
  • Appendix 17 A The driving device according to Appendix 12A, wherein the capacitor group and the resistor group are arranged in the thickness direction and the second direction orthogonal to the first direction.
  • Appendix 14 A The driving device according to Appendix 13A, wherein the first diode is sandwiched between the capacitor group and the resistor group in the
  • the drive device according to any one of Supplementary note 13A to Supplementary note 16A, wherein the first terminal is mounted on the circuit board.
  • Appendix 18 A The drive device according to Appendix 17A, wherein the first terminal is arranged between the capacitor group and the resistor group in the second direction.
  • Appendix 19 A It also has a second terminal to which a surface-mounted laser diode can be connected.
  • the drive device according to any one of Supplementary note 10A to Supplementary note 18A, wherein the second terminal is mounted on the circuit board.
  • Appendix 20 A The driving device according to Appendix 19A, wherein the second terminal is arranged along an edge of the circuit board when viewed in the thickness direction of the circuit board.
  • FIGS. 14 to 24 are attached independently of the reference numerals in FIGS. 1 to 13 (first side surface). Therefore, in FIGS. 14 to 24 and FIGS. 1 to 13, the same reference numerals may refer to different elements, or the same (or similar) elements may be referred to.
  • FIG. 14 is a diagram showing a schematic configuration of a laser device based on the embodiment of the second aspect.
  • the illustrated laser device 1 includes a laser diode LD1 and a laser diode driving device 2.
  • the laser diode drive device 2 includes an NMOS (N-channel Metal Oxide Semiconductor) transistor Q1, a control unit CNT1, a capacitor C1, a diode D1, and a shunt resistor R1.
  • the NMOS transistor Q1 is used as the switching element, but a switching element other than the NMOS transistor Q1 may be used instead of the NMOS transistor Q1.
  • the diode D1 is used as the rectifying element, but a rectifying element other than the diode D1 may be used instead of the diode D1.
  • the configuration shown in FIG. 14 also has the same characteristics as the configuration according to the first aspect described above. That is, the laser diode driving device 2 shown in FIG.
  • the 14 has a switching element (Q1) that switches between a conduction state and a cutoff state, a capacitor (C1), a first diode (D1), and an input terminal to which a power supply voltage is supplied. (Upper end of PS1) and.
  • the first end (lower end) of the capacitor (C1) is connected to the cathode of the laser diode (LD1), and the second end (upper end) is connected to the switching element (Q1).
  • the anode of the first diode (D1) is connected to a connection point between the first end (lower end) of the capacitor (C1) and the cathode of the laser diode (LD1).
  • the input terminal (upper end of PS1) is connected to a connection point between the second end (upper end) of the capacitor (C1) and the switching element (Q1). Therefore, the above-mentioned technical effect regarding the first aspect is also exhibited in the configuration (second aspect) shown in FIG.
  • the configuration according to the second aspect described below it is also possible to apply the configuration according to the second aspect described below to the drive device according to the first aspect.
  • the configuration of the control unit CNT1 according to the second aspect and the control mode thereof can be applied to the drive device according to the first aspect.
  • the gate signal G1 output from the control unit CNT1 is supplied to the gate of the NMOS transistor Q1.
  • One end of the capacitor C1 and the drain of the NMOS transistor Q1 are connected to the positive electrode of the DC power supply PS1.
  • the other end of the capacitor C1 is connected to the anode of the diode D1 and the cathode of the laser diode LD1.
  • the cathode of the diode D1 and the anode of the laser diode LD1 are connected to one end of the shunt resistor R1.
  • the other end of the shunt resistor R1, the source of the NMOS transistor Q1, and the negative electrode of the DC power supply PS1 are connected to the ground potential.
  • the control unit CNT1 controls the NMOS transistor Q1 on / off by the gate signal G1.
  • the NMOS transistor Q1 When the NMOS transistor Q1 is on, a closed circuit is formed by the NMOS transistor Q1, the capacitor C1, the diode D1, the laser diode LD1, and the shunt resistor R1.
  • the closed circuit contains parasitic inductance. Therefore, the closed circuit becomes an LCR resonant circuit.
  • the NMOS transistor Q1 When the NMOS transistor Q1 is switched from off to on while the electric charge is stored in the capacitor C1, the LCR resonance circuit starts resonance.
  • the resonance current Ires of the LCR resonance circuit is attenuated with the passage of time as shown by the thick dotted line shown in FIG.
  • the path through which the resonant current Ires flows when the resonant current Ires is positive includes the laser diode LD1 as shown in FIG. Therefore, when the positive resonance current Ires flows, the laser diode LD1 emits light.
  • the path through which the resonance current Ires flows when the resonance current Ires is negative does not include the laser diode LD1 as shown in FIG. Therefore, the laser diode LD1 does not emit light even when a negative resonance current Ires flows.
  • the direction from the drain to the source of the NMOS transistor Q1 is defined as the positive direction of the resonance current Ires, and the direction from the source to the drain of the NMOS transistor Q1 is defined as the negative direction of the resonance current Ires.
  • the high level period of the gate signal G1 that is, the on-time of the NMOS transistor Q1 is shorter than half of the resonance period T of the LCR resonance circuit.
  • the on-time of the NMOS transistor Q1 means the time during which the NMOS transistor Q1 is continuously on. Specifically, the period from the time t1 to the time t2 shown in FIG. 15 is the on-time of the NMOS transistor Q1 in the present embodiment.
  • the output period of the laser beam does not completely match the on-time of the NMOS transistor Q1, and is a little longer than the on-time of the NMOS transistor Q1.
  • the period from time t1 to time t3 is the output period of the laser beam in the present embodiment.
  • the laser device 1 Since the resonance current Ires becomes substantially zero after the time t3, the laser device 1 does not output the laser light until the next high level period of the gate signal G1 arrives after the time t3.
  • the high level period of the gate signal G1 is maintained even after the resonance attenuation of the LCR resonance circuit is completed.
  • the high level period of the gate signal G1 that is, the on-time of the NMOS transistor Q1 is longer than half of the resonance period T of the LCR resonance circuit.
  • the period in which the resonance current Ires is positive (the period from time t1 to time t4, the period from time t5 to time t6)
  • the laser beam is output in the period from time t7 to time t8). That is, the period from time t1 to time t4 is the output period of the laser beam in the reference example. Further, in the reference example, unnecessary laser light output is generated in the period from the time t5 to the time t6 and the period from the time t7 to the time t8. Unwanted light output during these periods can lead to malfunction of the laser radar device, for example in a vehicle.
  • the laser diode driving device 2 and the laser device 1 can shorten the output period of the laser beam and suppress unnecessary laser beam output.
  • the higher the power of the laser light it is required that the higher the power of the laser light, the shorter the output period of the laser light.
  • the laser diode driving device 2 and the laser device 1 are very useful.
  • an unnecessary laser light output can cause erroneous detection, so that the laser diode driving device 2 and the laser device 1 capable of suppressing the unnecessary laser light output are very useful. ..
  • the on-time of the NMOS transistor Q1 is preferably shorter than the period from the time t1 to the second timing TM2 in which the resonance current Ires becomes half of the maximum value MAX.
  • the first timing TM1 in which the resonance current Ires becomes half of the maximum value MAX is also shown.
  • the pulse width of the laser beam emitted from the laser diode LD1 is usually defined by the full width at half maximum of the current flowing through the laser diode LD1. Therefore, by making the on-time of the NMOS transistor Q1 shorter than the period from the time t1 to the second timing TM2 in which the resonance current Ires becomes half of the maximum value MAX, the pulse width of the laser beam is made larger than that of the above-mentioned reference example. It can be shortened.
  • the on-time of the NMOS transistor Q1 is preferably one-fourth or more of the resonance period T of the LCR resonance circuit. Since it is possible to prevent the NMOS transistor Q1 from turning off before the resonance current Ires reaches the maximum value MAX, it is possible to suppress a decrease in the power of the laser beam.
  • FIG. 18 is a diagram showing a configuration example of the control unit CNT1.
  • the control unit CNT1 of the configuration example shown in FIG. 18 includes an input terminal 11, a delay unit 12, a waveform shaping unit 13, a calculation unit 14, and a driver unit 15.
  • the arithmetic unit 14 and the driver unit 15 may be configured by a single IC (Integrated Circuit), or may be separate components.
  • the input terminal 11 inputs the first pulse signal P1.
  • the delay unit 12 delays the signal based on the first pulse signal P1 to generate the delay signal DL1.
  • the signal based on the first pulse signal P1 may be the first pulse signal P1 itself.
  • the waveform shaping unit 13 shapes the waveform of the delay signal DL1 to generate the second pulse signal P2.
  • the waveform shaping unit 13 may perform processing other than waveform shaping on the delay signal DL1.
  • the calculation unit 14 generates a third pulse signal P3 having a shorter pulse width than the first pulse signal P1 by calculation using the first pulse signal P1 and the second pulse signal P2.
  • the driver unit 15 amplifies the third pulse signal P3 to generate the gate signal G1.
  • the driver unit 15 provides a current output (for example, 5 A or more) that has a small signal delay, can handle an input signal of a high frequency, ultrashort pulse (for example, a pulse width of 5 nex or less), and can further drive a high output laser. It is preferable that the driver portion has. Further, the smaller the self-inductance of the driver unit 15, the better so that high-speed switching operation is possible. When using an LSI-IC, it is preferable to select a CSP package or a bare chip product.
  • the NMOS transistor Q1 that receives the gate signal G1 from the driver unit 15 is preferably a transistor having a small input capacitance (for example, 500 pF or less) and a small input impedance (for example, 0.5 ⁇ or less) so that high-speed switching operation is possible. .. Since a large current flows through the NMOS transistor Q1, it is preferable to use a transistor having a small on-resistance (for example, 20 m ⁇ or less). Further, it is preferable to select a CSP package or a bare chip product having a small self-inductance of the NMOS transistor Q1.
  • the pulse width W3 of the third pulse signal P3 and thus the pulse width of the gate signal G1 can be made shorter than the pulse width W1 of the first pulse signal P1 (for example, FIG. 19B described later). reference).
  • the pulse width of the gate signal G1 that is, the high level period of the gate signal G1 can be set. It can be shorter than half of the resonance period T of the LCR resonance circuit.
  • the pulse width of the first pulse signal P1 is set to half or more of the resonance period T of the LCR resonance circuit. As a result, the cost of the pulse signal generator that generates the first pulse signal P1 can be reduced.
  • the pulse widths of the first pulse signal P1, the third pulse signal P3, and the gate signal G1 are each high level period of the first pulse signal P1, the third pulse signal P3, and the gate signal G1.
  • the low level period may be the pulse width depending on the characteristics of the switching element, the use of the inverter, and the like.
  • FIG. 19A is a diagram showing a specific example of the control unit CNT1 of the configuration example shown in FIG.
  • FIG. 19B is a time chart of each signal of the control unit CNT1 shown in FIG. 19A.
  • the control unit CNT1 shown in FIG. 19A includes a hysteresis inverter INV1 in addition to the input terminal 11, the delay unit 12, the waveform shaping unit 13, the calculation unit 14, and the driver unit 15.
  • the hysteresis inverter INV1 inverts the first pulse signal P1 and supplies the inverted signal of the first pulse signal P1 to the delay unit 12.
  • the delay unit 12 of the control unit CNT1 shown in FIG. 19A is configured by the resistor 12A and the capacitor 12B, and the waveform shaping unit 13 of the control unit CNT1 shown in FIG. 19A is composed of the hysteresis inverter INV2.
  • the hysteresis inverter INV2 shapes the waveform of the delay signal DL1 while inverting the delay signal DL1. Specifically, as shown in FIG. 19B, the hysteresis inverter INV2 shapes the waveform of the delay signal DL1 so that the switching between the high level and the low level becomes steep while inverting the delay signal DL1.
  • the waveform shaping unit 14 of the control unit CNT1 shown in FIG. 19A performs arithmetic processing for subtracting the second pulse signal G2 from the first pulse signal G1 to generate the third pulse signal P3.
  • FIG. 19C is a diagram showing another specific example of the control unit CNT1 of the configuration example shown in FIG.
  • the control unit CNT1 shown in FIG. 19C is different from the control unit CNT1 shown in FIG. 19A in that the hysteresis inverter INV1 is provided between the delay unit 12 and the hysteresis inverter INV2.
  • the waveform shaping unit 13 of the control unit CNT1 shown in FIG. 19C is composed of the hysteresis inverters INV1 and INV2.
  • the waveform shaping unit 13 of the control unit CNT1 shown in FIG. 19C shapes the waveform of the delay signal DL1 while inverting the delay signal DL1 twice.
  • only one hysteresis inverter may be provided in the path from the input terminal 11 to the calculation unit 14 via the delay unit 12.
  • the third pulse signal P3 may be generated by performing arithmetic processing for subtracting the second pulse signal G2 from the first pulse signal G1.
  • the calculation unit 14 of the control unit CNT1 of the configuration example shown in FIG. 19D The second pulse signal G2 may be inverted inside the arithmetic unit 14, and then the arithmetic processing of subtracting the inverted signal of the second pulse signal G2 from the first pulse signal G1 may be performed to generate the third pulse signal P3. ..
  • the arrangement of the hysteresis inverter INV1 of the control unit CNT1 shown in FIG. 19A is changed to FIG. 19E so that the first pulse signal P1 having a large slew rate of the rising edge and the falling edge can be appropriately handled.
  • the configuration shown may be used.
  • the hysteresis inverter INV1 is used as the waveform shaping unit 13'that generates the waveform of the first pulse signal P1 and supplies the pulse signal P1'after the waveform shaping to the calculation unit 14.
  • the time chart of each signal of the control unit CNT1 shown in FIG. 19E is as shown in FIG. 19F.
  • H1 in FIG. 19F shows the hysteresis amount of the hysteresis inverter INV1
  • H2 in FIG. 19F shows the hysteresis amount of the hysteresis inverter INV2.
  • the control unit CNT1 shown in FIG. 19A, the control unit CNT1 shown in FIG. 19C, the control unit CNT1 shown in FIG. 19D, and the control unit CNT1 shown in FIG. 19E are configured to include a hysteresis inverter, but instead of the hysteresis inverter, for example, A hysteresis comparator may be used.
  • the control unit CNT1 shown in FIG. 19E may be configured as shown in FIG. 19G by using the hysteresis comparators COM1 and COM2 instead of the hysteresis inverters INV1 and INV2.
  • the control unit CNT1 shown in FIG. 19G is different from the control unit CNT1 shown in FIG.
  • the waveform shaping units 13 and 13'do not invert signals may be inverted in the waveform shaping unit by exchanging the inverting input terminal and the non-inverting input terminal of the hysteresis comparator.
  • the control unit CNT1 shown in FIG. 19A, the control unit CNT1 shown in FIG. 19C, the control unit CNT1 shown in FIG. 19D, the control unit CNT1 shown in FIG. 19E, and the control unit CNT1 shown in FIG. 19G include a hysteresis inverter or a hysteresis comparator. Although it has a configuration, an inverter having no hysteresis characteristic may be used instead of the hysteresis inverter, and a comparator having no hysteresis characteristic may be used instead of the hysteresis comparator.
  • FIG. 20 is a diagram showing a configuration example of the shunt resistor R1.
  • the shunt resistor R1 of the configuration example shown in FIG. 20 has a configuration in which a plurality of resistance elements RE1 are connected in parallel. By connecting a plurality of resistance elements RE1 in parallel, it becomes easy to reduce the resistance value of the shunt resistor R1.
  • the plurality of resistance elements RE1 shown in the figure can correspond to the plurality of resistors R1 shown in FIG.
  • the on-time of the NMOS transistor Q1 is shorter than half of the resonance period T of the LCR resonance circuit, the power of the laser light is reduced.
  • the number of resistance elements RE1 connected in parallel is not limited to three, and may be a plurality.
  • the number of resistance elements RE1 connected in parallel may be determined in consideration of the balance between the required resistance value of the shunt resistor R1 and the required mounting area of the shunt resistor R1.
  • the inductance component of the LCR resonance circuit should be small.
  • the mutual inductance M of the adjacent resistance elements RE1 can be expressed by the following equation (1).
  • LN is the length of the resistance element RE1
  • d is the distance between the adjacent resistance elements RE1.
  • the unit of the mutual inductance M is [H]
  • the unit of the length LN and the unit of the interval d are [m], respectively.
  • M 2LN (ln (2LN / d) -1) x 10-7 ... (1)
  • the condition for suppressing the mutual inductance M to zero can be expressed by the following equation (2).
  • e is the number of Napiers. ln (2LN / d) -1 ⁇ 0 d ⁇ 2LN / e ⁇ ⁇ ⁇ (2)
  • the interval d between the adjacent resistance elements RE1 is preferably a value or more obtained by dividing twice the length LN of the resistance element RE1 by the number of napiers.
  • the laser device 1 shown in FIG. 14 includes a substrate B1.
  • FIG. 21 is a top view of the substrate B1
  • FIG. 22 is a schematic view showing a cross section of the substrate B1.
  • three directions (x direction, y direction, and z direction) orthogonal to each other are referred to.
  • the z direction corresponds to the thickness direction of the substrate B1.
  • a plurality of electronic components in the circuit configuration shown in FIG. 14 are mounted on the substrate B1.
  • FIG. 21 shows the component layout and land pattern on the board B1.
  • a plurality of electronic components are shown by imaginary lines (dashed-dotted lines).
  • the substrate B1 has a rectangular shape in the z-direction view (plan view).
  • the substrate B1 is a laminated substrate, and as shown in FIG. 22, includes four wiring layers Ly1 to Ly4 laminated with each other via an insulating layer Ly0.
  • the number of wiring layers is not limited to four, and may be a plurality. Unlike this embodiment, it is also possible to use a single layer substrate.
  • the wiring layer Ly1 is the first layer and the uppermost layer in the substrate B1.
  • a solder layer is formed on the upper surface of the wiring layer Ly1. This solder layer is partially covered with a resist film (not shown). The solder exposed from the resist film corresponds to the land pattern shown in FIG.
  • the wiring layer Ly4 is the fourth layer and the lowest layer in the substrate B1.
  • the wiring layers Ly2 and Ly3 are intermediate layers in the substrate B1.
  • the wiring layer Ly2 is a second layer on the substrate B1 and is sandwiched between the wiring layer Ly1 and the wiring layer Ly3 in the z direction.
  • the wiring layer Ly3 is a third layer on the substrate B1 and is sandwiched between the wiring layer Ly2 and the wiring layer Ly4 in the z direction.
  • the wiring layer Ly2 is a ground layer to which a ground potential is applied. In the wiring layer Ly2, the ground of the signal system and the ground of the power supply system are not separated, and the ground of the signal system and the ground of the power supply system are shared.
  • the plurality of wiring layers Ly1 to Ly4 are electrically connected to each other by a penetrating via TV penetrating the insulating layer Ly0.
  • the penetrating via TV is shown by a dotted line.
  • the thickness d0 of the insulating layer Ly0 sandwiched between the wiring layer Ly1 and the wiring layer Ly3 is preferably 200 ⁇ m or less.
  • the length of the penetrating via TV between the wiring layer Ly1 and the wiring layer Ly3 becomes shorter than that of the normal laminated substrate, and the inductance of the penetrating via TV between the wiring layer Ly1 and the wiring layer Ly3 becomes smaller.
  • the inductance of the LCR resonant circuit can be reduced.
  • the length of the penetrating via TV between the wiring layer Ly1 and the wiring layer Ly3 is about 700 ⁇ m.
  • through holes TH are formed in the four corners of the substrate B1. Each through hole TH penetrates the substrate B1 in the z direction. Each through hole TH is provided to fix the substrate B1 to the support member, and a fastener such as a bolt is inserted through the through hole TH.
  • the plurality of capacitors C0 are arranged side by side in the x direction.
  • a plurality of capacitors C0 are connected in parallel by the wiring layer Ly1 to form the capacitor C1.
  • two terminals are arranged in the y direction.
  • Each capacitor C0 is, for example, a chip type, but may be a lead type. It is very effective to connect a plurality of capacitors C0 in parallel to form the capacitor C1 in order to reduce the parasitic inductance of the capacitor C1.
  • the plurality of resistance elements RE1 are arranged side by side in the x direction.
  • the plurality of resistance elements RE1 are connected in parallel by the wiring layer Ly1 to form a shunt resistor R1.
  • each resistance element RE1 two terminals are arranged in the y direction.
  • Each resistance element RE1 is, for example, a chip type, but may be a lead type. Further, according to the above equation (2), it is preferable to select a resistance element (long-side resistance element) having a length LN as short as possible with respect to the interval d, or a metal electrode resistance element.
  • the capacitor C1 and the shunt resistor R1 are aligned in the y direction.
  • a diode D1 and a laser diode LD1 are arranged between the capacitor C1 and the shunt resistor R1.
  • the diode D1 and the laser diode LD1 are arranged in the y direction.
  • Three mounting regions for the laser diode LD1 are provided so that different types of laser diode LD1 can be mounted.
  • the 1st pin (anode of the laser diode) of the TO-Can package type laser diode LD1 and the 3rd pin (cathode of the laser diode) of the TO-Can package type laser diode LD1 are aligned in the y direction. More specifically, the direction from the 1st pin of the TO-Can package type laser diode LD1 to the 3rd pin of the TO-Can package laser diode LD1 is substantially parallel to the y direction.
  • the direction from the cathode of the chip-type laser diode LD1 mounted on the right end of the substrate B1 to the anode of the laser diode LD1 on the chip side mounted on the right end of the substrate B1 is also substantially parallel to the y direction.
  • the second pin of the TO-Can package type laser diode LD1 is the cathode of the light receiving element built in the TO-Can package.
  • the switching element Q1 is aligned with the capacitor C1 in the y direction.
  • the switching element Q1 is adjacent to the capacitor C1 in the y direction.
  • the capacitor C1 is sandwiched between the switching element Q1 and the shunt resistor R1.
  • FIG. 21 shows an input terminal 11 which is a coaxial connector, an inverter INV1, a delay unit 12 composed of a resistor 12A and a capacitor 12B, an inverter INV2, and an IC package U1 including a calculation unit 14 and a drive unit 15. As shown above, they are arranged in the x direction. As a result, the wiring length in the control unit CNT1 can be shortened.
  • the number of through vias provided in the right half region of the substrate B1 (the region on which the diode D1, the laser diode LD1, the switching element Q1 and the shunt resistor R1 are mounted) is the left of the substrate B1. More than the number of penetrating diodes provided in the half area. Thereby, the ground in the LCR resonance circuit can be particularly strengthened.
  • the laser device 1 shown in FIG. 14 described above is used, for example, as a part of the laser radar device X1 shown in FIG. 23.
  • the laser radar device X1 shown in FIG. 23 is a scanning laser radar device, and includes a laser device 1, a light receiving device 3, an optical system 4, and an overall control unit 5.
  • the overall control unit 5 controls the output of the laser device 1 and the direction of the mirror in the optical system 4, calculates the distance to the object based on the control content of the output of the laser device 1 and the output signal of the light receiving device 3, and optics.
  • the direction of the object is calculated based on the control content of the direction of the mirror in the system 4.
  • the laser radar device X1 shown in FIG. 23 is provided at the front end of the vehicle Y1 shown in FIG. 24, for example, and detects an object located in front of the vehicle Y1.
  • the arrangement of the parallel circuit of the capacitor C1, the diode D1 and the laser diode LD1 and the shunt resistor R1 does not have to be the configuration shown in FIG.
  • the shunt resistor R1 may not be provided.
  • the laser diode driving device according to the first side surface may be used for the laser device 1 shown in FIG.
  • the laser device 1 may be used for the laser radar device X1 shown in FIG. 23 (and by extension, the vehicle Y1 shown in FIG. 24).
  • Appendix 1 B A drive device that controls the drive of a laser diode.
  • Switching element and A control unit that controls the switching element on / off,
  • the control unit is a drive device that shortens the on-time of the switching element to less than half of the resonance period of the closed circuit.
  • the parallel connection between the laser diode and the rectifying element is not limited to the parallel connection between the laser diode only and the rectifying element only, and the parallel connection between the circuit including the laser diode and the rectifying element only. It may be a parallel connection of only the laser diode and the circuit including the rectifying element, or a parallel connection of the circuit including the laser diode and the circuit including the rectifying element.
  • Appendix 2 B The control unit makes the on-time of the switching element shorter than the period from the timing when the switching element is switched from off to on to the second timing when the resonance current of the closed circuit becomes half of the maximum value.
  • the driving device according to Appendix 1B or Appendix 2B, wherein the control unit sets the on-time of the switching element to one-fourth or more of the resonance period of the closed circuit.
  • Appendix 4 B The control unit A delay unit that delays a signal based on the first pulse signal to generate a delay signal, A waveform shaping unit that shapes the waveform of the delay signal and generates a second pulse signal, A calculation unit that generates a third pulse signal having a pulse width shorter than that of the first pulse signal by a calculation using the first pulse signal and the second pulse signal.
  • the driving device according to Appendix 4B, wherein the pulse width of the first pulse signal is at least half of the resonance period of the closed circuit.
  • Appendix 6 B The drive device according to any one of Appendix 1B to 5B, further comprising a shunt resistor for detecting a current flowing through the laser diode, wherein the closed circuit includes the shunt resistor.
  • Appendix 7 B The driving device according to Appendix 6B, wherein the shunt resistor includes a plurality of resistance elements connected in parallel.
  • the plurality of resistance elements include a first resistance element and a second resistance element having the same length and adjacent to each other, and the distance between the first resistance element and the second resistance element is 2 having the same length.
  • the drive device according to Appendix 7B which is equal to or greater than the value obtained by dividing the multiple by the number of napiers.
  • Appendix 9B The drive device according to any one of Appendix 1B to 8B, and With the laser diode A laser device.
  • Appendix 10 B With more boards The laser device according to Appendix 9B, wherein the switching element, the parallel circuit including the rectifying element and the laser diode, and the capacitor are arranged side by side in the first direction orthogonal to the thickness direction of the substrate.
  • Appendix 11B The laser apparatus according to Appendix 10B, wherein the direction from the anode of the laser diode to the cathode of the laser diode is substantially parallel to the first direction.
  • Appendix 12 B The laser apparatus according to Appendix 10B, wherein the direction from the anode of the laser diode to the cathode of the laser diode is substantially parallel to the first direction.
  • the drive device is the drive device described in Appendix 4B.
  • the substrate is a laminated substrate including a first wiring layer and a second wiring layer, the second wiring layer functions as a ground layer, and the distance between the first wiring layer and the second wiring layer is 200 ⁇ m or less.
  • Appendix 14B The laser device according to Appendix 13B, wherein the ground of the signal system and the ground of the power supply system are shared in the second wiring layer.
  • Appendix 15 B A laser radar device including the laser device according to any one of Appendix 9B to 14B.
  • Appendix 16 B A vehicle comprising the laser radar device according to Appendix 15B.
  • FIGS. 25 to 43 An embodiment based on the third aspect of the present disclosure will be described with reference to FIGS. 25 to 43.
  • the reference numerals in FIGS. 25 to 43 are attached independently of the reference numerals in FIGS. 1 to 13 (first side surface) and 14 to 24 (second side surface). Therefore, in FIGS. 25 to 43 and 1 to 24, the same reference numerals may refer to different elements, or the same (or similar) elements may be referred to.
  • the drive device A1 controls the drive (irradiation of laser light) of the laser diode LD.
  • the drive device A1 causes the laser diode LD to emit light by supplying a drive current to the laser diode LD.
  • the laser diode LD may be built in a so-called TO-Can package type laser module, or may be built in a surface mount type laser module.
  • the package structure of the laser module is not limited to these.
  • a photodiode is built in in addition to the laser diode LD, but the photodiode may not be built in.
  • the TO-Can package type laser module is provided with three lead terminals, that is, a lead terminal that conducts to the anode of the laser diode LD, a lead terminal that conducts to the cathode of the photodiode, and a cathode and photo of the laser diode LD.
  • the number of lead terminals may be two or four instead of three.
  • the drive device A1 includes a switching element Q1, a plurality of capacitors C1, a plurality of shunt resistors R1, a feedback diode D1, a drive circuit DR, two resistors R2, a pulse generation circuit PG, and a plurality of connector terminals. It includes T1 to T3, a connection terminal T4, and two power supply units PS1 and PS2.
  • FIG. 25 also shows a laser diode LD that is driven and controlled by the driving device A1.
  • the configuration shown in FIG. 25 also has the same characteristics as the configuration according to the first aspect described above. That is, the laser diode driving device A1 shown in FIG.
  • the 25 has a switching element (Q1) that switches between a conduction state and a cutoff state, a capacitor (C1), a first diode (D1), and an input terminal to which a power supply voltage is supplied. (See VLD) and.
  • the first end (lower end) of the capacitor (C1) is connected to the cathode of the laser diode (LD1), and the second end (upper end) is connected to the switching element (Q1).
  • the anode of the first diode (D1) is connected to a connection point between the first end (lower end) of the capacitor (C1) and the cathode of the laser diode (LD1).
  • the input terminal (see VLD) is connected to a connection point between the second end (upper end) of the capacitor (C1) and the switching element (Q1). Therefore, the above-mentioned technical effect on the first aspect is also exhibited in the configuration (third aspect) shown in FIG. On the contrary, it is also possible to apply the configuration according to the third aspect described below to the drive device according to the first aspect.
  • the switching element Q1 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
  • the switching element Q1 is not limited to the MOSFET, and may be another transistor.
  • the switching element Q1 is made of a semiconductor material.
  • the semiconductor material is, for example, GaN (gallium nitride).
  • the semiconductor material is not limited to GaN, and may be Si (silicon), SiC (silicon carbide), GaAs (gallium arsenide), Ga 2 O 3 (gallium oxide), or the like.
  • the switching element Q1 has a drain connected to each capacitor C1, a source connected to the ground terminal GND, and a gate connected to the drive circuit DR.
  • the ground terminal GND gives a reference potential.
  • a drive signal is input to the gate of the switching element Q1 from the drive circuit DR, and the conduction state and the cutoff state are switched according to the drive signal.
  • an operation of switching between a conduction state and a cutoff state may be referred to as a “switching operation”.
  • the conductive state is a state in which a current flows between the drain and the source
  • the cutoff state is a state in which no current flows between the drain and the source.
  • the drive signal is, for example, a pulse wave in which an on signal and an off signal are alternately switched.
  • the switching element Q1 is in a conductive state when the drive signal is an on signal, and is in a cutoff state when the drive signal is an off signal.
  • the plurality of capacitors C1 are connected in parallel with each other.
  • the first end C11 is connected to the cathode of the laser diode LD, and the second end C12 is connected to the drain of the switching element Q1. Further, the first end C11 of each capacitor C1 is also connected to the anode of the feedback diode D1.
  • Each capacitor C1 (second end C12) is connected to the power supply unit PS1, and the power supply voltage VLD is applied from the power supply unit PS1.
  • the number of capacitors C1 is not limited to this.
  • the plurality of shunt resistors R1 are connected in parallel with each other.
  • the first end R11 is connected to the cathode of the feedback diode D1 and the anode of the laser diode LD, and the second end R12 is connected to the ground end GND.
  • the case where three shunt resistors R1 are connected in parallel will be described, but the number of shunt resistors R1 is not limited to this.
  • a plurality of shunt resistors R1 are connected to monitor the drive current of the laser diode LD. The current value monitored by the shunt resistor R1 can be detected from the connector terminal T3.
  • the feedback diode D1 has an anode connected to the cathode of the laser diode LD and a cathode connected to the anode of the laser diode LD. Further, in the feedback diode D1, the anode is connected to the first end C11 of each capacitor C1, and the cathode is connected to the first end R11 of each shunt resistor R1. As shown in FIG. 25, in the feedback diode D1, the anode is connected to the connection point between the first end C11 of each capacitor C1 and the cathode of the laser diode LD, and the cathode is connected to the first end R11 of each shunt resistor R1.
  • PN junction diode for example, a fast recovery diode
  • a Schottky barrier diode may be used.
  • the pulse generation circuit PG generates a pulse signal for controlling the switching operation of the switching element Q1.
  • the pulse generation circuit PG receives a control signal from the connector terminal T1 and generates a pulse signal based on the control signal.
  • the pulse generation circuit PG outputs the generated pulse signal to the drive circuit DR.
  • the pulse signal in this embodiment is, for example, a square wave having a frequency of 10 kHz and a duty ratio of 0.005%. Further, this pulse signal has a pulse width of 5 nsec and a pulse rise time of 1 nsec.
  • a pulse signal for driving the laser diode LD in 5 nsec or less is generated. It should be noted that each parameter of the pulse signal is an example and is not limited to this.
  • the drive circuit DR generates a drive signal for driving (switching operation) the switching element Q1.
  • a pulse signal is input from the pulse generation circuit PG, and a drive signal is generated based on the pulse signal.
  • the drive signal is, for example, a signal obtained by boosting the pulse signal to a voltage required for driving the switching element Q1.
  • the drive circuit DR includes a drive IC 9, and a drive signal is generated by the drive IC 9.
  • each of the two resistors R2 is connected between the drive IC 9 and the gate of the switching element Q1.
  • the drive signal output from the drive IC is input to the gate of the switching element Q1 via either resistor R2.
  • Each resistor R2 is a so-called gate resistor.
  • the current value input to the switching element Q1 is set according to the resistance value of each resistor R2. Further, each resistor R2 controls the switching speed of the switching element Q1.
  • the connector terminal T1 is an input terminal for the power supply voltage VLD.
  • a DC power supply (external power supply) provided outside the drive device A1 is connected to the connector terminal T1, and a power supply voltage VLD is supplied from this external power supply.
  • the power supply voltage VLD is used to drive the laser diode LD, and is, for example, 3 V or more and 100 V or less.
  • the connector terminal T1 is also an input terminal for a control signal.
  • the connector terminal T1 is, for example, a plug-type terminal.
  • Each connector terminal T2 and T3 is a jack type terminal to which a coaxial cable can be connected, for example.
  • connection terminal T4 is a terminal for connecting a laser module (laser diode LD).
  • the power supply unit PS1 is connected between the connector terminal T1 and the plurality of capacitors C1.
  • the power supply unit PS1 includes an electrolytic capacitor C2, a backflow prevention diode D3, a reactor L1, two charging resistors R3, and the like.
  • the electrolytic capacitor C2 is a so-called bypass capacitor and stabilizes the input voltage (power supply voltage VLD).
  • the backflow prevention diode D3 prevents current from flowing from each capacitor C1 side to the external power supply (connector terminal T1) side.
  • the reactor L1 boosts the input voltage.
  • Each charging resistor R3 adjusts the amount of current of the current from the external power supply (connector terminal T1) side toward each capacitor C1. These may be connected as needed.
  • the power supply unit PS2 generates an operating voltage V1.
  • the operating voltage V1 is mainly used for driving each electronic component constituting the pulse generation circuit PG.
  • the operating voltage V1 is, for example, 3.3 V, but is not limited thereto.
  • the drive device A1 includes a plurality of test points TP1 to TP6 and a plurality of ground points GP1 to GP4 in its circuit configuration.
  • Each test point TP1 to TP6 is a terminal for signal detection.
  • Each ground point GP1 to GP4 is a terminal grounded to a reference potential.
  • FIGS. 26 and 27 are diagrams in which main electronic components in the light emitting operation of the laser diode LD are extracted from the circuit configuration of the drive device A1 shown in FIG. 25.
  • a plurality of capacitors C1 and a plurality of shunt resistors R1 are shown one by one.
  • the DC power supply shown in FIGS. 26 and 27 corresponds to the external power supply connected to the connector terminal T1 shown in FIG. 25 and the power supply unit PS1.
  • FIG. 26 shows the case where the switching element Q1 is in the cutoff state
  • FIG. 27 shows the case where the switching element Q1 is in the conductive state.
  • each capacitor C1 when the switching element Q1 is brought into a conductive state, as shown in FIG. 27, the second end C12 of each capacitor C1 conducts to the ground end GND via the switching element Q1. As a result, the electric charge accumulated in each capacitor C1 flows into the switching element Q1, and a current flows from each capacitor C1 to the ground terminal GND via the switching element Q1. Then, a forward current flows from the grounded end GND to the laser diode LD through each shunt resistor R1, and the laser diode LD emits light (see the current path LP shown by the broken line). When each capacitor C1 is completely discharged, this current stops flowing and the laser diode LD does not emit light.
  • the module configuration of the drive device A1 will be described with reference to FIGS. 28 to 35.
  • three directions (x direction, y direction, and z direction) orthogonal to each other are appropriately referred to.
  • the z direction is the thickness direction of the drive device A1.
  • the drive device A1 includes a circuit board 10, a plurality of electronic components, and a plurality of terminals.
  • the plurality of electronic components and the plurality of terminals correspond to the plurality of electronic components and the plurality of terminals in the circuit configuration shown in FIG. 25, and are mounted on the circuit board 10.
  • FIG. 28 shows the component layout and land pattern on the circuit board 10.
  • a plurality of electronic components and a plurality of terminals are shown by an imaginary line (dashed line).
  • FIG. 29 is an enlarged view of a part of FIG. 28, and a main part is extracted.
  • the drive device A1 is provided with two socket terminals T41 and T42 and a pad terminal T43 as the connection terminals T4 having the circuit configuration shown in FIG. 25. It is not necessary to provide all of the two socket terminals T41 and T42 and the pad terminal T43 as the connection terminal T4, and it is sufficient to provide any one of them.
  • the circuit board 10 has a substantially rectangular shape in a plan view.
  • the thickness direction of the circuit board 10 coincides with the z direction.
  • the circuit board 10 has, for example, a dimension of 70.0 mm in the x direction and a dimension of 45.0 mm in the y direction.
  • the plan view dimensions of the circuit board 10 are not limited to this, and can be changed as appropriate.
  • the circuit board 10 is, for example, a laminated board, and includes a plurality of wiring layers Ly1 to Ly4 that are laminated with each other via an insulating layer in the z direction.
  • 30 to 33 are plan views showing the respective wiring layers Ly1 to Ly4, respectively.
  • the wiring layer Ly1 is formed by the wiring pattern 21
  • the wiring layer Ly2 is formed by the wiring pattern 22
  • the wiring layer Ly3 is formed by the wiring pattern 23
  • the wiring layer Ly4 is formed by the wiring pattern 24. Is formed of.
  • the wiring patterns 21 to 24 are painted in black.
  • the wiring layer Ly1 is the first layer and the uppermost layer in the circuit board 10. Each electronic component is mounted on the wiring layer Ly1. For example, a solder layer is formed on the upper surface of the wiring layer Ly1, and the solder layer is partially covered with a resist film (not shown). The solder layer exposed from the resist film forms the land pattern shown in FIG. 28. This land pattern includes five resistance lands 20 as shown in FIG. Each of the five resistor lands 20 may be joined with each shunt resistor R1.
  • the wiring layer Ly4 is the fourth layer and the lowest layer in the circuit board 10. For example, a solder layer is formed on the lower surface of the wiring layer Ly4, and the solder layer is partially covered with a resist film (not shown).
  • the wiring layers Ly2 and Ly3 are intermediate layers in the circuit board 10.
  • the wiring layer Ly2 is the second layer on the circuit board 10, and the wiring layer Ly3 is the third layer on the circuit board 10.
  • the wiring layer Ly2 is sandwiched between the wiring layer Ly1 and the wiring layer Ly3 in the z direction, and the wiring layer Ly3 is sandwiched between the wiring layer Ly2 and the wiring layer Ly4 in the z direction.
  • the wiring pattern 22 (wiring layer Ly2) is a GND (ground) pattern that is grounded to the reference potential. As shown in FIG. 31, the wiring pattern 22 is a solid pattern.
  • the wiring pattern 23 (wiring layer Ly3) is a power supply pattern. As shown in FIG. 32, the wiring pattern 23 is divided into a plurality of regions, and the value of the voltage applied in each region is different.
  • the wiring pattern 24 (wiring layer Ly4) is mainly a GND pattern grounded at a reference potential. However, a part of the wiring pattern 24 (pattern 241 in FIG. 33) is a power supply pattern.
  • each thickness (dimension in the z direction) of the plurality of wiring layers Ly1 to Ly4 is, for example, about 115 ⁇ m.
  • the thickness of the wiring layer is generally 350 ⁇ m or 700 ⁇ m, for example, so that the thickness of each wiring layer Ly1 to Ly4 in the drive device A1 is thin.
  • the plurality of wiring layers Ly1 to Ly4 only the wiring layer Ly1 has a thickness of about 115 ⁇ m, and the other wiring layers Ly2 to Ly4 may have a general thickness of about 350 ⁇ m or 700 ⁇ m.
  • a plurality of through electrodes 30 are formed on the circuit board 10.
  • the plurality of through electrodes 30 penetrate the circuit board 10 in the z direction.
  • the plurality of wiring layers Ly1 to Ly4 are electrically connected to each other by the plurality of through electrodes 30. In FIG. 28, only a part of the plurality of through electrodes 30 is designated.
  • the circuit board 10 includes two aggregation regions AG1 and AG2 in which a plurality of through electrodes 30 are densely arranged in a plan view.
  • Each through electrode 30 arranged in each of the gathering regions AG1 and AG2 conducts at least the wiring layer Ly1 and the wiring layer Ly2, and does not conduct to the wiring layer Ly3.
  • the through silicon vias 30 arranged in the gathering regions AG1 and AG2 may or may not be electrically connected to the wiring layer Ly4.
  • the wiring layer Ly4 has a GND pattern, and it is preferable that the wiring layer Ly4 is electrically connected to the wiring layer Ly4.
  • the gathering region AG1 is located in the y2 direction with respect to the shunt resistance group R0 and is adjacent to the shunt resistance group R0.
  • the collecting region AG2 is located in the y1 direction with respect to the switching element Q1 and is adjacent to the switching element Q1.
  • through holes HL are formed at each of the four corners in the plan view of the circuit board 10.
  • Each through hole HL penetrates the circuit board 10 in the z direction.
  • Each through hole HL is provided to fix the drive device A1 to the support member, and a fastener such as a bolt can be inserted therethrough.
  • Each through hole HL is arranged so that the center in a plan view overlaps each of the four corners of the circuit board 10 at a position of, for example, 3.5 mm in the x direction and 3.5 mm in the y direction.
  • the circuit board 10 includes two mounting regions M1 and M2 in a plan view.
  • a laser module (laser diode LD) can be mounted in each of the mounting regions M1 and M2.
  • the socket terminals T41 and T42 are attached to the mounting areas M1 and M2, and the TO-Can package type laser module is mounted via the socket terminals T41 and T42.
  • each mounting area M1 and M2 includes three terminal connection portions Ma, Mb, and Mc.
  • Each lead terminal of the TO-Can package type laser module is connected to each terminal connection portion Ma, Mb, Mc.
  • a lead terminal conducting to the anode of the laser diode LD is connected to the terminal connection portion Ma.
  • a lead terminal conducting to the cathode of the photodiode is connected to the terminal connection portion Mb.
  • Leads conducting to the cathode of the laser diode LD and the anode of the photodiode are connected to the terminal connection portion Mc.
  • each mounting area M1 and M2 includes four terminal connection portions.
  • each mounting area M1 and M2 may be configured to include two terminal connecting portions or may be configured to include three or more terminal connecting portions.
  • the terminal connection portion Ma and the terminal connection portion Mc are aligned in the y direction, and the terminal connection portion Ma is located in the y1 direction with respect to the terminal connection portion Mc. ..
  • the lead terminal conducting to the anode of the laser diode LD and the lead terminal conducting to the cathode of the laser diode LD are aligned in the y direction, and the laser diode
  • the lead terminal conducting to the anode of the LD is located in the y1 direction with respect to the lead terminal conducting to the cathode of the laser diode LD. This also applies when the laser module is mounted in the mounting area M2 via the socket terminal T42.
  • the terminal connection portion Mb and the terminal connection portion Mc are aligned in the x direction, and the terminal connection portion Mc is located in the x1 direction with respect to the terminal connection portion Mb. To do. On the contrary, the terminal connection portion Mc may be located in the x2 direction with respect to the terminal connection portion Mb.
  • the plurality of capacitors C1 are arranged side by side in the x direction.
  • two terminals first end C11 and second end C12
  • the second end C12 is located in the y2 direction with respect to the first end C11.
  • the first ends C11 of the plurality of capacitors C1 are electrically connected to each other by the wiring pattern 21 of the wiring layer Ly1, and the second ends C12 of the plurality of capacitors C1 are electrically connected to each other by the wiring pattern 21 of the wiring layer Ly1.
  • Each capacitor C1 is, for example, a chip type, but may be a lead type.
  • the capacitances of the plurality of capacitors C1 are substantially the same, and the plan-view dimensions are also substantially the same.
  • the capacitor group C0 is formed by the plurality of capacitors C1.
  • the plurality of shunt resistors R1 are arranged side by side in the x direction.
  • two terminals first end R11 and second end R12
  • the first end R11 is located in the y2 direction with respect to the second end R12.
  • the first ends R11 of the plurality of shunt resistors R1 are electrically connected to each other by the wiring pattern 21 of the wiring layer Ly1, and the second ends R12 of the plurality of shunt resistors R1 are connected to each other by the wiring pattern 21 of the wiring layer Ly1. They are conducting with each other.
  • Each shunt resistor R1 is, for example, a chip type, but may be a lead type.
  • the plurality of shunt resistors R1 have substantially the same resistance value, and the plan view dimensions are also substantially the same.
  • Each shunt resistor R1 has, for example, an x-direction dimension (dimension Dx in FIG. 29) of 3.2 mm and a y-direction dimension (dimension D in FIG. 29) of 6.4 mm.
  • the plan view dimension of each shunt resistor R1 is not limited to this, and generally, the larger the resistance value, the larger the plan view area.
  • the shunt resistor group R0 is formed by the plurality of shunt resistors R1.
  • the separation distance SD1 between the two shunt resistors R1 adjacent to each other in the x direction is equal to or larger than a predetermined size.
  • this predetermined size is the x-direction dimension Dx of one shunt resistor R1. That is, one shunt resistor having the same magnitude as each shunt resistor R1 can be arranged between two shunt resistors R1 adjacent to each other in the x direction.
  • the separation distance SD1 is, for example, about 5.0 mm. In the example shown in FIG.
  • resistance lands 20 are formed under the three shunt resistors R1 and between the two shunt resistors R1 adjacent to each other in the x direction. Therefore, five resistance lands 20 arranged in the x direction are formed on the circuit board 10, and the shunt resistor R1 is mounted on the resistance lands 20 at both ends in the x direction and the resistance lands 20 in the center of the x direction. Has been done. In this way, the separation distance SD1 is set to be equal to or greater than the x-direction dimension Dx of one shunt resistor R1.
  • the capacitor group C0 and the shunt resistor group R0 are aligned in the y direction.
  • mounting regions M1 and M2 are arranged between the capacitor group C0 and the shunt resistor group R0.
  • the edge of the capacitor group C0 on the x1 direction side overlaps with the shunt resistance R1 arranged in the x1 direction of the shunt resistance group R0 when viewed in the y direction, and the capacitor group C0
  • the edge on the x2 direction side overlaps with the shunt resistance R1 arranged in the x2 direction of the shunt resistance group R0 when viewed in the y direction.
  • the switching element Q1 is aligned with the capacitor group C0 in the y direction.
  • the switching element Q1 is adjacent to the capacitor group C0 in the y direction.
  • the switching element Q1 is located on the opposite side of the shunt resistance group R0 with respect to the capacitor group C0 in the y direction. That is, the switching element Q1 is located in the y2 direction with respect to the capacitor group C0.
  • the switching element Q1 overlaps the center of the capacitor group C0 in the x direction when viewed in the y direction. As a result, the difference in the conduction path from the switching element Q1 to each capacitor C1 becomes small.
  • the switching element Q1 has a plurality of electrodes Q11, Q12, and Q13 formed on the lower surface in the z direction in the module configuration of the drive device A1.
  • the plurality of electrodes Q11 are gate electrodes in the switching element Q1.
  • the plurality of electrodes Q12 are drain electrodes in the switching element Q1.
  • the plurality of electrodes Q13 are source electrodes in the switching element Q1.
  • a plurality of electrodes Q11 gate electrodes
  • a plurality of electrodes Q11 are arranged along the edge on the x1 direction side in a plan view.
  • the arrangement of the electrodes Q11, Q12, and Q13 is not limited to the example shown in FIG. 34.
  • Each resistor R2 is arranged between the drive IC 9 and the switching element Q1 in the x direction, and is adjacent to these. As a result, the transmission path of the drive signal output from the drive IC9 (drive circuit DR) and input to the gate of the switching element Q1 via the resistor R2 becomes linear.
  • the drive IC9, the switching element Q1, and each resistor R2 overlap each other when viewed in the x direction.
  • the two socket terminals T41 and T42 are terminals for connecting a TO-Can package type (3 terminals) laser module, respectively.
  • the laser module to be connected is a TO-Can package type
  • the laser module is connected to either the socket terminal T41 or the socket terminal T42.
  • Each of the socket terminals T41 and T42 can be inserted with each lead terminal of the TO-Can package type laser module.
  • the two socket terminals T41 and T42 have different sizes, and one of them is selected according to the size of the laser module to be connected.
  • the sizes of the two socket terminals T41 and T42 are not limited to different ones, and may be the same.
  • a feedback diode D1 is arranged next to the socket terminal T41 in the y1 direction. As shown in FIGS. 28 and 29, the socket terminal T41 is attached to the mounting area M1, and the socket terminal T42 is attached to the mounting area M2.
  • the pad terminal T43 is a terminal for connecting a surface-mounted laser module.
  • the pad terminal T43 includes two land patterns that are separated from each other, as shown in FIGS. 28 and 29.
  • the laser module to be connected is a surface mount type
  • the laser module is connected to each land pattern of the pad terminal T43.
  • the pad terminal T43 is arranged along the edge of the circuit board 10 in a plan view.
  • the cathode of the laser diode is connected to the land pattern in the y2 direction, and the anode of the laser diode is connected to the land pattern in the y1 direction. It is also possible to connect a TO-Can package type laser module to the pad terminal T43.
  • the pad terminal T43 can be connected to the TO-Can package type.
  • a laser module can be connected.
  • switching element Q1 drive circuit DR, capacitor group C0 (plurality of capacitors C1), shunt resistor group R0 (plurality of shunt resistors R1), feedback diode D1, socket terminals T41, T42, and pads.
  • the terminal T43 is arranged on one side of the center of the circuit board 10 in the x direction.
  • the drive device A1 includes a plurality of shunt resistors R1.
  • the plurality of shunt resistors R1 are connected in parallel with each other, and each is connected in series with the laser diode LD. According to this configuration, since the plurality of shunt resistors R1 are connected in parallel with each other, the drive current supplied to the laser diode LD is divided into the respective shunt resistors R1. In particular, when the resistance values of the shunt resistors R1 are the same, the drive current is evenly divided into the shunt resistors R1. As a result, the current flowing through one shunt resistor R1 is reduced, so that the current reduction due to the parasitic inductance component is suppressed in each shunt resistor R1. That is, the drive device A1 can efficiently make the laser diode LD emit light.
  • the plurality of shunt resistors R1 are arranged in the x direction, and the separation distance SD1 of the two shunt resistors R1 adjacent to each other in the x direction is equal to or larger than the x-direction dimension Dx of each shunt resistor R1.
  • mutual inductance in two shunt resistors R1 adjacent to each other in the x direction can be reduced.
  • the inductance component in the drive device A1 can be reduced. Therefore, the drive device A1 can suppress a decrease in the drive current to the laser diode LD, and can make the laser diode LD emit light efficiently.
  • L is the length of each shunt resistor R1 (corresponding to the y-direction dimension Dy in FIG. 29)
  • d is the separation distance between two adjacent shunt resistors R1 (corresponding to the separation distance SD1 in FIG. 29). is there.
  • the parasitic inductance of each shunt resistor R1 is set to 1 nH. From this equation, it can be seen that the larger the separation distance d (separation distance SD1), the smaller the mutual inductance M.
  • the separation distance d is preferably set to d ⁇ (2L / e) ⁇ 0.74 ⁇ L.
  • FIG. 35 shows the result of simulating the time change of the voltage (shunt resistance voltage) applied to each shunt resistor R1.
  • the solid line in FIG. 35 is the result when the drive device A1, that is, between two shunt resistors R1 adjacent to each other in the x direction is equal to or larger than the x-direction dimension Dx of each shunt resistor R1.
  • the broken line in FIG. 35 is a drive device different from the drive device A1 (hereinafter referred to as “comparative drive device”), and a shunt similar to that of each shunt resistor R1 is also between two shunt resistors R1 adjacent to each other in the x direction. This is the result when a resistor is mounted.
  • the simulation results shown in FIG. 35 are shown in a simplified manner.
  • the shunt resistance voltage vibrates several times as shown in the waveform of the period Ta'in the broken line in FIG. 35.
  • the vibration of the shunt resistance voltage is suppressed as shown in the waveform of the period Ta.
  • the drive device A1 can suppress this flicker.
  • the period Tb from the rise to the fall of the first wave in the drive device A1 is the period from the rise to the fall of the first wave in the comparative drive device. Shorter than Tb'(see the dashed waveform in FIG. 35). That is, the fluctuation cycle of the shunt voltage in the drive device A1 is smaller than the fluctuation cycle of the shunt voltage in the comparative drive device (the resonance frequency is larger). This is because the inductance component of the drive device A1 is smaller than the inductance component of the comparative drive device. Therefore, by reducing the inductance component, the drive current of the laser diode LD can be shortened and increased in current.
  • each capacitor C1 is connected between the DC power supply and the laser diode LD. According to this configuration, the power supply voltage from the DC power supply is not directly applied to the laser diode LD. Therefore, the load applied to the laser diode LD is reduced, and the failure of the laser diode LD is suppressed.
  • the drive device A1 a plurality of capacitors C1, a socket terminal T41 (or a socket terminal T42), and a plurality of shunt resistors R1 are arranged in this order in the y direction.
  • the conduction path of the drive current flowing from each shunt resistor R1 through the laser diode LD to each capacitor C1 can be made linear.
  • the parasitic inductance of the wiring in the current path LP (see FIG. 27) when the switching element Q1 is in the conductive state can be reduced. That is, since the inductance component in the drive device A1 can be reduced, the drive device A1 can suppress a decrease in the drive current to the laser diode LD, and the laser diode LD can efficiently emit light.
  • the circuit board 10 has a mounting region M1 for mounting a laser module (laser diode LD).
  • the mounting region M1 includes a terminal connection portion Ma connected to the anode of the laser diode LD and a terminal connection portion Mc connected to the cathode of the laser diode LD.
  • the terminal connection portion Ma and the terminal connection portion Mc are arranged in the y direction, and the terminal connection portion Mc is arranged on the capacitor group C0 side and the terminal connection portion Ma is arranged on the shunt resistance group R0 side in the y direction. According to this configuration, the conduction path of the drive current flowing from each shunt resistor R1 to each capacitor C1 via the laser diode LD can be further made linear.
  • the parasitic inductance of the wiring in the current path LP (see FIG. 27) when the switching element Q1 is in the conductive state can be reduced. Therefore, since the inductance component in the drive device A1 can be reduced, the drive device A1 can improve the luminous efficiency of the laser diode LD. The same applies to the mounting area M2.
  • the switching element Q1 and the drive IC9 are arranged in the x direction, and only the resistor R2 is arranged between the switching element Q1 and the drive IC9.
  • the distance between the drive IC 9 and the switching element Q1 can be shortened, so that the transmission time of the drive signal output from the drive IC 9 and input to the switching element Q1 can be shortened.
  • This shortening of drive signal transmission improves the responsiveness of the switching operation. That is, the drive device A1 can improve the responsiveness of the switching operation of the switching element Q1.
  • the drive IC9 and the switching element Q1 are placed adjacent to each other without providing each resistor R2. The distance of may be further shortened.
  • the circuit board 10 includes the gathering regions AG1 and AG2 in which a plurality of through electrodes 30 are densely arranged.
  • the plurality of through electrodes 30 arranged in the collecting regions AG1 and AG2 are electrically connected to the wiring pattern 21 of the wiring layer Ly1 and the wiring pattern 22 of the wiring layer Ly2. According to this configuration, the conductivity between the wiring layer Ly1 and the wiring layer Ly2 becomes good.
  • the plurality of through electrodes 30 in the gathering region AG1 conduct the one end (second end R12) of each shunt resistor R1 and the GND pattern (wiring pattern 22), and the plurality of through electrodes 30 in the gathering region AG2 are The source of the switching element Q1 and the GND pattern (wiring pattern 22) are made conductive.
  • each shunt resistor R1 and the source of the switching element Q1 to the reference potential (GND) is strengthened, the quality of each signal in the drive device A1 is improved (for example, noise reduction), and the shunt resistance voltage is described. Vibration (fluctuation of reference potential) can be reduced.
  • the circuit board 10 includes a plurality of wiring layers Ly1 to Ly4.
  • the z-direction dimensions (thickness) of the plurality of wiring layers Ly1 to Ly4 are thinner than the general thickness (about 700 ⁇ m).
  • the z-direction dimensions of the plurality of through electrodes 30 are reduced. Therefore, the parasitic inductance of each through electrode 30 can be reduced.
  • the wiring layer Ly1 passes through the wiring layer Ly2 via the plurality of through electrodes 30 arranged in the gathering region AG1, and returns to the wiring layer Ly1 by the plurality of penetrating electrodes 30 arranged in the gathering region AG2. Since the incoming current path (corresponding to the current path LP in FIG. 27) can be shortened, the parasitic inductance of the wiring in this current path can be reduced.
  • the socket terminals T41 and T42 are attached to the mounting areas M1 and M2
  • the present invention is not limited to this, and the socket terminals T41 and T42 may not be attached.
  • the TO-Can package type laser module is directly mounted in each mounting area M1 and M2 by, for example, soldering.
  • the case where three shunt resistors R1 are arranged is shown, but the number of shunt resistors R1 is not limited to this.
  • two shunt resistors R1 may be arranged.
  • one shunt resistor R1 is joined to each of the five resistor lands 20 located at both ends in the x direction.
  • the circuit configuration of the drive device shown in FIG. 36 is shown in FIG. 37.
  • FIG. 37 a part of the circuit configuration shown in FIG. 25 is excerpted.
  • the configuration may be such that two shunt resistors R1 are arranged. In the example shown in FIG.
  • FIG. 39 a part of the circuit configuration shown in FIG. 25 is excerpted.
  • FIGS. 36 and 38 corresponds to FIG. 29.
  • the number of shunt resistors R1 is appropriately determined according to the specifications required for the drive device A1.
  • the resistance land 20 is arranged between two shunt resistors R1 adjacent to each other in the x direction in a plan view
  • the present invention is not limited to this.
  • the resistor land 20 may not be arranged between two shunt resistors R1 adjacent to each other in the x direction.
  • the circuit configuration of the drive device shown in FIG. 40 is shown in FIG. In FIG. 41, a part of the circuit configuration shown in FIG. 25 is excerpted. Further, as shown in FIG. 42, a solid pattern 29 may be arranged instead of the resistance land 20 between two adjacent shunt resistors R1 in the x direction.
  • the solid pattern 29 may be designed as a microstrip line or a coplanar line.
  • the circuit configuration of the drive device shown in FIG. 42 is shown in FIG. 43. In FIG. 43, a part of the circuit configuration shown in FIG. 25 is excerpted. Each layout diagram of FIGS. 40 and 42 corresponds to FIG. 29.
  • the drive device according to the present disclosure is not limited to the above-described embodiment.
  • the specific configuration of each part of the drive device of the present disclosure can be freely redesigned.
  • Appendix 1 C.I With multiple electronic components that supply the drive current to the laser diode, A circuit board on which the plurality of electronic components are mounted and Is equipped with The plurality of electronic components include a switching element that switches between a conduction state and a cutoff state, a plurality of resistors connected in parallel with each other and each connected in series with the anode of the laser diode, and a cathode of the laser diode. It includes a capacitor connected to the switching element and The plurality of resistors are arranged in a first direction orthogonal to the thickness direction of the circuit board.
  • the plurality of resistors include two resistors adjacent to each other in the first direction, and the distance between the two resistors in the first direction is such that the distance between the two resistors in the first direction is one of the plurality of resistors in the first direction.
  • a drive that is greater than or equal to the dimensions.
  • the switching element is a transistor having a first terminal, a second terminal, and a third terminal, and the conduction state and the cutoff state are switched according to a control signal input to the third terminal.
  • Appendix 3C The first end of any one of the plurality of resistors is connected to the anode of the laser diode.
  • the second end of any one of the plurality of resistors is grounded to a reference potential.
  • the first end of the capacitor is connected to the cathode of the laser diode and The second end of the capacitor is connected to the first terminal of the switching element.
  • the driving device according to Appendix 2C wherein the second terminal of the switching element is grounded to the reference potential.
  • Appendix 4 C The plurality of electronic components further include a drive circuit that generates the control signal.
  • the drive device according to Appendix 3C, wherein the drive circuit and the switching element are arranged in the first direction.
  • Appendix 5C The plurality of electronic components further include a current value setting element connected between the drive circuit and the third terminal.
  • the drive device according to Appendix 4C, wherein the current value setting element is arranged between the drive circuit and the switching element on the circuit board.
  • Appendix 6 C.I. It also has an input terminal to which the power supply voltage is supplied.
  • the drive device according to any one of Supplementary note 3C to Supplementary note 5C, wherein the capacitor is connected to the input terminal, and the power supply voltage is applied to the capacitor when the switching element is in the cutoff state.
  • Appendix 7 C.I. The driving device according to any one of Supplementary note 1C to Supplementary note 6C, wherein a land pattern is formed between the two resistors when viewed in the thickness direction of the circuit board.
  • the plurality of resistors form a group of resistors, and the plurality of resistors form a group of resistors.
  • the driving device according to any one of Supplementary note 1C to Supplementary note 7C, wherein the capacitor and the resistor group are arranged in the thickness direction and the second direction orthogonal to the first direction.
  • the circuit board includes a mounting area for mounting the laser diode.
  • apparatus Appendix 10 C.I.
  • the mounting region includes an anode connection for connecting the anode of the laser diode and a cathode connection for connecting the cathode of the laser diode.
  • the driving device according to Appendix 9C, wherein the anode connecting portion and the cathode connecting portion are arranged in the second direction when viewed in the thickness direction.
  • Appendix 11 C.I. It is connected in parallel with the capacitor and further includes an additional capacitor aligned with the resistor group in the second direction.
  • the drive device according to any one of Supplementary note 8C to Supplementary note 10C, wherein a capacitor group is formed by the capacitor and the additional capacitor.
  • the driving device wherein the switching element is arranged on the side opposite to the side where the resistor group is located with respect to the capacitor group in the second direction, and is adjacent to the capacitor group.
  • the plurality of resistors include a first resistor and a second resistor.
  • the first resistor is arranged on the most one side of the plurality of resistors in the first direction.
  • the second resistor is arranged on the farthest side of the plurality of resistors in the first direction.
  • the one-sided edge of the capacitor group in the first direction overlaps the first resistor when viewed in the second direction, and the other-side edge of the first direction of the capacitor group is the first.
  • the drive device according to Appendix 11C or Appendix 12C, which overlaps the second resistor when viewed in two directions.
  • the plurality of electronic components further include the first resistor and a third resistor connected in parallel with the second resistor.
  • the driving device according to Appendix 13C, wherein the third resistor is arranged between the first resistor and the second resistor in the first direction.
  • the circuit board includes an insulating layer and a first wiring layer and a second wiring layer laminated in the thickness direction and insulated from each other via the insulating layer.
  • the drive device according to any one of Supplementary note 8C to Supplementary note 14C, wherein the second wiring layer is grounded to a reference potential.
  • the circuit board includes an assembly region in which a plurality of through electrodes are arranged when viewed in the thickness direction.
  • the plurality of through electrodes penetrate the insulating layer and conduct the first wiring layer and the second wiring layer.
  • the circuit board is arranged on the side opposite to the first wiring layer in the thickness direction and includes a third wiring layer on which a power supply pattern is formed.
  • the basic configuration based on the first aspect of the present disclosure can be applied to both the second aspect and the third aspect (see paragraphs 0068, 0140).
  • appendices 1D to 16D first side surface + second side surface
  • appendices 1E to 17E first side surface + third side surface
  • Appendix 1D A drive device that controls the drive of a laser diode.
  • a switching element that switches between a conductive state and a cutoff state, With a capacitor With the first diode
  • the input terminal to which the power supply voltage is supplied and A control unit that controls the switching element on / off, Is equipped with The capacitor has a first end connected to the cathode of the laser diode and a second end connected to the switching element.
  • the anode is connected to the connection point between the first end of the capacitor and the cathode of the laser diode.
  • the input terminal is connected to a connection point between the second end of the capacitor and the switching element.
  • the control unit is a drive device that shortens the on-time of the switching element to less than half of the resonance period of the closed circuit.
  • Appendix 2D The control unit makes the on-time of the switching element shorter than the period from the timing when the switching element is switched from the off state to the on state to the second timing when the resonance current of the closed circuit becomes half of the maximum value.
  • Appendix 3D The driving device according to Appendix 1D, wherein the control unit sets the on-time of the switching element to one-fourth or more of the resonance period of the closed circuit.
  • Appendix 4D The drive device according to Appendix 1D, wherein the control unit sets the on-time of the switching element to one-fourth or more of the resonance period of the closed circuit.
  • the control unit A delay unit that delays a signal based on the first pulse signal to generate a delay signal, A waveform shaping unit that shapes the waveform of the delay signal and generates a second pulse signal, A calculation unit that generates a third pulse signal having a pulse width shorter than that of the first pulse signal by a calculation using the first pulse signal and the second pulse signal.
  • a delay unit that delays a signal based on the first pulse signal to generate a delay signal
  • a waveform shaping unit that shapes the waveform of the delay signal and generates a second pulse signal
  • a calculation unit that generates a third pulse signal having a pulse width shorter than that of the first pulse signal by a calculation using the first pulse signal and the second pulse signal.
  • the drive device according to any one of Supplementary note 1D to 5D, further comprising a shunt resistor for detecting a current flowing through the laser diode, wherein the closed circuit includes the shunt resistor.
  • Appendix 7D The driving device according to Appendix 6D, wherein the shunt resistor includes a plurality of resistance elements connected in parallel to each other.
  • Appendix 8D The plurality of resistance elements include a first resistance element and a second resistance element having the same length and adjacent to each other, and the distance between the first resistance element and the second resistance element is 2 having the same length.
  • the drive device according to Appendix 7D, which is greater than or equal to the value obtained by dividing the multiple by the number of napiers. Appendix 9D.
  • the drive device according to any one of Appendix 1D to 8D, and With the laser diode A laser device.
  • Appendix 10D With more boards The laser device according to Appendix 9D, wherein the switching element, the parallel circuit including the first diode and the laser diode, and the capacitor are arranged side by side in the first direction orthogonal to the thickness direction of the substrate. .. Appendix 11D.
  • the laser apparatus according to Appendix 10D wherein the direction from the anode of the laser diode to the cathode of the laser diode is substantially parallel to the first direction.
  • Appendix 12D The drive device is the drive device described in Appendix 4D.
  • the laser device according to Appendix 10D or 11D, wherein the delay unit, the waveform shaping unit, and the calculation unit are arranged in a second direction orthogonal to the thickness direction and the first direction.
  • Appendix 13D The substrate is a laminated substrate including a first wiring layer and a second wiring layer, the second wiring layer functions as a ground layer, and the distance between the first wiring layer and the second wiring layer is 200 ⁇ m or less.
  • Appendix 14D The laser apparatus according to Appendix 13D, wherein the ground of the signal system and the ground of the power supply system are shared in the second wiring layer.
  • Appendix 15D A laser radar device including the laser device according to any one of Appendix 9D to 14D.
  • Appendix 16D A vehicle comprising the laser radar device according to Appendix 15D.
  • Appendix 1 E A drive device that controls the drive of a laser diode.
  • a switching element that switches between a conductive state and a cutoff state, With a capacitor With the first diode
  • the anode is connected to the connection point between the first end of the capacitor and the cathode of the laser diode.
  • the input terminal is connected to a connection point between the second end of the capacitor and the switching element.
  • the plurality of resistors are arranged in a first direction orthogonal to the thickness direction of the circuit board.
  • the plurality of resistors include two resistors adjacent to each other in the first direction, and the distance between the two resistors in the first direction is the distance between the two resistors in the first direction of any one of the plurality of resistors.
  • Drive device that is greater than or equal to the dimensions in.
  • the switching element is a transistor having a first terminal, a second terminal, and a third terminal, and the conduction state and the cutoff state are switched according to a control signal input to the third terminal. The drive device described. Appendix 3E.
  • the first end of any one of the plurality of resistors is connected to the anode of the laser diode, and the second end of any one of the plurality of resistors is grounded to a reference potential.
  • the driving device according to Appendix 2E wherein the second terminal of the switching element is grounded to the reference potential.
  • Appendix 4 E It further includes a drive circuit that generates the control signal.
  • the drive device according to Appendix 2E wherein the drive circuit and the switching element are arranged in the first direction.
  • Appendix 5E Further, a current value setting element connected between the drive circuit and the third terminal is provided.
  • the drive device according to Appendix 4E, wherein the current value setting element is arranged between the drive circuit and the switching element on the circuit board.
  • Appendix 6 E is
  • the drive device according to any one of Appendix 1E to 5E, wherein the capacitor is connected to the input terminal, and the power supply voltage is applied to the capacitor when the switching element is in the cutoff state.
  • Appendix 7E The drive device according to any one of Appendix 1E to 6E, wherein a land pattern is formed between the two resistors when viewed in the thickness direction of the circuit board.
  • Appendix 8 E The plurality of resistors form a group of resistors, and the plurality of resistors form a group of resistors.
  • the driving device according to any one of Supplementary note 1E to 7E, wherein the capacitor and the resistor group are arranged in the thickness direction and the second direction orthogonal to the first direction.
  • Appendix 9E Appendix 9E.
  • the circuit board includes a mounting area for mounting the laser diode.
  • the mounting region includes an anode connection for connecting the anode of the laser diode and a cathode connection for connecting the cathode of the laser diode.
  • the driving device according to Appendix 9E, wherein the anode connecting portion and the cathode connecting portion are arranged in the second direction when viewed in the thickness direction.
  • Appendix 11 E It is connected in parallel with the capacitor and further includes an additional capacitor aligned with the resistor group in the second direction.
  • the drive device according to any one of Appendix 8E to 10E, wherein a capacitor group is formed by the capacitor and the additional capacitor.
  • Appendix 12 E The driving device according to Appendix 11E, wherein the switching element is arranged on the side opposite to the side where the resistor group is located with respect to the capacitor group in the second direction, and is adjacent to the capacitor group.
  • the plurality of resistors include a first resistor and a second resistor. The first resistor is arranged on the most one side of the plurality of resistors in the first direction. The second resistor is arranged on the farthest side of the plurality of resistors in the first direction.
  • the one-sided edge of the capacitor group in the first direction overlaps the first resistor when viewed in the second direction, and the other-side edge of the first direction of the capacitor group is the first.
  • the drive device according to Appendix 11E or 12E which overlaps the second resistor when viewed in two directions.
  • Appendix 14E The plurality of electronic components further include the first resistor and a third resistor connected in parallel with the second resistor.
  • the circuit board includes an insulating layer and a first wiring layer and a second wiring layer laminated in the thickness direction and insulated from each other via the insulating layer.
  • the drive device according to any one of Appendix 8E to 14E, wherein the second wiring layer is grounded to a reference potential.
  • the circuit board includes an assembly region in which a plurality of through electrodes are arranged when viewed in the thickness direction. The plurality of through electrodes penetrate the insulating layer and conduct the first wiring layer and the second wiring layer.
  • the driving device according to Appendix 15E, wherein the gathering region is arranged on the side opposite to the side where the capacitor is located with respect to the resistor group in the second direction.
  • Appendix 17 E The circuit board is arranged on the side opposite to the first wiring layer with respect to the second wiring layer in the thickness direction, and includes a third wiring layer in which a power supply pattern is formed.
  • the drive device according to 16E.

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Abstract

Provided is a drive device (A1) for controlling the driving of a laser diode (LD). The drive device (A1) comprises: a switching element (Q1) for switching a conduction state and a cut-off state; a capacitor (C1), a first diode (D1), and an input terminal (T1) that receives a power supply voltage (VLD). The capacitor (C1) has a first end (C11) connected to the cathode of the laser diode (LD) and a second end (C12) connected to the switching element (Q1). The anode of the first diode (D1) is connected to a junction point between the first end (C11) of the capacitor (C1) and the cathode of the laser diode (LD). The input terminal (T1) is connected to a junction point between the second end (C12) of the capacitor (C1) and the switching element (Q1).

Description

駆動装置Drive device
 本開示は、駆動装置に関し、特に、レーザダイオードの駆動制御を行うレーザダイオード駆動装置に関する。また、本開示は、レーザダイオード駆動装置を備えたレーザ装置、レーザレーダ装置及び車両に関する。 The present disclosure relates to a drive device, and more particularly to a laser diode drive device that controls the drive of a laser diode. The present disclosure also relates to a laser device, a laser radar device, and a vehicle provided with a laser diode driving device.
 光学ドライブの光ピックアップ、OA機器(コピー機やプリンターなど)、光ファイバーを用いた通信機器、および、光学式測距装置などにレーザダイオードが利用されている。特許文献1には、レーザダイオードの駆動装置が開示されている。この駆動装置は、スイッチング素子およびパルス生成回路を備えている。スイッチング素子は、パルス生成回路からの駆動パルスにより、導通状態と遮断状態とが切り替わる。スイッチング素子は、レーザダイオードに接続されており、スイッチング素子が導通状態になると、レーザダイオードに順方向電流が流れ、レーザダイオードが発光する。 Laser diodes are used in optical pickups of optical drives, OA equipment (copiers, printers, etc.), communication equipment using optical fibers, and optical ranging devices. Patent Document 1 discloses a drive device for a laser diode. This drive device includes a switching element and a pulse generation circuit. The switching element switches between a conductive state and a cutoff state by a drive pulse from a pulse generation circuit. The switching element is connected to the laser diode, and when the switching element becomes conductive, a forward current flows through the laser diode and the laser diode emits light.
 特許文献2は、短パルスのレーザ光出力を可能にするレーザダイオード駆動装置を開示している。この駆動装置では、スイッチング素子をオフにしてコンデンサを充電し、その後スイッチング素子をオンにしてコンデンサを放電する。このときの放電電流によりレーザダイオードが発光する。レーザダイオードの発光が停止した後、スイッチング素子をオフにして再度コンデンサを充電する。周知のように、レーザ光のパルス幅(スイッチング素子がオンになってからコンデンサの放電電流が0になる迄の時間)は、LCR共振回路の回路定数によって決まる。同文献の開示において、LCR共振回路は、コンデンサと、レーザダイオードと、(オン状態の)スイッチング素子と、レーザダイオードに並列接続されるダイオードと、寄生のインダクタンスとを含む。 Patent Document 2 discloses a laser diode driving device that enables short pulse laser light output. In this drive, the switching element is turned off to charge the capacitor, and then the switching element is turned on to discharge the capacitor. The discharge current at this time causes the laser diode to emit light. After the laser diode stops emitting light, the switching element is turned off and the capacitor is charged again. As is well known, the pulse width of the laser beam (the time from when the switching element is turned on until the discharge current of the capacitor becomes 0) is determined by the circuit constant of the LCR resonance circuit. In the disclosure of the same document, the LCR resonant circuit includes a capacitor, a laser diode, a switching element (in the on state), a diode connected in parallel with the laser diode, and a parasitic inductance.
 特許文献3にも、レーザダイオード駆動装置(駆動回路)の一例が開示されている。同文献に記載の駆動装置は、レーザダイオードに直列に接続された抵抗器を備えている。 Patent Document 3 also discloses an example of a laser diode driving device (driving circuit). The drive device described in the document includes a resistor connected in series with a laser diode.
特開2016-161533号公報Japanese Unexamined Patent Publication No. 2016-161533 特開2016-152336号公報Japanese Unexamined Patent Publication No. 2016-152336 特開2002-16314号公報JP-A-2002-16314
 特許文献1の駆動装置においては、スイッチング素子が導通状態であるとき、レーザダイオードに電流が流れるとともに、スイッチング素子にも電流が流れる。この構成では、スイッチング素子の寄生インダクタンス成分や寄生抵抗成分によって、レーザダイオードに流れる電流量が減少する。 In the drive device of Patent Document 1, when the switching element is in a conductive state, a current flows through the laser diode and a current also flows through the switching element. In this configuration, the amount of current flowing through the laser diode is reduced by the parasitic inductance component and the parasitic resistance component of the switching element.
 特許文献2によれば、コンデンサに蓄積された電荷が無くなった時点で放電電流が0になり、レーザダイオードの発光が停止する。同文献のレーザダイオード駆動装置では、レーザ光の出力期間の短縮化が寄生インダクタンスによって制限されてしまい、レーザ光の出力期間を十分に短くすることができないおそれがある。また、同文献のレーザダイオード駆動装置では、スイッチング素子のオン時間がレーザ光の出力期間の千倍以上に設定されている。このため、上記LCR共振回路の共振が十分に減衰するまで、不要なレーザ光が断続的に出力される。 According to Patent Document 2, the discharge current becomes 0 when the electric charge accumulated in the capacitor disappears, and the light emission of the laser diode stops. In the laser diode driving device of the same document, the shortening of the output period of the laser beam is limited by the parasitic inductance, and the output period of the laser beam may not be sufficiently shortened. Further, in the laser diode driving device of the same document, the on-time of the switching element is set to 1000 times or more the output period of the laser beam. Therefore, unnecessary laser light is intermittently output until the resonance of the LCR resonance circuit is sufficiently attenuated.
 特許文献3によれば、レーザダイオードに駆動電流が流れると、これに直列接続された抵抗器にも駆動電流が流れる。このとき、抵抗器の寄生インダクタンスによって、レーザダイオードの駆動電流が低下する。特に、レーザダイオードを大電流・短パルスで駆動させるほど、寄生インダクタンスによる駆動電流の低下が顕著となる。 According to Patent Document 3, when a drive current flows through a laser diode, a drive current also flows through a resistor connected in series with the laser diode. At this time, the driving current of the laser diode decreases due to the parasitic inductance of the resistor. In particular, the more the laser diode is driven with a large current and a short pulse, the more remarkable the decrease in the drive current due to the parasitic inductance becomes.
 上記事情に鑑み、本開示の一の課題は、レーザダイオードを効率的に発光させることができるレーザダイオード駆動装置を提供することにある。 In view of the above circumstances, one object of the present disclosure is to provide a laser diode driving device capable of efficiently emitting a laser diode.
 また本開示の別の課題は、レーザ光の出力期間を短くすることができ且つ不要なレーザ光出力を抑制することができるレーザダイオード駆動装置を提供することにある。 Another object of the present disclosure is to provide a laser diode driving device capable of shortening the output period of the laser beam and suppressing unnecessary laser beam output.
 また本開示の別の課題は、上述したようなレーザダイオード駆動装置を備える種々の製品(たとえばレーザ装置、レーザレーダ装置及び車両等)を提供することにある。 Another object of the present disclosure is to provide various products (for example, a laser device, a laser radar device, a vehicle, etc.) including the laser diode driving device as described above.
 本開示の第1の側面によれば、レーザダイオードの駆動制御を行う駆動装置が提供される。当該駆動装置は、導通状態と遮断状態とが切り替わるスイッチング素子と、コンデンサと、第1ダイオードと、電源電圧が供給される入力端子と、を備えている。前記コンデンサは、第1端が前記レーザダイオードのカソードに接続され、第2端が前記スイッチング素子に接続されている。前記第1ダイオードは、アノードが、前記コンデンサの前記第1端と前記レーザダイオードのカソードとの接続点に接続されている。前記入力端子は、前記コンデンサの前記第2端と前記スイッチング素子との接続点に接続されている。 According to the first aspect of the present disclosure, a drive device for driving and controlling a laser diode is provided. The drive device includes a switching element that switches between a conduction state and a cutoff state, a capacitor, a first diode, and an input terminal to which a power supply voltage is supplied. The first end of the capacitor is connected to the cathode of the laser diode, and the second end is connected to the switching element. In the first diode, the anode is connected to the connection point between the first end of the capacitor and the cathode of the laser diode. The input terminal is connected to a connection point between the second end of the capacitor and the switching element.
 本開示の第2の側面によれば、レーザダイオードの駆動制御を行う駆動装置が提供される。当該駆動装置は、スイッチング素子と、前記スイッチング素子をオン/オフ制御する制御部と、前記レーザダイオードに対してアノード及びカソードが逆向きで並列接続される整流素子と、前記スイッチング素子がオフであるときに充電されるコンデンサであって、前記スイッチング素子がオンであるときに、前記スイッチング素子、前記レーザダイオード、及び前記整流素子とともに閉回路を形成するコンデンサと、を備える。前記制御部は、前記スイッチング素子のオン時間を前記閉回路の共振周期の半分より短くする構成とされている。 According to the second aspect of the present disclosure, a drive device that controls the drive of the laser diode is provided. The drive device has a switching element, a control unit that controls on / off of the switching element, a rectifying element in which an anode and a cathode are connected in parallel to the laser diode in opposite directions, and the switching element is off. A capacitor that is sometimes charged and that forms a closed circuit with the switching element, the laser diode, and the rectifying element when the switching element is on. The control unit is configured to make the on-time of the switching element shorter than half of the resonance period of the closed circuit.
 本開示の第3の側面によれば、レーザダイオードに駆動電流を供給する複数の電子部品と、前記複数の電子部品が搭載された回路基板と、を備える駆動装置が提供される。前記複数の電子部品は、導通状態と遮断状態とが切り替わるスイッチング素子と、互い並列に接続され且つ各々が前記レーザダイオードのアノードに直列に接続された複数の抵抗器と、前記レーザダイオードのカソードと前記スイッチング素子との間に接続されたコンデンサとを含んでいる。前記複数の抵抗器は、前記回路基板の厚さ方向に直交する第1方向に並んでいる。前記複数の抵抗器のうち前記第1方向に隣り合う2つの抵抗器は、前記第1方向における離間距離が前記複数の抵抗器のいずれかの前記第1方向の寸法以上である。 According to the third aspect of the present disclosure, there is provided a drive device including a plurality of electronic components for supplying a drive current to the laser diode and a circuit board on which the plurality of electronic components are mounted. The plurality of electronic components include a switching element that switches between a conduction state and a cutoff state, a plurality of resistors connected in parallel with each other and each connected in series with the anode of the laser diode, and a cathode of the laser diode. It includes a capacitor connected to the switching element. The plurality of resistors are arranged in a first direction orthogonal to the thickness direction of the circuit board. Of the plurality of resistors, two resistors adjacent to each other in the first direction have a separation distance in the first direction equal to or larger than the dimension of any one of the plurality of resistors in the first direction.
 本開示のさらなる特徴および利点については、添付の図面に基づく以下の詳細な説明により、さらに明らかとなろう。 Further features and advantages of this disclosure will be further clarified by the following detailed description based on the accompanying drawings.
第1の側面の実施形態に基づく駆動装置の回路構成を示す図である。It is a figure which shows the circuit structure of the drive device based on the embodiment of the 1st aspect. 駆動装置の動作例を示す図である。It is a figure which shows the operation example of a drive device. 駆動装置の動作例を示す図である。It is a figure which shows the operation example of a drive device. 駆動装置のモジュール構成を示す平面図であり、部品レイアウトおよびランドパターンを示している。It is a top view which shows the module structure of a drive device, and shows a component layout and a land pattern. 回路基板の配線層(第1層)を示す平面図である。It is a top view which shows the wiring layer (first layer) of a circuit board. 回路基板の配線層(第2層)を示す平面図である。It is a top view which shows the wiring layer (second layer) of a circuit board. 回路基板の配線層(第3層)を示す平面図である。It is a top view which shows the wiring layer (third layer) of a circuit board. 回路基板の配線層(第4層)を示す平面図である。It is a top view which shows the wiring layer (fourth layer) of a circuit board. 配線層(第1層)上に形成されたはんだ層を示す平面図である。It is a top view which shows the solder layer formed on the wiring layer (first layer). 配線層(第4層)下に形成されたはんだ層を示す平面図である。It is a top view which shows the solder layer formed under the wiring layer (fourth layer). スイッチング素子を示す平面図である。It is a top view which shows the switching element. 第1の側面に基づく変形例にかかる駆動装置のモジュール構成を示す平面図である。It is a top view which shows the module structure of the drive device which concerns on the modification based on 1st side surface. 第1の側面に基づく変形例にかかる駆動装置のモジュール構成を示す平面図である。It is a top view which shows the module structure of the drive device which concerns on the modification based on 1st side surface. 第2の側面の実施形態に基づくレーザ装置の概略構成を示す図である。It is a figure which shows the schematic structure of the laser apparatus based on the embodiment of the 2nd aspect. 共振電流及びゲート信号のタイムチャートを示す図である。It is a figure which shows the time chart of a resonance current and a gate signal. 正の共振電流が流れる経路を示す図である。It is a figure which shows the path through which a positive resonance current flows. 負の共振電流が流れる経路を示す図である。It is a figure which shows the path through which a negative resonance current flows. 制御部の一構成例を示す図である。It is a figure which shows one configuration example of a control part. 図18に示す構成例の制御部の具体例を示す図である。It is a figure which shows the specific example of the control part of the configuration example shown in FIG. 図19Aに示す制御部の各信号のタイムチャートを示す図である。It is a figure which shows the time chart of each signal of the control part shown in FIG. 19A. 図18に示す構成例の制御部の他の具体例を示す図である。It is a figure which shows the other specific example of the control part of the configuration example shown in FIG. 図18に示す構成例の制御部の更に他の具体例を示す図である。It is a figure which shows still more specific example of the control part of the configuration example shown in FIG. 図19Aに示す制御部の変形例を示す図である。It is a figure which shows the modification of the control part shown in FIG. 19A. 図19Eに示す制御部の各信号のタイムチャートを示す図である。It is a figure which shows the time chart of each signal of the control part shown in FIG. 19E. 図19Eに示す制御部の変形例を示す図である。It is a figure which shows the modification of the control part shown in FIG. 19E. シャント抵抗の構成例を示す図である。It is a figure which shows the structural example of a shunt resistor. 基板の上面図である。It is a top view of the substrate. 基板の断面を示す模式図である。It is a schematic diagram which shows the cross section of a substrate. レーザレーダ装置の概略構成を示す図である。It is a figure which shows the schematic structure of the laser radar apparatus. 車両の外観図である。It is an external view of a vehicle. 第3の側面の実施形態に基づく駆動装置の回路構成を示す図である。It is a figure which shows the circuit structure of the drive device based on the embodiment of the 3rd aspect. 駆動装置の動作例を示す図である。It is a figure which shows the operation example of a drive device. 駆動装置の動作例を示す図である。It is a figure which shows the operation example of a drive device. 駆動装置のモジュール構成を示す平面図であり、部品レイアウトおよびランドパターンを示している。It is a top view which shows the module structure of a drive device, and shows a component layout and a land pattern. 図28の一部を拡大した部分拡大図である。It is a partially enlarged view which is a part of FIG. 28 enlarged. 回路基板の配線層(第1層)を示す平面図である。It is a top view which shows the wiring layer (first layer) of a circuit board. 回路基板の配線層(第2層)を示す平面図である。It is a top view which shows the wiring layer (second layer) of a circuit board. 回路基板の配線層(第3層)を示す平面図である。It is a top view which shows the wiring layer (third layer) of a circuit board. 回路基板の配線層(第4層)を示す平面図である。It is a top view which shows the wiring layer (fourth layer) of a circuit board. スイッチング素子を示す平面図である。It is a top view which shows the switching element. シャント抵抗に印加される電圧の時間変化を示した図である。It is a figure which showed the time change of the voltage applied to a shunt resistor. 変形例にかかる駆動装置を示す平面図(レイアウト図)である。It is a top view (layout view) which shows the driving device which concerns on a modification. 図36の駆動装置の回路構成図である。It is a circuit block diagram of the drive device of FIG. 変形例にかかる駆動装置を示す平面図(レイアウト図)である。It is a top view (layout view) which shows the driving device which concerns on a modification. 図38の駆動装置の回路構成図である。It is a circuit block diagram of the drive device of FIG. 38. 変形例にかかる駆動装置を示す平面図(レイアウト図)である。It is a top view (layout view) which shows the driving device which concerns on a modification. 図40の駆動装置の回路構成図である。It is a circuit block diagram of the drive device of FIG. 40. 変形例にかかる駆動装置を示す平面図(レイアウト図)である。It is a top view (layout view) which shows the driving device which concerns on a modification. 図42の駆動装置の回路構成図である。It is a circuit block diagram of the drive device of FIG. 42.
 本開示の第1の側面に基づく実施形態について、図1~13を参照して以下に説明する。図1~13において、同一あるいは類似の構成要素については、同じ符号を付してその説明を省略する。 An embodiment based on the first aspect of the present disclosure will be described below with reference to FIGS. 1 to 13. In FIGS. 1 to 13, the same or similar components are designated by the same reference numerals and the description thereof will be omitted.
 図1~図11は、第1の側面の実施形態に基づく駆動装置A1を示している。駆動装置A1は、レーザダイオードLDの駆動(たとえばレーザ光の照射)を制御する。駆動装置A1は、レーザダイオードLDに駆動電流を供給し、駆動電流に応じた輝度で、レーザダイオードLDを発光させる。駆動装置A1に接続されるレーザダイオードLDは、TO-Canパッケージ型であってもよいし、面実装型であってもよい。 1 to 11 show the drive device A1 based on the embodiment of the first aspect. The drive device A1 controls the drive of the laser diode LD (for example, irradiation of laser light). The drive device A1 supplies a drive current to the laser diode LD, and causes the laser diode LD to emit light with a brightness corresponding to the drive current. The laser diode LD connected to the drive device A1 may be a TO-Can package type or a surface mount type.
 駆動装置A1の回路構成例について、図1を参照して、説明する。図1に示すように、駆動装置A1は、スイッチング素子Q1、複数のコンデンサC1、複数のシャント抵抗R1、帰還ダイオード(整流素子)D1、放電ダイオードD2、ドライブ回路DR、パルス生成回路PG、複数のコネクタ端子T1~T3、ソケット端子T4、接続端子T5、および、2つの電源部PS1,PS2を備えている。図1においては、レーザダイオードLDの接続を想像線(二点鎖線)で示している。 An example of the circuit configuration of the drive device A1 will be described with reference to FIG. As shown in FIG. 1, the drive device A1 includes a switching element Q1, a plurality of capacitors C1, a plurality of shunt resistors R1, a feedback diode (rectifier element) D1, a discharge diode D2, a drive circuit DR, a pulse generation circuit PG, and a plurality of shunt resistors R1. It includes connector terminals T1 to T3, socket terminals T4, connection terminals T5, and two power supply units PS1 and PS2. In FIG. 1, the connection of the laser diode LD is shown by an imaginary line (dashed line).
 スイッチング素子Q1は、たとえばMOSFET(Metal Oxide Semiconductor Field Effect Transistor:電界効果トランジスタ)である。スイッチング素子Q1は、MOSFETに限定されず、その他のトランジスタであってもよい。スイッチング素子Q1は、半導体材料から構成される。当該半導体材料は、たとえばGaN(窒化ガリウム)である。当該半導体材料は、GaNに限定されず、Si(ケイ素)、SiC(炭化ケイ素)、GaAs(ヒ化ガリウム)、あるいは、Ga23(酸化ガリウム)などであってもよい。 The switching element Q1 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The switching element Q1 is not limited to the MOSFET, and may be another transistor. The switching element Q1 is made of a semiconductor material. The semiconductor material is, for example, GaN (gallium nitride). The semiconductor material is not limited to GaN, and may be Si (silicon), SiC (silicon carbide), GaAs (gallium arsenide), Ga 2 O 3 (gallium oxide), or the like.
 スイッチング素子Q1は、図1に示すように、ドレインが各コンデンサC1に接続され、ソースが接地端GNDに接続され、ゲートがドライブ回路DRに接続されている。接地端GNDは、基準電位を与える。スイッチング素子Q1は、ドライブ回路DRからゲートに駆動信号が入力され、当該駆動信号に応じて、導通状態と遮断状態とが切り替わる。以下において、導通状態(オン状態)と遮断状態(オフ状態)とが切り替わる動作を「スイッチング動作」という場合がある。導通状態は、ドレイン-ソース間に電流が流れる状態であり、遮断状態は、ドレイン-ソース間に電流が流れない状態である。駆動信号は、たとえばオン信号とオフ信号とが交互に切り替わるパルス波である。スイッチング素子Q1は、たとえば、駆動信号がオン信号の時に導通状態となり、駆動信号がオフ信号の時に遮断状態となる。 As shown in FIG. 1, in the switching element Q1, the drain is connected to each capacitor C1, the source is connected to the ground end GND, and the gate is connected to the drive circuit DR. The ground terminal GND gives a reference potential. A drive signal is input to the gate of the switching element Q1 from the drive circuit DR, and the conduction state and the cutoff state are switched according to the drive signal. In the following, an operation of switching between a conduction state (on state) and a cutoff state (off state) may be referred to as a “switching operation”. The conductive state is a state in which a current flows between the drain and the source, and the cutoff state is a state in which no current flows between the drain and the source. The drive signal is, for example, a pulse wave in which an on signal and an off signal are alternately switched. The switching element Q1 is in a conductive state when the drive signal is an on signal, and is in a cutoff state when the drive signal is an off signal, for example.
 複数のコンデンサC1は、図1に示すように、互いに並列に接続されている。各コンデンサC1は、第1端C11がレーザダイオードLDのカソードに接続され、第2端C12がスイッチング素子Q1のドレインに接続されている。また、各コンデンサC1の第1端C11は、帰還ダイオードD1のアノードおよび放電ダイオードD2のアノードにもそれぞれ接続されている。各コンデンサC1は、電源部PS1に接続されており、電源部PS1から電源電圧VLDが印加される。 As shown in FIG. 1, a plurality of capacitors C1 are connected in parallel with each other. In each capacitor C1, the first end C11 is connected to the cathode of the laser diode LD, and the second end C12 is connected to the drain of the switching element Q1. Further, the first end C11 of each capacitor C1 is also connected to the anode of the feedback diode D1 and the anode of the discharge diode D2, respectively. Each capacitor C1 is connected to the power supply unit PS1, and the power supply voltage VLD is applied from the power supply unit PS1.
 複数のシャント抵抗R1は、図1に示すように、互いに並列に接続されている。各シャント抵抗R1は、第1端R11が帰還ダイオードD1のカソードおよびレーザダイオードLDのアノードに接続され、第2端R12が接地端GNDに接続されている。 As shown in FIG. 1, a plurality of shunt resistors R1 are connected in parallel with each other. In each shunt resistor R1, the first end R11 is connected to the cathode of the feedback diode D1 and the anode of the laser diode LD, and the second end R12 is connected to the ground end GND.
 帰還ダイオードD1は、図1に示すように、アノードがレーザダイオードLDのカソードに接続され、カソードがレーザダイオードLDのアノードに接続されている。また、帰還ダイオードD1は、アノードが各コンデンサC1の第2端C12に接続され、カソードが各シャント抵抗R1の第1端R11に接続されている。帰還ダイオードD1は、図1に示すように、アノードが各コンデンサC1の第2端C12とレーザダイオードLDのカソードとの接続点に接続されている。図1に示す例においては、帰還ダイオードD1は、ショットキーバリアダイオードである。 As shown in FIG. 1, the feedback diode D1 has an anode connected to the cathode of the laser diode LD and a cathode connected to the anode of the laser diode LD. Further, in the feedback diode D1, the anode is connected to the second end C12 of each capacitor C1, and the cathode is connected to the first end R11 of each shunt resistor R1. As shown in FIG. 1, the feedback diode D1 has an anode connected to a connection point between the second end C12 of each capacitor C1 and the cathode of the laser diode LD. In the example shown in FIG. 1, the feedback diode D1 is a Schottky barrier diode.
 放電ダイオードD2は、図1に示すように、アノードがコンデンサC1の第2端C12に接続され、カソードが抵抗器を介して接地端GNDに接続されている。図1に示す例においては、放電ダイオードD2は、ショットキーバリアダイオードである。 As shown in FIG. 1, the discharge diode D2 has an anode connected to the second end C12 of the capacitor C1 and a cathode connected to the ground end GND via a resistor. In the example shown in FIG. 1, the discharge diode D2 is a Schottky barrier diode.
 パルス生成回路PGは、スイッチング素子Q1のスイッチング動作を制御するためのパルス信号を生成する。パルス生成回路PGは、コネクタ端子T1から制御信号が入力され、当該制御信号に基づき、パルス信号を生成する。パルス生成回路PGは、生成したパルス信号をドライブ回路DRに出力する。本実施形態におけるパルス信号は、たとえば、周波数が20kHz(周期が50000nsec)、オン時間は50nsecである矩形波である。このパルス信号のデューティ比は0.1%である。 The pulse generation circuit PG generates a pulse signal for controlling the switching operation of the switching element Q1. The pulse generation circuit PG receives a control signal from the connector terminal T1 and generates a pulse signal based on the control signal. The pulse generation circuit PG outputs the generated pulse signal to the drive circuit DR. The pulse signal in the present embodiment is, for example, a square wave having a frequency of 20 kHz (period of 50,000 nsec) and an on-time of 50 nsec. The duty ratio of this pulse signal is 0.1%.
 ドライブ回路DRは、スイッチング素子Q1を駆動させる(スイッチング動作させる)ための駆動信号を生成する。ドライブ回路DRは、パルス生成回路PGからパルス信号が入力され、当該パルス信号に基づき、駆動信号を生成する。駆動信号は、たとえば、パルス信号をスイッチング素子Q1の駆動に必要な電圧まで昇圧した信号である。ドライブ回路DRは、ドライブIC9を含んでおり、駆動信号はこのドライブIC9により生成される。ドライブ回路DRは、生成した駆動信号を、ゲート抵抗R2を介して、スイッチング素子Q1のゲートに出力する。ゲート抵抗R2は、場合によっては設けなくてもよい。 The drive circuit DR generates a drive signal for driving (switching operation) the switching element Q1. In the drive circuit DR, a pulse signal is input from the pulse generation circuit PG, and a drive signal is generated based on the pulse signal. The drive signal is, for example, a signal obtained by boosting the pulse signal to a voltage required for driving the switching element Q1. The drive circuit DR includes a drive IC 9, and a drive signal is generated by the drive IC 9. The drive circuit DR outputs the generated drive signal to the gate of the switching element Q1 via the gate resistor R2. The gate resistor R2 may not be provided in some cases.
 コネクタ端子T1は、電源電圧VLDの入力端子である。コネクタ端子T1には、駆動装置A1の外部に設けられた直流電源(外部電源)が接続され、この外部電源から電源電圧VLDが供給される。電源電圧VLDは、レーザダイオードLDの駆動に利用され、たとえば3V以上かつ100V以下である。コネクタ端子T1は、制御信号の入力端子でもある。コネクタ端子T1は、たとえばプラグ型の端子である。 The connector terminal T1 is an input terminal for the power supply voltage VLD. A DC power supply (external power supply) provided outside the drive device A1 is connected to the connector terminal T1, and a power supply voltage VLD is supplied from this external power supply. The power supply voltage VLD is used for driving the laser diode LD, and is, for example, 3 V or more and 100 V or less. The connector terminal T1 is also an input terminal for a control signal. The connector terminal T1 is, for example, a plug-type terminal.
 各コネクタ端子T2,T3は、たとえば同軸ケーブルが接続されうるジャック型の端子である。 Each connector terminal T2 and T3 is a jack type terminal to which a coaxial cable can be connected, for example.
 ソケット端子T4は、TO-Canパッケージ型のレーザダイオードを接続するための端子である。レーザダイオードLDがTO-Canパッケージ型の場合、ソケット端子T4にレーザダイオードLDが接続される。 The socket terminal T4 is a terminal for connecting a TO-Can package type laser diode. When the laser diode LD is a TO-Can package type, the laser diode LD is connected to the socket terminal T4.
 接続端子T5は、面実装型のレーザダイオードを接続するための端子である。レーザダイオードLDが面実装型の場合、接続端子T5にレーザダイオードLDが接続される。 The connection terminal T5 is a terminal for connecting a surface-mounted laser diode. When the laser diode LD is a surface mount type, the laser diode LD is connected to the connection terminal T5.
 電源部PS1は、図1に示すように、コネクタ端子T1と複数のコンデンサC1との間に接続される。電源部PS1は、電解コンデンサC2、逆流防止ダイオードD3、リアクトルL1、充電抵抗R3などを含んでいる。電解コンデンサC2は、バイパスコンデンサであって、入力される電圧(電源電圧VLD)を安定させる。逆流防止ダイオードD3は、各コンデンサC1側から外部電源(コネクタ端子T1)側に電流が流れることを防止する。リアクトルL1は、入力される電圧を昇圧する。充電抵抗R3は、外部電源(コネクタ端子T1)側から各コンデンサC1に向かう電流の電流量を調整する。 As shown in FIG. 1, the power supply unit PS1 is connected between the connector terminal T1 and the plurality of capacitors C1. The power supply unit PS1 includes an electrolytic capacitor C2, a backflow prevention diode D3, a reactor L1, a charging resistor R3, and the like. The electrolytic capacitor C2 is a bypass capacitor and stabilizes the input voltage (power supply voltage VLD). The backflow prevention diode D3 prevents current from flowing from each capacitor C1 side to the external power supply (connector terminal T1) side. The reactor L1 boosts the input voltage. The charging resistor R3 adjusts the amount of current of the current from the external power supply (connector terminal T1) side toward each capacitor C1.
 電源部PS2は、動作電圧V1を発生させる。動作電圧V1は、主に、パルス生成回路PGを構成する各電子部品の駆動に利用される。動作電圧V1は、たとえば3.3Vであるが、これに限定されない。 The power supply unit PS2 generates an operating voltage V1. The operating voltage V1 is mainly used for driving each electronic component constituting the pulse generation circuit PG. The operating voltage V1 is, for example, 3.3 V, but is not limited thereto.
 駆動装置A1は、図1に示すように、2つのテストポイントTP1,TP2を備えている。各テストポイントTP1,TP2は、信号検出用の端子である。 As shown in FIG. 1, the drive device A1 includes two test points TP1 and TP2. Each test point TP1 and TP2 is a terminal for signal detection.
 駆動装置A1によるレーザダイオードLDの駆動制御(発光動作)について、図2および図3を参照して、説明する。図2および図3は、図1に示す駆動装置A1の回路構成から、レーザダイオードLDの発光動作における主要な電子部品を抜粋した図である。図2および図3においては、複数のコンデンサC1および複数のシャント抵抗R1をそれぞれ1つずつ示している。図2および図3に示す直流電源は、図1に示すコネクタ端子T1に接続された外部電源と、電源部PS1とに相当する。図2は、スイッチング素子Q1が遮断状態であるときを示しており、図3は、スイッチング素子Q1が導通状態であるときを示している。 The drive control (light emission operation) of the laser diode LD by the drive device A1 will be described with reference to FIGS. 2 and 3. 2 and 3 are diagrams in which the main electronic components in the light emitting operation of the laser diode LD are extracted from the circuit configuration of the drive device A1 shown in FIG. In FIGS. 2 and 3, a plurality of capacitors C1 and a plurality of shunt resistors R1 are shown one by one. The DC power supply shown in FIGS. 2 and 3 corresponds to the external power supply connected to the connector terminal T1 shown in FIG. 1 and the power supply unit PS1. FIG. 2 shows the case where the switching element Q1 is in the cutoff state, and FIG. 3 shows the case where the switching element Q1 is in the conductive state.
 スイッチング素子Q1を遮断状態にすると、図2に示すように、直流電源から各コンデンサC1に電流が流れる(破線で示す電流経路参照)。この電流により、各コンデンサC1の第2端C12に電荷がたまり、各コンデンサC1が充電される。このとき、直流電源の電源電圧がVLDとすると、各コンデンサC1の第2端C12の電位は、電源電圧VLDとなる。各コンデンサC1が満充電になると、この電流は流れなくなる。スイッチング素子Q1が遮断状態のとき、レーザダイオードLDには電圧が印加されず、レーザダイオードLDは発光しない。 When the switching element Q1 is cut off, a current flows from the DC power supply to each capacitor C1 as shown in FIG. 2 (see the current path shown by the broken line). Due to this current, electric charge is accumulated in the second end C12 of each capacitor C1 and each capacitor C1 is charged. At this time, assuming that the power supply voltage of the DC power supply is VLD, the potential of the second end C12 of each capacitor C1 is the power supply voltage VLD. When each capacitor C1 is fully charged, this current stops flowing. When the switching element Q1 is in the cutoff state, no voltage is applied to the laser diode LD and the laser diode LD does not emit light.
 スイッチング素子Q1を導通状態にすると、図3に示すように、スイッチング素子Q1を介して、各コンデンサC1の第2端C12が接地端GNDに導通する。これにより、当該第2端C12が基準電位に接地され、各コンデンサC1の第2端C12の電位が基準電位に変動する(低下する)。このとき、各コンデンサC1の第1端C11と第2端C12との電位差は一定であるため、各コンデンサC1の第1端C11の電位も、第2端C12の電位変動分、変動する(低下する)。つまり、図3に示すようにコンデンサC1の第1端C11の電位は基準電位(GND)となり、第2端C12の電位は、基準電位と電源電圧VLDとの差(GND-VLD)となる。これにより、レーザダイオードLDのアノード側がカソード側よりも高電位となり、レーザダイオードLDに順方向電流が流れ、レーザダイオードLDが発光する。本実施形態においては、図3に示すように、シャント抵抗R1からレーザダイオードLD、放電ダイオードD2を通る電流経路と 、レーザダイオードLDと帰還ダイオードD1とを通る電流経路とが生じる(破線で示す各電流経路参照)。 When the switching element Q1 is brought into a conductive state, as shown in FIG. 3, the second end C12 of each capacitor C1 conducts to the ground end GND via the switching element Q1. As a result, the second end C12 is grounded to the reference potential, and the potential of the second end C12 of each capacitor C1 fluctuates (decreases) to the reference potential. At this time, since the potential difference between the first end C11 and the second end C12 of each capacitor C1 is constant, the potential of the first end C11 of each capacitor C1 also fluctuates (decreases) by the potential fluctuation of the second end C12. To do). That is, as shown in FIG. 3, the potential of the first end C11 of the capacitor C1 becomes the reference potential (GND), and the potential of the second end C12 becomes the difference (GND-VLD) between the reference potential and the power supply voltage VLD. As a result, the anode side of the laser diode LD has a higher potential than the cathode side, a forward current flows through the laser diode LD, and the laser diode LD emits light. In the present embodiment, as shown in FIG. 3, a current path passing through the laser diode LD and the discharge diode D2 and a current path passing through the laser diode LD and the feedback diode D1 are generated from the shunt resistor R1 (each shown by a broken line). See current path).
 駆動装置A1のモジュール構成例について、図4~図11を参照して説明する。便宜上、互いに直交する3つの方向(x方向、y方向およびz方向)を適宜参照する。z方向は、駆動装置A1(または回路基板10)の厚さ方向に対応する。 An example of the module configuration of the drive device A1 will be described with reference to FIGS. 4 to 11. For convenience, the three directions orthogonal to each other (x direction, y direction and z direction) are appropriately referred to. The z direction corresponds to the thickness direction of the drive device A1 (or the circuit board 10).
 駆動装置A1は、回路基板10と、複数の電子部品とを備えている。当該複数の電子部品は、図1に示す回路構成における複数の電子部品に対応しており、回路基板10に実装されている。 The drive device A1 includes a circuit board 10 and a plurality of electronic components. The plurality of electronic components correspond to the plurality of electronic components in the circuit configuration shown in FIG. 1, and are mounted on the circuit board 10.
 図4は、回路基板10上の部品レイアウトおよびランドパターンを示している。図4においては、複数の電子部品を想像線(二点鎖線)で示している。 FIG. 4 shows the component layout and land pattern on the circuit board 10. In FIG. 4, a plurality of electronic components are shown by imaginary lines (dashed-dotted lines).
 回路基板10は、図4に示すように、平面視において、略矩形状である。回路基板10は、たとえば、x方向の寸法が70.0mmであり、y方向の寸法が45.0mmである。回路基板10の平面視寸法は、これに限定されず、適宜変更されうる。 As shown in FIG. 4, the circuit board 10 has a substantially rectangular shape in a plan view. The circuit board 10 has, for example, a dimension of 70.0 mm in the x direction and a dimension of 45.0 mm in the y direction. The plan view dimensions of the circuit board 10 are not limited to this, and can be changed as appropriate.
 回路基板10は、たとえば積層基板であり、互いに積層された複数の配線層Ly1~Ly4を含んでいる。配線層Ly1~Ly4は、絶縁層を介して互いに離間している。図5~図8はそれぞれ、各配線層Ly1~Ly4を示す平面図である。図5~図8に示すように、各配線層Ly1~Ly4には、配線パターン20(黒色で塗りつぶされた部分)が配置されている。 The circuit board 10 is, for example, a laminated board, and includes a plurality of wiring layers Ly1 to Ly4 that are laminated to each other. The wiring layers Ly1 to Ly4 are separated from each other via an insulating layer. 5 to 8 are plan views showing each wiring layer Ly1 to Ly4, respectively. As shown in FIGS. 5 to 8, wiring patterns 20 (parts painted in black) are arranged in the wiring layers Ly1 to Ly4.
 配線層Ly1は、回路基板10における第1層(最上層)である。配線層Ly1上に、各電子部品が搭載される。配線層Ly1の上面には、図9に示すはんだ層21が形成されている。図9において、はんだ210が形成される領域を黒色で塗りつぶしている。はんだ層21は、部分的にレジスト膜(図示略)で覆われている。このレジスト膜から露出したはんだ210が、図4に示すランドパターンに相当する。配線層Ly4は、回路基板10における第4層(最下層)である。配線層Ly4の下面には、図10に示すはんだ層22が形成されている。図10において、はんだ220が形成される領域を黒色で塗りつぶしている。はんだ層22は、部分的にレジスト膜(図示略)で覆われている。各配線層Ly2,Ly3は、回路基板10における中間層である。配線層Ly2は、回路基板10における第2層であり、z方向において、配線層Ly1と配線層Ly3とに挟まれている。配線層Ly3は、回路基板10における第3層であり、z方向において、配線層Ly2と配線層Ly4とに挟まれている。各配線層Ly2,Ly3は、図6および図7に示すように、平面視において、基準電位に接地された配線パターン20が外周縁に沿って形成されている。複数の配線層Ly1~Ly4は、上記絶縁層を貫通する貫通ビアによって互いに導通する。 The wiring layer Ly1 is the first layer (top layer) of the circuit board 10. Each electronic component is mounted on the wiring layer Ly1. The solder layer 21 shown in FIG. 9 is formed on the upper surface of the wiring layer Ly1. In FIG. 9, the region where the solder 210 is formed is painted in black. The solder layer 21 is partially covered with a resist film (not shown). The solder 210 exposed from the resist film corresponds to the land pattern shown in FIG. The wiring layer Ly4 is a fourth layer (bottom layer) in the circuit board 10. The solder layer 22 shown in FIG. 10 is formed on the lower surface of the wiring layer Ly4. In FIG. 10, the region where the solder 220 is formed is painted in black. The solder layer 22 is partially covered with a resist film (not shown). The wiring layers Ly2 and Ly3 are intermediate layers in the circuit board 10. The wiring layer Ly2 is a second layer in the circuit board 10, and is sandwiched between the wiring layer Ly1 and the wiring layer Ly3 in the z direction. The wiring layer Ly3 is a third layer in the circuit board 10, and is sandwiched between the wiring layer Ly2 and the wiring layer Ly4 in the z direction. As shown in FIGS. 6 and 7, each wiring layer Ly2 and Ly3 has a wiring pattern 20 grounded at a reference potential formed along the outer peripheral edge in a plan view. The plurality of wiring layers Ly1 to Ly4 are electrically connected to each other by the penetrating vias penetrating the insulating layer.
 回路基板10には、図4~図10に示すように、その四隅にそれぞれ貫通孔HLが形成されている。各貫通孔HLは、回路基板10をz方向に貫通している。各貫通孔HLは、駆動装置A1を支持部材に固定するために設けられており、ボルトなどの締結具などが挿通されうる。平面視において、各貫通孔HLの周囲は、各配線層Ly1~Ly4にそれぞれ、基準電位に接地された配線パターン20が配置されており、接地端GNDとして利用される。各貫通孔HLは、平面視における中央が、回路基板10の四隅のそれぞれから、 たとえばx方向に3.5mm、y方向に3.5mmの位置にそれぞれ重なるように配置されている。 As shown in FIGS. 4 to 10, the circuit board 10 is formed with through holes HL at its four corners, respectively. Each through hole HL penetrates the circuit board 10 in the z direction. Each through hole HL is provided to fix the drive device A1 to the support member, and a fastener such as a bolt can be inserted therethrough. In a plan view, wiring patterns 20 grounded at a reference potential are arranged in each of the wiring layers Ly1 to Ly4 around each through hole HL, and are used as a grounding end GND. Each through hole HL is arranged so that the center in a plan view overlaps with each of the four corners of the circuit board 10 at positions of, for example, 3.5 mm in the x direction and 3.5 mm in the y direction.
 回路基板10に実装された各電子部品について、図4に基づいて説明する。 Each electronic component mounted on the circuit board 10 will be described with reference to FIG.
 図4から理解されるように、複数のコンデンサC1は、x方向に並んで(図示の例では所定の間隔を以ってx方向に互いに隣接して)配置されて、コンデンサ群C0を形成している。すなわち、複数のコンデンサC1は、互いに十分短い離間距離を以って隣接しており、他の要素(たとえば機能性素子)が複数のコンデンサC1の間に配置されないよう構成されている。同図に示すように、各コンデンサC1の2つの端子(C11およびC12)は、y方向に並ぶように配置されている。各コンデンサC1は、たとえばチップタイプであるが、リードタイプであってもよい。 As can be seen from FIG. 4, a plurality of capacitors C1 are arranged side by side in the x direction (adjacent to each other in the x direction at predetermined intervals in the illustrated example) to form the capacitor group C0. ing. That is, the plurality of capacitors C1 are adjacent to each other with a sufficiently short separation distance, and other elements (for example, functional elements) are configured not to be arranged between the plurality of capacitors C1. As shown in the figure, the two terminals (C11 and C12) of each capacitor C1 are arranged so as to be arranged in the y direction. Each capacitor C1 is, for example, a chip type, but may be a lead type.
 複数のシャント抵抗R1は、図4に示すように、x方向に並んで配置されており、シャント抵抗群R0を形成する。各シャント抵抗R1は、2つの端子(第1端R11および第2端R12)がy方向に並んでいる。各シャント抵抗R1は、たとえばチップタイプであるが、リードタイプであってもよい。 As shown in FIG. 4, a plurality of shunt resistors R1 are arranged side by side in the x direction to form a shunt resistor group R0. In each shunt resistor R1, two terminals (first end R11 and second end R12) are arranged in the y direction. Each shunt resistor R1 is, for example, a chip type, but may be a lead type.
 コンデンサ群C0とシャント抵抗群R0とは、図4に示すように、y方向に並んでいる。y方向において、コンデンサ群C0とシャント抵抗群R0との間には、ソケット端子T4および帰還ダイオードD1が配置されている。ソケット端子T4と帰還ダイオードD1とは、y方向に隣接している。 The capacitor group C0 and the shunt resistor group R0 are aligned in the y direction as shown in FIG. In the y direction, a socket terminal T4 and a feedback diode D1 are arranged between the capacitor group C0 and the shunt resistor group R0. The socket terminal T4 and the feedback diode D1 are adjacent to each other in the y direction.
 スイッチング素子Q1は、図4に示すように、y方向において、コンデンサ群C0と並んでいる。図4に示す例においては、スイッチング素子Q1は、y方向において、コンデンサ群C0に隣接している。スイッチング素子Q1は、y方向において、コンデンサ群C0を基準に、シャント抵抗群R0とは反対側に位置する。 As shown in FIG. 4, the switching element Q1 is aligned with the capacitor group C0 in the y direction. In the example shown in FIG. 4, the switching element Q1 is adjacent to the capacitor group C0 in the y direction. The switching element Q1 is located on the side opposite to the shunt resistance group R0 with respect to the capacitor group C0 in the y direction.
 ドライブIC9とスイッチング素子Q1とは、図4に示すように、y方向に隣り合っている。スイッチング素子Q1は、図11に示すように、z方向下面に複数の電極Q11,Q12,Q13が形成されている。複数の電極Q11は、スイッチング素子Q1におけるゲート端子である。複数の電極Q12は、スイッチング素子Q1におけるドレイン端子である。複数の電極Q13は、スイッチング素子Q1におけるソース端子である。本実施形態においては、スイッチング素子Q1は、複数の電極Q11(ゲート端子)が、y方向においてドライブIC9の近くに配置されるように、回路基板10上に実装されている。各電極Q11,Q12,Q13の配置は、図11に示す例に限定されない。 As shown in FIG. 4, the drive IC 9 and the switching element Q1 are adjacent to each other in the y direction. As shown in FIG. 11, the switching element Q1 has a plurality of electrodes Q11, Q12, and Q13 formed on the lower surface in the z direction. The plurality of electrodes Q11 are gate terminals in the switching element Q1. The plurality of electrodes Q12 are drain terminals in the switching element Q1. The plurality of electrodes Q13 are source terminals in the switching element Q1. In the present embodiment, the switching element Q1 is mounted on the circuit board 10 so that a plurality of electrodes Q11 (gate terminals) are arranged near the drive IC 9 in the y direction. The arrangement of the electrodes Q11, Q12, and Q13 is not limited to the example shown in FIG.
 ドライブ回路DRを構成する各電子部品(図1参照)は、図4に示すように、y方向において、コンデンサ群C0に並んでおり、コンデンサ群C0を基準に、シャント抵抗群R0とは反対側に位置する。ドライブ回路DRを構成する各電子部品とスイッチング素子Q1とは、電磁シールド28によって覆われている。図4に示すランドパターンには、電磁シールド28が接合されるパターン29が示されている。電磁シールド28は、ドライブ回路DRを構成する各電子部品やスイッチング素子Q1にノイズが重畳されることを抑制する。これにより、ドライブ回路DRを構成する各電子部品(たとえばドライブIC9)やスイッチング素子Q1がノイズによって誤動作することを抑制している。 As shown in FIG. 4, each electronic component (see FIG. 1) constituting the drive circuit DR is arranged in the capacitor group C0 in the y direction, and is on the opposite side of the shunt resistor group R0 with reference to the capacitor group C0. Located in. Each electronic component constituting the drive circuit DR and the switching element Q1 are covered with an electromagnetic shield 28. The land pattern shown in FIG. 4 shows a pattern 29 to which the electromagnetic shield 28 is joined. The electromagnetic shield 28 suppresses noise from being superimposed on each electronic component or switching element Q1 constituting the drive circuit DR. As a result, it is possible to prevent each electronic component (for example, drive IC9) and the switching element Q1 constituting the drive circuit DR from malfunctioning due to noise.
 図4に示すように、スイッチング素子Q1、ドライブ回路DR、コンデンサ群C0(複数のコンデンサC1)、シャント抵抗群R0(複数のシャント抵抗R1)、帰還ダイオードD1、放電ダイオードD2、ソケット端子T4、および、接続端子T5は、x方向において、回路基板10の中央よりも一方側に配置されている。 As shown in FIG. 4, switching element Q1, drive circuit DR, capacitor group C0 (plurality of capacitors C1), shunt resistance group R0 (plurality of shunt resistors R1), feedback diode D1, discharge diode D2, socket terminal T4, and , The connection terminal T5 is arranged on one side of the center of the circuit board 10 in the x direction.
 接続端子T5は、図4に示すように、平面視において、回路基板10の端縁に沿って配置されている。接続端子T5は、図4に示すように、ベタパターンである。図4において、接続端子T5は、y方向における上方に、レーザダイオードのカソードが接続され、y方向における下方に、レーザダイオードのアノードが接続される。接続端子T5においては、TO-Canパッケージ型のレーザダイオードLDを接続することも可能である。たとえば、TO-Canパッケージ型のレーザダイオードにおいて、アノードおよびカソードの各ピン端子を、はんだなどによって、直接接続端子T5にそれぞれ接合することで、接続端子T5にTO-Canパッケージ型のレーザダイオードを接続できる。 As shown in FIG. 4, the connection terminal T5 is arranged along the edge of the circuit board 10 in a plan view. As shown in FIG. 4, the connection terminal T5 has a solid pattern. In FIG. 4, the connection terminal T5 has the cathode of the laser diode connected to the upper side in the y direction and the anode of the laser diode connected to the lower side in the y direction. It is also possible to connect a TO-Can package type laser diode LD to the connection terminal T5. For example, in a TO-Can package type laser diode, the TO-Can package type laser diode is connected to the connection terminal T5 by joining the anode and cathode pin terminals to the direct connection terminal T5 with solder or the like. it can.
 放電ダイオードD2は、図4に示すように、ドライブ回路DRやスイッチング素子Q1のx方向の隣に配置され、平面視において、回路基板10の端縁に沿って配置されている。放電ダイオードD2と接続端子T5とは、y方向に並んでいる。放電ダイオードD2は、y方向において、コンデンサ群C0と接地端GND(右上の貫通孔HL)との間に配置されている。 As shown in FIG. 4, the discharge diode D2 is arranged next to the drive circuit DR and the switching element Q1 in the x direction, and is arranged along the edge of the circuit board 10 in a plan view. The discharge diode D2 and the connection terminal T5 are aligned in the y direction. The discharge diode D2 is arranged between the capacitor group C0 and the grounding end GND (through hole HL on the upper right) in the y direction.
 駆動装置A1の作用・効果は、以下の通りである。 The actions and effects of the drive device A1 are as follows.
 駆動装置A1は、スイッチング素子Q1およびコンデンサC1を備えている。コンデンサC1は、第1端C11がレーザダイオードLDのカソードに接続され、第2端C12がスイッチング素子Q1に接続されている。電源電圧VLDが入力されるコネクタ端子T1は、コンデンサC1の第2端C12と、スイッチング素子Q1との接続点に接続されており、これにより、電源電圧VLDは、コンデンサC1の第2端C12とスイッチング素子Q1との接続点に印加される。この構成によると、スイッチング素子Q1のスイッチング動作によって、コンデンサC1の電荷を変動させ、この電荷変動によって、レーザダイオードLDに順方向電流が流れる(レーザダイオードLDが発光する)。このとき、図2および図3に示すように、レーザダイオードLDに流れる電流経路上に、スイッチング素子Q1がないため、スイッチング素子Q1に流れる電流を抑制できる。したがって、駆動装置A1は、スイッチング素子Q1の寄生インダクタンス成分や寄生抵抗成分によりレーザダイオードLDに流れる電流量が低下することを抑制できる。つまり、駆動装置A1は、レーザダイオードLDを効率的に発光させることができる。 The drive device A1 includes a switching element Q1 and a capacitor C1. In the capacitor C1, the first end C11 is connected to the cathode of the laser diode LD, and the second end C12 is connected to the switching element Q1. The connector terminal T1 to which the power supply voltage VLD is input is connected to the connection point between the second end C12 of the capacitor C1 and the switching element Q1, whereby the power supply voltage VLD is connected to the second end C12 of the capacitor C1. It is applied to the connection point with the switching element Q1. According to this configuration, the charge of the capacitor C1 is fluctuated by the switching operation of the switching element Q1, and the forward current flows through the laser diode LD (the laser diode LD emits light) due to this charge fluctuation. At this time, as shown in FIGS. 2 and 3, since the switching element Q1 is not on the current path flowing through the laser diode LD, the current flowing through the switching element Q1 can be suppressed. Therefore, the drive device A1 can suppress a decrease in the amount of current flowing through the laser diode LD due to the parasitic inductance component and the parasitic resistance component of the switching element Q1. That is, the drive device A1 can efficiently make the laser diode LD emit light.
 駆動装置A1では、直流電源と、レーザダイオードLDとの間に各コンデンサC1が接続されている(図1~図3参照)。この構成によると、直流電源からの電源電圧VLDが、直接レーザダイオードLDに印加されない。したがって、レーザダイオードLDにかかる負荷が低減され、レーザダイオードLDの故障が抑制される。 In the drive device A1, each capacitor C1 is connected between the DC power supply and the laser diode LD (see FIGS. 1 to 3). According to this configuration, the power supply voltage VLD from the DC power supply is not directly applied to the laser diode LD. Therefore, the load applied to the laser diode LD is reduced, and the failure of the laser diode LD is suppressed.
 駆動装置A1は、コンデンサ群C0とシャント抵抗群R0とはy方向に並んでおり、これらの間にレーザダイオードLDが接続されるソケット端子T4および接続端子T5を含んでいる(図4参照)。また、放電ダイオードD2が、接地端GND(図4の右上の貫通孔HL)と、ソケット端子T4あるいは接続端子T5との間に配置されている。この構成によると、駆動装置A1において、シャント抵抗R1から、レーザダイオードLDおよび放電ダイオードD2を介して、接地端GNDに流れる電流経路(図3参照)を短くすることができる。これにより、駆動装置A1内部の寄生インダクタンス成分や寄生抵抗成分が低減される。 In the drive device A1, the capacitor group C0 and the shunt resistor group R0 are aligned in the y direction, and include a socket terminal T4 and a connection terminal T5 to which the laser diode LD is connected between them (see FIG. 4). Further, the discharge diode D2 is arranged between the grounding end GND (through hole HL in the upper right of FIG. 4) and the socket terminal T4 or the connection terminal T5. According to this configuration, in the drive device A1, the current path (see FIG. 3) flowing from the shunt resistor R1 to the grounding end GND via the laser diode LD and the discharge diode D2 can be shortened. As a result, the parasitic inductance component and the parasitic resistance component inside the drive device A1 are reduced.
 駆動装置A1は、ソケット端子T4の直近に帰還ダイオードD1が配置されている(図4参照)。この構成によると、各コンデンサC1のキャパシタンス成分と、帰還ダイオードD1や配線などの寄生インダクタンス成分とによる共振現象を抑制できる。また、レーザダイオードLDと帰還ダイオードD1とを循環するループ経路(図3参照)を短くできるので、このループ経路における寄生インダクタンス成分や寄生抵抗成分とが抑制される。駆動装置A1において、帰還ダイオードD1が、ソケット端子T4と接続端子T5との間に配置されていてもよい。この場合、レーザダイオードLDが、ソケット端子T4および接続端子T5のいずれに接続された場合であっても、上記共振現象を抑制できる。 In the drive device A1, the feedback diode D1 is arranged in the immediate vicinity of the socket terminal T4 (see FIG. 4). According to this configuration, the resonance phenomenon due to the capacitance component of each capacitor C1 and the parasitic inductance component such as the feedback diode D1 and the wiring can be suppressed. Further, since the loop path (see FIG. 3) circulating between the laser diode LD and the feedback diode D1 can be shortened, the parasitic inductance component and the parasitic resistance component in this loop path are suppressed. In the drive device A1, the feedback diode D1 may be arranged between the socket terminal T4 and the connection terminal T5. In this case, the resonance phenomenon can be suppressed regardless of whether the laser diode LD is connected to the socket terminal T4 or the connection terminal T5.
 駆動装置A1は、互いに並列に接続された複数のコンデンサC1を備えている。この構成によると、駆動装置A1内部の寄生インダクタンス成分を減少させることができる。これにより、駆動装置A1内部の寄生インダクタンス成分による電流量の減少と、レーザダイオードLDに入力されるパルス幅の増加とを抑制できる。また、駆動装置A1は、互いに並列に接続された複数のシャント抵抗R1を備えている。この構成によると、複数のコンデンサC1と同様に、駆動装置A1内部の寄生インダクタンス成分を減少させることができる。 The drive device A1 includes a plurality of capacitors C1 connected in parallel to each other. According to this configuration, the parasitic inductance component inside the drive device A1 can be reduced. As a result, it is possible to suppress a decrease in the amount of current due to the parasitic inductance component inside the drive device A1 and an increase in the pulse width input to the laser diode LD. Further, the drive device A1 includes a plurality of shunt resistors R1 connected in parallel with each other. According to this configuration, the parasitic inductance component inside the drive device A1 can be reduced as in the case of the plurality of capacitors C1.
 本実施形態では、駆動装置A1は、ソケット端子T4と接続端子T5との両方を備えた場合を示したが、いずれか一方のみを備えた構成であってもよい。たとえば、ソケット端子T4を備え、接続端子T5を備えない場合、図12に示すように構成されうる。一方、ソケット端子T4を備えず、接続端子T5を備えた場合、図13に示すように構成されうる。図13に示す構成においては、コンデンサ群C0とシャント抵抗群R0とがy方向に隣接し、帰還ダイオードD1と接続端子T5とがx方向に隣接している。 In the present embodiment, the drive device A1 is provided with both the socket terminal T4 and the connection terminal T5, but may be configured to include only one of them. For example, when the socket terminal T4 is provided and the connection terminal T5 is not provided, it can be configured as shown in FIG. On the other hand, when the socket terminal T4 is not provided and the connection terminal T5 is provided, it can be configured as shown in FIG. In the configuration shown in FIG. 13, the capacitor group C0 and the shunt resistor group R0 are adjacent to each other in the y direction, and the feedback diode D1 and the connection terminal T5 are adjacent to each other in the x direction.
 本実施形態では、駆動装置A1は、放電ダイオードD2(および放電ダイオードD2と接地端GNDとの間の抵抗器)を備えた場合を示したが、これを備えていなくてもよい。ただし、放電ダイオードD2を設けた場合、これを設けない場合よりも、レーザダイオードLDの順方向電流の向上、および、レーザダイオードLDの電流-電圧特性の測定安定化の向上を図ることができる。 In the present embodiment, the drive device A1 is provided with the discharge diode D2 (and the resistor between the discharge diode D2 and the grounding end GND), but it may not be provided. However, when the discharge diode D2 is provided, the forward current of the laser diode LD can be improved and the measurement stabilization of the current-voltage characteristic of the laser diode LD can be improved as compared with the case where the discharge diode D2 is provided.
 第1の側面に基づく駆動装置は、上記した実施形態に限定されるものではない。駆動装置の各部の具体的な構成は、種々に設計変更自在である。 The drive device based on the first aspect is not limited to the above-described embodiment. The specific configuration of each part of the drive device can be freely redesigned.
 第1の側面に基づき提供される構成は、以下の付記1A~20Aに記載された実施形態を含む。
 付記1A.レーザダイオードの駆動制御を行う駆動装置であって、
 導通状態と遮断状態とが切り替わるスイッチング素子と、
 コンデンサと、
 第1ダイオードと、
 電源電圧が供給される入力端子と、
を備えており、
 前記コンデンサは、第1端が前記レーザダイオードのカソードに接続され、第2端が前記スイッチング素子に接続されており、
 前記第1ダイオードは、アノードが、前記コンデンサの前記第1端と前記レーザダイオードのカソードとの接続点に接続されており、
 前記入力端子は、前記コンデンサの前記第2端と前記スイッチング素子との接続点に接続されている、駆動装置。
 付記2A.第1端が前記レーザダイオードのアノードに接続された抵抗器をさらに備える、付記1Aに記載の駆動装置。
 付記3A.前記抵抗器は、第2端が基準電位に接地されている、付記2Aに記載の駆動装置。
 付記4A.アノードが前記コンデンサの前記第1端に接続された第2ダイオードをさらに備える、 付記2Aまたは付記3Aに記載の駆動装置。
 付記5A.前記第2ダイオードは、カソードが、基準電位に接地されている、付記4Aに記載の駆動装置。
 付記6A.前記スイッチング素子は、電界効果トランジスタである、付記A2ないし付記5Aのいずれか1つに記載の駆動装置。
 付記7A.前記スイッチング素子のドレインは、前記コンデンサの前記第2端に接続され、
 前記スイッチング素子のソースは、基準電位に接地されており、
 前記スイッチング素子のゲートには、前記導通状態と前記遮断状態とを切り替えるための駆動信号が入力される、付記6Aに記載の駆動装置。
 付記8A.前記駆動信号を生成するドライブ回路をさらに備えている、付記7Aに記載の駆動装置。
 付記9A.前記スイッチング素子は、半導体材料からなる、付記6Aないし付記8Aのいずれか1つに記載の駆動装置。
 付記10A.前記コンデンサ、前記第1ダイオード、前記入力端子、前記抵抗器が実装された回路基板をさらに備えている、付記2Aないし付記9Aのいずれか1つに記載の駆動装置。
 付記11A.前記コンデンサに並列に接続された追加のコンデンサをさらに備えており、
 前記コンデンサと前記追加のコンデンサとは、前記回路基板の厚さ方向に直交する第1方向において並んで配置され、コンデンサ群を形成する、付記10Aに記載の駆動装置。
 付記12A.前記抵抗器に並列に接続された追加の抵抗器をさらに備えており、
 前記抵抗器と前記追加の抵抗器とは、前記第1方向に並んで配置され、抵抗器群を形成する、付記11Aに記載の駆動装置。
 付記13A.前記コンデンサ群と前記抵抗器群とは、前記厚さ方向および前記第1方向に直交する第2方向に並んでいる、付記12Aに記載の駆動装置。
 付記14A.前記第1ダイオードは、前記第2方向において、前記コンデンサ群と前記抵抗器群との間に挟まれている、付記13Aに記載の駆動装置。
 付記15A.前記スイッチング素子は、前記第2方向において、前記コンデンサ群を基準に、前記抵抗器群と反対側に位置する、付記13Aまたは付記14Aに記載の駆動装置。
 付記16A.前記スイッチング素子は、前記第2方向において、前記コンデンサ群に隣接する、付記15Aに記載の駆動装置。
 付記17A.TO-Canパッケージ型のレーザダイオードを接続可能な第1端子をさらに備えており、
 前記第1端子は、前記回路基板に実装されている、付記13Aないし付記16Aのいずれか1つに記載の駆動装置。
 付記18A.前記第1端子は、前記第2方向において、前記コンデンサ群と、前記抵抗器群との間に配置される、付記17Aに記載の駆動装置。
 付記19A.面実装型のレーザダイオードを接続可能な第2端子をさらに備えており、
 前記第2端子は、前記回路基板に実装されている、付記10Aないし付記18Aのいずれか1つに記載の駆動装置。
 付記20A.前記第2端子は、前記回路基板の厚さ方向に見て、前記回路基板の端縁に沿って配置されている、付記19Aに記載の駆動装置。
The configuration provided based on the first aspect includes the embodiments described in Appendix 1A-20A below.
Appendix 1 A. A drive device that controls the drive of a laser diode.
A switching element that switches between a conductive state and a cutoff state,
With a capacitor
With the first diode
The input terminal to which the power supply voltage is supplied and
Is equipped with
The capacitor has a first end connected to the cathode of the laser diode and a second end connected to the switching element.
In the first diode, the anode is connected to the connection point between the first end of the capacitor and the cathode of the laser diode.
The input terminal is a drive device connected to a connection point between the second end of the capacitor and the switching element.
Appendix 2 A. The drive device according to Appendix 1A, further comprising a resistor whose first end is connected to the anode of the laser diode.
Appendix 3A. The driving device according to Appendix 2A, wherein the resistor has a second end grounded to a reference potential.
Appendix 4 A. The drive according to Appendix 2A or Appendix 3A, further comprising a second diode whose anode is connected to the first end of the capacitor.
Appendix 5A. The driving device according to Appendix 4A, wherein the second diode has a cathode grounded to a reference potential.
Appendix 6 A. The driving device according to any one of Supplementary A2 to Appendix 5A, wherein the switching element is a field effect transistor.
Appendix 7A. The drain of the switching element is connected to the second end of the capacitor.
The source of the switching element is grounded to the reference potential.
The drive device according to Appendix 6A, wherein a drive signal for switching between the conduction state and the cutoff state is input to the gate of the switching element.
Appendix 8A. The drive device according to Appendix 7A, further comprising a drive circuit for generating the drive signal.
Appendix 9A. The drive device according to any one of Supplementary note 6A to Supplementary note 8A, wherein the switching element is made of a semiconductor material.
Appendix 10 A. The drive device according to any one of Appendix 2A to Appendix 9A, further comprising a circuit board on which the capacitor, the first diode, the input terminal, and the resistor are mounted.
Appendix 11A. It also has an additional capacitor connected in parallel with the capacitor.
The driving device according to Appendix 10A, wherein the capacitor and the additional capacitor are arranged side by side in a first direction orthogonal to the thickness direction of the circuit board to form a capacitor group.
Appendix 12 A. It also has an additional resistor connected in parallel with the resistor.
The driving device according to Appendix 11A, wherein the resistor and the additional resistor are arranged side by side in the first direction to form a group of resistors.
Appendix 13 A. The driving device according to Appendix 12A, wherein the capacitor group and the resistor group are arranged in the thickness direction and the second direction orthogonal to the first direction.
Appendix 14 A. The driving device according to Appendix 13A, wherein the first diode is sandwiched between the capacitor group and the resistor group in the second direction.
Appendix 15 A. The driving device according to Appendix 13A or Appendix 14A, wherein the switching element is located on the opposite side of the resistor group with respect to the capacitor group in the second direction.
Appendix 16 A. The driving device according to Appendix 15A, wherein the switching element is adjacent to the capacitor group in the second direction.
Appendix 17 A. It also has a first terminal to which a TO-Can package type laser diode can be connected.
The drive device according to any one of Supplementary note 13A to Supplementary note 16A, wherein the first terminal is mounted on the circuit board.
Appendix 18 A. The drive device according to Appendix 17A, wherein the first terminal is arranged between the capacitor group and the resistor group in the second direction.
Appendix 19 A. It also has a second terminal to which a surface-mounted laser diode can be connected.
The drive device according to any one of Supplementary note 10A to Supplementary note 18A, wherein the second terminal is mounted on the circuit board.
Appendix 20 A. The driving device according to Appendix 19A, wherein the second terminal is arranged along an edge of the circuit board when viewed in the thickness direction of the circuit board.
 <図1~図13における符号>
A1  :駆動装置
10  :回路基板
20  :配線パターン
29  :パターン
21,22:はんだ層
210,220:はんだ
28  :電磁シールド
C0  :コンデンサ群
C1  :コンデンサ
C11 :第1端
C12 :第2端
C2  :電解コンデンサ
D1  :帰還ダイオード
D2  :放電ダイオード
D3  :逆流防止ダイオード
DR  :ドライブ回路
9   :ドライブIC
GND :接地端
HL  :貫通孔
L1  :リアクトル
LD  :レーザダイオード
Ly1~Ly4:配線層
PG  :パルス生成回路
PS1,PS2:電源部
Q1  :スイッチング素子
Q11,Q12,Q13:電極
R0  :シャント抵抗群
R1  :シャント抵抗
R11 :第1端
R12 :第2端
R2  :ゲート抵抗
R3  :充電抵抗
T1,T2,T3:コネクタ端子
T4  :ソケット端子
T5  :接続端子
<Code in FIGS. 1 to 13>
A1: Drive device 10: Circuit board 20: Wiring pattern 29: Patterns 21 and 22: Solder layer 210, 220: Solder 28: Electromagnetic shield C0: Capacitor group C1: Capacitor C11: First end C12: Second end C2: Electrolytic Capacitor D1: Feedback diode D2: Discharge diode D3: Backflow prevention diode DR: Drive circuit 9: Drive IC
GND: Grounding end HL: Through hole L1: Reactor LD: Laser diode Ly1 to Ly4: Wiring layer PG: Pulse generation circuit PS1, PS2: Power supply unit Q1: Switching element Q11, Q12, Q13: Electrode R0: Shunt resistor group R1: Shunt resistance R11: 1st end R12: 2nd end R2: Gate resistance R3: Charging resistance T1, T2, T3: Connector terminal T4: Socket terminal T5: Connection terminal
 次に、図14~図24を参照して、本開示の第2の側面に基づく実施形態について説明する。なお、図14~図24における参照符号は、図1~13(第1の側面)における参照符号とは独立に付されている。そのため、図14~図24と図1~13とにおいて、同じ符号が異なる要素を指している場合もあれば、同じ(あるいは類似の)要素を指している場合もある。 Next, an embodiment based on the second aspect of the present disclosure will be described with reference to FIGS. 14 to 24. The reference numerals in FIGS. 14 to 24 are attached independently of the reference numerals in FIGS. 1 to 13 (first side surface). Therefore, in FIGS. 14 to 24 and FIGS. 1 to 13, the same reference numerals may refer to different elements, or the same (or similar) elements may be referred to.
 図14は、第2の側面の実施形態に基づくレーザ装置の概略構成を示す図である。図示されたレーザ装置1は、レーザダイオードLD1及びレーザダイオード駆動装置2を備える。 FIG. 14 is a diagram showing a schematic configuration of a laser device based on the embodiment of the second aspect. The illustrated laser device 1 includes a laser diode LD1 and a laser diode driving device 2.
 レーザダイオード駆動装置2は、NMOS(N-channel Metal Oxide Semiconductor)トランジスタQ1と、制御部CNT1と、コンデンサC1と、ダイオードD1と、シャント抵抗R1と、を備える。本実施形態では、スイッチング素子としてNMOSトランジスタQ1を用いているが、NMOSトランジスタQ1の代わりにNMOSトランジスタQ1以外のスイッチング素子を用いてもよい。また、本実施形態では、整流素子としてダイオードD1を用いているが、ダイオードD1の代わりにダイオードD1以外の整流素子を用いてもよい。なお、図14に示す構成も、上述した第1の側面に係る構成と同様の特徴を有している。すなわち、図14に示すレーザダイオード駆動装置2は、導通状態と遮断状態とが切り替わるスイッチング素子(Q1)と、コンデンサ(C1)と、第1ダイオード(D1)と、電源電圧が供給される入力端子(PS1の上端)と、を備えている。前記コンデンサ(C1)は、第1端(下端)がレーザダイオード(LD1)のカソードに接続され、第2端(上端)が前記スイッチング素子(Q1)に接続されている。前記第1ダイオード(D1)は、アノードが前記コンデンサ(C1)の前記第1端(下端)と前記レーザダイオード(LD1)のカソードとの接続点に接続されている。前記入力端子(PS1の上端)は、前記コンデンサ(C1)の前記第2端(上端)と前記スイッチング素子(Q1)との接続点に接続されている。したがって、第1の側面について上述した技術的効果は、図14に示す構成(第2の側面)においても奏される。また逆に、以下で述べる第2の側面に係る構成を第1の側面に係る駆動装置に適用することも可能である。特に、第2の側面に係る制御部CNT1の構成及びその制御態様等を、第1の側面に係る駆動装置にも適用しうることが、当業者には理解されるであろう。 The laser diode drive device 2 includes an NMOS (N-channel Metal Oxide Semiconductor) transistor Q1, a control unit CNT1, a capacitor C1, a diode D1, and a shunt resistor R1. In the present embodiment, the NMOS transistor Q1 is used as the switching element, but a switching element other than the NMOS transistor Q1 may be used instead of the NMOS transistor Q1. Further, in the present embodiment, the diode D1 is used as the rectifying element, but a rectifying element other than the diode D1 may be used instead of the diode D1. The configuration shown in FIG. 14 also has the same characteristics as the configuration according to the first aspect described above. That is, the laser diode driving device 2 shown in FIG. 14 has a switching element (Q1) that switches between a conduction state and a cutoff state, a capacitor (C1), a first diode (D1), and an input terminal to which a power supply voltage is supplied. (Upper end of PS1) and. The first end (lower end) of the capacitor (C1) is connected to the cathode of the laser diode (LD1), and the second end (upper end) is connected to the switching element (Q1). The anode of the first diode (D1) is connected to a connection point between the first end (lower end) of the capacitor (C1) and the cathode of the laser diode (LD1). The input terminal (upper end of PS1) is connected to a connection point between the second end (upper end) of the capacitor (C1) and the switching element (Q1). Therefore, the above-mentioned technical effect regarding the first aspect is also exhibited in the configuration (second aspect) shown in FIG. On the contrary, it is also possible to apply the configuration according to the second aspect described below to the drive device according to the first aspect. In particular, those skilled in the art will understand that the configuration of the control unit CNT1 according to the second aspect and the control mode thereof can be applied to the drive device according to the first aspect.
 制御部CNT1から出力されるゲート信号G1は、NMOSトランジスタQ1のゲートに供給される。コンデンサC1の一端及びNMOSトランジスタQ1のドレインは、直流電源PS1の正極に接続される。コンデンサC1の他端は、ダイオードD1のアノード及びレーザダイオードLD1のカソードに接続される。ダイオードD1のカソード及びレーザダイオードLD1のアノードは、シャント抵抗R1の一端に接続される。シャント抵抗R1の他端、NMOSトランジスタQ1のソース、及び直流電源PS1の負極は、グラウンド電位に接続される。 The gate signal G1 output from the control unit CNT1 is supplied to the gate of the NMOS transistor Q1. One end of the capacitor C1 and the drain of the NMOS transistor Q1 are connected to the positive electrode of the DC power supply PS1. The other end of the capacitor C1 is connected to the anode of the diode D1 and the cathode of the laser diode LD1. The cathode of the diode D1 and the anode of the laser diode LD1 are connected to one end of the shunt resistor R1. The other end of the shunt resistor R1, the source of the NMOS transistor Q1, and the negative electrode of the DC power supply PS1 are connected to the ground potential.
 制御部CNT1は、ゲート信号G1によってNMOSトランジスタQ1をオン/オフ制御する。 The control unit CNT1 controls the NMOS transistor Q1 on / off by the gate signal G1.
 NMOSトランジスタQ1がオフであるとき、直流電源PS1の正極から、コンデンサC1、ダイオードD1、シャント抵抗R1を順に経由して直流電源PS1の負極に向かって電流が流れ、コンデンサC1が充電される。直流電源PS1の出力電圧とコンデンサC1の両端電位差が略釣り合うと、電流が流れなくなりコンデンサC1の充電が停止する。 When the NMOS transistor Q1 is off, a current flows from the positive electrode of the DC power supply PS1 to the negative electrode of the DC power supply PS1 via the capacitor C1, the diode D1 and the shunt resistor R1 in this order, and the capacitor C1 is charged. When the output voltage of the DC power supply PS1 and the potential difference across the capacitor C1 are substantially balanced, the current stops flowing and the charging of the capacitor C1 stops.
 NMOSトランジスタQ1がオンであるとき、NMOSトランジスタQ1、コンデンサC1、ダイオードD1、レーザダイオードLD1、及びシャント抵抗R1によって閉回路が形成される。上記閉回路は、寄生のインダクタンスを含む。したがって、上記閉回路はLCR共振回路になる。コンデンサC1に電荷が蓄えられている状態でNMOSトランジスタQ1がオフからオンに切り替わると、上記LCR共振回路は共振を開始する。 When the NMOS transistor Q1 is on, a closed circuit is formed by the NMOS transistor Q1, the capacitor C1, the diode D1, the laser diode LD1, and the shunt resistor R1. The closed circuit contains parasitic inductance. Therefore, the closed circuit becomes an LCR resonant circuit. When the NMOS transistor Q1 is switched from off to on while the electric charge is stored in the capacitor C1, the LCR resonance circuit starts resonance.
 NMOSトランジスタQ1のオンを継続すると、上記LCR共振回路の共振電流Iresは図15に示す太点線のように時間経過とともに減衰する。共振電流Iresが正であるときの共振電流Iresが流れる経路は、図16に示す通りレーザダイオードLD1を含んでいる。したがって、正の共振電流Iresが流れると、レーザダイオードLD1は発光する。共振電流Iresが負であるときの共振電流Iresが流れる経路は、図17に示す通りレーザダイオードLD1を含んでいない。したがって、負の共振電流Iresが流れても、レーザダイオードLD1は発光しない。本実施形態では、NMOSトランジスタQ1のドレインからソースに向かう向きを共振電流Iresの正方向と定義し、NMOSトランジスタQ1のソースからドレインに向かう向きを共振電流Iresの負方向と定義している。 When the NMOS transistor Q1 is continuously turned on, the resonance current Ires of the LCR resonance circuit is attenuated with the passage of time as shown by the thick dotted line shown in FIG. The path through which the resonant current Ires flows when the resonant current Ires is positive includes the laser diode LD1 as shown in FIG. Therefore, when the positive resonance current Ires flows, the laser diode LD1 emits light. The path through which the resonance current Ires flows when the resonance current Ires is negative does not include the laser diode LD1 as shown in FIG. Therefore, the laser diode LD1 does not emit light even when a negative resonance current Ires flows. In the present embodiment, the direction from the drain to the source of the NMOS transistor Q1 is defined as the positive direction of the resonance current Ires, and the direction from the source to the drain of the NMOS transistor Q1 is defined as the negative direction of the resonance current Ires.
 本実施形態では、ゲート信号G1のハイレベル期間すなわちNMOSトランジスタQ1のオン時間は、上記LCR共振回路の共振周期Tの半分よりも短い。NMOSトランジスタQ1のオン時間とは、NMOSトランジスタQ1が連続してオンである時間を意味する。具体的には、図15に示す時間t1から時間t2迄の期間が、本実施形態におけるNMOSトランジスタQ1のオン時間となる。 In the present embodiment, the high level period of the gate signal G1, that is, the on-time of the NMOS transistor Q1 is shorter than half of the resonance period T of the LCR resonance circuit. The on-time of the NMOS transistor Q1 means the time during which the NMOS transistor Q1 is continuously on. Specifically, the period from the time t1 to the time t2 shown in FIG. 15 is the on-time of the NMOS transistor Q1 in the present embodiment.
 NMOSトランジスタQ1がオフになった後も暫くの間は、NMOSトランジスタQ1のドレイン-ソース間の寄生容量を介して共振電流Iresが流れる。そのため、レーザ光の出力期間は、NMOSトランジスタQ1のオン時間と完全には一致せず、NMOSトランジスタQ1のオン時間より少し長い期間となる。具体的は、時間t1から時間t3迄の期間が、本実施形態におけるレーザ光の出力期間となる。 For a while after the NMOS transistor Q1 is turned off, the resonance current Ires flows through the parasitic capacitance between the drain and source of the NMOS transistor Q1. Therefore, the output period of the laser beam does not completely match the on-time of the NMOS transistor Q1, and is a little longer than the on-time of the NMOS transistor Q1. Specifically, the period from time t1 to time t3 is the output period of the laser beam in the present embodiment.
 時間t3以降は共振電流Iresが略零になるため、時間t3以降は次のゲート信号G1のハイレベル期間が到来するまでレーザ装置1はレーザ光を出力しない。 Since the resonance current Ires becomes substantially zero after the time t3, the laser device 1 does not output the laser light until the next high level period of the gate signal G1 arrives after the time t3.
 参考例(図15における最も下のグラフ参照)では、特許文献2で開示されているレーザダイオード駆動装置と同様に、上記LCR共振回路の共振の減衰が終了してもゲート信号G1のハイレベル期間が続く。したがって、参考例では、ゲート信号G1のハイレベル期間すなわちNMOSトランジスタQ1のオン時間は、上記LCR共振回路の共振の周期Tの半分よりも長い。上記LCR共振回路の共振の減衰が終了してもゲート信号G1のハイレベル期間が続くため、共振電流Iresが正の期間(時間t1から時間t4迄の期間、時間t5から時間t6迄の期間、時間t7から時間t8迄の期間)においてレーザ光が出力される。すなわち、時間t1から時間t4迄の期間が、参考例におけるレーザ光の出力期間となる。さらに、参考例では、時間t5から時間t6迄の期間と時間t7から時間t8迄の期間とにおいて、不要なレーザ光出力が発生する。これらの期間における不要な光出力は例えば車両などにおけるレーザレーダ装置の誤動作を招く可能性がある。 In the reference example (see the graph at the bottom in FIG. 15), similarly to the laser diode driving device disclosed in Patent Document 2, the high level period of the gate signal G1 is maintained even after the resonance attenuation of the LCR resonance circuit is completed. Followed. Therefore, in the reference example, the high level period of the gate signal G1, that is, the on-time of the NMOS transistor Q1 is longer than half of the resonance period T of the LCR resonance circuit. Since the high level period of the gate signal G1 continues even after the attenuation of the resonance of the LCR resonance circuit is completed, the period in which the resonance current Ires is positive (the period from time t1 to time t4, the period from time t5 to time t6, The laser beam is output in the period from time t7 to time t8). That is, the period from time t1 to time t4 is the output period of the laser beam in the reference example. Further, in the reference example, unnecessary laser light output is generated in the period from the time t5 to the time t6 and the period from the time t7 to the time t8. Unwanted light output during these periods can lead to malfunction of the laser radar device, for example in a vehicle.
 以上の説明から明らかな通り、レーザダイオード駆動装置2及びレーザ装置1は、レーザ光の出力期間を短くすることができ且つ不要なレーザ光出力を抑制することができる。 As is clear from the above description, the laser diode driving device 2 and the laser device 1 can shorten the output period of the laser beam and suppress unnecessary laser beam output.
 レーザ光が人体の目に害を与えないようにするためには、レーザ光が高パワーであるほど、レーザ光の出力期間を短くすることが求められる。例えば、レーザレーダ装置では、レーザ光のパワーを高めて測距可能距離を向上させる開発が進められており、人体の目に関する安全性を確保する観点からレーザ光の出力期間を短くすることができるレーザダイオード駆動装置2及びレーザ装置1は非常に有用である。また、例えば、レーザレーダ装置では、不要なレーザ光出力は誤検出の原因になり得るため、不要なレーザ光出力を抑制することができるレーザダイオード駆動装置2及びレーザ装置1は非常に有用である。 In order to prevent the laser light from harming the human eye, it is required that the higher the power of the laser light, the shorter the output period of the laser light. For example, in laser radar devices, development is underway to increase the power of laser light to improve the distance that can be measured, and the output period of laser light can be shortened from the viewpoint of ensuring safety for the human eye. The laser diode driving device 2 and the laser device 1 are very useful. Further, for example, in a laser radar device, an unnecessary laser light output can cause erroneous detection, so that the laser diode driving device 2 and the laser device 1 capable of suppressing the unnecessary laser light output are very useful. ..
 NMOSトランジスタQ1のオン時間は、時間t1から共振電流Iresが最大値MAXの半分になる2度目のタイミングTM2迄の期間より短いことが好ましい。図15では、理解を容易にするために、共振電流Iresが最大値MAXの半分になる一度目のタイミングTM1も図示している。 The on-time of the NMOS transistor Q1 is preferably shorter than the period from the time t1 to the second timing TM2 in which the resonance current Ires becomes half of the maximum value MAX. In FIG. 15, for ease of understanding, the first timing TM1 in which the resonance current Ires becomes half of the maximum value MAX is also shown.
 レーザダイオードLD1から射出されるレーザ光のパルス幅は、通常、レーザダイオードLD1を流れる電流の半値全幅で定義される。したがって、NMOSトランジスタQ1のオン時間を、時間t1から共振電流Iresが最大値MAXの半分になる2度目のタイミングTM2迄の期間より短くすることで、レーザ光のパルス幅を上述した参考例よりも短くすることできる。 The pulse width of the laser beam emitted from the laser diode LD1 is usually defined by the full width at half maximum of the current flowing through the laser diode LD1. Therefore, by making the on-time of the NMOS transistor Q1 shorter than the period from the time t1 to the second timing TM2 in which the resonance current Ires becomes half of the maximum value MAX, the pulse width of the laser beam is made larger than that of the above-mentioned reference example. It can be shortened.
 NMOSトランジスタQ1のオン時間は、上記LCR共振回路の共振周期Tの4分の1以上であることが好ましい。共振電流Iresが最大値MAXに到達する前にNMOSトランジスタQ1がオフになることを防止することができるので、レーザ光のパワー低下を抑制することができる。 The on-time of the NMOS transistor Q1 is preferably one-fourth or more of the resonance period T of the LCR resonance circuit. Since it is possible to prevent the NMOS transistor Q1 from turning off before the resonance current Ires reaches the maximum value MAX, it is possible to suppress a decrease in the power of the laser beam.
 図18は、制御部CNT1の一構成例を示す図である。図18に示す構成例の制御部CNT1は、入力端子11と、遅延部12と、波形整形部13と、演算部14と、ドライバ部15と、を備える。演算部14及びドライバ部15は、単一のIC(Integrated Circuit)によって構成されてもよく、それぞれ別個の部品であってもよい。 FIG. 18 is a diagram showing a configuration example of the control unit CNT1. The control unit CNT1 of the configuration example shown in FIG. 18 includes an input terminal 11, a delay unit 12, a waveform shaping unit 13, a calculation unit 14, and a driver unit 15. The arithmetic unit 14 and the driver unit 15 may be configured by a single IC (Integrated Circuit), or may be separate components.
 入力端子11は、第1パルス信号P1を入力する。 The input terminal 11 inputs the first pulse signal P1.
 遅延部12は、第1パルス信号P1に基づく信号を遅延して遅延信号DL1を生成する。第1パルス信号P1に基づく信号は第1パルス信号P1そのものであってもよい。 The delay unit 12 delays the signal based on the first pulse signal P1 to generate the delay signal DL1. The signal based on the first pulse signal P1 may be the first pulse signal P1 itself.
 波形整形部13は、遅延信号DL1の波形を整形して第2パルス信号P2を生成する。波形整形部13は、遅延信号DL1に対して波形整形以外の処理を行ってもよい。 The waveform shaping unit 13 shapes the waveform of the delay signal DL1 to generate the second pulse signal P2. The waveform shaping unit 13 may perform processing other than waveform shaping on the delay signal DL1.
 演算部14は、第1パルス信号P1及び第2パルス信号P2を用いた演算により第1パルス信号P1よりパルス幅が短い第3パルス信号P3を生成する。 The calculation unit 14 generates a third pulse signal P3 having a shorter pulse width than the first pulse signal P1 by calculation using the first pulse signal P1 and the second pulse signal P2.
 ドライバ部15は、第3パルス信号P3を増幅してゲート信号G1を生成する。ドライバ部15は、信号遅延が小さく且つ高周波、超短パルス(例えばパルス幅5nec以下)の入力信号に対応可能であり、更に高出力レーザを駆動させることが可能な電流出力(例えば5A以上)を持つドライバ部であることが好ましい。また、高速スイッチング動作が可能なように、ドライバ部15が持つ自己インダクタンスが小さいほど良い。LSI-ICを使用した場合、CSPパッケージ、またはベアチップ品を選ぶと良い。 The driver unit 15 amplifies the third pulse signal P3 to generate the gate signal G1. The driver unit 15 provides a current output (for example, 5 A or more) that has a small signal delay, can handle an input signal of a high frequency, ultrashort pulse (for example, a pulse width of 5 nex or less), and can further drive a high output laser. It is preferable that the driver portion has. Further, the smaller the self-inductance of the driver unit 15, the better so that high-speed switching operation is possible. When using an LSI-IC, it is preferable to select a CSP package or a bare chip product.
 ドライバ部15からゲート信号G1を受け取るNMOSトランジスタQ1は、高速スイッチング動作が可能なように、入力容量が小さく(例えば500pF以下)且つ入力インピーダンスが小さい(例えば0.5Ω以下)トランジスタであることが好ましい。NMOSトランジスタQ1は、大電流が流れるため、オン抵抗が小さい(例えば20mΩ以下)トランジスタであることが好ましい。さらに、NMOSトランジスタQ1が持つ自己インダクタンスが小さいCSPパッケージまたはベアチップ品を選ぶと良い。 The NMOS transistor Q1 that receives the gate signal G1 from the driver unit 15 is preferably a transistor having a small input capacitance (for example, 500 pF or less) and a small input impedance (for example, 0.5 Ω or less) so that high-speed switching operation is possible. .. Since a large current flows through the NMOS transistor Q1, it is preferable to use a transistor having a small on-resistance (for example, 20 mΩ or less). Further, it is preferable to select a CSP package or a bare chip product having a small self-inductance of the NMOS transistor Q1.
 図18に示す構成例の制御部CNT1によると、第3パルス信号P3のパルス幅W3ひいてはゲート信号G1のパルス幅を第1パルス信号P1のパルス幅W1よりも短くできる(例えば、後述する図19B参照)。これにより、パルス信号のパルス幅を十分に短くすることができない安価なパルス信号生成器によって第1パルス信号P1が生成された場合でも、ゲート信号G1のパルス幅すなわちゲート信号G1のハイレベル期間を上記LCR共振回路の共振周期Tの半分よりも短くすることができる。 According to the control unit CNT1 of the configuration example shown in FIG. 18, the pulse width W3 of the third pulse signal P3 and thus the pulse width of the gate signal G1 can be made shorter than the pulse width W1 of the first pulse signal P1 (for example, FIG. 19B described later). reference). As a result, even when the first pulse signal P1 is generated by an inexpensive pulse signal generator that cannot sufficiently shorten the pulse width of the pulse signal, the pulse width of the gate signal G1, that is, the high level period of the gate signal G1 can be set. It can be shorter than half of the resonance period T of the LCR resonance circuit.
 したがって、図18に示す構成例の制御部CNT1を用いる場合、第1パルス信号P1のパルス幅を上記LCR共振回路の共振周期Tの半分以上にすることが好ましい。これにより、第1パルス信号P1を生成するパルス信号生成器の低コスト化を図ることができる。 Therefore, when the control unit CNT1 of the configuration example shown in FIG. 18 is used, it is preferable that the pulse width of the first pulse signal P1 is set to half or more of the resonance period T of the LCR resonance circuit. As a result, the cost of the pulse signal generator that generates the first pulse signal P1 can be reduced.
 本実施形態では、第1パルス信号P1、第3パルス信号P3、及びゲート信号G1の各パルス幅は第1パルス信号P1、第3パルス信号P3、及びゲート信号G1の各ハイレベル期間であるが、スイッチング素子の特性やインバータの利用等に応じてローレベル期間がパルス幅であってもよい。 In the present embodiment, the pulse widths of the first pulse signal P1, the third pulse signal P3, and the gate signal G1 are each high level period of the first pulse signal P1, the third pulse signal P3, and the gate signal G1. The low level period may be the pulse width depending on the characteristics of the switching element, the use of the inverter, and the like.
 図19Aは、図18に示す構成例の制御部CNT1の具体例を示す図である。図19Bは、図19Aに示す制御部CNT1の各信号のタイムチャートである。 FIG. 19A is a diagram showing a specific example of the control unit CNT1 of the configuration example shown in FIG. FIG. 19B is a time chart of each signal of the control unit CNT1 shown in FIG. 19A.
 図19Aに示す制御部CNT1は、入力端子11、遅延部12、波形整形部13、演算部14、及びドライバ部15の他にヒステリシスインバータINV1を備える。ヒステリシスインバータINV1は、第1パルス信号P1を反転させ、その第1パルス信号P1の反転信号を遅延部12に供給する。図19Aに示す制御部CNT1の遅延部12は、抵抗12A及びコンデンサ12Bによって遅延部12を構成され、図19Aに示す制御部CNT1の波形整形部13は、ヒステリシスインバータINV2によって構成される。 The control unit CNT1 shown in FIG. 19A includes a hysteresis inverter INV1 in addition to the input terminal 11, the delay unit 12, the waveform shaping unit 13, the calculation unit 14, and the driver unit 15. The hysteresis inverter INV1 inverts the first pulse signal P1 and supplies the inverted signal of the first pulse signal P1 to the delay unit 12. The delay unit 12 of the control unit CNT1 shown in FIG. 19A is configured by the resistor 12A and the capacitor 12B, and the waveform shaping unit 13 of the control unit CNT1 shown in FIG. 19A is composed of the hysteresis inverter INV2.
 ヒステリシスインバータINV2は、図19Bに示す通り、遅延信号DL1を反転させつつ遅延信号DL1の波形を整形する。具体的には、ヒステリシスインバータINV2は、図19Bに示す通り、遅延信号DL1を反転させつつ遅延信号DL1の波形をハイレベルとローレベルとの間の切り替わりが急峻になるように整形する。 As shown in FIG. 19B, the hysteresis inverter INV2 shapes the waveform of the delay signal DL1 while inverting the delay signal DL1. Specifically, as shown in FIG. 19B, the hysteresis inverter INV2 shapes the waveform of the delay signal DL1 so that the switching between the high level and the low level becomes steep while inverting the delay signal DL1.
 図19Aに示す制御部CNT1の波形整形部14は、第1パルス信号G1から第2パルス信号G2を減算する演算処理を行って第3パルス信号P3を生成する。 The waveform shaping unit 14 of the control unit CNT1 shown in FIG. 19A performs arithmetic processing for subtracting the second pulse signal G2 from the first pulse signal G1 to generate the third pulse signal P3.
 図19Cは、図18に示す構成例の制御部CNT1の他の具体例を示す図である。図19Cに示す制御部CNT1は、ヒステリシスインバータINV1を遅延部12とヒステリシスインバータINV2との間に設ける点で図19Aに示す制御部CNT1と異なる。図19Cに示す制御部CNT1の波形整形部13は、ヒステリシスインバータINV1及びINV2によって構成される。図19Cに示す制御部CNT1の波形整形部13は、遅延信号DL1を2回反転させつつ遅延信号DL1の波形を整形する。 FIG. 19C is a diagram showing another specific example of the control unit CNT1 of the configuration example shown in FIG. The control unit CNT1 shown in FIG. 19C is different from the control unit CNT1 shown in FIG. 19A in that the hysteresis inverter INV1 is provided between the delay unit 12 and the hysteresis inverter INV2. The waveform shaping unit 13 of the control unit CNT1 shown in FIG. 19C is composed of the hysteresis inverters INV1 and INV2. The waveform shaping unit 13 of the control unit CNT1 shown in FIG. 19C shapes the waveform of the delay signal DL1 while inverting the delay signal DL1 twice.
 図19Dに示す構成例の制御部CNT1のように、入力端子11から遅延部12を経由して演算部14に至る経路にヒステリシスインバータを一つのみ設けてもよい。 As in the control unit CNT1 of the configuration example shown in FIG. 19D, only one hysteresis inverter may be provided in the path from the input terminal 11 to the calculation unit 14 via the delay unit 12.
 ゲート信号G1の論理が図19Aに示す制御部CNT1や図19Cに示す制御部CNT1に対して反転してもよい場合には、図19Dに示す構成例の制御部CNT1の演算部14は、第1パルス信号G1から第2パルス信号G2を減算する演算処理を行って第3パルス信号P3を生成すればよい。 When the logic of the gate signal G1 may be inverted with respect to the control unit CNT1 shown in FIG. 19A and the control unit CNT1 shown in FIG. 19C, the calculation unit 14 of the control unit CNT1 of the configuration example shown in FIG. The third pulse signal P3 may be generated by performing arithmetic processing for subtracting the second pulse signal G2 from the first pulse signal G1.
 一方、ゲート信号G1の論理が図19Aに示す制御部CNT1や図19Cに示す制御部CNT1に対して反転してはいけない場合には、図19Dに示す構成例の制御部CNT1の演算部14は、第2パルス信号G2を演算部14の内部で反転させた後、第1パルス信号G1から第2パルス信号G2の反転信号を減算する演算処理を行って第3パルス信号P3を生成すればよい。 On the other hand, when the logic of the gate signal G1 must not be inverted with respect to the control unit CNT1 shown in FIG. 19A and the control unit CNT1 shown in FIG. 19C, the calculation unit 14 of the control unit CNT1 of the configuration example shown in FIG. 19D , The second pulse signal G2 may be inverted inside the arithmetic unit 14, and then the arithmetic processing of subtracting the inverted signal of the second pulse signal G2 from the first pulse signal G1 may be performed to generate the third pulse signal P3. ..
 第1パルス信号P1を生成するパルス信号生成器の性能が低い場合、第1パルス信号P1の立ち上がりエッジ及び立ち下がりエッジのスルーレートが大きくなり得る。したがって、立ち上がりエッジ及び立ち下がりエッジのスルーレートが大きい第1パルス信号P1が入力されても適切に対応できるように、図19Aに示す制御部CNT1のヒステリシスインバータINV1の配置を変更して図19Eに示す構成にしてもよい。 If the performance of the pulse signal generator that generates the first pulse signal P1 is low, the slew rate of the rising edge and the falling edge of the first pulse signal P1 can be large. Therefore, the arrangement of the hysteresis inverter INV1 of the control unit CNT1 shown in FIG. 19A is changed to FIG. 19E so that the first pulse signal P1 having a large slew rate of the rising edge and the falling edge can be appropriately handled. The configuration shown may be used.
 図19Eに示す制御部CNT1において、ヒステリシスインバータINV1は、第1パルス信号P1の波形を生成し、波形整形後のパルス信号P1'を演算部14に供給する波形整形部13'として用いられる。図19Bは、図19Eに示す制御部CNT1の各信号のタイムチャートは図19Fのようになる。図19F中のH1はヒステリシスインバータINV1のヒステリシス量を示しており、図19F中のH2はヒステリシスインバータINV2のヒステリシス量を示している。 In the control unit CNT1 shown in FIG. 19E, the hysteresis inverter INV1 is used as the waveform shaping unit 13'that generates the waveform of the first pulse signal P1 and supplies the pulse signal P1'after the waveform shaping to the calculation unit 14. In FIG. 19B, the time chart of each signal of the control unit CNT1 shown in FIG. 19E is as shown in FIG. 19F. H1 in FIG. 19F shows the hysteresis amount of the hysteresis inverter INV1, and H2 in FIG. 19F shows the hysteresis amount of the hysteresis inverter INV2.
 上述した図19Aに示す制御部CNT1、図19Cに示す制御部CNT1、図19Dに示す制御部CNT1、及び図19Eに示す制御部CNT1はヒステリシスインバータを備える構成であるが、ヒステリシスインバータの代わりに例えばヒステリシスコンパレータを用いてもよい。例えば、図19Eに示す制御部CNT1においてヒステリシスインバータINV1及びINV2の代わりにヒステリシスコンパレータCOM1及びCOM2を用いて図19Gに示すような構成にしてもよい。図19Gに示す制御部CNT1は、波形整形部13及び13'が信号の反転を行わない点で、図19Eに示す制御部CNT1と異なっている。ただし、ヒステリシスコンパレータの反転入力端子と非反転入力端子とを入れ替えることで波形整形部において信号の反転が行われるようにしてもよい。 The control unit CNT1 shown in FIG. 19A, the control unit CNT1 shown in FIG. 19C, the control unit CNT1 shown in FIG. 19D, and the control unit CNT1 shown in FIG. 19E are configured to include a hysteresis inverter, but instead of the hysteresis inverter, for example, A hysteresis comparator may be used. For example, the control unit CNT1 shown in FIG. 19E may be configured as shown in FIG. 19G by using the hysteresis comparators COM1 and COM2 instead of the hysteresis inverters INV1 and INV2. The control unit CNT1 shown in FIG. 19G is different from the control unit CNT1 shown in FIG. 19E in that the waveform shaping units 13 and 13'do not invert signals. However, the signal may be inverted in the waveform shaping unit by exchanging the inverting input terminal and the non-inverting input terminal of the hysteresis comparator.
 上述した図19Aに示す制御部CNT1、図19Cに示す制御部CNT1、図19Dに示す制御部CNT1、図19Eに示す制御部CNT1、及び図19Gに示す制御部CNT1はヒステリシスインバータ又はヒステリシスコンパレータを備える構成であるが、ヒステリシスインバータの代わりにヒステリシス特性を有さないインバータを用いてもよく、ヒステリシスコンパレータの代わりにヒステリシス特性を有さないコンパレータを用いてもよい。 The control unit CNT1 shown in FIG. 19A, the control unit CNT1 shown in FIG. 19C, the control unit CNT1 shown in FIG. 19D, the control unit CNT1 shown in FIG. 19E, and the control unit CNT1 shown in FIG. 19G include a hysteresis inverter or a hysteresis comparator. Although it has a configuration, an inverter having no hysteresis characteristic may be used instead of the hysteresis inverter, and a comparator having no hysteresis characteristic may be used instead of the hysteresis comparator.
 図20は、シャント抵抗R1の構成例を示す図である。図20に示す構成例のシャント抵抗R1は、複数の抵抗素子RE1を並列接続した構成である。複数の抵抗素子RE1を並列接続することにより、シャント抵抗R1の抵抗値を小さくすることが容易になる。なお、同図に示す複数の抵抗素子RE1は、図1に示す複数の抵抗R1に対応しうる。 FIG. 20 is a diagram showing a configuration example of the shunt resistor R1. The shunt resistor R1 of the configuration example shown in FIG. 20 has a configuration in which a plurality of resistance elements RE1 are connected in parallel. By connecting a plurality of resistance elements RE1 in parallel, it becomes easy to reduce the resistance value of the shunt resistor R1. The plurality of resistance elements RE1 shown in the figure can correspond to the plurality of resistors R1 shown in FIG.
 図14に示すレーザ装置1では、NMOSトランジスタQ1のオン時間を上記LCR共振回路の共振周期Tの半分よりも短くしているため、レーザ光のパワーは減少する。このレーザ光のパワー減少を抑制するためには、コンデンサC1の容量を大きくしてレーザダイオードLD1に流れる電流を大きくする必要がある。コンデンサC1の容量を大きくする場合、上記LCR共振回路の共振周期Tが長くなることを抑制するためにシャント抵抗R1の抵抗値を小さくする必要がある。したがって、図14に示すレーザ装置1において、シャント抵抗R1の抵抗値を小さくすることは重要である。 In the laser device 1 shown in FIG. 14, since the on-time of the NMOS transistor Q1 is shorter than half of the resonance period T of the LCR resonance circuit, the power of the laser light is reduced. In order to suppress the power decrease of the laser beam, it is necessary to increase the capacitance of the capacitor C1 and increase the current flowing through the laser diode LD1. When increasing the capacitance of the capacitor C1, it is necessary to decrease the resistance value of the shunt resistor R1 in order to suppress the increase in the resonance period T of the LCR resonance circuit. Therefore, in the laser apparatus 1 shown in FIG. 14, it is important to reduce the resistance value of the shunt resistor R1.
 図20に示す構成例では、3個の抵抗素子RE1を並列接続しているが、並列接続される抵抗素子RE1の個数は3個に限定されることはなく、複数であればよい。ただし、並列接続される抵抗素子RE1の個数が多いほど、シャント抵抗R1の抵抗値を小さくすることが容易になるがシャント抵抗R1の実装面積が大きくなる。したがって、要求されるシャント抵抗R1の抵抗値と要求されるシャント抵抗R1の実装面積との兼ね合いを考慮して、並列接続される抵抗素子RE1の個数を決定すればよい。 In the configuration example shown in FIG. 20, three resistance elements RE1 are connected in parallel, but the number of resistance elements RE1 connected in parallel is not limited to three, and may be a plurality. However, as the number of resistance elements RE1 connected in parallel increases, it becomes easier to reduce the resistance value of the shunt resistor R1, but the mounting area of the shunt resistor R1 increases. Therefore, the number of resistance elements RE1 connected in parallel may be determined in consideration of the balance between the required resistance value of the shunt resistor R1 and the required mounting area of the shunt resistor R1.
 上記LCR共振回路の共振周期Tが長くなることを抑制し且つ上記LCR共振回路の共振電流Iresの最大値を大きくするには、上記LCR共振回路のインダクタンス成分は小さい方がよい。図20に示す構成例のシャント抵抗R1で形成される寄生のインダクタンスをできるだけ小さくするために、隣接する抵抗素子RE1の相互インダクタンスMを零にすることが好ましい。 In order to suppress the long resonance period T of the LCR resonance circuit and increase the maximum value of the resonance current Ires of the LCR resonance circuit, the inductance component of the LCR resonance circuit should be small. In order to minimize the parasitic inductance formed by the shunt resistor R1 of the configuration example shown in FIG. 20, it is preferable to set the mutual inductance M of the adjacent resistance elements RE1 to zero.
 隣接する抵抗素子RE1の相互インダクタンスMは、下記の式(1)で表せる。ただし、LNは抵抗素子RE1の長さであり、dは隣接する抵抗素子RE1の間隔である。相互インダクタンスMの単位は[H]、長さLNの単位及び間隔dの単位はそれぞれ[m]である。
  M=2LN(ln(2LN/d)-1)×10-7 ・・・(1)
The mutual inductance M of the adjacent resistance elements RE1 can be expressed by the following equation (1). However, LN is the length of the resistance element RE1, and d is the distance between the adjacent resistance elements RE1. The unit of the mutual inductance M is [H], the unit of the length LN and the unit of the interval d are [m], respectively.
M = 2LN (ln (2LN / d) -1) x 10-7 ... (1)
 相互インダクタンスMを零に抑えるための条件は、下記の式(2)で表せる。ただし、eはネイピア数である。
  ln(2LN/d)-1≦0
  d≧2LN/e ・・・(2)
 隣接する抵抗素子RE1の間隔dは、抵抗素子RE1の長さLNの2倍をネイピア数で除して得られる値以上であることが好ましい。
The condition for suppressing the mutual inductance M to zero can be expressed by the following equation (2). However, e is the number of Napiers.
ln (2LN / d) -1 ≤ 0
d ≧ 2LN / e ・ ・ ・ (2)
The interval d between the adjacent resistance elements RE1 is preferably a value or more obtained by dividing twice the length LN of the resistance element RE1 by the number of napiers.
 図14に示すレーザ装置1は、基板B1を備える。図21は基板B1の上面図であり、図22は基板B1の断面を示す模式図である。説明の便宜上、図21及び図22において、互いに直交する3つの方向(x方向、y方向、z方向)を参照する。z方向は、基板B1の厚さ方向に対応する。 The laser device 1 shown in FIG. 14 includes a substrate B1. FIG. 21 is a top view of the substrate B1, and FIG. 22 is a schematic view showing a cross section of the substrate B1. For convenience of explanation, in FIGS. 21 and 22, three directions (x direction, y direction, and z direction) orthogonal to each other are referred to. The z direction corresponds to the thickness direction of the substrate B1.
 図14に示す回路構成における複数の電子部品が基板B1に実装される。 A plurality of electronic components in the circuit configuration shown in FIG. 14 are mounted on the substrate B1.
 図21は、基板B1上の部品レイアウトおよびランドパターンを示している。図21においては、複数の電子部品を想像線(二点鎖線)で示している。 FIG. 21 shows the component layout and land pattern on the board B1. In FIG. 21, a plurality of electronic components are shown by imaginary lines (dashed-dotted lines).
 基板B1は、z方向視(平面視)において矩形状である。 The substrate B1 has a rectangular shape in the z-direction view (plan view).
 基板B1は、積層基板であり、図22に示すように、互いに絶縁層Ly0を介して積層された4層の配線層Ly1~Ly4を含んでいる。配線層の数は4層に限定されることはなく、複数であればよい。本実施形態とは異なり、単層基板を用いることも可能である。 The substrate B1 is a laminated substrate, and as shown in FIG. 22, includes four wiring layers Ly1 to Ly4 laminated with each other via an insulating layer Ly0. The number of wiring layers is not limited to four, and may be a plurality. Unlike this embodiment, it is also possible to use a single layer substrate.
 配線層Ly1は、基板B1における第1層であり、最上層である。配線層Ly1の上面にははんだ層が形成されている。このはんだ層は、部分的にレジスト膜(図示略)で覆われている。このレジスト膜から露出したはんだは、図21に示すランドパターンに相当する。 The wiring layer Ly1 is the first layer and the uppermost layer in the substrate B1. A solder layer is formed on the upper surface of the wiring layer Ly1. This solder layer is partially covered with a resist film (not shown). The solder exposed from the resist film corresponds to the land pattern shown in FIG.
 配線層Ly4は、基板B1における第4層であり、最下層である。配線層Ly2及びLy3は、基板B1における中間層である。配線層Ly2は、基板B1における第2層であり、z方向において、配線層Ly1と配線層Ly3とに挟まれている。配線層Ly3は、基板B1における第3層であり、z方向において、配線層Ly2と配線層Ly4とに挟まれている。配線層Ly2はグラウンド電位が印加されるグラウンド層である。配線層Ly2では、信号系のグラウンドと電源系のグラウンドとを分離せず、信号系のグラウンドと電源系のグラウンドとを共通にしている。これにより、信号系と電源系との基準電位にずれが生じることを抑制することができる。複数の配線層Ly1~Ly4は、絶縁層Ly0を貫通する貫通ビアTVによって互いに導通する。図21においては、貫通ビアTVを点線で示している。 The wiring layer Ly4 is the fourth layer and the lowest layer in the substrate B1. The wiring layers Ly2 and Ly3 are intermediate layers in the substrate B1. The wiring layer Ly2 is a second layer on the substrate B1 and is sandwiched between the wiring layer Ly1 and the wiring layer Ly3 in the z direction. The wiring layer Ly3 is a third layer on the substrate B1 and is sandwiched between the wiring layer Ly2 and the wiring layer Ly4 in the z direction. The wiring layer Ly2 is a ground layer to which a ground potential is applied. In the wiring layer Ly2, the ground of the signal system and the ground of the power supply system are not separated, and the ground of the signal system and the ground of the power supply system are shared. As a result, it is possible to suppress the deviation of the reference potential between the signal system and the power supply system. The plurality of wiring layers Ly1 to Ly4 are electrically connected to each other by a penetrating via TV penetrating the insulating layer Ly0. In FIG. 21, the penetrating via TV is shown by a dotted line.
 配線層Ly1と配線層Ly3とに挟まれている絶縁層Ly0の厚みd0は200μm以下であることが好ましい。これにより、配線層Ly1と配線層Ly3との間における貫通ビアTVの長さが通常の積層基板よりも短くなり、配線層Ly1と配線層Ly3との間における貫通ビアTVのインダクタンスが小さくなるので、上記LCR共振回路のインダクタンスを小さくすることができる。なお、通常の積層基板では、配線層Ly1と配線層Ly3との間における貫通ビアTVの長さは700μm程度である。 The thickness d0 of the insulating layer Ly0 sandwiched between the wiring layer Ly1 and the wiring layer Ly3 is preferably 200 μm or less. As a result, the length of the penetrating via TV between the wiring layer Ly1 and the wiring layer Ly3 becomes shorter than that of the normal laminated substrate, and the inductance of the penetrating via TV between the wiring layer Ly1 and the wiring layer Ly3 becomes smaller. , The inductance of the LCR resonant circuit can be reduced. In a normal laminated substrate, the length of the penetrating via TV between the wiring layer Ly1 and the wiring layer Ly3 is about 700 μm.
 高周波駆動によるノイズ除去などのため、電源層が存在した場合、配線層と電源層の間にグラウンド層を入れるといい。入れることが出来ない場合、出来るだけ配線層と電源層の間の距離を離すといい。 If there is a power supply layer for noise removal by high frequency drive, it is recommended to insert a ground layer between the wiring layer and the power supply layer. If it cannot be inserted, the distance between the wiring layer and the power supply layer should be as large as possible.
 基板B1には、図21に示すように、その四隅にそれぞれ貫通孔THが形成されている。各貫通孔THは、基板B1をz方向に貫通している。各貫通孔THは、基板B1を支持部材に固定するために設けられており、ボルトなどの締結具などが挿通される。 As shown in FIG. 21, through holes TH are formed in the four corners of the substrate B1. Each through hole TH penetrates the substrate B1 in the z direction. Each through hole TH is provided to fix the substrate B1 to the support member, and a fastener such as a bolt is inserted through the through hole TH.
 次に、基板B1に実装された各電子部品について図21を参照して説明する。 Next, each electronic component mounted on the substrate B1 will be described with reference to FIG.
 複数のコンデンサC0は、図21に示すように、x方向に並んで配置されている。複数のコンデンサC0は配線層Ly1によって並列接続され、コンデンサC1を構成する。各コンデンサC0は、2つの端子がy方向に並んでいる。各コンデンサC0は、たとえばチップタイプであるが、リードタイプであってもよい。複数のコンデンサC0を並列接続にしてコンデンサC1を構成することは、コンデンサC1が持つ寄生インダクタンスを低減するのに非常に有効である。 As shown in FIG. 21, the plurality of capacitors C0 are arranged side by side in the x direction. A plurality of capacitors C0 are connected in parallel by the wiring layer Ly1 to form the capacitor C1. In each capacitor C0, two terminals are arranged in the y direction. Each capacitor C0 is, for example, a chip type, but may be a lead type. It is very effective to connect a plurality of capacitors C0 in parallel to form the capacitor C1 in order to reduce the parasitic inductance of the capacitor C1.
 複数の抵抗素子RE1は、図21に示すように、x方向に並んで配置されている。複数の抵抗素子RE1は配線層Ly1によって並列接続され、シャント抵抗R1を構成する。各抵抗素子RE1は、2つの端子がy方向に並んでいる。各抵抗素子RE1は、たとえばチップタイプであるが、リードタイプであってもよい。さらに、上記の式(2)により、間隔dに比べできるだけ長さLNが短い抵抗素子(長辺抵抗素子)、または金属電極抵抗素子を選ぶと良い。 As shown in FIG. 21, the plurality of resistance elements RE1 are arranged side by side in the x direction. The plurality of resistance elements RE1 are connected in parallel by the wiring layer Ly1 to form a shunt resistor R1. In each resistance element RE1, two terminals are arranged in the y direction. Each resistance element RE1 is, for example, a chip type, but may be a lead type. Further, according to the above equation (2), it is preferable to select a resistance element (long-side resistance element) having a length LN as short as possible with respect to the interval d, or a metal electrode resistance element.
 コンデンサC1とシャント抵抗R1とは、図21に示すように、y方向に並んでいる。y方向において、コンデンサC1とシャント抵抗R1との間には、ダイオードD1及びレーザダイオードLD1が配置されている。ダイオードD1及びレーザダイオードLD1は、y方向に並んでいる。異なる種類のレーザダイオードLD1を実装できるように、レーザダイオードLD1の実装領域は3箇所設けられている。 As shown in FIG. 21, the capacitor C1 and the shunt resistor R1 are aligned in the y direction. In the y direction, a diode D1 and a laser diode LD1 are arranged between the capacitor C1 and the shunt resistor R1. The diode D1 and the laser diode LD1 are arranged in the y direction. Three mounting regions for the laser diode LD1 are provided so that different types of laser diode LD1 can be mounted.
 TO-Canパッケージ型のレーザダイオードLD1の1番ピン(レーザダイオードのアノード)とTO-Canパッケージ型のレーザダイオードLD1の3番ピン(レーザダイオードのカソード)とはy方向に並んでいる。より詳細には、TO-Canパッケージ型のレーザダイオードLD1の1番ピンからTO-CanパッケージのレーザダイオードLD1の3番ピンに向かう方向はy方向と略平行である。また、基板B1の右端に実装されるチップ型のレーザダイオードLD1のカソードから基板B1の右端に実装されるチップ側のレーザダイオードLD1のアノードに向かう方向もy方向と略平行である。これにより、レーザダイオードLD1とコンデンサC1との経路長及びレーザダイオードLD1とシャント抵抗R1との経路長の合計長さを最短にできる。なお、TO-Canパッケージ型のレーザダイオードLD1の2番ピンはTO-Canパッケージに内蔵される受光素子のカソードである。 The 1st pin (anode of the laser diode) of the TO-Can package type laser diode LD1 and the 3rd pin (cathode of the laser diode) of the TO-Can package type laser diode LD1 are aligned in the y direction. More specifically, the direction from the 1st pin of the TO-Can package type laser diode LD1 to the 3rd pin of the TO-Can package laser diode LD1 is substantially parallel to the y direction. Further, the direction from the cathode of the chip-type laser diode LD1 mounted on the right end of the substrate B1 to the anode of the laser diode LD1 on the chip side mounted on the right end of the substrate B1 is also substantially parallel to the y direction. As a result, the total length of the path length between the laser diode LD1 and the capacitor C1 and the path length between the laser diode LD1 and the shunt resistor R1 can be minimized. The second pin of the TO-Can package type laser diode LD1 is the cathode of the light receiving element built in the TO-Can package.
 スイッチング素子Q1は、図21に示すように、y方向において、コンデンサC1と並んでいる。図21に示す例においては、スイッチング素子Q1は、y方向において、コンデンサC1に隣接している。y方向において、コンデンサC1は、スイッチング素子Q1とシャント抵抗R1とに挟まれている。 As shown in FIG. 21, the switching element Q1 is aligned with the capacitor C1 in the y direction. In the example shown in FIG. 21, the switching element Q1 is adjacent to the capacitor C1 in the y direction. In the y direction, the capacitor C1 is sandwiched between the switching element Q1 and the shunt resistor R1.
 同軸コネクタである入力端子11と、インバータINV1と、抵抗12A及びコンデンサ12Bによって構成される遅延部12と、インバータINV2と、演算部14及びドライブ部15を含むICパッケージU1とは、図21に示すように、x方向に並んでいる。これにより、制御部CNT1内の配線長さを短くすることができる。 FIG. 21 shows an input terminal 11 which is a coaxial connector, an inverter INV1, a delay unit 12 composed of a resistor 12A and a capacitor 12B, an inverter INV2, and an IC package U1 including a calculation unit 14 and a drive unit 15. As shown above, they are arranged in the x direction. As a result, the wiring length in the control unit CNT1 can be shortened.
 図21に示すように、基板B1の右半分領域(ダイオードD1、レーザダイオードLD1、スイッチング素子Q1、及びシャント抵抗R1が実装される側の領域)に設けられる貫通ビアの個数は、基板B1の左半分領域に設けられる貫通ビアの個数よりも多い。これにより、上記LCR共振回路におけるグラウンドを特に強化することができる。 As shown in FIG. 21, the number of through vias provided in the right half region of the substrate B1 (the region on which the diode D1, the laser diode LD1, the switching element Q1 and the shunt resistor R1 are mounted) is the left of the substrate B1. More than the number of penetrating diodes provided in the half area. Thereby, the ground in the LCR resonance circuit can be particularly strengthened.
 上述した図14に示すレーザ装置1は、例えば図23に示すレーザレーダ装置X1の一部として用いられる。図23に示すレーザレーダ装置X1は、走査型レーザレーダ装置であって、レーザ装置1と、受光装置3と、光学系4と、全体制御部5と、を備える。全体制御部5は、レーザ装置1の出力及び光学系4内のミラーの向きを制御し、レーザ装置1の出力の制御内容及び受光装置3の出力信号に基づき物体までの距離を演算し、光学系4内のミラーの向きの制御内容に基づき物体の方向を演算する。 The laser device 1 shown in FIG. 14 described above is used, for example, as a part of the laser radar device X1 shown in FIG. 23. The laser radar device X1 shown in FIG. 23 is a scanning laser radar device, and includes a laser device 1, a light receiving device 3, an optical system 4, and an overall control unit 5. The overall control unit 5 controls the output of the laser device 1 and the direction of the mirror in the optical system 4, calculates the distance to the object based on the control content of the output of the laser device 1 and the output signal of the light receiving device 3, and optics. The direction of the object is calculated based on the control content of the direction of the mirror in the system 4.
 図23に示すレーザレーダ装置X1は、例えば図24に示す車両Y1の前端に設けられ、車両Y1の前方に位置する物体を検知する。 The laser radar device X1 shown in FIG. 23 is provided at the front end of the vehicle Y1 shown in FIG. 24, for example, and detects an object located in front of the vehicle Y1.
 上記実施形態は、例示であって、制限的なものではないと考えられるべきである。 The above embodiment should be considered as an example and not restrictive.
 例えば、コンデンサC1と、ダイオードD1及びレーザダイオードLD1の並列回路と、シャント抵抗R1との並び方は、図14に示す構成でなくてもよい。 For example, the arrangement of the parallel circuit of the capacitor C1, the diode D1 and the laser diode LD1 and the shunt resistor R1 does not have to be the configuration shown in FIG.
 例えば、レーザダイオードLD1を流れる電流を検出する必要がない場合や他の手法でレーザダイオードLD1を流れる電流を検出する場合には、シャント抵抗R1を設けない構成にしてもよい。 For example, when it is not necessary to detect the current flowing through the laser diode LD1 or when the current flowing through the laser diode LD1 is detected by another method, the shunt resistor R1 may not be provided.
 例えば、本明細書中に示される複数の実施形態及び変形例は可能な範囲で組み合わせて実施されてよい。さらには、第1の側面に係るレーザダイオード駆動装置を図14に示すレーザ装置1に用いてもよい。また、そのレーザ装置1を図23に示すレーザレーダ装置X1(延いては図24に示す車両Y1)に用いてもよい。 For example, a plurality of embodiments and modifications shown in the present specification may be combined and implemented to the extent possible. Further, the laser diode driving device according to the first side surface may be used for the laser device 1 shown in FIG. Further, the laser device 1 may be used for the laser radar device X1 shown in FIG. 23 (and by extension, the vehicle Y1 shown in FIG. 24).
 第2の側面に基づき提供される構成は、以下の付記1B~16Bに記載された実施形態を含む。
 付記1B.レーザダイオードの駆動制御を行う駆動装置であって、
 スイッチング素子と、
 前記スイッチング素子をオン/オフ制御する制御部と、
 前記レーザダイオードに対してアノード及びカソードが逆向きで並列接続される整流素子と、
 前記スイッチング素子がオフであるときに充電されるコンデンサであって、前記スイッチング素子がオンであるときに、前記スイッチング素子、前記レーザダイオード、及び前記整流素子とともに閉回路を形成するコンデンサと、
 を備え、
 前記制御部は、前記スイッチング素子のオン時間を前記閉回路の共振周期の半分より短くする、駆動装置。
 なお、前記レーザダイオードと前記整流素子との並列接続は、前記レーザダイオードのみと前記整流素子のみとの並列接続に限定されず、前記レーザダイオードを含む回路と前記整流素子のみとの並列接続、前記レーザダイオードのみと前記整流素子を含む回路との並列接続、又は、前記レーザダイオードを含む回路と前記整流素子を含む回路との並列接続であってもよい。
 付記2B.前記制御部は、前記スイッチング素子のオン時間を前記スイッチング素子がオフからオンに切り替わったタイミングから前記閉回路の共振電流が最大値の半分になる2度目のタイミング迄の期間より短くする、付記1Bに記載の駆動装置。
 付記3B.
 前記制御部は、前記スイッチング素子のオン時間を前記閉回路の共振周期の4分の1以上にする、付記1B又は付記2Bに記載の駆動装置。
 付記4B.前記制御部は、
 第1パルス信号に基づく信号を遅延して遅延信号を生成する遅延部と、
 前記遅延信号の波形を整形して第2パルス信号を生成する波形整形部と、
 前記第1パルス信号及び前記第2パルス信号を用いた演算により前記第1パルス信号よりパルス幅が短い第3パルス信号を生成する演算部と、
 を備え、
 前記第3パルス信号に基づき前記スイッチング素子をオン/オフ制御する、付記1B~3Bのいずれか1つに記載の駆動装置。
 付記5B.前記第1パルス信号のパルス幅は、前記閉回路の共振周期の半分以上である、付記4Bに記載の駆動装置。
 付記6B.前記レーザダイオードを流れる電流を検出するシャント抵抗をさらに備え、前記閉回路は前記シャント抵抗を含む、付記1B~5Bのいずれか1つに記載の駆動装置。
 付記7B.前記シャント抵抗は、並列接続された複数の抵抗素子を含む、付記6Bに記載の駆動装置。
 付記8B.前記複数の抵抗素子は、同じ長さを有しかつ互いに隣り合う第1抵抗素子および第2抵抗素子を含み、前記第1抵抗素子および前記第2抵抗素子の間隔は、前記同じ長さの2倍をネイピア数で除して得られる値以上である、付記7Bに記載の駆動装置。
 付記9B.付記1B~8Bのいずれか1つに記載の駆動装置と、
 前記レーザダイオードと、
 を備える、レーザ装置。
 付記10B.
 基板をさらに備え、
 前記スイッチング素子と、前記整流素子及び前記レーザダイオードを含む並列回路と、前記コンデンサとは、前記基板の厚さ方向に直交する第1方向に並んで配置される、付記9Bに記載のレーザ装置。
 付記11B.前記レーザダイオードのアノードから前記レーザダイオードのカソードに向かう方向は前記第1方向と略平行である、付記10Bに記載のレーザ装置。
 付記12B.前記駆動装置が付記4Bに記載の駆動装置であって、
 前記遅延部と、前記波形整形部と、前記演算部とは、前記厚さ方向および前記第1方向に直交する第2方向に並んでいる、付記10B又は付記11Bに記載のレーザ装置。
 付記13B.前記基板は、第1配線層および第2配線層を含む積層基板であり、前記第2配線層はグラウンド層として機能し、前記第1配線層と前記第2配線層との間隔が、200μm以下である、付記10B~付記12Bのいずれか1つに記載のレーザ装置。
 付記14B.前記第2配線層において、信号系のグラウンドと電源系のグラウンドとが共通化されている、付記13Bに記載のレーザ装置。
 付記15B.付記9B~14Bのいずれか1つに記載のレーザ装置を備える、レーザレーダ装置。
 付記16B.付記15Bに記載のレーザレーダ装置を備える、車両。
The configuration provided based on the second aspect includes the embodiments described in Appendix 1B-16B below.
Appendix 1 B. A drive device that controls the drive of a laser diode.
Switching element and
A control unit that controls the switching element on / off,
A rectifying element in which the anode and cathode are connected in parallel to the laser diode in opposite directions,
A capacitor that is charged when the switching element is off, and a capacitor that forms a closed circuit with the switching element, the laser diode, and the rectifying element when the switching element is on.
With
The control unit is a drive device that shortens the on-time of the switching element to less than half of the resonance period of the closed circuit.
The parallel connection between the laser diode and the rectifying element is not limited to the parallel connection between the laser diode only and the rectifying element only, and the parallel connection between the circuit including the laser diode and the rectifying element only. It may be a parallel connection of only the laser diode and the circuit including the rectifying element, or a parallel connection of the circuit including the laser diode and the circuit including the rectifying element.
Appendix 2 B. The control unit makes the on-time of the switching element shorter than the period from the timing when the switching element is switched from off to on to the second timing when the resonance current of the closed circuit becomes half of the maximum value. The drive device described in.
Appendix 3B.
The driving device according to Appendix 1B or Appendix 2B, wherein the control unit sets the on-time of the switching element to one-fourth or more of the resonance period of the closed circuit.
Appendix 4 B. The control unit
A delay unit that delays a signal based on the first pulse signal to generate a delay signal,
A waveform shaping unit that shapes the waveform of the delay signal and generates a second pulse signal,
A calculation unit that generates a third pulse signal having a pulse width shorter than that of the first pulse signal by a calculation using the first pulse signal and the second pulse signal.
With
The drive device according to any one of Appendix 1B to 3B, which controls on / off of the switching element based on the third pulse signal.
Appendix 5 B. The driving device according to Appendix 4B, wherein the pulse width of the first pulse signal is at least half of the resonance period of the closed circuit.
Appendix 6 B. The drive device according to any one of Appendix 1B to 5B, further comprising a shunt resistor for detecting a current flowing through the laser diode, wherein the closed circuit includes the shunt resistor.
Appendix 7 B. The driving device according to Appendix 6B, wherein the shunt resistor includes a plurality of resistance elements connected in parallel.
Appendix 8 B. The plurality of resistance elements include a first resistance element and a second resistance element having the same length and adjacent to each other, and the distance between the first resistance element and the second resistance element is 2 having the same length. The drive device according to Appendix 7B, which is equal to or greater than the value obtained by dividing the multiple by the number of napiers.
Appendix 9B. The drive device according to any one of Appendix 1B to 8B, and
With the laser diode
A laser device.
Appendix 10 B.
With more boards
The laser device according to Appendix 9B, wherein the switching element, the parallel circuit including the rectifying element and the laser diode, and the capacitor are arranged side by side in the first direction orthogonal to the thickness direction of the substrate.
Appendix 11B. The laser apparatus according to Appendix 10B, wherein the direction from the anode of the laser diode to the cathode of the laser diode is substantially parallel to the first direction.
Appendix 12 B. The drive device is the drive device described in Appendix 4B.
The laser device according to Appendix 10B or Appendix 11B, wherein the delay unit, the waveform shaping unit, and the calculation unit are arranged in a second direction orthogonal to the thickness direction and the first direction.
Appendix 13B. The substrate is a laminated substrate including a first wiring layer and a second wiring layer, the second wiring layer functions as a ground layer, and the distance between the first wiring layer and the second wiring layer is 200 μm or less. The laser device according to any one of Supplementary note 10B to Supplementary note 12B.
Appendix 14B. The laser device according to Appendix 13B, wherein the ground of the signal system and the ground of the power supply system are shared in the second wiring layer.
Appendix 15 B. A laser radar device including the laser device according to any one of Appendix 9B to 14B.
Appendix 16 B. A vehicle comprising the laser radar device according to Appendix 15B.
 <図14~図24における符号>
   1 レーザ装置
   2 レーザダイオード駆動装置
   12 遅延部
   13 波形整形部
   14 演算部
   C1 コンデンサ
   CNT1 制御部
   D1 ダイオード
   LD1 レーザダイオード
   R1 シャント抵抗
   RE1 抵抗素子
   Q1 NMOSトランジスタ
   X1 レーザレーダ装置
   Y1 車両
<Code in FIGS. 14 to 24>
1 Laser device 2 Laser diode drive device 12 Delay section 13 Waveform shaping section 14 Calculation section C1 Capacitor CNT1 Control section D1 Diode LD1 Laser diode R1 Shunt resistance RE1 Resistor Q1 NMOS transistor X1 Laser radar device Y1 Vehicle
 次に、図25~図43を参照して、本開示の第3の側面に基づく実施形態について説明する。なお、図25~図43における参照符号は、図1~13(第1の側面)および図14~24(第2の側面)における参照符号とは独立に付されている。そのため、図25~図43と図1~24とにおいて、同じ符号が異なる要素を指している場合もあれば、同じ(あるいは類似の)要素を指している場合もある。 Next, an embodiment based on the third aspect of the present disclosure will be described with reference to FIGS. 25 to 43. The reference numerals in FIGS. 25 to 43 are attached independently of the reference numerals in FIGS. 1 to 13 (first side surface) and 14 to 24 (second side surface). Therefore, in FIGS. 25 to 43 and 1 to 24, the same reference numerals may refer to different elements, or the same (or similar) elements may be referred to.
 図25~図34は、第3の側面の実施形態に基づく駆動装置A1を示している。駆動装置A1は、レーザダイオードLDの駆動(レーザ光の照射)を制御する。駆動装置A1は、レーザダイオードLDに駆動電流を供給することで、レーザダイオードLDを発光させる。 25 to 34 show the drive device A1 based on the embodiment of the third aspect. The drive device A1 controls the drive (irradiation of laser light) of the laser diode LD. The drive device A1 causes the laser diode LD to emit light by supplying a drive current to the laser diode LD.
 レーザダイオードLDは、いわゆるTO-Canパッケージ型のレーザモジュールに内蔵されていてもよいし、面実装型のレーザモジュールに内蔵されていてもよい。レーザモジュールのパッケージ構造は、これらに限定されない。TO-Canパッケージ型のレーザモジュールでは、レーザダイオードLDの他、フォトダイオードが内蔵されているものとするが、フォトダイオードが内蔵されていなくてもよい。TO-Canパッケージ型のレーザモジュールにおいては、3つのリード端子を備えており、レーザダイオードLDのアノードに導通するリード端子と、フォトダイオードのカソードに導通するリード端子と、レーザダイオードLDのカソードおよびフォトダイオードのアノードに導通するリード端子とがある。フォトダイオードの接続(アノードとカソードとの接続)は反対であってもよい。TO-Canパッケージ型のレーザモジュールにおいては、リード端子の数が、3つではなく、2つであったり、4つであったりしてもよい。 The laser diode LD may be built in a so-called TO-Can package type laser module, or may be built in a surface mount type laser module. The package structure of the laser module is not limited to these. In the TO-Can package type laser module, it is assumed that a photodiode is built in in addition to the laser diode LD, but the photodiode may not be built in. The TO-Can package type laser module is provided with three lead terminals, that is, a lead terminal that conducts to the anode of the laser diode LD, a lead terminal that conducts to the cathode of the photodiode, and a cathode and photo of the laser diode LD. There is a lead terminal that conducts to the anode of the diode. The photodiode connections (anode-cathode connections) may be reversed. In the TO-Can package type laser module, the number of lead terminals may be two or four instead of three.
 駆動装置A1の回路構成例について、図25を参照して説明する。図25に示すように、駆動装置A1は、スイッチング素子Q1、複数のコンデンサC1、複数のシャント抵抗R1、帰還ダイオードD1、ドライブ回路DR、2つの抵抗器R2、パルス生成回路PG、複数のコネクタ端子T1~T3、接続端子T4、および、2つの電源部PS1,PS2を備えている。図25には、駆動装置A1によって駆動制御されるレーザダイオードLDも示されている。なお、図25に示す構成も、上述した第1の側面に係る構成と同様の特徴を有している。すなわち、図25に示すレーザダイオード駆動装置A1は、導通状態と遮断状態とが切り替わるスイッチング素子(Q1)と、コンデンサ(C1)と、第1ダイオード(D1)と、電源電圧が供給される入力端子(VLD参照)と、を備えている。前記コンデンサ(C1)は、第1端(下端)がレーザダイオード(LD1)のカソードに接続され、第2端(上端)が前記スイッチング素子(Q1)に接続されている。前記第1ダイオード(D1)は、アノードが前記コンデンサ(C1)の前記第1端(下端)と前記レーザダイオード(LD1)のカソードとの接続点に接続されている。前記入力端子(VLD参照)は、前記コンデンサ(C1)の前記第2端(上端)と前記スイッチング素子(Q1)との接続点に接続されている。したがって、第1の側面について上述した技術的効果は、図25に示す構成(第3の側面)においても奏される。また逆に、以下で述べる第3の側面に係る構成を第1の側面に係る駆動装置に適用することも可能である。 An example of the circuit configuration of the drive device A1 will be described with reference to FIG. As shown in FIG. 25, the drive device A1 includes a switching element Q1, a plurality of capacitors C1, a plurality of shunt resistors R1, a feedback diode D1, a drive circuit DR, two resistors R2, a pulse generation circuit PG, and a plurality of connector terminals. It includes T1 to T3, a connection terminal T4, and two power supply units PS1 and PS2. FIG. 25 also shows a laser diode LD that is driven and controlled by the driving device A1. The configuration shown in FIG. 25 also has the same characteristics as the configuration according to the first aspect described above. That is, the laser diode driving device A1 shown in FIG. 25 has a switching element (Q1) that switches between a conduction state and a cutoff state, a capacitor (C1), a first diode (D1), and an input terminal to which a power supply voltage is supplied. (See VLD) and. The first end (lower end) of the capacitor (C1) is connected to the cathode of the laser diode (LD1), and the second end (upper end) is connected to the switching element (Q1). The anode of the first diode (D1) is connected to a connection point between the first end (lower end) of the capacitor (C1) and the cathode of the laser diode (LD1). The input terminal (see VLD) is connected to a connection point between the second end (upper end) of the capacitor (C1) and the switching element (Q1). Therefore, the above-mentioned technical effect on the first aspect is also exhibited in the configuration (third aspect) shown in FIG. On the contrary, it is also possible to apply the configuration according to the third aspect described below to the drive device according to the first aspect.
 スイッチング素子Q1は、図25に示すように、たとえばMOSFET(Metal Oxide Semiconductor Field Effect Transistor:電界効果トランジスタ)である。スイッチング素子Q1は、MOSFETに限定されず、その他のトランジスタであってもよい。スイッチング素子Q1は、半導体材料から構成される。当該半導体材料は、たとえばGaN(窒化ガリウム)である。当該半導体材料は、GaNに限定されず、Si(ケイ素)、SiC(炭化ケイ素)、GaAs(ヒ化ガリウム)、あるいは、Ga23(酸化ガリウム)などであってもよい。 As shown in FIG. 25, the switching element Q1 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The switching element Q1 is not limited to the MOSFET, and may be another transistor. The switching element Q1 is made of a semiconductor material. The semiconductor material is, for example, GaN (gallium nitride). The semiconductor material is not limited to GaN, and may be Si (silicon), SiC (silicon carbide), GaAs (gallium arsenide), Ga 2 O 3 (gallium oxide), or the like.
 スイッチング素子Q1は、図25に示すように、ドレインが各コンデンサC1に接続され、ソースが接地端GNDに接続され、ゲートがドライブ回路DRに接続されている。接地端GNDは、基準電位を与える。スイッチング素子Q1は、ドライブ回路DRからゲートに駆動信号が入力され、当該駆動信号に応じて、導通状態と遮断状態とが切り替わる。以下において、導通状態と遮断状態とが切り替わる動作を「スイッチング動作」という場合がある。導通状態は、ドレイン-ソース間に電流が流れる状態であり、遮断状態は、ドレイン-ソース間に電流が流れない状態である。駆動信号は、たとえばオン信号とオフ信号とが交互に切り替わるパルス波である。スイッチング素子Q1は、たとえば、駆動信号がオン信号の時に、導通状態となり、駆動信号がオフ信号の時に、遮断状態となる。 As shown in FIG. 25, the switching element Q1 has a drain connected to each capacitor C1, a source connected to the ground terminal GND, and a gate connected to the drive circuit DR. The ground terminal GND gives a reference potential. A drive signal is input to the gate of the switching element Q1 from the drive circuit DR, and the conduction state and the cutoff state are switched according to the drive signal. In the following, an operation of switching between a conduction state and a cutoff state may be referred to as a “switching operation”. The conductive state is a state in which a current flows between the drain and the source, and the cutoff state is a state in which no current flows between the drain and the source. The drive signal is, for example, a pulse wave in which an on signal and an off signal are alternately switched. For example, the switching element Q1 is in a conductive state when the drive signal is an on signal, and is in a cutoff state when the drive signal is an off signal.
 複数のコンデンサC1は、図25に示すように、互いに並列に接続されている。各コンデンサC1は、第1端C11がレーザダイオードLDのカソードに接続され、第2端C12がスイッチング素子Q1のドレインに接続されている。また、各コンデンサC1の第1端C11は、帰還ダイオードD1のアノードにも接続されている。各コンデンサC1(第2端C12)は、電源部PS1に接続されており、電源部PS1から電源電圧VLDが印加される。本実施形態では、10個のコンデンサC1が並列接続された場合を説明するが、コンデンサC1の数はこれに限定されない。 As shown in FIG. 25, the plurality of capacitors C1 are connected in parallel with each other. In each capacitor C1, the first end C11 is connected to the cathode of the laser diode LD, and the second end C12 is connected to the drain of the switching element Q1. Further, the first end C11 of each capacitor C1 is also connected to the anode of the feedback diode D1. Each capacitor C1 (second end C12) is connected to the power supply unit PS1, and the power supply voltage VLD is applied from the power supply unit PS1. In the present embodiment, the case where 10 capacitors C1 are connected in parallel will be described, but the number of capacitors C1 is not limited to this.
 複数のシャント抵抗R1は、図25に示すように、互いに並列に接続されている。各シャント抵抗R1は、第1端R11が帰還ダイオードD1のカソードおよびレーザダイオードLDのアノードに接続され、第2端R12が接地端GNDに接続されている。本実施形態では、3つのシャント抵抗R1が並列接続された場合を説明するが、シャント抵抗R1の数はこれに限定されない。複数のシャント抵抗R1は、レーザダイオードLDの駆動電流をモニターするために接続されている。シャント抵抗R1によってモニターする電流値は、コネクタ端子T3から検出可能である。 As shown in FIG. 25, the plurality of shunt resistors R1 are connected in parallel with each other. In each shunt resistor R1, the first end R11 is connected to the cathode of the feedback diode D1 and the anode of the laser diode LD, and the second end R12 is connected to the ground end GND. In the present embodiment, the case where three shunt resistors R1 are connected in parallel will be described, but the number of shunt resistors R1 is not limited to this. A plurality of shunt resistors R1 are connected to monitor the drive current of the laser diode LD. The current value monitored by the shunt resistor R1 can be detected from the connector terminal T3.
 帰還ダイオードD1は、図25に示すように、アノードがレーザダイオードLDのカソードに接続され、カソードがレーザダイオードLDのアノードに接続されている。また、帰還ダイオードD1は、アノードが各コンデンサC1の第1端C11に接続され、カソードが各シャント抵抗R1の第1端R11に接続されている。帰還ダイオードD1は、図25に示すように、アノードが各コンデンサC1の第1端C11とレーザダイオードLDのカソードとの接続点に接続されており、カソードが各シャント抵抗R1の第1端R11とレーザダイオードLDのアノードの接続点に接続されている。図25に示す例においては、帰還ダイオードD1として、PN接合のダイオード(たとえばファーストリカバリダイオード)を用いているが、ショットキーバリアダイオードを用いてもよい。 As shown in FIG. 25, the feedback diode D1 has an anode connected to the cathode of the laser diode LD and a cathode connected to the anode of the laser diode LD. Further, in the feedback diode D1, the anode is connected to the first end C11 of each capacitor C1, and the cathode is connected to the first end R11 of each shunt resistor R1. As shown in FIG. 25, in the feedback diode D1, the anode is connected to the connection point between the first end C11 of each capacitor C1 and the cathode of the laser diode LD, and the cathode is connected to the first end R11 of each shunt resistor R1. It is connected to the connection point of the anode of the laser diode LD. In the example shown in FIG. 25, a PN junction diode (for example, a fast recovery diode) is used as the feedback diode D1, but a Schottky barrier diode may be used.
 パルス生成回路PGは、スイッチング素子Q1のスイッチング動作を制御するためのパルス信号を生成する。パルス生成回路PGは、コネクタ端子T1から制御信号が入力され、当該制御信号に基づき、パルス信号を生成する。パルス生成回路PGは、生成したパルス信号をドライブ回路DRに出力する。本実施形態におけるパルス信号は、たとえば、周波数が10kHz、デューティ比が0.005%である矩形波である。また、このパルス信号は、パルス幅が5nsecであり、パルスの立上り時間が1nsecである。駆動装置A1においては、レーザダイオードLDを5nsec以下で駆動させるパルス信号が生 成される。なお、上記パルス信号の各パラメータは一例であってこれに限定されない。 The pulse generation circuit PG generates a pulse signal for controlling the switching operation of the switching element Q1. The pulse generation circuit PG receives a control signal from the connector terminal T1 and generates a pulse signal based on the control signal. The pulse generation circuit PG outputs the generated pulse signal to the drive circuit DR. The pulse signal in this embodiment is, for example, a square wave having a frequency of 10 kHz and a duty ratio of 0.005%. Further, this pulse signal has a pulse width of 5 nsec and a pulse rise time of 1 nsec. In the drive device A1, a pulse signal for driving the laser diode LD in 5 nsec or less is generated. It should be noted that each parameter of the pulse signal is an example and is not limited to this.
 ドライブ回路DRは、スイッチング素子Q1を駆動させる(スイッチング動作させる)ための駆動信号を生成する。ドライブ回路DRは、パルス生成回路PGからパルス信号が入力され、当該パルス信号に基づき、駆動信号を生成する。駆動信号は、たとえば、パルス信号をスイッチング素子Q1の駆動に必要な電圧まで昇圧した信号である。ドライブ回路DRは、ドライブIC9を含んでおり、駆動信号はこのドライブIC9により生成される。 The drive circuit DR generates a drive signal for driving (switching operation) the switching element Q1. In the drive circuit DR, a pulse signal is input from the pulse generation circuit PG, and a drive signal is generated based on the pulse signal. The drive signal is, for example, a signal obtained by boosting the pulse signal to a voltage required for driving the switching element Q1. The drive circuit DR includes a drive IC 9, and a drive signal is generated by the drive IC 9.
 2つの抵抗器R2はそれぞれ、図25に示すように、ドライブIC9とスイッチング素子Q1のゲートとの間に接続されている。ドライブICから出力される駆動信号は、いずれかの抵抗器R2を介して、スイッチング素子Q1のゲートに入力される。各抵抗器R2は、いわゆるゲート抵抗である。各抵抗器R2の抵抗値に応じて、スイッチング素子Q1に入力される電流値が設定される。また、各抵抗器R2は、スイッチング素子Q1のスイッチング速度を制御する。 As shown in FIG. 25, each of the two resistors R2 is connected between the drive IC 9 and the gate of the switching element Q1. The drive signal output from the drive IC is input to the gate of the switching element Q1 via either resistor R2. Each resistor R2 is a so-called gate resistor. The current value input to the switching element Q1 is set according to the resistance value of each resistor R2. Further, each resistor R2 controls the switching speed of the switching element Q1.
 コネクタ端子T1は、電源電圧VLDの入力端子である。コネクタ端子T1には、駆動装置A1の外部に設けられた直流電源(外部電源)が接続され、この外部電源から電源電圧VLDが供給される。電源電圧VLDは、レーザダイオードLDの駆動に利用され、たとえば3V以上100V以下である。また、コネクタ端子T1は、制御信号の入力端子でもある。コネクタ端子T1は、たとえばプラグ型の端子である。 The connector terminal T1 is an input terminal for the power supply voltage VLD. A DC power supply (external power supply) provided outside the drive device A1 is connected to the connector terminal T1, and a power supply voltage VLD is supplied from this external power supply. The power supply voltage VLD is used to drive the laser diode LD, and is, for example, 3 V or more and 100 V or less. The connector terminal T1 is also an input terminal for a control signal. The connector terminal T1 is, for example, a plug-type terminal.
 各コネクタ端子T2,T3は、たとえば同軸ケーブルが接続されうるジャック型の端子である。 Each connector terminal T2 and T3 is a jack type terminal to which a coaxial cable can be connected, for example.
 接続端子T4は、レーザモジュール(レーザダイオードLD)を接続するための端子である。 The connection terminal T4 is a terminal for connecting a laser module (laser diode LD).
 電源部PS1は、図25に示すように、コネクタ端子T1と複数のコンデンサC1との間に接続される。電源部PS1は、電解コンデンサC2、逆流防止ダイオードD3、リアクトルL1、2つの充電抵抗R3などを含んでいる。電解コンデンサC2は、いわゆるバイパスコンデンサであって、入力される電圧(電源電圧VLD)を安定させる。逆流防止ダイオードD3は、各コンデンサC1側から外部電源(コネクタ端子T1)側に電流が流れることを防止する。リアクトルL1は、入力される電圧を昇圧する。各充電抵抗R3は、外部電源(コネクタ端子T1)側から各コンデンサC1に向かう電流の電流量を調整する。これらは適宜必要に応じて接続すればよい。 As shown in FIG. 25, the power supply unit PS1 is connected between the connector terminal T1 and the plurality of capacitors C1. The power supply unit PS1 includes an electrolytic capacitor C2, a backflow prevention diode D3, a reactor L1, two charging resistors R3, and the like. The electrolytic capacitor C2 is a so-called bypass capacitor and stabilizes the input voltage (power supply voltage VLD). The backflow prevention diode D3 prevents current from flowing from each capacitor C1 side to the external power supply (connector terminal T1) side. The reactor L1 boosts the input voltage. Each charging resistor R3 adjusts the amount of current of the current from the external power supply (connector terminal T1) side toward each capacitor C1. These may be connected as needed.
 電源部PS2は、動作電圧V1を発生させる。動作電圧V1は、主にパルス生成回路PGを構成する各電子部品の駆動に利用される。動作電圧V1は、たとえば3.3Vであるが、これに限定されない。 The power supply unit PS2 generates an operating voltage V1. The operating voltage V1 is mainly used for driving each electronic component constituting the pulse generation circuit PG. The operating voltage V1 is, for example, 3.3 V, but is not limited thereto.
 その他、駆動装置A1は、その回路構成において、図25に示すように、複数のテストポイントTP1~TP6および複数のグラウンドポイントGP1~GP4を備えている。各テストポイントTP1~TP6は、信号検出用の端子である。各グラウンドポイントGP1~GP4は、基準電位に接地される端子である。 In addition, as shown in FIG. 25, the drive device A1 includes a plurality of test points TP1 to TP6 and a plurality of ground points GP1 to GP4 in its circuit configuration. Each test point TP1 to TP6 is a terminal for signal detection. Each ground point GP1 to GP4 is a terminal grounded to a reference potential.
 駆動装置A1によるレーザダイオードLDの駆動制御(発光動作)について、図26および図27を参照して、説明する。図26および図27は、図25に示す駆動装置A1の回路構成から、レーザダイオードLDの発光動作における主要な電子部品を抜粋した図である。図26および図27においては、複数のコンデンサC1および複数のシャント抵抗R1をそれぞれ1つずつ示している。また、図26および図27に示す直流電源は、図25に示すコネクタ端子T1に接続された外部電源と、電源部PS1とに相当する。図26は、スイッチング素子Q1が遮断状態であるときを示しており、図27は、スイッチング素子Q1が導通状態であるときを示している。 The drive control (light emission operation) of the laser diode LD by the drive device A1 will be described with reference to FIGS. 26 and 27. 26 and 27 are diagrams in which main electronic components in the light emitting operation of the laser diode LD are extracted from the circuit configuration of the drive device A1 shown in FIG. 25. In FIGS. 26 and 27, a plurality of capacitors C1 and a plurality of shunt resistors R1 are shown one by one. The DC power supply shown in FIGS. 26 and 27 corresponds to the external power supply connected to the connector terminal T1 shown in FIG. 25 and the power supply unit PS1. FIG. 26 shows the case where the switching element Q1 is in the cutoff state, and FIG. 27 shows the case where the switching element Q1 is in the conductive state.
 スイッチング素子Q1を遮断状態にすると、図26に示すように、直流電源から各コンデンサC1に電流が流れる(破線で示す電流経路参照)。この電流により、各コンデンサC1の第2端C12に電荷がたまり、各コンデンサC1が充電される。このとき、直流電源の電源電圧がVLDとすると、各コンデンサC1の第2端C12の電位は、電源電圧VLDとなる。各コンデンサC1が満充電になると、この電流は流れなくなる。スイッチング素子Q1が遮断状態のとき、レーザダイオードLDには電流が流れず、レーザダイオードLDは発光しない。 When the switching element Q1 is cut off, a current flows from the DC power supply to each capacitor C1 as shown in FIG. 26 (see the current path shown by the broken line). Due to this current, electric charge is accumulated in the second end C12 of each capacitor C1 and each capacitor C1 is charged. At this time, assuming that the power supply voltage of the DC power supply is VLD, the potential of the second end C12 of each capacitor C1 is the power supply voltage VLD. When each capacitor C1 is fully charged, this current stops flowing. When the switching element Q1 is in the cutoff state, no current flows through the laser diode LD and the laser diode LD does not emit light.
 一方、スイッチング素子Q1を導通状態にすると、図27に示すように、スイッチング素子Q1を介して、各コンデンサC1の第2端C12が接地端GNDに導通する。これにより、各コンデンサC1に蓄積された電荷がスイッチング素子Q1に流れ込み、各コンデンサC1からスイッチング素子Q1を介して接地端GNDに電流が流れる。そして、接地端GNDから、各シャント抵抗R1を介して、レーザダイオードLDに順方向電流が流れ、レーザダイオードLDが発光する(破線で示す電流経路LP参照)。各コンデンサC1が完全に放電されると、この電流が流れなくなり、レーザダイオードLDは発光しなくなる。 On the other hand, when the switching element Q1 is brought into a conductive state, as shown in FIG. 27, the second end C12 of each capacitor C1 conducts to the ground end GND via the switching element Q1. As a result, the electric charge accumulated in each capacitor C1 flows into the switching element Q1, and a current flows from each capacitor C1 to the ground terminal GND via the switching element Q1. Then, a forward current flows from the grounded end GND to the laser diode LD through each shunt resistor R1, and the laser diode LD emits light (see the current path LP shown by the broken line). When each capacitor C1 is completely discharged, this current stops flowing and the laser diode LD does not emit light.
 駆動装置A1のモジュール構成について、図28~図35を参照して説明する。説明の便宜上、図28~図35において、互いに直交する3つの方向(x方向、y方向、z方向)を適宜参照する。z方向は、駆動装置A1の厚さ方向である。 The module configuration of the drive device A1 will be described with reference to FIGS. 28 to 35. For convenience of explanation, in FIGS. 28 to 35, three directions (x direction, y direction, and z direction) orthogonal to each other are appropriately referred to. The z direction is the thickness direction of the drive device A1.
 駆動装置A1は回路基板10と、複数の電子部品と、複数の端子とを備えている。複数の電子部品および複数の端子は、図25に示す回路構成における複数の電子部品および複数の端子に対応しており、回路基板10に実装されている。 The drive device A1 includes a circuit board 10, a plurality of electronic components, and a plurality of terminals. The plurality of electronic components and the plurality of terminals correspond to the plurality of electronic components and the plurality of terminals in the circuit configuration shown in FIG. 25, and are mounted on the circuit board 10.
 図28は、回路基板10上の部品レイアウトおよびランドパターンを示している。図28においては、複数の電子部品および複数の端子を想像線(二点鎖線)で示している。図29は、図28の一部を拡大した図であって、要部を抜き出している。図28および図29に示す例では、駆動装置A1は、図25に示す回路構成の接続端子T4として、2つのソケット端子T41,T42およびパッド端子T43を設けている。接続端子T4として、2つのソケット端子T41,T42およびパッド端子T43のすべてを設ける必要はなく、いずれか1つを設けていればよい。 FIG. 28 shows the component layout and land pattern on the circuit board 10. In FIG. 28, a plurality of electronic components and a plurality of terminals are shown by an imaginary line (dashed line). FIG. 29 is an enlarged view of a part of FIG. 28, and a main part is extracted. In the example shown in FIGS. 28 and 29, the drive device A1 is provided with two socket terminals T41 and T42 and a pad terminal T43 as the connection terminals T4 having the circuit configuration shown in FIG. 25. It is not necessary to provide all of the two socket terminals T41 and T42 and the pad terminal T43 as the connection terminal T4, and it is sufficient to provide any one of them.
 回路基板10は、図28に示すように、平面視において略矩形状である。回路基板10の厚さ方向は、z方向と一致する。回路基板10は、たとえば、x方向の寸法が70.0 mmであり、y方向の寸法が45.0mmである。回路基板10の平面視寸法は、これに限定されず、適宜変更されうる。 As shown in FIG. 28, the circuit board 10 has a substantially rectangular shape in a plan view. The thickness direction of the circuit board 10 coincides with the z direction. The circuit board 10 has, for example, a dimension of 70.0 mm in the x direction and a dimension of 45.0 mm in the y direction. The plan view dimensions of the circuit board 10 are not limited to this, and can be changed as appropriate.
 回路基板10は、たとえば積層基板であり、z方向において、互いに絶縁層を介して積層された複数の配線層Ly1~Ly4を含んでいる。図30~図33はそれぞれ、各配線層Ly1~Ly4を示す平面図である。図30~図33に示すように、配線層Ly1は配線パターン21で形成され、配線層Ly2は配線パターン22で形成され、配線層Ly3は配線パターン23で形成され、配線層Ly4は配線パターン24で形成されている。図30~図33において、各配線パターン21~24を黒色で塗りつぶしている。 The circuit board 10 is, for example, a laminated board, and includes a plurality of wiring layers Ly1 to Ly4 that are laminated with each other via an insulating layer in the z direction. 30 to 33 are plan views showing the respective wiring layers Ly1 to Ly4, respectively. As shown in FIGS. 30 to 33, the wiring layer Ly1 is formed by the wiring pattern 21, the wiring layer Ly2 is formed by the wiring pattern 22, the wiring layer Ly3 is formed by the wiring pattern 23, and the wiring layer Ly4 is formed by the wiring pattern 24. Is formed of. In FIGS. 30 to 33, the wiring patterns 21 to 24 are painted in black.
 配線層Ly1は、回路基板10における第1層であり、最上層である。配線層Ly1上に、各電子部品が搭載される。配線層Ly1の上面には、たとえばはんだ層が形成されており、このはんだ層は、部分的にレジスト膜(図示略)で覆われている。このレジスト膜から露出したはんだ層が、図28に示すランドパターンとなる。このランドパターンは、図29に示すように、5つの抵抗用ランド20を含んでいる。5つの抵抗用ランド20はそれぞれ、各シャント抵抗R1が接合されうる。配線層Ly4は、回路基板10における第4層であり、最下層である。配線層Ly4の下面には、たとえば、はんだ層が形成されており、このはんだ層は、部分的にレジスト膜(図示略)で覆われている。各配線層Ly2,Ly3は、回路基板10における中間層である。配線層Ly2は、回路基板10における第2層であり、配線層Ly3は、回路基板10における第3層である。配線層Ly2は、z方向において、配線層Ly1と配線層Ly3とに挟まれており、配線層Ly3は、z方向において、配線層Ly2と配線層Ly4とに挟まれている。 The wiring layer Ly1 is the first layer and the uppermost layer in the circuit board 10. Each electronic component is mounted on the wiring layer Ly1. For example, a solder layer is formed on the upper surface of the wiring layer Ly1, and the solder layer is partially covered with a resist film (not shown). The solder layer exposed from the resist film forms the land pattern shown in FIG. 28. This land pattern includes five resistance lands 20 as shown in FIG. Each of the five resistor lands 20 may be joined with each shunt resistor R1. The wiring layer Ly4 is the fourth layer and the lowest layer in the circuit board 10. For example, a solder layer is formed on the lower surface of the wiring layer Ly4, and the solder layer is partially covered with a resist film (not shown). The wiring layers Ly2 and Ly3 are intermediate layers in the circuit board 10. The wiring layer Ly2 is the second layer on the circuit board 10, and the wiring layer Ly3 is the third layer on the circuit board 10. The wiring layer Ly2 is sandwiched between the wiring layer Ly1 and the wiring layer Ly3 in the z direction, and the wiring layer Ly3 is sandwiched between the wiring layer Ly2 and the wiring layer Ly4 in the z direction.
 配線パターン22(配線層Ly2)は、基準電位に接地されるGND(グラウンド)パターンである。配線パターン22は、図31に示すように、ベタパターンである。配線パターン23(配線層Ly3)は、電源パターンである。配線パターン23は、図32に示すように、複数の領域に分割されており、各領域で印加される電圧の値が異なる。配線パターン24(配線層Ly4)は、主に、基準電位に接地されるGNDパターンである。ただし、配線パターン24の一部(図33のパターン241)は、電源パターンである。 The wiring pattern 22 (wiring layer Ly2) is a GND (ground) pattern that is grounded to the reference potential. As shown in FIG. 31, the wiring pattern 22 is a solid pattern. The wiring pattern 23 (wiring layer Ly3) is a power supply pattern. As shown in FIG. 32, the wiring pattern 23 is divided into a plurality of regions, and the value of the voltage applied in each region is different. The wiring pattern 24 (wiring layer Ly4) is mainly a GND pattern grounded at a reference potential. However, a part of the wiring pattern 24 (pattern 241 in FIG. 33) is a power supply pattern.
 回路基板10において、複数の配線層Ly1~Ly4の各厚さ(z方向寸法)は、たとえば115μm程度である。駆動装置A1と異なる駆動装置では、一般的に、配線層の厚さがたとえば350μmや700μmであるので、駆動装置A1における各配線層Ly1~Ly4の厚さは薄い。複数の配線層Ly1~Ly4のうち、配線層Ly1のみ、厚さが115μm程度で、他の配線層Ly2~Ly4の厚さは、一般的な350μmや700μm程度であってもよい。 In the circuit board 10, each thickness (dimension in the z direction) of the plurality of wiring layers Ly1 to Ly4 is, for example, about 115 μm. In a drive device different from the drive device A1, the thickness of the wiring layer is generally 350 μm or 700 μm, for example, so that the thickness of each wiring layer Ly1 to Ly4 in the drive device A1 is thin. Of the plurality of wiring layers Ly1 to Ly4, only the wiring layer Ly1 has a thickness of about 115 μm, and the other wiring layers Ly2 to Ly4 may have a general thickness of about 350 μm or 700 μm.
 図28に示すように、回路基板10には、複数の貫通電極30が形成されている。複数の貫通電極30は、回路基板10をz方向に貫通する。複数の配線層Ly1~Ly4(複数の配線パターン21~24)は、複数の貫通電極30によって互いに導通する。図28においては、複数の貫通電極30の一部のみに符号を付けている。 As shown in FIG. 28, a plurality of through electrodes 30 are formed on the circuit board 10. The plurality of through electrodes 30 penetrate the circuit board 10 in the z direction. The plurality of wiring layers Ly1 to Ly4 (plurality of wiring patterns 21 to 24) are electrically connected to each other by the plurality of through electrodes 30. In FIG. 28, only a part of the plurality of through electrodes 30 is designated.
 図28に示すように、回路基板10は、平面視において、複数の貫通電極30が密に配置された2つの集合領域AG1,AG2を含んでいる。各集合領域AG1,AG2に配置された各貫通電極30は、少なくとも配線層Ly1と配線層Ly2とを導通させ、配線層Ly3には導通していない。各集合領域AG1,AG2に配置された各貫通電極30は、さらに配線層Ly4に導通していてもよいし、配線層Ly4に導通していなくてもよい。ただし、配線層Ly4はGNDパターンであり、配線層Ly4に導通しているほうが好ましい。集合領域AG1は、シャント抵抗群R0よりもy2方向に位置し、シャント抵抗群R0に隣接する。集合領域AG2は、スイッチング素子Q1よりもy1方向に位置し、スイッチング素子Q1に隣接する。 As shown in FIG. 28, the circuit board 10 includes two aggregation regions AG1 and AG2 in which a plurality of through electrodes 30 are densely arranged in a plan view. Each through electrode 30 arranged in each of the gathering regions AG1 and AG2 conducts at least the wiring layer Ly1 and the wiring layer Ly2, and does not conduct to the wiring layer Ly3. The through silicon vias 30 arranged in the gathering regions AG1 and AG2 may or may not be electrically connected to the wiring layer Ly4. However, the wiring layer Ly4 has a GND pattern, and it is preferable that the wiring layer Ly4 is electrically connected to the wiring layer Ly4. The gathering region AG1 is located in the y2 direction with respect to the shunt resistance group R0 and is adjacent to the shunt resistance group R0. The collecting region AG2 is located in the y1 direction with respect to the switching element Q1 and is adjacent to the switching element Q1.
 図28および図30~図33に示すように、回路基板10には、平面視における四隅にそれぞれ貫通孔HLが形成されている。各貫通孔HLは、回路基板10をz方向に貫通している。各貫通孔HLは、駆動装置A1を支持部材に固定するために設けられており、ボルトなどの締結具などが挿通されうる。各貫通孔HLは、平面視における中央が、回路基板10の四隅のそれぞれから、たとえばx方向に3.5mm、y方向に3.5mmの位置にそれぞれ重なるように配置されている。 As shown in FIGS. 28 and 30 to 33, through holes HL are formed at each of the four corners in the plan view of the circuit board 10. Each through hole HL penetrates the circuit board 10 in the z direction. Each through hole HL is provided to fix the drive device A1 to the support member, and a fastener such as a bolt can be inserted therethrough. Each through hole HL is arranged so that the center in a plan view overlaps each of the four corners of the circuit board 10 at a position of, for example, 3.5 mm in the x direction and 3.5 mm in the y direction.
 図28および図29に示すように、回路基板10は、平面視において、2つの実装領域M1,M2を含んでいる。各実装領域M1,M2には、レーザモジュール(レーザダイオードLD)が実装されうる。本実施形態においては、各実装領域M1,M2には、各ソケット端子T41,T42が取り付けられており、各ソケット端子T41,T42を介して、TO-Canパッケージ型のレーザモジュールが実装される。 As shown in FIGS. 28 and 29, the circuit board 10 includes two mounting regions M1 and M2 in a plan view. A laser module (laser diode LD) can be mounted in each of the mounting regions M1 and M2. In the present embodiment, the socket terminals T41 and T42 are attached to the mounting areas M1 and M2, and the TO-Can package type laser module is mounted via the socket terminals T41 and T42.
 図29に示すように、各実装領域M1,M2には、3つの端子接続部Ma,Mb,Mcを含んでいる。各端子接続部Ma,Mb,Mcは、TO-Canパッケージ型のレーザモジュールの各リード端子が接続される。端子接続部Maには、レーザダイオードLDのアノードに導通するリード端子が接続される。端子接続部Mbには、フォトダイオードのカソードに導通するリード端子が接続される。端子接続部Mcには、レーザダイオードLDのカソードおよびフォトダイオードのアノードに導通するリードが接続される。図29に示す例においては、実装領域M1の各端子接続部Ma,Mb,Mcと実装領域M2の各端子接続部Ma,Mb,Mcとは、平面視寸法が異なっているが、同じであってもよい。TO-Canパッケージ型のレーザモジュールにおいて、リード端子の数が4つの場合、各実装領域M1,M2は、4つの端子接続部を含んでいる。また、リード端子の数が2つの場合、各実装領域M1,M2は、2つの端子接続部を含む構成であってもよいし、3つ以上の端子接続部を含む構成であってもよい。 As shown in FIG. 29, each mounting area M1 and M2 includes three terminal connection portions Ma, Mb, and Mc. Each lead terminal of the TO-Can package type laser module is connected to each terminal connection portion Ma, Mb, Mc. A lead terminal conducting to the anode of the laser diode LD is connected to the terminal connection portion Ma. A lead terminal conducting to the cathode of the photodiode is connected to the terminal connection portion Mb. Leads conducting to the cathode of the laser diode LD and the anode of the photodiode are connected to the terminal connection portion Mc. In the example shown in FIG. 29, the terminal connection portions Ma, Mb, Mc in the mounting area M1 and the terminal connection portions Ma, Mb, Mc in the mounting area M2 are different in plan view dimensions, but are the same. You may. In the TO-Can package type laser module, when the number of lead terminals is four, each mounting area M1 and M2 includes four terminal connection portions. When the number of lead terminals is two, each mounting area M1 and M2 may be configured to include two terminal connecting portions or may be configured to include three or more terminal connecting portions.
 図29に示すように、各実装領域M1,M2において、端子接続部Maと端子接続部Mcとは、y方向に並んでおり、端子接続部Maは端子接続部Mcよりもy1方向に位置する。レーザモジュールがソケット端子T41を介して実装領域M1に実装された場合、レーザダイオードLDのアノードに導通するリード端子と、レーザダイオードLDのカソードに導通するリード端子とが、y方向に並び、レーザダイオードLDのアノードに導通するリード端子が、レーザダイオードLDのカソードに導通するリード端子よりもy1方向に位置する。このことは、レーザモジュールがソケット端子T42を介して実装領域M2に実装された場合も同様である。 As shown in FIG. 29, in each mounting area M1 and M2, the terminal connection portion Ma and the terminal connection portion Mc are aligned in the y direction, and the terminal connection portion Ma is located in the y1 direction with respect to the terminal connection portion Mc. .. When the laser module is mounted in the mounting region M1 via the socket terminal T41, the lead terminal conducting to the anode of the laser diode LD and the lead terminal conducting to the cathode of the laser diode LD are aligned in the y direction, and the laser diode The lead terminal conducting to the anode of the LD is located in the y1 direction with respect to the lead terminal conducting to the cathode of the laser diode LD. This also applies when the laser module is mounted in the mounting area M2 via the socket terminal T42.
 図29に示すように、各実装領域M1,M2において、端子接続部Mbと端子接続部Mcとは、x方向に並んでおり、端子接続部Mcは、端子接続部Mbよりもx1方向に位置する。反対に、端子接続部Mcが、端子接続部Mbよりもx2方向に位置していてもよい。 As shown in FIG. 29, in the mounting areas M1 and M2, the terminal connection portion Mb and the terminal connection portion Mc are aligned in the x direction, and the terminal connection portion Mc is located in the x1 direction with respect to the terminal connection portion Mb. To do. On the contrary, the terminal connection portion Mc may be located in the x2 direction with respect to the terminal connection portion Mb.
 次いで、駆動装置A1のモジュール構成における複数の電子部品および複数の端子について説明する。 Next, a plurality of electronic components and a plurality of terminals in the module configuration of the drive device A1 will be described.
 複数のコンデンサC1は、図28および図29に示すように、x方向に並んで配置されている。各コンデンサC1は、2つの端子(第1端C11および第2端C12)がy方向に並んでいる。駆動装置A1においては、第2端C12が第1端C11よりもy2方向に位置する。複数のコンデンサC1の第1端C11同士は、配線層Ly1の配線パターン21によって、互いに導通しており、複数のコンデンサC1の第2端C12同士は、配線層Ly1の配線パターン21によって、互いに導通している。各コンデンサC1は、たとえばチップタイプであるが、リードタイプであってもよい。複数のコンデンサC1は、容量が略同じであり、平面視寸法も略同じである。駆動装置A1のモジュール構成において、複数のコンデンサC1によって、コンデンサ群C0が形成される。 As shown in FIGS. 28 and 29, the plurality of capacitors C1 are arranged side by side in the x direction. In each capacitor C1, two terminals (first end C11 and second end C12) are arranged in the y direction. In the drive device A1, the second end C12 is located in the y2 direction with respect to the first end C11. The first ends C11 of the plurality of capacitors C1 are electrically connected to each other by the wiring pattern 21 of the wiring layer Ly1, and the second ends C12 of the plurality of capacitors C1 are electrically connected to each other by the wiring pattern 21 of the wiring layer Ly1. doing. Each capacitor C1 is, for example, a chip type, but may be a lead type. The capacitances of the plurality of capacitors C1 are substantially the same, and the plan-view dimensions are also substantially the same. In the module configuration of the drive device A1, the capacitor group C0 is formed by the plurality of capacitors C1.
 複数のシャント抵抗R1は、図28および図29に示すように、x方向に並んで配置されている。各シャント抵抗R1は、2つの端子(第1端R11および第2端R12)がy方向に並んでいる。駆動装置A1においては、第1端R11が第2端R12よりもy2方向に位置する。複数のシャント抵抗R1の第1端R11同士は、配線層Ly1の配線パターン21によって、互いに導通しており、複数のシャント抵抗R1の第2端R12同士は、配線層Ly1の配線パターン21によって、互いに導通している。各シャント抵抗R1は、たとえばチップタイプであるが、リードタイプであってもよい。複数のシャント抵抗R1は、抵抗値が略同じであり、平面視寸法も略同じである。各シャント抵抗R1は、たとえば、x方向寸法(図29の寸法Dx)が3.2mmであり、y方向寸法(図29の寸法Dy)が6.4mmである。各シャント抵抗R1の平面視寸法はこれに限定されず、一般的に抵抗値が大きいほど、平面視面積は大きくなる。駆動装置A1のモジュール構成において、複数のシャント抵抗R1によって、シャント抵抗群R0が形成される。 As shown in FIGS. 28 and 29, the plurality of shunt resistors R1 are arranged side by side in the x direction. In each shunt resistor R1, two terminals (first end R11 and second end R12) are arranged in the y direction. In the drive device A1, the first end R11 is located in the y2 direction with respect to the second end R12. The first ends R11 of the plurality of shunt resistors R1 are electrically connected to each other by the wiring pattern 21 of the wiring layer Ly1, and the second ends R12 of the plurality of shunt resistors R1 are connected to each other by the wiring pattern 21 of the wiring layer Ly1. They are conducting with each other. Each shunt resistor R1 is, for example, a chip type, but may be a lead type. The plurality of shunt resistors R1 have substantially the same resistance value, and the plan view dimensions are also substantially the same. Each shunt resistor R1 has, for example, an x-direction dimension (dimension Dx in FIG. 29) of 3.2 mm and a y-direction dimension (dimension D in FIG. 29) of 6.4 mm. The plan view dimension of each shunt resistor R1 is not limited to this, and generally, the larger the resistance value, the larger the plan view area. In the module configuration of the drive device A1, the shunt resistor group R0 is formed by the plurality of shunt resistors R1.
 図29に示すように、シャント抵抗群R0において、x方向に隣り合う2つのシャント抵抗R1の離間距離SD1は、所定の大きさ以上である。駆動装置A1では、この所定の大きさは、1つのシャント抵抗R1のx方向寸法Dxである。つまり、x方向に隣り合う2つのシャント抵抗R1の間には、各シャント抵抗R1と同じ大きさのシャント抵抗が1つ配置可能である。駆動装置A1では、上記離間距離SD1は、たとえば5.0mm程度である。図29に示す例では、シャント抵抗群R0におけるx方向両端に配置された2つシャント抵抗R1の間に、3つのシャント抵抗R1が配置可能な領域があり、この領域のx方向中央に1つのシャント抵抗R1が配置されている。 As shown in FIG. 29, in the shunt resistance group R0, the separation distance SD1 between the two shunt resistors R1 adjacent to each other in the x direction is equal to or larger than a predetermined size. In the drive device A1, this predetermined size is the x-direction dimension Dx of one shunt resistor R1. That is, one shunt resistor having the same magnitude as each shunt resistor R1 can be arranged between two shunt resistors R1 adjacent to each other in the x direction. In the drive device A1, the separation distance SD1 is, for example, about 5.0 mm. In the example shown in FIG. 29, there is a region in which three shunt resistors R1 can be arranged between the two shunt resistors R1 arranged at both ends in the x direction in the shunt resistor group R0, and one in the center of this region in the x direction. A shunt resistor R1 is arranged.
 図29に示すように、駆動装置A1では、3つのシャント抵抗R1の下、および、x方向に隣り合う2つのシャント抵抗R1の間にはそれぞれ、抵抗用ランド20が形成されている。よって、回路基板10には、x方向に並ぶ5つの抵抗用ランド20が形成され、このうちの、x方向両端の抵抗用ランド20とx方向中央の抵抗用ランド20とにシャント抵抗R1が実装されている。このようにして、離間距離SD1を、1つのシャント抵抗R1のx方向寸法Dx以上にしている。 As shown in FIG. 29, in the drive device A1, resistance lands 20 are formed under the three shunt resistors R1 and between the two shunt resistors R1 adjacent to each other in the x direction. Therefore, five resistance lands 20 arranged in the x direction are formed on the circuit board 10, and the shunt resistor R1 is mounted on the resistance lands 20 at both ends in the x direction and the resistance lands 20 in the center of the x direction. Has been done. In this way, the separation distance SD1 is set to be equal to or greater than the x-direction dimension Dx of one shunt resistor R1.
 図28および図29に示すように、コンデンサ群C0とシャント抵抗群R0とは、y方向に並んでいる。y方向において、コンデンサ群C0とシャント抵抗群R0との間には、各実装領域M1,M2(各ソケット端子T41,T42)が配置されている。また、図29に示すように、コンデンサ群C0のx1方向側の端縁は、y方向に見て、シャント抵抗群R0のうち最もx1方向に配置されたシャント抵抗R1に重なり、コンデンサ群C0のx2方向側の端縁は、y方向に見て、シャント抵抗群R0のうち最もx2方向に配置されたシャント抵抗R1に重なる。 As shown in FIGS. 28 and 29, the capacitor group C0 and the shunt resistor group R0 are aligned in the y direction. In the y direction, mounting regions M1 and M2 (socket terminals T41 and T42) are arranged between the capacitor group C0 and the shunt resistor group R0. Further, as shown in FIG. 29, the edge of the capacitor group C0 on the x1 direction side overlaps with the shunt resistance R1 arranged in the x1 direction of the shunt resistance group R0 when viewed in the y direction, and the capacitor group C0 The edge on the x2 direction side overlaps with the shunt resistance R1 arranged in the x2 direction of the shunt resistance group R0 when viewed in the y direction.
 スイッチング素子Q1は、図28に示すように、y方向において、コンデンサ群C0と並んでいる。図28に示す例においては、スイッチング素子Q1は、y方向において、コンデンサ群C0に隣接している。スイッチング素子Q1は、y方向において、コンデンサ群 C0を基準に、シャント抵抗群R0とは反対側に位置する。つまり、スイッチング素子Q1は、コンデンサ群C0よりもy2方向に位置する。スイッチング素子Q1は、y方向に見て、コンデンサ群C0のx方向中央に重なる。これにより、スイッチング素子Q1から各コンデンサC1への導通経路の差が小さくなる。 As shown in FIG. 28, the switching element Q1 is aligned with the capacitor group C0 in the y direction. In the example shown in FIG. 28, the switching element Q1 is adjacent to the capacitor group C0 in the y direction. The switching element Q1 is located on the opposite side of the shunt resistance group R0 with respect to the capacitor group C0 in the y direction. That is, the switching element Q1 is located in the y2 direction with respect to the capacitor group C0. The switching element Q1 overlaps the center of the capacitor group C0 in the x direction when viewed in the y direction. As a result, the difference in the conduction path from the switching element Q1 to each capacitor C1 becomes small.
 スイッチング素子Q1は、駆動装置A1のモジュール構成において、図34に示すように、z方向下面に複数の電極Q11,Q12,Q13が形成されている。複数の電極Q11は、スイッチング素子Q1におけるゲート電極である。複数の電極Q12は、スイッチング素子Q1におけるドレイン電極である。複数の電極Q13は、スイッチング素子Q1におけるソース電極である。スイッチング素子Q1が回路基板10に実装された状態においては、平面視において、複数の電極Q11(ゲート電極)がx1方向側の端縁に沿って配置されている。これは、ドライブIC9が、スイッチング素子Q1よりもx1方向側に位置しており、ドライブIC9と複数の電極Q11との距離を短くするためのである。各電極Q11,Q12,Q13の配置は、図34に示す例に限定されない。 As shown in FIG. 34, the switching element Q1 has a plurality of electrodes Q11, Q12, and Q13 formed on the lower surface in the z direction in the module configuration of the drive device A1. The plurality of electrodes Q11 are gate electrodes in the switching element Q1. The plurality of electrodes Q12 are drain electrodes in the switching element Q1. The plurality of electrodes Q13 are source electrodes in the switching element Q1. In the state where the switching element Q1 is mounted on the circuit board 10, a plurality of electrodes Q11 (gate electrodes) are arranged along the edge on the x1 direction side in a plan view. This is because the drive IC 9 is located on the x1 direction side of the switching element Q1 and the distance between the drive IC 9 and the plurality of electrodes Q11 is shortened. The arrangement of the electrodes Q11, Q12, and Q13 is not limited to the example shown in FIG. 34.
 各抵抗器R2は、x方向において、ドライブIC9とスイッチング素子Q1との間に配置され、かつ、これらに隣接している。これにより、ドライブIC9(ドライブ回路DR)から出力され、抵抗器R2を介して、スイッチング素子Q1のゲートに入力される駆動信号の伝達経路が直線的になる。ドライブIC9とスイッチング素子Q1と各抵抗器R2とは、x方向に見て重なる。 Each resistor R2 is arranged between the drive IC 9 and the switching element Q1 in the x direction, and is adjacent to these. As a result, the transmission path of the drive signal output from the drive IC9 (drive circuit DR) and input to the gate of the switching element Q1 via the resistor R2 becomes linear. The drive IC9, the switching element Q1, and each resistor R2 overlap each other when viewed in the x direction.
 2つのソケット端子T41,T42はそれぞれ、TO-Canパッケージ型(3端子)のレーザモジュールを接続するための端子である。接続するレーザモジュールがTO-Canパッケージ型の場合、ソケット端子T41あるいはソケット端子T42のいずれかにレーザモジュールが接続される。各ソケット端子T41,T42は、TO-Canパッケージ型のレーザモジュールの各リード端子を挿通可能である。2つのソケット端子T41,T42は、互いに大きさが異なっており、接続するレーザモジュールの大きさにあわせて、いずれかが選択される。2つのソケット端子T41,T42の大きさは、互いに異なるものに限定されず、同じであってもよい。ソケット端子T41のy1方向の隣には、帰還ダイオードD1が配置されている。図28および図29に示すように、ソケット端子T41は、実装領域M1に取り付けられており、ソケット端子T42は、実装領域M2に取り付けられている。 The two socket terminals T41 and T42 are terminals for connecting a TO-Can package type (3 terminals) laser module, respectively. When the laser module to be connected is a TO-Can package type, the laser module is connected to either the socket terminal T41 or the socket terminal T42. Each of the socket terminals T41 and T42 can be inserted with each lead terminal of the TO-Can package type laser module. The two socket terminals T41 and T42 have different sizes, and one of them is selected according to the size of the laser module to be connected. The sizes of the two socket terminals T41 and T42 are not limited to different ones, and may be the same. A feedback diode D1 is arranged next to the socket terminal T41 in the y1 direction. As shown in FIGS. 28 and 29, the socket terminal T41 is attached to the mounting area M1, and the socket terminal T42 is attached to the mounting area M2.
 パッド端子T43は、面実装型のレーザモジュールを接続するための端子である。パッド端子T43は、図28および図29に示すように、互い離間した2つのランドパターンを含む。接続するレーザモジュールが面実装型の場合、パッド端子T43の各ランドパターンにレーザモジュールが接続される。パッド端子T43は、図28に示すように、平面視において、回路基板10の端縁に沿って配置されている。パッド端子T43は、y2方向のランドパターンにレーザダイオードのカソードが接続され、y1方向のランドパターンに、レーザダイオードのアノードが接続される。なお、パッド端子T43に、TO-Canパッケージ型のレーザモジュールを接続することも可能である。たとえば、TO-Canパッケージ型のレーザモジュールにおいて、レーザダイオードLDのアノードおよびカソードの各リード端子を、はんだなどによって、直接パッド端子T43にそれぞれ接合することで、パッド端子T43にTO-Canパッケージ型のレーザモジュールを接続できる。 The pad terminal T43 is a terminal for connecting a surface-mounted laser module. The pad terminal T43 includes two land patterns that are separated from each other, as shown in FIGS. 28 and 29. When the laser module to be connected is a surface mount type, the laser module is connected to each land pattern of the pad terminal T43. As shown in FIG. 28, the pad terminal T43 is arranged along the edge of the circuit board 10 in a plan view. In the pad terminal T43, the cathode of the laser diode is connected to the land pattern in the y2 direction, and the anode of the laser diode is connected to the land pattern in the y1 direction. It is also possible to connect a TO-Can package type laser module to the pad terminal T43. For example, in a TO-Can package type laser module, by joining the anode and cathode lead terminals of the laser diode LD directly to the pad terminal T43 with solder or the like, the pad terminal T43 can be connected to the TO-Can package type. A laser module can be connected.
 図28に示すように、スイッチング素子Q1、ドライブ回路DR、コンデンサ群C0(複数のコンデンサC1)、シャント抵抗群R0(複数のシャント抵抗R1)、帰還ダイオードD1、ソケット端子T41,T42、および、パッド端子T43は、x方向において、回路基板10の中央よりも一方側に配置されている。 As shown in FIG. 28, switching element Q1, drive circuit DR, capacitor group C0 (plurality of capacitors C1), shunt resistor group R0 (plurality of shunt resistors R1), feedback diode D1, socket terminals T41, T42, and pads. The terminal T43 is arranged on one side of the center of the circuit board 10 in the x direction.
 複数の電子部品および複数の端子は、回路基板10に実装されることで、各配線パターン21~24によって、適宜導通接続され、図25に示す回路構成となる。 By mounting the plurality of electronic components and the plurality of terminals on the circuit board 10, they are appropriately conductively connected by the wiring patterns 21 to 24, and the circuit configuration shown in FIG. 25 is obtained.
 以上のように構成された駆動装置A1の作用・効果は、次の通りである。 The actions and effects of the drive device A1 configured as described above are as follows.
 駆動装置A1は、複数のシャント抵抗R1を備えている。複数のシャント抵抗R1は、互い並列に接続され、かつ、各々がレーザダイオードLDに直列に接続されている。この構成によると、複数のシャント抵抗R1が、互いに並列に接続されているので、レーザダイオードLDに供給される駆動電流は、各シャント抵抗R1に分割される。特に、各シャント抵抗R1の抵抗値が同じである場合、駆動電流は、各シャント抵抗R1に均等に分割される。これにより、1つのシャント抵抗R1に流れる電流が低減されるため、各シャント抵抗R1に寄生インダクタンス成分による電流低下が抑制される。つまり、駆動装置A1は、レーザダイオードLDを効率良く発光させることができる。 The drive device A1 includes a plurality of shunt resistors R1. The plurality of shunt resistors R1 are connected in parallel with each other, and each is connected in series with the laser diode LD. According to this configuration, since the plurality of shunt resistors R1 are connected in parallel with each other, the drive current supplied to the laser diode LD is divided into the respective shunt resistors R1. In particular, when the resistance values of the shunt resistors R1 are the same, the drive current is evenly divided into the shunt resistors R1. As a result, the current flowing through one shunt resistor R1 is reduced, so that the current reduction due to the parasitic inductance component is suppressed in each shunt resistor R1. That is, the drive device A1 can efficiently make the laser diode LD emit light.
 駆動装置A1では、複数のシャント抵抗R1は、x方向に並んでおり、x方向に隣り合う2つのシャント抵抗R1の離間距離SD1は、各シャント抵抗R1のx方向寸法Dx以上である。この構成によると、x方向に隣り合う2つのシャント抵抗R1における相互インダクタンスを低減できる。これにより、駆動装置A1におけるインダクタンス成分を低減できる。したがって、駆動装置A1は、レーザダイオードLDへの駆動電流の低下を抑制でき、レーザダイオードLDを効率良く発光させることができる。隣り合う2つのシャント抵抗R1に発生する相互インダクタンスMは、M=2L(ln(2L/d)-1)×10-7で算出される。この式において、Lは、各シャント抵抗R1の長さ(図29のy方向寸法Dyに相当)、dは、隣り合う2つのシャント抵抗R1の離間距離(図29の離間距離SD1に相当)である。また、この式においては、各シャント抵抗R1の寄生インダクタンスをそれぞれ1nHとしている。この式から、離間距離d(離間距離SD1)が大きいほど、相互インダクタンスMが小さくなることが分かる。さらに、相互インダクタンスMを0に抑えるためには、上記式に基づいて、ln(2L/d)-1≦0となる離間距離dにするとよい。つまり、離間距離dは、d≧(2L/e)≒0.74×Lにすることが好ましい。eは、ネイピア数であり、e=2.718・・・である。 In the drive device A1, the plurality of shunt resistors R1 are arranged in the x direction, and the separation distance SD1 of the two shunt resistors R1 adjacent to each other in the x direction is equal to or larger than the x-direction dimension Dx of each shunt resistor R1. According to this configuration, mutual inductance in two shunt resistors R1 adjacent to each other in the x direction can be reduced. As a result, the inductance component in the drive device A1 can be reduced. Therefore, the drive device A1 can suppress a decrease in the drive current to the laser diode LD, and can make the laser diode LD emit light efficiently. The mutual inductance M generated in two adjacent shunt resistors R1 is calculated by M = 2L (ln (2L / d) -1) × 10 -7. In this equation, L is the length of each shunt resistor R1 (corresponding to the y-direction dimension Dy in FIG. 29), and d is the separation distance between two adjacent shunt resistors R1 (corresponding to the separation distance SD1 in FIG. 29). is there. Further, in this equation, the parasitic inductance of each shunt resistor R1 is set to 1 nH. From this equation, it can be seen that the larger the separation distance d (separation distance SD1), the smaller the mutual inductance M. Further, in order to suppress the mutual inductance M to 0, it is preferable to set the separation distance d such that ln (2L / d) -1 ≦ 0 based on the above equation. That is, the separation distance d is preferably set to d ≧ (2L / e) ≈0.74 × L. e is the number of Napiers, and e = 2.718 ....
 図35は、各シャント抵抗R1に印加される電圧(シャント抵抗電圧)の時間変化をシミュレーションした結果を示している。図35の実線は、駆動装置A1、つまり、x方向に隣り合う2つのシャント抵抗R1の間を各シャント抵抗R1のx方向寸法Dx以上にした場合の結果である。図35の破線は、駆動装置A1と異なる駆動装置(以下、「比較用駆動装置」という)であって、x方向に隣り合う2つのシャント抵抗R1の間にも各シャント抵抗R1と同様のシャント抵抗を実装した場合の結果である。なお、図35に示す各シミュレーション結果は、簡略化して示している。 FIG. 35 shows the result of simulating the time change of the voltage (shunt resistance voltage) applied to each shunt resistor R1. The solid line in FIG. 35 is the result when the drive device A1, that is, between two shunt resistors R1 adjacent to each other in the x direction is equal to or larger than the x-direction dimension Dx of each shunt resistor R1. The broken line in FIG. 35 is a drive device different from the drive device A1 (hereinafter referred to as “comparative drive device”), and a shunt similar to that of each shunt resistor R1 is also between two shunt resistors R1 adjacent to each other in the x direction. This is the result when a resistor is mounted. The simulation results shown in FIG. 35 are shown in a simplified manner.
 比較用駆動装置では、図35の破線において、期間Ta’の波形に示すように、シャント抵抗電圧が数回振動している。一方、駆動装置A1では、図35の実線において、期間Taの波形に示すように、シャント抵抗電圧の振動が抑制されている。これらの振動は、駆動装置A1および比較用駆動装置における各インダクタンスによって発生するものであり、インダクタンス値が高いほど、振動回数が多くなる。したがって、駆動装置A1は、比較用駆動装置よりも、シャント抵抗電圧の振動が抑制されているため、インダクタンス成分が低減されている。また、この振動は、たとえばレーザダイオードLDの発光時のちらつきの原因であるため、駆動装置A1は、このちらつきを抑制できる。さらに、駆動装置A1における、1つ目の波の立上りから立下りまでの期間Tb(図35の実線の波形参照)は、比較用駆動装置における1つ目の波の立上りから立下りまでの期間Tb’(図35の破線の波形参照)よりも短い。つまり、駆動装置A1におけるシャント電圧の変動周期が、比較用駆動装置におけるシャント電圧の変動周期よりも小さくなっている(共振周波数が大きくなっている)。これは、駆動装置A1のインダクタンス成分が、比較用駆動装置のインダクタンス成分よりも低減されているからである。よって、インダクタンス成分を低減させることで、レーザダイオードLDの駆動電流を、短パルス化かつ大電流化させることができる。 In the comparison drive device, the shunt resistance voltage vibrates several times as shown in the waveform of the period Ta'in the broken line in FIG. 35. On the other hand, in the drive device A1, in the solid line of FIG. 35, the vibration of the shunt resistance voltage is suppressed as shown in the waveform of the period Ta. These vibrations are generated by each inductance in the drive device A1 and the comparison drive device, and the higher the inductance value, the higher the number of vibrations. Therefore, in the drive device A1, the vibration of the shunt resistance voltage is suppressed as compared with the comparison drive device, so that the inductance component is reduced. Further, since this vibration is a cause of flicker at the time of light emission of the laser diode LD, for example, the drive device A1 can suppress this flicker. Further, the period Tb from the rise to the fall of the first wave in the drive device A1 (see the waveform of the solid line in FIG. 35) is the period from the rise to the fall of the first wave in the comparative drive device. Shorter than Tb'(see the dashed waveform in FIG. 35). That is, the fluctuation cycle of the shunt voltage in the drive device A1 is smaller than the fluctuation cycle of the shunt voltage in the comparative drive device (the resonance frequency is larger). This is because the inductance component of the drive device A1 is smaller than the inductance component of the comparative drive device. Therefore, by reducing the inductance component, the drive current of the laser diode LD can be shortened and increased in current.
 駆動装置A1は、その回路構成(図25~図27参照)において、直流電源と、レーザダイオードLDとの間に各コンデンサC1が接続されている。この構成によると、直流電源からの電源電圧が、直接レーザダイオードLDに印加されない。したがって、レーザダイオードLDにかかる負荷が低減され、レーザダイオードLDの故障が抑制される。 In the circuit configuration of the drive device A1 (see FIGS. 25 to 27), each capacitor C1 is connected between the DC power supply and the laser diode LD. According to this configuration, the power supply voltage from the DC power supply is not directly applied to the laser diode LD. Therefore, the load applied to the laser diode LD is reduced, and the failure of the laser diode LD is suppressed.
 駆動装置A1では、複数のコンデンサC1、ソケット端子T41(あるいはソケット端子T42)、および、複数のシャント抵抗R1がy方向にこの順で並んでいる。この構成によると、各シャント抵抗R1から、レーザダイオードLDを介して、各コンデンサC1に流れる駆動電流の導通経路を、直線状にできる。これにより、スイッチング素子Q1が導通状態であるときの電流経路LP(図27参照)における配線の寄生インダクタンスを低減できる。つまり、駆動装置A1におけるインダクタンス成分を低減できるので、駆動装置A1は、レーザダイオードLDへの駆動電流の低下を抑制でき、レーザダイオードLDを効率良く発光させることができる。 In the drive device A1, a plurality of capacitors C1, a socket terminal T41 (or a socket terminal T42), and a plurality of shunt resistors R1 are arranged in this order in the y direction. According to this configuration, the conduction path of the drive current flowing from each shunt resistor R1 through the laser diode LD to each capacitor C1 can be made linear. As a result, the parasitic inductance of the wiring in the current path LP (see FIG. 27) when the switching element Q1 is in the conductive state can be reduced. That is, since the inductance component in the drive device A1 can be reduced, the drive device A1 can suppress a decrease in the drive current to the laser diode LD, and the laser diode LD can efficiently emit light.
 駆動装置A1では、回路基板10には、レーザモジュール(レーザダイオードLD)を実装する実装領域M1がある。実装領域M1は、レーザダイオードLDのアノードに接続される端子接続部MaおよびレーザダイオードLDのカソードに接続される端子接続部Mcを含んでいる。端子接続部Maと端子接続部Mcとは、y方向に並んでおり、y方向において、端子接続部Mcがコンデンサ群C0側に、端子接続部Maがシャント抵抗群R0側に配置されている。この構成によると、各シャント抵抗R1から、レーザダイオードLDを介して、各コンデンサC1に流れる駆動電流の導通経路をさらに直線状にできる。これにより、スイッチング素子Q1が導通状態であるときの電流経路LP(図27参照)における配線の寄生インダクタンスを低減できる。したがって、駆動装置A1におけるインダクタンス成分を低減できるので、駆動装置A1は、レーザダイオードLDの発光効率を向上させることができる。また、実装領域M2においても同様である。 In the drive device A1, the circuit board 10 has a mounting region M1 for mounting a laser module (laser diode LD). The mounting region M1 includes a terminal connection portion Ma connected to the anode of the laser diode LD and a terminal connection portion Mc connected to the cathode of the laser diode LD. The terminal connection portion Ma and the terminal connection portion Mc are arranged in the y direction, and the terminal connection portion Mc is arranged on the capacitor group C0 side and the terminal connection portion Ma is arranged on the shunt resistance group R0 side in the y direction. According to this configuration, the conduction path of the drive current flowing from each shunt resistor R1 to each capacitor C1 via the laser diode LD can be further made linear. As a result, the parasitic inductance of the wiring in the current path LP (see FIG. 27) when the switching element Q1 is in the conductive state can be reduced. Therefore, since the inductance component in the drive device A1 can be reduced, the drive device A1 can improve the luminous efficiency of the laser diode LD. The same applies to the mounting area M2.
 駆動装置A1では、スイッチング素子Q1とドライブIC9とがx方向に並んでおり、スイッチング素子Q1とドライブIC9との間には、抵抗器R2のみが配置されている。この構成によると、ドライブIC9とスイッチング素子Q1との距離を短くできるので、ドライブIC9から出力され、スイッチング素子Q1に入力される駆動信号の伝達時間を短くできる。この駆動信号の伝達の短縮は、スイッチング動作の応答性を向上させる。つまり、駆動装置A1は、スイッチング素子Q1のスイッチング動作の応答性を向上できる。なお、よりスイッチング素子Q1のスイッチング特性(スイッチング速度)の向上が要求される場合においては、各抵抗器R2を設けず、ドライブIC9とスイッチング素子Q1とを隣接させて、ドライブIC9とスイッチング素子Q1との距離をさらに短くしてもよい。 In the drive device A1, the switching element Q1 and the drive IC9 are arranged in the x direction, and only the resistor R2 is arranged between the switching element Q1 and the drive IC9. According to this configuration, the distance between the drive IC 9 and the switching element Q1 can be shortened, so that the transmission time of the drive signal output from the drive IC 9 and input to the switching element Q1 can be shortened. This shortening of drive signal transmission improves the responsiveness of the switching operation. That is, the drive device A1 can improve the responsiveness of the switching operation of the switching element Q1. When the switching characteristic (switching speed) of the switching element Q1 is required to be improved, the drive IC9 and the switching element Q1 are placed adjacent to each other without providing each resistor R2. The distance of may be further shortened.
 駆動装置A1では、回路基板10は、複数の貫通電極30が密に配置された集合領域AG1,AG2を含んでいる。集合領域AG1,AG2に配置された複数の貫通電極30は、配線層Ly1の配線パターン21と配線層Ly2の配線パターン22とに導通する。この構成によると、配線層Ly1と配線層Ly2との導電性が良好となる。特に、集合領域AG1の複数の貫通電極30は、各シャント抵抗R1の一端(第2端R12)と、GNDパターン(配線パターン22)とを導通させ、集合領域AG2の複数の貫通電極30は、スイッチング素子Q1のソースと、GNDパターン(配線パターン22)とを導通させている。したがって、各シャント抵抗R1の一端およびスイッチング素子Q1のソースの、 基準電位(GND)への接地が強化され、駆動装置A1における各信号の品質改善(たとえばノイズ低減など)、および、上記シャント抵抗電圧の振動(基準電位の揺れ)の低減を図ることができる。 In the drive device A1, the circuit board 10 includes the gathering regions AG1 and AG2 in which a plurality of through electrodes 30 are densely arranged. The plurality of through electrodes 30 arranged in the collecting regions AG1 and AG2 are electrically connected to the wiring pattern 21 of the wiring layer Ly1 and the wiring pattern 22 of the wiring layer Ly2. According to this configuration, the conductivity between the wiring layer Ly1 and the wiring layer Ly2 becomes good. In particular, the plurality of through electrodes 30 in the gathering region AG1 conduct the one end (second end R12) of each shunt resistor R1 and the GND pattern (wiring pattern 22), and the plurality of through electrodes 30 in the gathering region AG2 are The source of the switching element Q1 and the GND pattern (wiring pattern 22) are made conductive. Therefore, the grounding of one end of each shunt resistor R1 and the source of the switching element Q1 to the reference potential (GND) is strengthened, the quality of each signal in the drive device A1 is improved (for example, noise reduction), and the shunt resistance voltage is described. Vibration (fluctuation of reference potential) can be reduced.
 駆動装置A1では、回路基板10は、複数の配線層Ly1~Ly4を含んでいる。複数の配線層Ly1~Ly4は、z方向寸法(厚さ)が一般的な厚さ(700μm程度)よりも薄い。この構成によると、複数の貫通電極30のz方向寸法が小さくなる。よって、各貫通電極30の寄生インダクタンスを低減できる。たとえば、配線層Ly1から集合領域AG1に配置された複数の貫通電極30を介して、配線層Ly2を通り、そして、集合領域AG2に配置された複数の貫通電極30によって、配線層Ly1に戻ってくる電流経路(図27の電流経路LPに相当)を短くできるので、この電流経路における配線の寄生インダクタンスを低減できる。 In the drive device A1, the circuit board 10 includes a plurality of wiring layers Ly1 to Ly4. The z-direction dimensions (thickness) of the plurality of wiring layers Ly1 to Ly4 are thinner than the general thickness (about 700 μm). According to this configuration, the z-direction dimensions of the plurality of through electrodes 30 are reduced. Therefore, the parasitic inductance of each through electrode 30 can be reduced. For example, the wiring layer Ly1 passes through the wiring layer Ly2 via the plurality of through electrodes 30 arranged in the gathering region AG1, and returns to the wiring layer Ly1 by the plurality of penetrating electrodes 30 arranged in the gathering region AG2. Since the incoming current path (corresponding to the current path LP in FIG. 27) can be shortened, the parasitic inductance of the wiring in this current path can be reduced.
 本実施形態では、各実装領域M1,M2には、各ソケット端子T41,T42が取り付けられている場合を示したが、これに限定されず、各ソケット端子T41,T42を取り付けなくてもよい。この場合、TO-Canパッケージ型のレーザモジュールは、たとえばはんだ付けなどによって、各実装領域M1,M2に直接実装される。 In the present embodiment, the case where the socket terminals T41 and T42 are attached to the mounting areas M1 and M2 is shown, but the present invention is not limited to this, and the socket terminals T41 and T42 may not be attached. In this case, the TO-Can package type laser module is directly mounted in each mounting area M1 and M2 by, for example, soldering.
 本実施形態では、3つのシャント抵抗R1が配置された場合を示したが、シャント抵抗R1の数はこれに限定されない。たとえば、図36に示すように、2つのシャント抵抗R1が配置された構成であってもよい。図36に示す例においては、5つの抵抗用ランド20のうち、x方向両端に位置する抵抗用ランド20に、シャント抵抗R1がそれぞれ1つずつ接合されている。図36に示す駆動装置の回路構成は、図37で示される。図37においては、図25に示す回路構成の一部を抜粋している。また、図38に示すように、2つのシャント抵抗R1が配置された構成であってもよい。図38に示す例においては、5つの抵抗用ランド20のうち、x方向中央に位置する抵抗用ランド20の両隣の抵抗用ランド20に、シャント抵抗R1がそれぞれ1つずつ接合されている。図38に示す駆動装置の回路構成は、図39で示される。図39においては、図25に示す回路構成の一部を抜粋している。図36および図38の各レイアウト図は、図29に対応する。ただし、シャント抵抗R1が2つの場合、シャント抵抗R1が3つの場合に比べて、各シャント抵抗R1の寄生インダクタンスによる電流低下を抑制する効果が小さくなるが、回路基板10上の実装面積を小さくすることが可能となる。シャント抵抗R1の数は、駆動装置A1に要求される仕様に応じて、適宜決められる。 In the present embodiment, the case where three shunt resistors R1 are arranged is shown, but the number of shunt resistors R1 is not limited to this. For example, as shown in FIG. 36, two shunt resistors R1 may be arranged. In the example shown in FIG. 36, one shunt resistor R1 is joined to each of the five resistor lands 20 located at both ends in the x direction. The circuit configuration of the drive device shown in FIG. 36 is shown in FIG. 37. In FIG. 37, a part of the circuit configuration shown in FIG. 25 is excerpted. Further, as shown in FIG. 38, the configuration may be such that two shunt resistors R1 are arranged. In the example shown in FIG. 38, one shunt resistor R1 is joined to each of the five resistor lands 20 on both sides of the resistor lands 20 located at the center in the x direction. The circuit configuration of the drive device shown in FIG. 38 is shown in FIG. 39. In FIG. 39, a part of the circuit configuration shown in FIG. 25 is excerpted. Each layout diagram of FIGS. 36 and 38 corresponds to FIG. 29. However, when there are two shunt resistors R1, the effect of suppressing the current decrease due to the parasitic inductance of each shunt resistor R1 is smaller than when the shunt resistors R1 are three, but the mounting area on the circuit board 10 is reduced. It becomes possible. The number of shunt resistors R1 is appropriately determined according to the specifications required for the drive device A1.
 本実施形態では、平面視において、x方向に隣り合う2つのシャント抵抗R1の間に、抵抗用ランド20が配置された場合を示したが、これに限定されない。たとえば、図40に示すように、x方向に隣り合う2つのシャント抵抗R1の間に、抵抗用ランド20が配置されない構成であってもよい。図40に示す駆動装置の回路構成は、図41で示される。図41においては、図25に示す回路構成の一部を抜粋している。また、図42に示すように、x方向の隣り合う2つのシャント抵抗R1の間の抵抗用ランド20の代わりに、ベタパターン29が配置された構成であってもよい。この場合、このベタパターン29を、マイクロストリップラインやコプレーナ線路として設計してもよい。図42に示す駆動装置の回路構成は、図43で示される。図43においては、図25に示す回路構成の一部を抜粋している。図40および図42の各レイアウト図は、図29に対応する。 In the present embodiment, a case where the resistance land 20 is arranged between two shunt resistors R1 adjacent to each other in the x direction in a plan view is shown, but the present invention is not limited to this. For example, as shown in FIG. 40, the resistor land 20 may not be arranged between two shunt resistors R1 adjacent to each other in the x direction. The circuit configuration of the drive device shown in FIG. 40 is shown in FIG. In FIG. 41, a part of the circuit configuration shown in FIG. 25 is excerpted. Further, as shown in FIG. 42, a solid pattern 29 may be arranged instead of the resistance land 20 between two adjacent shunt resistors R1 in the x direction. In this case, the solid pattern 29 may be designed as a microstrip line or a coplanar line. The circuit configuration of the drive device shown in FIG. 42 is shown in FIG. 43. In FIG. 43, a part of the circuit configuration shown in FIG. 25 is excerpted. Each layout diagram of FIGS. 40 and 42 corresponds to FIG. 29.
 本開示にかかる駆動装置は、上記した実施形態に限定されるものではない。本開示の駆動装置の各部の具体的な構成は、種々に設計変更自在である。 The drive device according to the present disclosure is not limited to the above-described embodiment. The specific configuration of each part of the drive device of the present disclosure can be freely redesigned.
 第3の側面により提供される構成は、以下の付記1C~17Cに記載された実施形態を含む。
 付記1C.レーザダイオードに駆動電流を供給する複数の電子部品と、
 前記複数の電子部品が搭載された回路基板と、
を備えており、
 前記複数の電子部品は、導通状態と遮断状態とが切り替わるスイッチング素子と、互い並列に接続され且つ各々が前記レーザダイオードのアノードに直列に接続された複数の抵抗器と、前記レーザダイオードのカソードと前記スイッチング素子との間に接続されたコンデンサとを含んでおり、
 前記複数の抵抗器は、前記回路基板の厚さ方向に直交する第1方向に並んでおり、
 前記複数の抵抗器は、前記第1方向に隣り合う2つの抵抗器を含み、当該2つの抵抗器の第1方向における離間距離は、前記複数の抵抗器のいずれか1つの前記第1方向における寸法以上である、駆動装置。
 付記2C.前記スイッチング素子は、第1端子、第2端子および第3端子を有するトランジスタであり、前記第3端子に入力される制御信号に応じて、前記導通状態と前記遮断状態とが切り替わる、付記1Cに記載の駆動装置。
 付記3C.前記複数の抵抗器の前記いずれか1つの第1端は、前記レーザダイオードのアノードに接続され、
 前記複数の抵抗器の前記いずれか1つの第2端は、基準電位に接地され、
 前記コンデンサの第1端は、前記レーザダイオードのカソードに接続され、
 前記コンデンサの第2端は、前記スイッチング素子の前記第1端子に接続され、
 前記スイッチング素子の前記第2端子は、前記基準電位に接地されている、付記2Cに記載の駆動装置。
 付記4C.前記複数の電子部品は、前記制御信号を生成するドライブ回路をさらに含んでおり、
 前記ドライブ回路と前記スイッチング素子とは、前記第1方向に並んでいる、付記3Cに記載の駆動装置。
 付記5C.前記複数の電子部品は、前記ドライブ回路と前記第3端子との間に接続される電流値設定素子をさらに含んでおり、
 前記電流値設定素子は、前記回路基板上において、前記ドライブ回路と前記スイッチング素子との間に配置されている、付記4Cに記載の駆動装置。
 付記6C.電源電圧が供給される入力端子をさらに備えており、
 前記コンデンサは、前記入力端子に接続され、前記スイッチング素子が前記遮断状態のときに、前記電源電圧が前記コンデンサに印加される、付記3Cないし付記5Cのいずれか1つに記載の駆動装置。
 付記7C.前記回路基板には、前記厚さ方向に見て、前記2つの抵抗器の間に、ランドパターンが形成されている、付記1Cないし付記6Cのいずれか1つに記載の駆動装置。
 付記8C.前記複数の抵抗器は抵抗器群を形成しており、
 前記コンデンサと前記抵抗器群とは、前記厚さ方向および前記第1方向に直交する第2方向に並んでいる、付記1Cないし付記7Cのいずれか1つに記載の駆動装置。
 付記9C.前記回路基板は、前記レーザダイオードを実装する実装領域を含み、
 前記実装領域は、前記第1方向に見て、前記コンデンサと前記抵抗器群との間に位置しており、かつ、前記コンデンサと前記抵抗器群とにそれぞれ隣接する、付記8Cに記載の駆動装置。
 付記10C.前記実装領域には、前記レーザダイオードのアノードを接続するアノード接続部、および、前記レーザダイオードのカソードを接続するカソード接続部を含み、
 前記アノード接続部と前記カソード接続部とは、前記厚さ方向に見て、前記第2方向に並んでいる、付記9Cに記載の駆動装置。
 付記11C.前記コンデンサと並列に接続され、かつ、前記抵抗器群と前記第2方向に並ぶ追加のコンデンサをさらに備えており、
 前記コンデンサと前記追加のコンデンサとによって、コンデンサ群が形成されている、付記8Cないし付記10Cのいずれか1つに記載の駆動装置。
 付記12C.前記スイッチング素子は、前記第2方向において、前記コンデンサ群よりも前記抵抗器群が位置する側と反対側に配置されており、かつ、前記コンデンサ群に隣接する、付記11Cに記載の駆動装置。
 付記13C.前記複数の抵抗器は、第1抵抗器および第2抵抗器を含んでおり、
 前記第1抵抗器は、前記複数の抵抗器のうち前記第1方向の最も一方側に配置され、
 前記第2抵抗器は、前記複数の抵抗器のうち前記第1方向の最も他方側に配置され、
 前記コンデンサ群の前記第1方向の一方側の端縁は、前記第2方向に見て、前記第1抵抗器に重なり、前記コンデンサ群の前記第1方向の他方側の端縁は、前記第2方向に見て、前記第2抵抗器に重なる、付記11Cまたは付記12Cに記載の駆動装置。
 付記14C.前記複数の電子部品は、前記第1抵抗器および前記第2抵抗器と並列に接続された第3抵抗器をさらに含んでおり、
 前記第3抵抗器は、前記第1方向において、前記第1抵抗器と前記第2抵抗器との間に配置されている、付記13Cに記載の駆動装置。
 付記15C.前記回路基板は、絶縁層と、前記厚さ方向に積層され且つ前記絶縁層を介して互いに絶縁された第1配線層および第2配線層とを含んでおり、
 前記第2配線層は、基準電位に接地されている、付記8Cないし付記14Cのいずれか1つに記載の駆動装置。
 付記16C.前記回路基板は、前記厚さ方向に見て、複数の貫通電極が配置された集合領域を含んでおり、
 前記複数の貫通電極は、前記絶縁層を貫通し、かつ、前記第1配線層と前記第2配線層とを導通させており、
 前記集合領域は、前記第2方向において、前記抵抗器群よりも、前記コンデンサが位置する側と反対側に配置されている、付記15Cに記載の駆動装置。
 付記17C.前記回路基板は、前記厚さ方向において、前記第2配線層よりも前記第1配線層と反対側に配置され、かつ、電源パターンが形成された第3配線層を含んでいる、付記15Cまたは付記16Cに記載の駆動装置。
The configuration provided by the third aspect includes the embodiments described in Appendix 1C-17C below.
Appendix 1 C.I. With multiple electronic components that supply the drive current to the laser diode,
A circuit board on which the plurality of electronic components are mounted and
Is equipped with
The plurality of electronic components include a switching element that switches between a conduction state and a cutoff state, a plurality of resistors connected in parallel with each other and each connected in series with the anode of the laser diode, and a cathode of the laser diode. It includes a capacitor connected to the switching element and
The plurality of resistors are arranged in a first direction orthogonal to the thickness direction of the circuit board.
The plurality of resistors include two resistors adjacent to each other in the first direction, and the distance between the two resistors in the first direction is such that the distance between the two resistors in the first direction is one of the plurality of resistors in the first direction. A drive that is greater than or equal to the dimensions.
Appendix 2 C.I. The switching element is a transistor having a first terminal, a second terminal, and a third terminal, and the conduction state and the cutoff state are switched according to a control signal input to the third terminal. The drive device described.
Appendix 3C. The first end of any one of the plurality of resistors is connected to the anode of the laser diode.
The second end of any one of the plurality of resistors is grounded to a reference potential.
The first end of the capacitor is connected to the cathode of the laser diode and
The second end of the capacitor is connected to the first terminal of the switching element.
The driving device according to Appendix 2C, wherein the second terminal of the switching element is grounded to the reference potential.
Appendix 4 C. The plurality of electronic components further include a drive circuit that generates the control signal.
The drive device according to Appendix 3C, wherein the drive circuit and the switching element are arranged in the first direction.
Appendix 5C. The plurality of electronic components further include a current value setting element connected between the drive circuit and the third terminal.
The drive device according to Appendix 4C, wherein the current value setting element is arranged between the drive circuit and the switching element on the circuit board.
Appendix 6 C.I. It also has an input terminal to which the power supply voltage is supplied.
The drive device according to any one of Supplementary note 3C to Supplementary note 5C, wherein the capacitor is connected to the input terminal, and the power supply voltage is applied to the capacitor when the switching element is in the cutoff state.
Appendix 7 C.I. The driving device according to any one of Supplementary note 1C to Supplementary note 6C, wherein a land pattern is formed between the two resistors when viewed in the thickness direction of the circuit board.
Appendix 8C. The plurality of resistors form a group of resistors, and the plurality of resistors form a group of resistors.
The driving device according to any one of Supplementary note 1C to Supplementary note 7C, wherein the capacitor and the resistor group are arranged in the thickness direction and the second direction orthogonal to the first direction.
Appendix 9C. The circuit board includes a mounting area for mounting the laser diode.
The drive according to Appendix 8C, wherein the mounting region is located between the capacitor and the resistor group when viewed in the first direction, and is adjacent to the capacitor and the resistor group, respectively. apparatus.
Appendix 10 C.I. The mounting region includes an anode connection for connecting the anode of the laser diode and a cathode connection for connecting the cathode of the laser diode.
The driving device according to Appendix 9C, wherein the anode connecting portion and the cathode connecting portion are arranged in the second direction when viewed in the thickness direction.
Appendix 11 C.I. It is connected in parallel with the capacitor and further includes an additional capacitor aligned with the resistor group in the second direction.
The drive device according to any one of Supplementary note 8C to Supplementary note 10C, wherein a capacitor group is formed by the capacitor and the additional capacitor.
Appendix 12 C.I. The driving device according to Appendix 11C, wherein the switching element is arranged on the side opposite to the side where the resistor group is located with respect to the capacitor group in the second direction, and is adjacent to the capacitor group.
Appendix 13 C.I. The plurality of resistors include a first resistor and a second resistor.
The first resistor is arranged on the most one side of the plurality of resistors in the first direction.
The second resistor is arranged on the farthest side of the plurality of resistors in the first direction.
The one-sided edge of the capacitor group in the first direction overlaps the first resistor when viewed in the second direction, and the other-side edge of the first direction of the capacitor group is the first. The drive device according to Appendix 11C or Appendix 12C, which overlaps the second resistor when viewed in two directions.
Appendix 14C. The plurality of electronic components further include the first resistor and a third resistor connected in parallel with the second resistor.
The driving device according to Appendix 13C, wherein the third resistor is arranged between the first resistor and the second resistor in the first direction.
Appendix 15 C.I. The circuit board includes an insulating layer and a first wiring layer and a second wiring layer laminated in the thickness direction and insulated from each other via the insulating layer.
The drive device according to any one of Supplementary note 8C to Supplementary note 14C, wherein the second wiring layer is grounded to a reference potential.
Appendix 16 C.I. The circuit board includes an assembly region in which a plurality of through electrodes are arranged when viewed in the thickness direction.
The plurality of through electrodes penetrate the insulating layer and conduct the first wiring layer and the second wiring layer.
The driving device according to Appendix 15C, wherein the gathering region is arranged on the side opposite to the side where the capacitor is located with respect to the resistor group in the second direction.
Appendix 17 C.I. The circuit board is arranged on the side opposite to the first wiring layer in the thickness direction and includes a third wiring layer on which a power supply pattern is formed. The drive device according to Appendix 16C.
 <図25~図43における符号>
A1  :駆動装置
LD  :レーザダイオード
R0  :シャント抵抗群
R1  :シャント抵抗
R11 :第1端
R12 :第2端
C0  :コンデンサ群
C1  :コンデンサ
C11 :第1端
C12 :第2端
D1  :帰還ダイオード
Q1  :スイッチング素子
Q11,Q12,Q13:電極
DR  :ドライブ回路
9   :ドライブIC
R2  :抵抗器
GND :接地端
PG  :パルス生成回路
PS1 :電源部
C2  :電解コンデンサ
L1  :リアクトル
D3  :逆流防止ダイオード
R3  :充電抵抗
PS2 :電源部
T1~T3:コネクタ端子
T4  :接続端子
T41,T42:ソケット端子
T43 :パッド端子
LP  :電流経路
10  :回路基板
Ly1~Ly4:配線層
20  :抵抗用ランド
21~24:配線パターン
29  :ベタパターン
30  :貫通電極
241 :パターン
HL  :貫通孔
AG1,AG2:集合領域
M1,M2:実装領域
Ma,Mb,Mc:端子接続部
<Code in FIGS. 25 to 43>
A1: Drive device LD: Laser diode R0: Shunt resistance group R1: Shunt resistance R11: First end R12: Second end C0: Capacitor group C1: Capacitor C11: First end C12: Second end D1: Feedback diode Q1: Switching elements Q11, Q12, Q13: Electrode DR: Drive circuit 9: Drive IC
R2: Resistor GND: Ground terminal PG: Pulse generation circuit PS1: Power supply unit C2: Electrolytic capacitor L1: Reactor D3: Backflow prevention diode R3: Charging resistance PS2: Power supply unit T1 to T3: Connector terminal T4: Connection terminals T41, T42 : Socket terminal T43: Pad terminal LP: Current path 10: Circuit board Ly1 to Ly4: Wiring layer 20: Resistor land 21 to 24: Wiring pattern 29: Solid pattern 30: Through electrode 241: Pattern HL: Through hole AG1, AG2 : Assembly area M1, M2: Mounting area Ma, Mb, Mc: Terminal connection
 上述のとおり、本開示の第1の側面に基づく基本構成は、第2の側面および第3の側面のいずれにも適用して実施することができる(段落0068、0140参照)。以下では、そのような実施形態を付記1D~16D(第1の側面+第2の側面)および付記1E~17E(第1の側面+第3の側面)として記載する。 As described above, the basic configuration based on the first aspect of the present disclosure can be applied to both the second aspect and the third aspect (see paragraphs 0068, 0140). Hereinafter, such embodiments will be described as appendices 1D to 16D (first side surface + second side surface) and appendices 1E to 17E (first side surface + third side surface).
 付記1D.レーザダイオードの駆動制御を行う駆動装置であって、
 導通状態と遮断状態とが切り替わるスイッチング素子と、
 コンデンサと、
 第1ダイオードと、
 電源電圧が供給される入力端子と、
 前記スイッチング素子をオン/オフ制御する制御部と、
を備えており、
 前記コンデンサは、第1端が前記レーザダイオードのカソードに接続され、第2端が前記スイッチング素子に接続されており、
 前記第1ダイオードは、アノードが、前記コンデンサの前記第1端と前記レーザダイオードのカソードとの接続点に接続されており、
 前記入力端子は、前記コンデンサの前記第2端と前記スイッチング素子との接続点に接続されており、
 前記スイッチング素子がオン状態であるときに、前記スイッチング素子、前記レーザダイオード、前記第1ダイオードおよび前記コンデンサが閉回路を形成し、
 前記制御部は、前記スイッチング素子のオン時間を前記閉回路の共振周期の半分より短くする、駆動装置。
 付記2D.前記制御部は、前記スイッチング素子のオン時間を前記スイッチング素子がオフ状態からオン状態に切り替わったタイミングから前記閉回路の共振電流が最大値の半分になる2度目のタイミング迄の期間より短くする、付記1Dに記載の駆動装置。
 付記3D.前記制御部は、前記スイッチング素子のオン時間を前記閉回路の共振周期の4分の1以上にする、付記1Dに記載の駆動装置。
 付記4D.前記制御部は、
 第1パルス信号に基づく信号を遅延して遅延信号を生成する遅延部と、
 前記遅延信号の波形を整形して第2パルス信号を生成する波形整形部と、
 前記第1パルス信号及び前記第2パルス信号を用いた演算により前記第1パルス信号よりパルス幅が短い第3パルス信号を生成する演算部と、
 を備え、
 前記第3パルス信号に基づき前記スイッチング素子のオン/オフ制御が行われる、付記1D~3Dのいずれか1つに記載の駆動装置。
 付記5D.前記第1パルス信号のパルス幅は、前記閉回路の共振周期の半分以上である、付記4Dに記載の駆動装置。
 付記6D.前記レーザダイオードを流れる電流を検出するシャント抵抗をさらに備え、前記閉回路は前記シャント抵抗を含む、付記1D~5Dのいずれか1つに記載の駆動装置。
 付記7D.前記シャント抵抗は、互いに並列接続された複数の抵抗素子を含む、付記6Dに記載の駆動装置。
 付記8D.前記複数の抵抗素子は、同じ長さを有しかつ互いに隣り合う第1抵抗素子および第2抵抗素子を含み、前記第1抵抗素子および前記第2抵抗素子の間隔は、前記同じ長さの2倍をネイピア数で除して得られる値以上である、付記7Dに記載の駆動装置。
 付記9D.付記1D~8Dのいずれか1つに記載の駆動装置と、
 前記レーザダイオードと、
 を備える、レーザ装置。
 付記10D.基板をさらに備え、
 前記スイッチング素子と、前記第1ダイオード及び前記レーザダイオードを含む並列回路と、前記コンデンサとは、前記基板の厚さ方向に直交する第1方向に並んで配置される、付記9Dに記載のレーザ装置。
 付記11D.前記レーザダイオードのアノードから前記レーザダイオードのカソードに向かう方向は前記第1方向と略平行である、付記10Dに記載のレーザ装置。
 付記12D.前記駆動装置が付記4Dに記載の駆動装置であって、
 前記遅延部と、前記波形整形部と、前記演算部とは、前記厚さ方向および前記第1方向に直交する第2方向に並んでいる、付記10Dまたは11Dに記載のレーザ装置。
 付記13D.前記基板は、第1配線層および第2配線層を含む積層基板であり、前記第2配線層はグラウンド層として機能し、前記第1配線層と前記第2配線層との間隔が、200μm以下である、付記10D~12Dのいずれか1つに記載のレーザ装置。
 付記14D.前記第2配線層において、信号系のグラウンドと電源系のグラウンドとが共通化されている、付記13Dに記載のレーザ装置。
 付記15D.
 付記9D~14Dのいずれか1つに記載のレーザ装置を備える、レーザレーダ装置。
 付記16D.付記15Dに記載のレーザレーダ装置を備える、車両。
Appendix 1D. A drive device that controls the drive of a laser diode.
A switching element that switches between a conductive state and a cutoff state,
With a capacitor
With the first diode
The input terminal to which the power supply voltage is supplied and
A control unit that controls the switching element on / off,
Is equipped with
The capacitor has a first end connected to the cathode of the laser diode and a second end connected to the switching element.
In the first diode, the anode is connected to the connection point between the first end of the capacitor and the cathode of the laser diode.
The input terminal is connected to a connection point between the second end of the capacitor and the switching element.
When the switching element is in the ON state, the switching element, the laser diode, the first diode, and the capacitor form a closed circuit.
The control unit is a drive device that shortens the on-time of the switching element to less than half of the resonance period of the closed circuit.
Appendix 2D. The control unit makes the on-time of the switching element shorter than the period from the timing when the switching element is switched from the off state to the on state to the second timing when the resonance current of the closed circuit becomes half of the maximum value. The drive device according to Appendix 1D.
Appendix 3D. The driving device according to Appendix 1D, wherein the control unit sets the on-time of the switching element to one-fourth or more of the resonance period of the closed circuit.
Appendix 4D. The control unit
A delay unit that delays a signal based on the first pulse signal to generate a delay signal,
A waveform shaping unit that shapes the waveform of the delay signal and generates a second pulse signal,
A calculation unit that generates a third pulse signal having a pulse width shorter than that of the first pulse signal by a calculation using the first pulse signal and the second pulse signal.
With
The drive device according to any one of Supplementary note 1D to 3D, wherein on / off control of the switching element is performed based on the third pulse signal.
Appendix 5D. The driving device according to Appendix 4D, wherein the pulse width of the first pulse signal is at least half of the resonance period of the closed circuit.
Appendix 6D. The drive device according to any one of Supplementary note 1D to 5D, further comprising a shunt resistor for detecting a current flowing through the laser diode, wherein the closed circuit includes the shunt resistor.
Appendix 7D. The driving device according to Appendix 6D, wherein the shunt resistor includes a plurality of resistance elements connected in parallel to each other.
Appendix 8D. The plurality of resistance elements include a first resistance element and a second resistance element having the same length and adjacent to each other, and the distance between the first resistance element and the second resistance element is 2 having the same length. The drive device according to Appendix 7D, which is greater than or equal to the value obtained by dividing the multiple by the number of napiers.
Appendix 9D. The drive device according to any one of Appendix 1D to 8D, and
With the laser diode
A laser device.
Appendix 10D. With more boards
The laser device according to Appendix 9D, wherein the switching element, the parallel circuit including the first diode and the laser diode, and the capacitor are arranged side by side in the first direction orthogonal to the thickness direction of the substrate. ..
Appendix 11D. The laser apparatus according to Appendix 10D, wherein the direction from the anode of the laser diode to the cathode of the laser diode is substantially parallel to the first direction.
Appendix 12D. The drive device is the drive device described in Appendix 4D.
The laser device according to Appendix 10D or 11D, wherein the delay unit, the waveform shaping unit, and the calculation unit are arranged in a second direction orthogonal to the thickness direction and the first direction.
Appendix 13D. The substrate is a laminated substrate including a first wiring layer and a second wiring layer, the second wiring layer functions as a ground layer, and the distance between the first wiring layer and the second wiring layer is 200 μm or less. The laser device according to any one of the appendices 10D to 12D.
Appendix 14D. The laser apparatus according to Appendix 13D, wherein the ground of the signal system and the ground of the power supply system are shared in the second wiring layer.
Appendix 15D.
A laser radar device including the laser device according to any one of Appendix 9D to 14D.
Appendix 16D. A vehicle comprising the laser radar device according to Appendix 15D.
 付記1E.レーザダイオードの駆動制御を行う駆動装置であって、
 導通状態と遮断状態とが切り替わるスイッチング素子と、
 コンデンサと、
 第1ダイオードと、
 電源電圧が供給される入力端子と、
 互い並列に接続され且つ各々が前記レーザダイオードのアノードに直列に接続された複数の抵抗器と、
 前記スイッチング素子、前記コンデンサ、前記第1ダイオードおよび前記複数の抵抗器が搭載された回路基板と、
を備えており、
 前記コンデンサは、第1端が前記レーザダイオードのカソードに接続され、第2端が前記スイッチング素子に接続されており、
 前記第1ダイオードは、アノードが、前記コンデンサの前記第1端と前記レーザダイオードのカソードとの接続点に接続されており、
 前記入力端子は、前記コンデンサの前記第2端と前記スイッチング素子との接続点に接続されており、
 前記複数の抵抗器は、前記回路基板の厚さ方向に直交する第1方向に並んでおり、
 前記複数の抵抗器は、前記第1方向に隣り合う2つの抵抗器を含み、当該2つの抵抗器の前記第1方向における離間距離は、前記複数の抵抗器のいずれか1つの前記第1方向における寸法以上である、駆動装置。
 付記2E.前記スイッチング素子は、第1端子、第2端子および第3端子を有するトランジスタであり、前記第3端子に入力される制御信号に応じて、前記導通状態と前記遮断状態とが切り替わる、付記1Eに記載の駆動装置。
 付記3E.
 前記複数の抵抗器の前記いずれか1つの第1端は、前記レーザダイオードのアノードに接続され、前記複数の抵抗器の前記いずれか1つの第2端は、基準電位に接地され、
 前記スイッチング素子の前記第2端子は、前記基準電位に接地されている、付記2Eに記載の駆動装置。
 付記4E.
 前記制御信号を生成するドライブ回路をさらに含んでおり、
 前記ドライブ回路と前記スイッチング素子とは、前記第1方向に並んでいる、付記2Eに記載の駆動装置。
 付記5E.
 前記ドライブ回路と前記第3端子との間に接続される電流値設定素子をさらに備えており、
 前記電流値設定素子は、前記回路基板上において、前記ドライブ回路と前記スイッチング素子との間に配置されている、付記4Eに記載の駆動装置。
 付記6E.
 前記コンデンサは前記入力端子に接続されており、前記スイッチング素子が前記遮断状態のときに、前記電源電圧が前記コンデンサに印加される、付記1E~5Eのいずれか1つに記載の駆動装置。
 付記7E.
 前記回路基板には、前記厚さ方向に見て、前記2つの抵抗器の間に、ランドパターンが形成されている、付記1E~6Eのいずれか1つに記載の駆動装置。
 付記8E.
 前記複数の抵抗器は抵抗器群を形成しており、
 前記コンデンサと前記抵抗器群とは、前記厚さ方向および前記第1方向に直交する第2方向に並んでいる、付記1E~7Eのいずれか1つに記載の駆動装置。
 付記9E.
 前記回路基板は、前記レーザダイオードを実装する実装領域を含み、
 前記実装領域は、前記第1方向に見て、前記コンデンサと前記抵抗器群との間に位置しており、かつ、前記コンデンサと前記抵抗器群とにそれぞれ隣接する、付記8Eに記載の駆動装置。
 付記10E.
 前記実装領域は、前記レーザダイオードのアノードを接続するアノード接続部、および、前記レーザダイオードのカソードを接続するカソード接続部を含み、
 前記アノード接続部と前記カソード接続部とは、前記厚さ方向に見て、前記第2方向に並んでいる、付記9Eに記載の駆動装置。
 付記11E.
 前記コンデンサと並列に接続され、かつ、前記抵抗器群と前記第2方向に並ぶ追加のコンデンサをさらに備えており、
 前記コンデンサと前記追加のコンデンサとによって、コンデンサ群が形成されている、付記8E~10Eのいずれか1つに記載の駆動装置。
 付記12E.
 前記スイッチング素子は、前記第2方向において前記コンデンサ群よりも前記抵抗器群が位置する側と反対側に配置されており、かつ、前記コンデンサ群に隣接する、付記11Eに記載の駆動装置。
 付記13E.
 前記複数の抵抗器は、第1抵抗器および第2抵抗器を含んでおり、
 前記第1抵抗器は、前記複数の抵抗器のうち前記第1方向の最も一方側に配置され、
 前記第2抵抗器は、前記複数の抵抗器のうち前記第1方向の最も他方側に配置され、
 前記コンデンサ群の前記第1方向の一方側の端縁は、前記第2方向に見て、前記第1抵抗器に重なり、前記コンデンサ群の前記第1方向の他方側の端縁は、前記第2方向に見て、前記第2抵抗器に重なる、付記11Eまたは12Eに記載の駆動装置。
 付記14E.
 前記複数の電子部品は、前記第1抵抗器および前記第2抵抗器と並列に接続された第3抵抗器をさらに含んでおり、
 前記第3抵抗器は、前記第1方向において、前記第1抵抗器と前記第2抵抗器との間に配置されている、付記13Eに記載の駆動装置。
 付記15E.
 前記回路基板は、絶縁層と、前記厚さ方向に積層され且つ前記絶縁層を介して互いに絶縁された第1配線層および第2配線層とを含んでおり、
 前記第2配線層は、基準電位に接地されている、付記8E~14Eのいずれか1つに記載の駆動装置。
 付記16E.
 前記回路基板は、前記厚さ方向に見て、複数の貫通電極が配置された集合領域を含んでおり、
 前記複数の貫通電極は、前記絶縁層を貫通し、かつ、前記第1配線層と前記第2配線層とを導通させており、
 前記集合領域は、前記第2方向において、前記抵抗器群よりも、前記コンデンサが位置する側と反対側に配置されている、付記15Eに記載の駆動装置。
 付記17E.
 前記回路基板は、前記厚さ方向において、前記第2配線層よりも前記第1配線層と反対側に配置され、かつ、電源パターンが形成された第3配線層を含んでいる、付記15Eまたは16Eに記載の駆動装置。
Appendix 1 E. A drive device that controls the drive of a laser diode.
A switching element that switches between a conductive state and a cutoff state,
With a capacitor
With the first diode
The input terminal to which the power supply voltage is supplied and
A plurality of resistors connected in parallel with each other and each connected in series with the anode of the laser diode.
A circuit board on which the switching element, the capacitor, the first diode, and the plurality of resistors are mounted,
Is equipped with
The capacitor has a first end connected to the cathode of the laser diode and a second end connected to the switching element.
In the first diode, the anode is connected to the connection point between the first end of the capacitor and the cathode of the laser diode.
The input terminal is connected to a connection point between the second end of the capacitor and the switching element.
The plurality of resistors are arranged in a first direction orthogonal to the thickness direction of the circuit board.
The plurality of resistors include two resistors adjacent to each other in the first direction, and the distance between the two resistors in the first direction is the distance between the two resistors in the first direction of any one of the plurality of resistors. Drive device that is greater than or equal to the dimensions in.
Appendix 2 E. The switching element is a transistor having a first terminal, a second terminal, and a third terminal, and the conduction state and the cutoff state are switched according to a control signal input to the third terminal. The drive device described.
Appendix 3E.
The first end of any one of the plurality of resistors is connected to the anode of the laser diode, and the second end of any one of the plurality of resistors is grounded to a reference potential.
The driving device according to Appendix 2E, wherein the second terminal of the switching element is grounded to the reference potential.
Appendix 4 E.
It further includes a drive circuit that generates the control signal.
The drive device according to Appendix 2E, wherein the drive circuit and the switching element are arranged in the first direction.
Appendix 5E.
Further, a current value setting element connected between the drive circuit and the third terminal is provided.
The drive device according to Appendix 4E, wherein the current value setting element is arranged between the drive circuit and the switching element on the circuit board.
Appendix 6 E.
The drive device according to any one of Appendix 1E to 5E, wherein the capacitor is connected to the input terminal, and the power supply voltage is applied to the capacitor when the switching element is in the cutoff state.
Appendix 7E.
The drive device according to any one of Appendix 1E to 6E, wherein a land pattern is formed between the two resistors when viewed in the thickness direction of the circuit board.
Appendix 8 E.
The plurality of resistors form a group of resistors, and the plurality of resistors form a group of resistors.
The driving device according to any one of Supplementary note 1E to 7E, wherein the capacitor and the resistor group are arranged in the thickness direction and the second direction orthogonal to the first direction.
Appendix 9E.
The circuit board includes a mounting area for mounting the laser diode.
The drive according to Appendix 8E, wherein the mounting region is located between the capacitor and the resistor group when viewed in the first direction, and is adjacent to the capacitor and the resistor group, respectively. apparatus.
Appendix 10 E.
The mounting region includes an anode connection for connecting the anode of the laser diode and a cathode connection for connecting the cathode of the laser diode.
The driving device according to Appendix 9E, wherein the anode connecting portion and the cathode connecting portion are arranged in the second direction when viewed in the thickness direction.
Appendix 11 E.
It is connected in parallel with the capacitor and further includes an additional capacitor aligned with the resistor group in the second direction.
The drive device according to any one of Appendix 8E to 10E, wherein a capacitor group is formed by the capacitor and the additional capacitor.
Appendix 12 E.
The driving device according to Appendix 11E, wherein the switching element is arranged on the side opposite to the side where the resistor group is located with respect to the capacitor group in the second direction, and is adjacent to the capacitor group.
Appendix 13 E.
The plurality of resistors include a first resistor and a second resistor.
The first resistor is arranged on the most one side of the plurality of resistors in the first direction.
The second resistor is arranged on the farthest side of the plurality of resistors in the first direction.
The one-sided edge of the capacitor group in the first direction overlaps the first resistor when viewed in the second direction, and the other-side edge of the first direction of the capacitor group is the first. The drive device according to Appendix 11E or 12E, which overlaps the second resistor when viewed in two directions.
Appendix 14E.
The plurality of electronic components further include the first resistor and a third resistor connected in parallel with the second resistor.
The driving device according to Appendix 13E, wherein the third resistor is arranged between the first resistor and the second resistor in the first direction.
Appendix 15 E.
The circuit board includes an insulating layer and a first wiring layer and a second wiring layer laminated in the thickness direction and insulated from each other via the insulating layer.
The drive device according to any one of Appendix 8E to 14E, wherein the second wiring layer is grounded to a reference potential.
Appendix 16 E.
The circuit board includes an assembly region in which a plurality of through electrodes are arranged when viewed in the thickness direction.
The plurality of through electrodes penetrate the insulating layer and conduct the first wiring layer and the second wiring layer.
The driving device according to Appendix 15E, wherein the gathering region is arranged on the side opposite to the side where the capacitor is located with respect to the resistor group in the second direction.
Appendix 17 E.
The circuit board is arranged on the side opposite to the first wiring layer with respect to the second wiring layer in the thickness direction, and includes a third wiring layer in which a power supply pattern is formed. The drive device according to 16E.

Claims (20)

  1.  レーザダイオードの駆動制御を行う駆動装置であって、
     導通状態と遮断状態とが切り替わるスイッチング素子と、
     コンデンサと、
     第1ダイオードと、
     電源電圧が供給される入力端子と、
    を備えており、
     前記コンデンサは、第1端が前記レーザダイオードのカソードに接続され、第2端が前記スイッチング素子に接続されており、
     前記第1ダイオードは、アノードが、前記コンデンサの前記第1端と前記レーザダイオードのカソードとの接続点に接続されており、
     前記入力端子は、前記コンデンサの前記第2端と前記スイッチング素子との接続点に接続されている、駆動装置。
    A drive device that controls the drive of a laser diode.
    A switching element that switches between a conductive state and a cutoff state,
    With a capacitor
    With the first diode
    The input terminal to which the power supply voltage is supplied and
    Is equipped with
    The capacitor has a first end connected to the cathode of the laser diode and a second end connected to the switching element.
    In the first diode, the anode is connected to the connection point between the first end of the capacitor and the cathode of the laser diode.
    The input terminal is a drive device connected to a connection point between the second end of the capacitor and the switching element.
  2.  第1端が前記レーザダイオードのアノードに接続された抵抗器をさらに備える、請求項1に記載の駆動装置。 The drive device according to claim 1, further comprising a resistor whose first end is connected to the anode of the laser diode.
  3.  前記抵抗器は、第2端が基準電位に接地されている、請求項2に記載の駆動装置。 The drive device according to claim 2, wherein the resistor has a second end grounded at a reference potential.
  4.  アノードが前記コンデンサの前記第1端に接続された第2ダイオードをさらに備える、請求項2または3に記載の駆動装置。 The drive device according to claim 2 or 3, further comprising a second diode whose anode is connected to the first end of the capacitor.
  5.  前記第2ダイオードは、カソードが、基準電位に接地されている、請求項4に記載の駆動装置。 The driving device according to claim 4, wherein the second diode has a cathode grounded to a reference potential.
  6.  前記スイッチング素子は、電界効果トランジスタである、請求項2ないし5のいずれか1つに記載の駆動装置。 The drive device according to any one of claims 2 to 5, wherein the switching element is a field effect transistor.
  7.  前記スイッチング素子のドレインは、前記コンデンサの前記第2端に接続され、
     前記スイッチング素子のソースは、基準電位に接地されており、
     前記スイッチング素子のゲートには、前記導通状態と前記遮断状態とを切り替えるための駆動信号が入力される、請求項6に記載の駆動装置。
    The drain of the switching element is connected to the second end of the capacitor.
    The source of the switching element is grounded to the reference potential.
    The drive device according to claim 6, wherein a drive signal for switching between the conduction state and the cutoff state is input to the gate of the switching element.
  8.  前記駆動信号を生成するドライブ回路をさらに備えている、請求項7に記載の駆動装置。 The drive device according to claim 7, further comprising a drive circuit for generating the drive signal.
  9.  前記スイッチング素子は、半導体材料からなる、請求項6ないし8のいずれか1つに記載の駆動装置。 The drive device according to any one of claims 6 to 8, wherein the switching element is made of a semiconductor material.
  10.  前記コンデンサ、前記第1ダイオード、前記入力端子、前記抵抗器が実装された回路基板をさらに備えている、請求項2ないし9のいずれか1つに記載の駆動装置。 The drive device according to any one of claims 2 to 9, further comprising a circuit board on which the capacitor, the first diode, the input terminal, and the resistor are mounted.
  11.  前記コンデンサに並列に接続された追加のコンデンサをさらに備えており、
     前記コンデンサと前記追加のコンデンサとは、前記回路基板の厚さ方向に直交する第1方向において並んで配置され、コンデンサ群を形成する、 請求項10に記載の駆動装置。
    It also has an additional capacitor connected in parallel with the capacitor.
    The driving device according to claim 10, wherein the capacitor and the additional capacitor are arranged side by side in a first direction orthogonal to the thickness direction of the circuit board to form a capacitor group.
  12.  前記抵抗器に並列に接続された追加の抵抗器をさらに備えており、
     前記抵抗器と前記追加の抵抗器とは、前記第1方向に並んで配置され、抵抗器群を形成する、請求項11に記載の駆動装置。
    It also has an additional resistor connected in parallel with the resistor.
    The driving device according to claim 11, wherein the resistor and the additional resistor are arranged side by side in the first direction to form a group of resistors.
  13.  前記コンデンサ群と前記抵抗器群とは、前記厚さ方向および前記第1方向に直交する第2方向に並んでいる、請求項12に記載の駆動装置。 The drive device according to claim 12, wherein the capacitor group and the resistor group are arranged in the thickness direction and the second direction orthogonal to the first direction.
  14.  前記第1ダイオードは、前記第2方向において、前記コンデンサ群と前記抵抗器群との間に挟まれている、請求項13に記載の駆動装置。 The drive device according to claim 13, wherein the first diode is sandwiched between the capacitor group and the resistor group in the second direction.
  15.  前記スイッチング素子は、前記第2方向において、前記コンデンサ群を基準に、前記抵抗器群と反対側に位置する、請求項13または14に記載の駆動装置。 The drive device according to claim 13 or 14, wherein the switching element is located on the opposite side of the resistor group with respect to the capacitor group in the second direction.
  16.  前記スイッチング素子は、前記第2方向において、前記コンデンサ群に隣接する、請求項15に記載の駆動装置。 The driving device according to claim 15, wherein the switching element is adjacent to the capacitor group in the second direction.
  17.  TO-Canパッケージ型のレーザダイオードを接続可能な第1端子をさらに備えており、
     前記第1端子は、前記回路基板に実装されている、請求項13ないし16のいずれか1つに記載の駆動装置。
    It also has a first terminal to which a TO-Can package type laser diode can be connected.
    The drive device according to any one of claims 13 to 16, wherein the first terminal is mounted on the circuit board.
  18.  前記第1端子は、前記第2方向において、前記コンデンサ群と、前記抵抗器群との間に配置される、請求項17に記載の駆動装置。 The drive device according to claim 17, wherein the first terminal is arranged between the capacitor group and the resistor group in the second direction.
  19.  面実装型のレーザダイオードを接続可能な第2端子をさらに備えており、
     前記第2端子は、前記回路基板に実装されている、請求項10ないし18のいずれか1つに記載の駆動装置。
    It also has a second terminal to which a surface-mounted laser diode can be connected.
    The drive device according to any one of claims 10 to 18, wherein the second terminal is mounted on the circuit board.
  20.  前記第2端子は、前記回路基板の厚さ方向に見て、前記回路基板の端縁に沿って配置されている、請求項19に記載の駆動装置。 The drive device according to claim 19, wherein the second terminal is arranged along an edge of the circuit board when viewed in the thickness direction of the circuit board.
PCT/JP2020/031298 2019-08-23 2020-08-19 Drive device WO2021039542A1 (en)

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JP2019152844A JP2022177325A (en) 2019-08-23 2019-08-23 Drive unit
JP2019-172267 2019-09-20
JP2019172267A JP2022177329A (en) 2019-09-20 2019-09-20 laser diode drive circuit
JP2019-173043 2019-09-24
JP2019173043A JP2022177330A (en) 2019-09-24 2019-09-24 Drive unit

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JP2016152336A (en) * 2015-02-18 2016-08-22 株式会社豊田中央研究所 Laser diode driving circuit and laser radar device
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Publication number Priority date Publication date Assignee Title
JP2009059929A (en) * 2007-08-31 2009-03-19 Seiko Epson Corp Drive circuit for semiconductor light emitting element and light source device using the same, lighting device, monitor device, and image display device
JP2010171460A (en) * 2010-04-23 2010-08-05 Panasonic Corp Laser drive circuit and optical communication device
JP2015179436A (en) * 2014-03-19 2015-10-08 古河電気工業株式会社 Drive circuit of light-emitting element, light source device, and driving method of light-emitting element
JP2016152336A (en) * 2015-02-18 2016-08-22 株式会社豊田中央研究所 Laser diode driving circuit and laser radar device
JP2017181062A (en) * 2016-03-28 2017-10-05 富士通株式会社 Laser radar device and control method of the same
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