WO2021036848A1 - 一种数据处理方法及装置 - Google Patents

一种数据处理方法及装置 Download PDF

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Publication number
WO2021036848A1
WO2021036848A1 PCT/CN2020/109613 CN2020109613W WO2021036848A1 WO 2021036848 A1 WO2021036848 A1 WO 2021036848A1 CN 2020109613 W CN2020109613 W CN 2020109613W WO 2021036848 A1 WO2021036848 A1 WO 2021036848A1
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Prior art keywords
block number
physical block
memory
file
logical
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PCT/CN2020/109613
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English (en)
French (fr)
Inventor
童朝柱
宋云龙
任磊
俞超
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华为技术有限公司
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Publication of WO2021036848A1 publication Critical patent/WO2021036848A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7201—Logical to physical mapping or translation of blocks or pages

Definitions

  • This application relates to the computer field, and in particular to a data processing method and device.
  • the file system is responsible for file management.
  • the processor can convert application access to files into data read and write operations.
  • the file system may be a flash file system (Flash Friendly File System, F2FS).
  • the memory may be an Embedded Multimedia Card (eMMC) or Universal Flash Storage (UFS).
  • eMMC Embedded Multimedia Card
  • UFS Universal Flash Storage
  • the mapping table contained in F2FS is used to save the mapping relationship between the file and the logical address of the stored data.
  • the mapping table contained in eMMC/UFS is used to store the mapping relationship between logical addresses and physical addresses.
  • the mapping table of the file system is Meta Data.
  • the memory mapping table refers to the Flash Translate Layer (FTL). In the process of data read and write operations, it is necessary to obtain the physical address for accessing the flash memory (such as Nand Flash) according to the mapping table of the file system and the mapping table of the memory.
  • FTL Flash Translate Layer
  • the mapping granularity of the memory mapping table can be set to block granularity.
  • the mapping granularity of the mapping table of the file system is usually the page granularity. Since the mapping granularity of the mapping table of the memory is different from the mapping granularity of the mapping table of the file system, the physical address for accessing the flash memory cannot be obtained according to the mapping table of the file system and the mapping table of the memory. Therefore, there is no definite solution for how to associate the memory mapping table with the file system mapping table, and perform data read and write operations based on the memory mapping table and the file system mapping table with different mapping granularities.
  • the present application provides a data processing method and device, which solves the problem of how to perform data read and write operations based on a mapping table of a memory with different mapping granularities and a mapping table of a file system.
  • the present application provides a data processing method, which can be applied to a memory, or the method can be applied to a communication device that can support the memory to implement the method, for example, the communication device includes a chip system.
  • the method includes: after receiving the write request, allocating the storage space indicated by the physical block number, and starting to write the data of the file at the address indicated by the offset value in the storage space indicated by the physical block number, and the write request includes the data of the file; , According to the physical block number and the offset value in the storage space indicated by the physical block number, a logical address is generated, and the logical address is fed back.
  • the logical address is used to indicate the logical block number corresponding to the physical block number and the offset value in the storage space indicated by the physical block number.
  • the memory mapping table only needs to store the relevant entries of the storage space divided by the block granularity, so that the mapping table of the file system stores the relevant entries of the storage space of the block granularity and the page granularity within the block.
  • the mapping table of the file system is associated with the mapping table of the memory, and data read and write operations are performed based on the mapping table of the memory and the mapping table of the file system with different mapping granularities.
  • mapping relationship between the physical block number and the logical block number corresponding to the physical block number is generated, and the mapping table of the memory includes an entry for the mapping relationship between the physical block number and the logical block number corresponding to the physical block number.
  • the mapping granularity of the entries of the memory mapping table is a block
  • the storage capacity corresponding to the block can reach hundreds of MB in size, so that the size of the memory mapping table can be reduced to a few KB level, thereby realizing the permanent resident mapping table of the memory
  • the memory of the memory can reduce the number of accesses to the memory (such as flash memory (Nand Flash)) when the mobile phone performs data access, and shorten the access delay of reading and writing data.
  • the present application provides a data processing method, which can be applied to a processor, or the method can be applied to a communication device that can support the processor to implement the method, for example, the communication device includes a chip system.
  • the method includes: after receiving the logical address, generating a mapping relationship between the file and the logical address according to the logical address, wherein the logical address is used to indicate the logical block number corresponding to the physical block number and the offset in the storage space indicated by the physical block number Value, the mapping table of the file system includes entries for the mapping relationship between files and logical addresses.
  • mapping table of the file system is associated with the mapping table of the memory, and data read and write operations are performed based on the mapping table of the memory and the mapping table of the file system with different mapping granularities.
  • the present application provides a data processing method, which can be applied to a memory, or the method can be applied to a communication device that can support the memory to implement the method, for example, the communication device includes a chip system.
  • the method includes: after obtaining the file information, querying the mapping table of the file system according to the file information to obtain the logical address corresponding to the file, and sending a read request, the read request including the logical address and the data length.
  • the file information includes the file name, file address, and data length, and the logical address is used to indicate the logical block number corresponding to the physical block number and the offset value in the storage space indicated by the physical block number.
  • the memory mapping table only needs to store the relevant entries of the storage space divided by the block granularity, so that the mapping table of the file system stores the relevant entries of the storage space of the block granularity and the page granularity within the block.
  • the mapping table of the file system is associated with the mapping table of the memory, and data read and write operations are performed based on the mapping table of the memory and the mapping table of the file system with different mapping granularities.
  • the present application provides a data processing method, which can be applied to a processor, or the method can be applied to a communication device that can support the processor to implement the method, for example, the communication device includes a chip system.
  • the method includes: after receiving the read request including the logical address and the data length, determining the logical block number and the offset value according to the logical address; querying the mapping table of the memory to obtain the physical block number corresponding to the logical block number; indicating from the physical block number Start reading data of data length according to the address indicated by the offset value in the storage space.
  • the logical address is used to indicate the logical block number corresponding to the physical block number and the offset value in the storage space indicated by the physical block number.
  • the memory mapping table only needs to store the relevant entries of the storage space divided by the block granularity, so that the mapping table of the file system stores the relevant entries of the storage space of the block granularity and the page granularity within the block.
  • the mapping table of the file system is associated with the mapping table of the memory, and data read and write operations are performed based on the mapping table of the memory and the mapping table of the file system with different mapping granularities.
  • this application also provides a communication device for implementing the method described in the first aspect.
  • the communication device is a communication device that supports a memory to implement the method described in the first aspect, for example, the communication device includes a chip system.
  • the communication device includes at least one processing unit and a transceiving unit, wherein the transceiving unit is used to receive a write request, and the write request includes file data; the processing unit is used to allocate storage space indicated by a physical block number; the processing The unit is also used to start writing data of the file at the address indicated by the offset value in the storage space indicated by the physical block number; the processing unit is also used to start writing data in the file according to the physical block number and the offset in the storage space indicated by the physical block number The value generates a logical address; the transceiver unit is also used to feed back the logical address to the processor.
  • the processing unit is also used to generate a mapping relationship between the physical block number and the logical block number corresponding to the physical block number, and the mapping table of the memory includes the physical block number and the logical block number corresponding to the physical block number. The entry of the mapping relationship.
  • this application also provides a communication device for implementing the method described in the second aspect.
  • the communication device is a communication device that supports a processor to implement the method described in the second aspect, for example, the communication device includes a chip system.
  • the communication device includes at least one processing unit and a transceiving unit, wherein the transceiving unit is used to receive a logical address, and the logical address is used to indicate the logical block number corresponding to the physical block number and the deviation in the storage space indicated by the physical block number. Value shift;
  • the processing unit is used to generate a mapping relationship between a file and a logical address according to the logical address fed back by the memory, and the mapping table of the file system includes an entry for the mapping relationship between the file and the logical address.
  • the present application also provides a communication device for implementing the method described in the third aspect.
  • the communication device is a communication device that supports a processor to implement the method described in the third aspect, for example, the communication device includes a chip system.
  • the communication device includes at least one processing unit and a transceiver unit, wherein the processing unit is used to obtain file information, and the file information includes file name, file address, and data length; the processing unit is also used to query the file according to the file information.
  • the mapping table of the system obtains the logical address corresponding to the file.
  • the logical address is used to indicate the logical block number corresponding to the physical block number and the offset value in the storage space indicated by the physical block number; the transceiver unit is used to send a read request to the memory ,
  • the read request includes the logical address and data length.
  • this application also provides a communication device for implementing the method described in the fourth aspect.
  • the communication device is a communication device that supports a memory to implement the method described in the fourth aspect, for example, the communication device includes a chip system.
  • the communication device includes at least one processing unit and a transceiving unit, wherein the transceiving unit is used to receive a read request including a logical address and a data length; the processing unit is used to determine the logical block number and the data length according to the logical address fed back by the processor.
  • the offset value, the logical address is used to indicate the logical block number corresponding to the physical block number and the offset value in the storage space indicated by the physical block number; the processing unit is also used to query the mapping table of the memory to obtain the logical block number corresponding to the logical block number Physical block number; the processing unit is also used to read data of data length starting from the address indicated by the offset value in the storage space indicated by the physical block number.
  • the functional modules of the fifth aspect and the eighth aspect described above can be implemented by hardware, or can be implemented by hardware executing corresponding software.
  • the hardware or software includes one or more modules corresponding to the above-mentioned functions.
  • the transceiver is used to complete the function of the transceiver unit
  • the processor is used to complete the function of the processing unit
  • the memory is used to process the program instructions of the method of the present application by the processor.
  • the processor, the transceiver, and the memory are connected through a bus and communicate with each other.
  • the present application also provides a memory for implementing the method described in the first aspect or the fourth aspect.
  • the memory is a communication device for a computer device to implement the method described in the first aspect or the fourth aspect, for example, the communication device includes a chip system.
  • the memory includes: an interface circuit and a processor.
  • the interface circuit is used to perform the functions of the transceiver unit in the fifth aspect or the eighth aspect, and the processor is used to perform the functions of the processing unit in the fifth aspect or the eighth aspect.
  • the specific data processing method is the same as the corresponding description in the first aspect or the fourth aspect, and will not be repeated here.
  • this application also provides a processor for implementing the method described in the second or third aspect.
  • the processor is a communication device for a computer device to implement the method described in the second aspect or the third aspect, for example, the communication device includes a chip system.
  • the processor includes: an interface circuit and a processing unit.
  • the interface circuit is used to perform the functions of the transceiver unit in the sixth aspect or the seventh aspect
  • the processing unit is used to perform the functions of the processing unit in the sixth aspect or the seventh aspect.
  • the specific data processing method is the same as the corresponding description in the second aspect or the third aspect, and will not be repeated here.
  • this application provides a computer device for implementing the methods described in the first and second aspects above.
  • the computer device is a communication device that supports the terminal to implement the methods described in the first aspect and the second aspect, for example, the communication device includes a chip system.
  • the computer device includes a processor, which is configured to implement the functions of the methods described in the first aspect and the second aspect.
  • the computer device may also include a memory for storing program instructions and data. The memory is coupled with the processor, and the processor can call and execute program instructions stored in the memory to implement the functions in the methods described in the first aspect and the second aspect.
  • the computer device may further include a communication interface, and the communication interface is used for the communication device to communicate with other devices. Exemplarily, if the computer device is a terminal, the other device is a network device.
  • the memory is used to allocate the storage space indicated by the physical block number after receiving the write request, and the write request includes the data of the file; the memory is also used to start writing at the address indicated by the offset value in the storage space indicated by the physical block number The data entered into the file; the memory is also used to generate a logical address according to the physical block number and the offset value in the storage space indicated by the physical block number.
  • the logical address is used to indicate the logical block number corresponding to the physical block number and the storage indicated by the physical block number
  • the offset value in the space is also used to feed back the logical address to the processor;
  • the processor is used to generate the mapping relationship between the file and the logical address according to the logical address fed back by the memory, the mapping table of the file system includes the mapping relationship between the file and the logical address Table entry.
  • the memory is also used to generate the mapping relationship between the physical block number and the logical block number corresponding to the physical block number
  • the mapping table of the memory includes the mapping relationship between the physical block number and the logical block number corresponding to the physical block number. Table entry.
  • this application provides a computer device for implementing the methods described in the third and fourth aspects above.
  • the computer equipment is a communication device that supports the terminal to implement the methods described in the third aspect and the fourth aspect, for example, the communication device includes a chip system.
  • the computer device includes a processor, configured to implement the functions of the methods described in the third aspect and the fourth aspect.
  • the computer device may also include a memory for storing program instructions and data. The memory is coupled with the processor, and the processor can call and execute program instructions stored in the memory to implement the functions in the methods described in the third aspect and the fourth aspect.
  • the computer device may further include a communication interface, and the communication interface is used for the communication device to communicate with other devices. Exemplarily, if the computer device is a terminal, the other device is a network device.
  • the processor is used to obtain file information, which includes file name, file address, and data length; the processor is also used to query the mapping table of the file system according to the file information to obtain the logical address corresponding to the file, and the logical address is used to indicate the physical The logical block number corresponding to the block number and the offset value in the storage space indicated by the physical block number; the processor is also used to send a read request to the memory, which includes the logical address and data length; the memory is used to respond to the logic fed back by the processor The address determines the logical block number and offset value; the memory is also used to query the memory mapping table to obtain the physical block number corresponding to the logical block number; the memory is also used to obtain the address indicated by the offset value from the storage space indicated by the physical block number Start reading data of data length.
  • the physical block number indicates the physical block
  • the size of the physical block is an integer multiple of the size of the erase block of the flash memory.
  • the size of the physical block may refer to the size of the storage space indicated by the physical block number.
  • the offset value is the start address of the page in the storage space indicated by the physical block number.
  • this application also provides a computer-readable storage medium, including: computer software instructions; when the computer software instructions are executed in a computer device, the computer device is caused to execute any one of the first to fourth aspects mentioned above. The method described in the aspect.
  • this application also provides a computer program product containing instructions, which when the computer program product runs in a computer device, causes the computer device to execute the method described in any one of the first to fourth aspects. .
  • the present application provides a chip system that includes a processor and may also include a memory for implementing the functions of the computer device in the above method.
  • the chip system can be composed of chips, or it can include chips and other discrete devices.
  • FIG. 1 is a schematic structural diagram of an electronic device provided by an embodiment of this application.
  • FIG. 2 is a flowchart of a data processing method provided by an embodiment of the application
  • FIG. 3 provides a flowchart of address translation for a write operation according to an embodiment of the application
  • FIG. 4 is a flowchart of another data processing method provided by an embodiment of the application.
  • FIG. 5 is a flowchart of address conversion for a read operation according to an embodiment of the application.
  • FIG. 6 is a schematic diagram of the composition of a communication device provided by this application.
  • FIG. 7 is a schematic diagram of the composition of another communication device provided by this application.
  • words such as “exemplary” or “for example” are used as examples, illustrations, or illustrations. Any embodiment or design solution described as “exemplary” or “for example” in the embodiments of the present application should not be construed as being more preferable or advantageous than other embodiments or design solutions. To be precise, words such as “exemplary” or “for example” are used to present related concepts in a specific manner.
  • File system is a method of storing and organizing user data. It uses the abstract logical concept of files and tree directories to replace the concept of data blocks used by storage devices such as hard disks and optical discs, providing convenience for users to access and find files.
  • the data of the directory needs to save the names and index (inode) numbers of all the sub-files in the directory.
  • the file name is visible to the user, and the user manages and accesses the file through the file name;
  • the inode number is the internal index of the file in the file system, and is used to associate the metadata of the file with the data of the file.
  • the file system Since the file system records the directory and file name to which the file belongs, in the application scenario of the file system, the user does not need to care about which data blocks of the storage device the data in the file is stored, but only needs to remember the directory and the file to which the file belongs.
  • the file name can complete the access to the data in the file.
  • the file system is an important part of the computer's operating system, used to control the access to the data stored in the computer's storage medium (such as flash memory).
  • the file system presents a continuous logical storage space to the application program, and the application program can perform random access in the continuous logical space.
  • file access needs to be indexed by inode, and each file uniquely corresponds to an inode.
  • the inode of the file includes basic information of the file (such as file name, file size, file creation time, file modification time, etc.), and pointer information that directly or indirectly points to the data block storing the file data. Therefore, after reading the inode of the file, the data of the file can be obtained according to the inode.
  • the inode index structure in different file systems is different.
  • the storage space provided by the memory includes multiple partitions, such as a system partition and a user partition.
  • the system partition is used to store system files
  • the user partition is used to store user data.
  • the multiple partitions are all mounted on one or more file systems. The data of each file is stored in a certain partition of the storage medium.
  • a file system mapping table and a memory mapping table are stored in the computer.
  • the mapping table of the file system is used to store the mapping relationship between the file and the logical address, and the logical address is allocated by the file system.
  • the memory mapping table is used to store the mapping relationship between the physical page number and the starting address of the storage space indicated by the physical page number. The data accessed by the application needs to go through two address translations of the file system mapping table and the memory mapping table.
  • the memory capacity ranges from tens of GB to hundreds of GB.
  • the mapping granularity of the memory mapping table is page granularity (4KB), and one entry can manage 4B of storage space. Therefore, the memory capacity is generally the size of the memory mapping table. 1000 times the size, the memory mapping table size is from tens of MB to hundreds of MB.
  • the memory of the memory is generally only a few MB in size, resulting in only a very small part of the memory mapping table entries that can be loaded into the memory.
  • the address range covered by these entries is usually less than 1 GB.
  • the memory will first obtain the entry of the memory mapping table corresponding to the data from the flash memory (Nand Flash), and after it is loaded into the memory, the data can be obtained by querying the entry of the memory mapping table. The actual storage address of, and then access the flash memory for the second time to obtain the data content according to this address, resulting in multiple accesses to the flash memory, causing a larger delay.
  • the flash memory Nand Flash
  • each partition of the storage medium is divided into a plurality of blocks.
  • each block has the same size.
  • the size of each block is 1024 bytes (byte) or 4096 bytes.
  • mapping granularity of the mapping table of the file system is usually the page granularity. Since the mapping granularity of the mapping table of the memory is different from the mapping granularity of the mapping table of the file system, the physical address for accessing the flash memory cannot be obtained according to the mapping table of the file system and the mapping table of the memory. Therefore, there is no definite solution for how to associate the memory mapping table with the file system mapping table, and perform data read and write operations based on the memory mapping table and the file system mapping table with different mapping granularities.
  • the embodiment of the present application provides a data processing method. After the memory determines the physical block number, a logical address is generated according to the physical block number and the starting address of the page granularity in the storage space indicated by the physical block number. The logical address is fed back to the processor, so that the processor generates the mapping relationship between the logical address and the file, and stores the table entry of the mapping relationship between the file and the logical address in the mapping table of the file system.
  • mapping table of the memory only needs to store the related entries of the storage space divided by the block granularity, and the mapping table of the file system stores the related entries of the storage space of the block granularity and the page granularity in the block, so that the mapping table of the file system and The memory mapping table association can perform data read and write operations based on the memory mapping table with different mapping granularities and the file system mapping table.
  • the computer device may be the electronic device 100.
  • the structure of the electronic device 100 may be as shown in FIG. 1.
  • the electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, and an antenna 2.
  • Mobile communication module 150 wireless communication module 160, audio module 170, speaker 170A, receiver 170B, microphone 170C, earphone jack 170D, sensor module 180, buttons 190, motor 191, indicator 192, camera 193, display screen 194, and Subscriber identification module (subscriber identification module, SIM) card interface 195, etc.
  • SIM Subscriber identification module
  • the sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, an air pressure sensor 180C, a magnetic sensor 180D, an acceleration sensor 180E, a distance sensor 180F, a proximity light sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, and ambient light Sensor 180L, bone conduction sensor 180M, etc.
  • the structure illustrated in this embodiment does not constitute a specific limitation on the electronic device 100.
  • the electronic device 100 may include more or fewer components than shown, or combine certain components, or split certain components, or arrange different components.
  • the illustrated components can be implemented in hardware, software, or a combination of software and hardware.
  • the processor 110 may include one or more processing units.
  • the processor 110 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), and an image signal processor. (image signal processor, ISP), controller, video codec, digital signal processor (digital signal processor, DSP), baseband processor, and/or neural-network processing unit (NPU), etc.
  • AP application processor
  • modem processor modem processor
  • GPU graphics processing unit
  • image signal processor image signal processor
  • ISP image signal processor
  • controller video codec
  • digital signal processor digital signal processor
  • DSP digital signal processor
  • NPU neural-network processing unit
  • the different processing units may be independent devices or integrated in one or more processors.
  • a memory may also be provided in the processor 110 to store instructions and data.
  • the memory in the processor 110 is a cache memory.
  • the memory can store instructions or data that the processor 110 has just used or used cyclically. If the processor 110 needs to use the instruction or data again, it can be directly called from the memory. Repeated accesses are avoided, the waiting time of the processor 110 is reduced, and the efficiency of the system is improved.
  • the processor 110 may include one or more interfaces.
  • Interfaces can include integrated circuit (I2C) interfaces, integrated circuit built-in audio (inter-integrated circuit sound, I2S) interfaces, pulse code modulation (PCM) interfaces, universal asynchronous transmitters receiver/transmitter, UART) interface, mobile industry processor interface (MIPI), general-purpose input/output (GPIO) interface, subscriber identity module (SIM) interface, and / Or Universal Serial Bus (USB) interface, etc.
  • I2C integrated circuit
  • I2S integrated circuit built-in audio
  • PCM pulse code modulation
  • UART mobile industry processor interface
  • MIPI mobile industry processor interface
  • GPIO general-purpose input/output
  • SIM subscriber identity module
  • USB Universal Serial Bus
  • the interface connection relationship between the modules illustrated in this embodiment is merely a schematic description, and does not constitute a structural limitation of the electronic device 100.
  • the electronic device 100 may also adopt different interface connection modes in the foregoing embodiments, or a combination of multiple interface connection modes.
  • the charging management module 140 is used to receive charging input from the charger.
  • the charger can be a wireless charger or a wired charger.
  • the charging management module 140 may receive the charging input of the wired charger through the USB interface 130.
  • the charging management module 140 may receive the wireless charging input through the wireless charging coil of the electronic device 100. While the charging management module 140 charges the battery 142, it can also supply power to the electronic device through the power management module 141.
  • the wireless communication function of the electronic device 100 can be implemented by the antenna 1, the antenna 2, the mobile communication module 150, the wireless communication module 160, the modem processor, and the baseband processor.
  • the antenna 1 and the antenna 2 are used to transmit and receive electromagnetic wave signals.
  • Each antenna in the electronic device 100 can be used to cover a single or multiple communication frequency bands. Different antennas can also be reused to improve antenna utilization.
  • Antenna 1 can be multiplexed as a diversity antenna of a wireless local area network.
  • the antenna can be used in combination with a tuning switch.
  • the mobile communication module 150 can provide a wireless communication solution including 2G/3G/4G/5G and the like applied to the electronic device 100.
  • the mobile communication module 150 may include at least one filter, switch, power amplifier, low noise amplifier (LNA), etc.
  • the mobile communication module 150 can receive electromagnetic waves by the antenna 1, and perform processing such as filtering, amplifying and transmitting the received electromagnetic waves to the modem processor for demodulation.
  • the mobile communication module 150 can also amplify the signal modulated by the modem processor, and convert it into electromagnetic wave radiation via the antenna 1.
  • at least part of the functional modules of the mobile communication module 150 may be provided in the processor 110.
  • at least part of the functional modules of the mobile communication module 150 and at least part of the modules of the processor 110 may be provided in the same device.
  • the modem processor may include a modulator and a demodulator.
  • the modulator is used to modulate the low frequency baseband signal to be sent into a medium and high frequency signal.
  • the demodulator is used to demodulate the received electromagnetic wave signal into a low-frequency baseband signal. Then the demodulator transmits the demodulated low-frequency baseband signal to the baseband processor for processing. After the low-frequency baseband signal is processed by the baseband processor, it is passed to the application processor.
  • the application processor outputs a sound signal through an audio device (not limited to the speaker 170A, the receiver 170B, etc.), or displays an image or video through the display screen 194.
  • the modem processor may be an independent device. In other embodiments, the modem processor may be independent of the processor 110 and be provided in the same device as the mobile communication module 150 or other functional modules.
  • the wireless communication module 160 can provide applications on the electronic device 100 including wireless local area networks (WLAN) (such as wireless fidelity (Wi-Fi) networks), bluetooth (BT), and global navigation satellites.
  • WLAN wireless local area networks
  • BT wireless fidelity
  • GNSS global navigation satellite system
  • FM frequency modulation
  • NFC near field communication technology
  • infrared technology infrared, IR
  • the wireless communication module 160 may be one or more devices integrating at least one communication processing module.
  • the wireless communication module 160 receives electromagnetic waves via the antenna 2, frequency modulates and filters the electromagnetic wave signals, and sends the processed signals to the processor 110.
  • the wireless communication module 160 can also receive the signal to be sent from the processor 110, perform frequency modulation, amplify it, and convert it into electromagnetic waves through the antenna 2 and radiate it out.
  • the antenna 1 of the electronic device 100 is coupled with the mobile communication module 150, and the antenna 2 is coupled with the wireless communication module 160, so that the electronic device 100 can communicate with the network and other devices through wireless communication technology.
  • the wireless communication technology may include global system for mobile communications (GSM), general packet radio service (GPRS), code division multiple access (CDMA), broadband Code division multiple access (wideband code division multiple access, WCDMA), time-division code division multiple access (TD-SCDMA), long term evolution (LTE), BT, GNSS, WLAN, NFC , FM, and/or IR technology, etc.
  • the GNSS may include global positioning system (GPS), global navigation satellite system (GLONASS), Beidou navigation satellite system (BDS), quasi-zenith satellite system (quasi -zenith satellite system, QZSS) and/or satellite-based augmentation systems (SBAS).
  • GPS global positioning system
  • GLONASS global navigation satellite system
  • BDS Beidou navigation satellite system
  • QZSS quasi-zenith satellite system
  • SBAS satellite-based augmentation systems
  • the electronic device 100 implements a display function through a GPU, a display screen 194, an application processor, and the like.
  • the GPU is an image processing microprocessor, which is connected to the display screen 194 and the application processor.
  • the GPU is used to perform mathematical and geometric calculations for graphics rendering.
  • the processor 110 may include one or more GPUs, which execute program instructions to generate or change display information.
  • the internal memory 121 may be used to store computer executable program code, and the executable program code includes instructions.
  • the processor 110 executes various functional applications and data processing of the electronic device 100 by running instructions stored in the internal memory 121.
  • the processor 110 may implement an address mapping function by executing instructions stored in the internal memory 121.
  • the internal memory 121 may include a storage program area and a storage data area.
  • the storage program area can store an operating system, at least one application program (such as a sound playback function, an image playback function, etc.) required by at least one function.
  • the data storage area can store data (such as audio data, phone book, etc.) created during the use of the electronic device 100.
  • the internal memory 121 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one flash memory device, universal flash storage (UFS), eMMC, and the like.
  • the processor 110 executes various functional applications and data processing of the electronic device 100 by running instructions stored in the internal memory 121 and/or instructions stored in a memory provided in the processor.
  • the internal memory 121 may be a flash memory device, and a memory mapping table is stored in the flash memory device.
  • the touch sensor 180K is also called a "touch device”.
  • the touch sensor 180K may be disposed on the display screen 194, and the touch screen is composed of the touch sensor 180K and the display screen 194, which is also called a “touch screen”.
  • the touch sensor 180K is used to detect touch operations acting on or near it.
  • the touch sensor can pass the detected touch operation to the application processor to determine the type of touch event.
  • the visual output related to the touch operation can be provided through the display screen 194.
  • the touch sensor 180K may also be disposed on the surface of the electronic device 100, which is different from the position of the display screen 194.
  • the operating system of the electronic device 100 may adopt a layered architecture, an event-driven architecture, a microkernel architecture, a microservice architecture, or a cloud architecture.
  • Fig. 2 is a flowchart of a data processing method provided by an embodiment of the application.
  • the electronic device is a mobile phone as an example.
  • the mobile phone includes a processor and memory.
  • the method may include:
  • the memory receives a write request.
  • the memory allocates storage space indicated by the physical block number.
  • the storage capacity of the memory may be pre-divided into multiple storage spaces according to block granularity, and one physical block number may be used to indicate one storage space.
  • the multiple storage spaces include a data storage space for storing hot data and a data storage space for storing cold data.
  • the write request includes data and data attributes, and the data attributes include at least one of hot data attributes and cold data attributes.
  • the memory can allocate storage space according to data attributes, store hot data in a storage space that can store hot data, and store cold data in a storage space that can store cold data. Data for the same data attribute can be stored in at least one storage space.
  • the write request also includes information such as file data and data length.
  • the memory starts to write data of the file at the address indicated by the offset value in the storage space indicated by the physical block number.
  • the storage space indicated by the physical block number is divided at page granularity, and when reading and writing the memory, the memory is read and written at the page granularity. Therefore, the memory starts to write data at the address indicated by the offset value in the storage space indicated by the physical block number. Specifically, the data of the data length included in the write request is written to the memory.
  • the offset value here may refer to the start address of the page in the storage space indicated by the physical block number.
  • the address indicated by the offset value may be the start address of the storage space indicated by the physical block number. If the storage space indicated by the physical block number has already stored other data, the address indicated by the offset value may be the start address of the page after the start address of the storage space indicated by the physical block number.
  • the memory generates a logical address according to the physical block number and the offset value in the storage space indicated by the physical block number.
  • the memory feeds back the logical address to the processor.
  • the processor receives a logical address.
  • the processor generates a mapping relationship between the file and the logical address according to the logical address fed back by the memory.
  • the logical address is generated according to the physical block number of the storage space of the data written to the file and the offset value in the storage space indicated by the physical block number, and the logical address is fed back to the processor.
  • Logical address the logical address is used to indicate the logical block number corresponding to the physical block number and the offset value in the storage space indicated by the physical block number.
  • the processor receives the logical address, it generates a mapping relationship between the file and the logical address according to the logical address fed back by the memory.
  • the processor updates the mapping table of the file system, and the mapping table of the file system includes table entries of the mapping relationship between the file and the logical address.
  • the file includes file name, file address, index number and data, etc.
  • the logical block number and offset value are fed back to the processor, so that the file stored in the mapping table of the file system corresponds to
  • the logical address of is notified by the memory, and the mapping table of the file system is associated with the mapping table of the memory through the offset value, so that data writing operations can be performed based on the mapping table of the memory and the mapping table of the file system with different mapping granularities.
  • the memory also needs to update the mapping table of the memory, as described in step S208.
  • S208 The memory generates a mapping relationship between the physical block number and the logical block number corresponding to the physical block number.
  • the memory may store a memory mapping table, and the memory mapping table is used to record the mapping relationship between the physical block number and the logical block number corresponding to the physical block number. "The mapping relationship between the physical block number and the logical block number corresponding to the physical block number" can also be described as the mapping relationship between the physical block number and the start address of the storage space indicated by the physical block number. The storage capacity between the start addresses of the two storage spaces represents the size of a physical block.
  • the mapping granularity of the entries of the memory mapping table is a block
  • the storage capacity corresponding to the block can reach hundreds of MB in size, so that the size of the memory mapping table can be reduced to a few KB level, thereby realizing the permanent resident mapping table of the memory
  • the memory of the memory can reduce the number of accesses to the memory (such as flash memory (Nand Flash)) when the mobile phone performs data access, and shorten the access delay of reading and writing data.
  • the memory After determining the physical block number and the logical block number corresponding to the physical block number, the memory generates a mapping relationship between the physical block number and the logical block number corresponding to the physical block number.
  • the memory updates the mapping table of the memory, and the mapping table of the memory includes an entry of the mapping relationship between the physical block number and the logical block number corresponding to the physical block number. So that when the memory receives the read request, it reads the data in the storage space indicated by the physical block number according to the entry.
  • sequence of the steps of the data processing method provided in the embodiments of the present application can be adjusted appropriately, and the steps can also be increased or decreased accordingly according to the situation.
  • sequence between S208 and S205 can be interchanged, that is, the memory can first generate the mapping relationship between the physical block number and the logical block number corresponding to the physical block number, and then feed back the logical address to the processor.
  • the processor may first allocate a temporary logical address according to the file name included in the file information.
  • the temporary logical address can be any logical address in the mapping table of the file system.
  • FIG. 3 provides an address translation flowchart for a write operation in an embodiment of the present application.
  • the processor can obtain the address of the file storing the application (for example: application logical block address (Logical Block Address, LBA)-application).
  • the processor performs address conversion according to the mapping table of the file system, that is, converts the file address into a logical address. Because when the processor writes data into the memory, the specific location where the data is written into the memory is determined by the memory. In order to comply with the provisions of the protocol, at this time, the logical address allocated by the processor is a temporary logical address.
  • LBA Logical Block Address
  • LBA-application For example, converting LBA-application to LBA-blockt+paget, where blockt is a logical block number of block granularity, and paget is an offset address in the storage space indicated by the physical block number corresponding to the logical block number. It should be noted that the offset address may be address information of page granularity in the storage space.
  • the processor sends the logical address (such as: LBA-blockt+paget) to the memory.
  • the controller of the memory reallocates a storage space according to the mapping table of the memory, obtains the new physical block number and offset value, and writes data from the address indicated by the offset value in the storage space indicated by the new physical block number, and
  • the new logical address is fed back to the processor.
  • LBA-blockn+pagex is fed back to the processor.
  • blockn represents the new logical block number
  • pagex represents the offset value in the storage space indicated by the physical block number corresponding to the new logical block number.
  • blockn' is the new physical block number.
  • the memory generates a mapping relationship between the new physical block number and the new logical block number, and updates the memory mapping table.
  • the memory mapping table includes entries for the mapping relationship between the new physical block number and the new logical block number.
  • the processor generates a new mapping relationship between the logical address and the file, and updates the mapping table of the file system.
  • the mapping table of the file system includes entries for the mapping relationship between the new logical address and the file.
  • FIG. 4 is a flowchart of a data processing method provided by an embodiment of the application.
  • the electronic device is a mobile phone as an example.
  • the mobile phone includes a processor and memory.
  • the method may include:
  • S401 The processor obtains file information.
  • the processor can obtain the file name, file address, offset value in the file, and data length included in the file information.
  • S402 The processor queries the mapping table of the file system according to the file information, and obtains the logical address corresponding to the file.
  • the mapping table of the file system is used to store the correspondence between the files managed by the file system and the logical addresses of the stored files.
  • the processor loads the mapping table of the file system into the memory (cache) of the processor, and the processor obtains the logical address corresponding to the file according to the mapping table of the file system.
  • the logical address is used to indicate the logical block number corresponding to the physical block number and the offset value in the storage space indicated by the physical block number.
  • the offset value is the start address of the page in the storage space indicated by the physical block number.
  • the processor sends a read request to the memory, and transmits the logical address and file information to the memory.
  • the processor sends a read request, where the read request includes a logical address and a data length.
  • the memory receives the read request.
  • the memory determines the logical block number and the offset value according to the logical address.
  • the memory first determines the storage capacity from the start address of the memory to the logical address, and then divides the storage capacity by the size of the physical block to obtain the quotient and remainder. Among them, the quotient represents the logical block number, and the remainder represents the offset value. If the remainder is 0, the offset value represents the starting address of the first page in the storage space indicated by the physical block number corresponding to the logical block number.
  • the size of the physical block is an integer multiple of the size of the erase block of the flash memory.
  • S406 The memory queries the mapping table of the memory to obtain the physical block number corresponding to the logical block number.
  • the controller of the memory queries the memory mapping table of the memory according to the logical block number to obtain the physical block number corresponding to the logical block number.
  • the mapping table of the memory includes table entries of the mapping relationship between the physical block number and the logical block number corresponding to the physical block number.
  • the memory starts to read data of the data length according to the address indicated by the offset value in the storage space indicated by the physical block number.
  • the logical block number and offset value are fed back to the processor, so that the file stored in the mapping table of the file system corresponds to The logical address is notified by the memory, and the mapping table of the file system is associated with the mapping table of the memory through the offset value, so that when the processor reads data, the memory determines the logical block number and offset according to the logical address fed back by the processor Value, query the mapping table of the memory to obtain the physical block number corresponding to the logical block number, so that the memory starts to read data of the data length from the address indicated by the offset value in the storage space indicated by the physical block number.
  • FIG. 5 provides an address conversion flowchart of a read operation according to an embodiment of the present application.
  • the processor can obtain the file address (such as: LBA-application) that stores the application, and the processor converts the file address into a logical address according to the mapping table of the file system (such as: LBA-blockn+pagex), where blockn is the logical block number of the block granularity, and pagex is the offset address in the storage space indicated by the physical block number corresponding to the logical block number.
  • the offset address may be address information of page granularity in the storage space.
  • the processor transmits the logical address to the memory, and the memory parses the logical address to obtain the logical block number and offset value.
  • the memory queries the memory mapping table to obtain the physical block number corresponding to the logical block number (for example: blockn'), the mapped address is LBA-blockn'+pagex, and this address points to the actual flash memory address where the data is stored.
  • the memory starts to read data of the data length according to the address indicated by the offset value (pagex) in the storage space indicated by the mapped physical block number (blockn').
  • the memory and the processor include corresponding hardware structures and/or software modules for performing respective functions.
  • the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed by hardware or computer software-driven hardware depends on the specific application scenarios and design constraints of the technical solution.
  • FIG. 6 and FIG. 7 are schematic structural diagrams of possible communication devices provided by embodiments of this application. These communication devices can be used to implement the functions of the memory or the processor in the foregoing method embodiments, and therefore can also achieve the beneficial effects of the foregoing method embodiments.
  • the communication device may be the electronic device 100 as shown in FIG. 1, or may be a module (such as a chip) applied to an electronic device.
  • the communication device 600 includes a processing unit 601 and a transceiving unit 602.
  • the communication device 600 is configured to implement the functions of the memory or the processor in the method embodiment shown in FIG. 2 or FIG. 4.
  • the transceiving unit 602 is used to support the communication device to perform S201 and S205;
  • the processing unit 601 is used to support the communication device to perform S202, S203, S204 and S208 .
  • the transceiving unit 602 is used to support the communication device to perform S206; the processing unit 601 is used to support the communication device to perform S207.
  • the transceiver unit 602 is used to support the communication device to perform S404; the processing unit 601 is used to support the communication device to perform S405-S407.
  • the transceiving unit 602 is used to support the communication device to perform S401 and S403; the processing unit 601 is used to support the communication device to perform S402.
  • processing unit 601 and the transceiver unit 602 can be obtained directly by referring to the relevant description in the method embodiment shown in FIG. 2 or FIG. 4, and will not be repeated here.
  • the communication device provided in the embodiment of the present application is used to execute the method of any of the foregoing embodiments, and therefore can achieve the same effect as the method of the foregoing embodiment.
  • the communication device 700 includes a processor 701 and an interface circuit 702.
  • the processor 701 and the interface circuit 702 are coupled to each other.
  • the interface circuit 702 may be a transceiver or an input/output interface.
  • the communication device 700 may further include a memory 703 for storing instructions executed by the processor 701 or storing input data required by the processor 701 to execute the instructions or storing data generated after the processor 701 executes the instructions.
  • the processor 701 is used to perform the function of the above-mentioned processing unit 601
  • the interface circuit 702 is used to perform the function of the above-mentioned transceiving unit 602.
  • the processor in the embodiments of the present application may be a central processing unit (Central Processing Unit, CPU), or other general-purpose processors, digital signal processors (Digital Signal Processors, DSPs), and application specific integrated circuits. (Application Specific Integrated Circuit, ASIC), Field Programmable Gate Array (Field Programmable Gate Array, FPGA) or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.
  • the general-purpose processor may be a microprocessor or any conventional processor.
  • the method steps in the embodiments of the present application can be implemented by hardware, or can be implemented by a processor executing software instructions.
  • Software instructions can be composed of corresponding software modules, which can be stored in random access memory (Random Access Memory, RAM), flash memory, read-only memory (Read-Only Memory, ROM), and programmable read-only memory (Programmable ROM) , PROM), Erasable Programmable Read-Only Memory (Erasable PROM, EPROM), Electrically Erasable Programmable Read-Only Memory (Electrically EPROM, EEPROM), register, hard disk, mobile hard disk, CD-ROM or well-known in the art Any other form of storage medium.
  • An exemplary storage medium is coupled to the processor, so that the processor can read information from the storage medium and can write information to the storage medium.
  • the storage medium may also be an integral part of the processor.
  • the processor and the storage medium may be located in the ASIC.
  • the ASIC can be located in a network device or a terminal device.
  • the processor and the storage medium may also exist as discrete components in the network device or the terminal device.
  • the above-mentioned embodiments it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof.
  • software it can be implemented in the form of a computer program product in whole or in part.
  • the computer program product includes one or more computer programs or instructions.
  • the computer may be a general-purpose computer, a special-purpose computer, a computer network, network equipment, user equipment, or other programmable devices.
  • the computer program or instruction may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium.
  • the computer program or instruction may be downloaded from a website, computer, The server or data center transmits to another website site, computer, server or data center through wired or wireless means.
  • the computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or a data center that integrates one or more available media.
  • the usable medium may be a magnetic medium, such as a floppy disk, a hard disk, and a magnetic tape; it may also be an optical medium, such as a digital video disc (digital video disc, DVD); and it may also be a semiconductor medium, such as a solid state drive (solid state drive). , SSD).
  • “at least one” refers to one or more, and “multiple” refers to two or more.
  • “And/or” describes the association relationship of the associated objects, indicating that there can be three relationships, for example, A and/or B, which can mean: A alone exists, A and B exist at the same time, and B exists alone, where A, B can be singular or plural.
  • the character “/” generally indicates that the associated object before and after is an “or” relationship; in the formula of this application, the character “/” indicates that the associated object before and after is a kind of "division" Relationship.

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Abstract

公开了一种数据处理方法及装置，涉及计算机领域，解决了如何基于映射粒度不同的存储器的映射表和文件系统的映射表进行数据读写操作的问题。该方法包括：在存储器确定了物理块号后，根据物理块号和物理块号指示的存储空间内的页粒度的起始地址生成逻辑地址，向处理器反馈逻辑地址，使处理器生成逻辑地址和文件的映射关系，在文件系统的映射表中存储文件与逻辑地址的映射关系的表项。从而，存储器的映射表中只需要存储与块粒度划分存储空间的相关表项，文件系统的映射表中存储块粒度和块内页粒度的存储空间的相关表项，使文件系统的映射表和存储器的映射表关联，基于映射粒度不同的存储器的映射表和文件系统的映射表进行数据读写操作。

Description

一种数据处理方法及装置
本申请要求于2019年08月26日提交国家知识产权局、申请号为201910792489.3、发明名称为“一种数据处理方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机领域，尤其涉及一种数据处理方法及装置。
背景技术
在电子设备中，数据以文件的方式保存在存储器上的。文件系统负责文件的管理。处理器可以将应用对文件的访问转化成数据读写操作。文件系统可以是闪存文件系统(Flash Friendly File System，F2FS)。存储器可以是嵌入式多媒体卡(Embedded Multimedia Card，eMMC)或通用闪存存储(Universal Flash Storage，UFS)。F2FS内部包含的映射表用于保存文件与存储数据的逻辑地址的映射关系。eMMC/UFS内部包含的映射表用于保存逻辑地址和物理地址的映射关系。文件系统的映射表就是元数据(Meta Data)。存储器的映射表是指闪存转换层(Flash Translate Layer，FTL)。在数据读写操作过程中，需要根据文件系统的映射表和存储器的映射表来获取访问闪存(如：Nand Flash)的物理地址。
在数据读写操作过程中，为了将存储器的映射表能够完全加载到内存中，存储器的映射表的映射粒度可以设置为块粒度。但是，文件系统的映射表的映射粒度通常是页粒度。由于存储器的映射表的映射粒度与文件系统的映射表的映射粒度不同，无法根据文件系统的映射表和存储器的映射表来获取访问闪存的物理地址。因此，如何将存储器的映射表与文件系统的映射表关联，基于映射粒度不同的存储器的映射表和文件系统的映射表进行数据读写操作还没有一个确定的方案。
发明内容
本申请提供一种数据处理方法及装置，解决了如何基于映射粒度不同的存储器的映射表和文件系统的映射表进行数据读写操作的问题。
为达到上述目的，本申请采用如下技术方案：
第一方面，本申请提供了一种数据处理方法，该方法可应用于存储器，或者该方法可应用于可以支持存储器实现该方法的通信装置，例如该通信装置包括芯片系统。该方法包括：接收到写请求后，分配物理块号指示的存储空间，在物理块号指示的存储空间内的偏移值指示的地址开始写入文件的数据，写请求包括文件的数据；然后，根据物理块号和物理块号指示的存储空间内的偏移值生成逻辑地址，反馈逻辑地址。其中，逻辑地址用于指示物理块号对应的逻辑块号和物理块号指示的存储空间内的偏移值。
本申请提供的数据处理方法，存储器的映射表中只需要存储与块粒度划分存储空间的相关表项，使文件系统的映射表中存储块粒度和块内页粒度的存储空间的相关表项，从而，文件系统的映射表和存储器的映射表关联，基于映射粒度不同的存储器的 映射表和文件系统的映射表进行数据读写操作。
进一步的，生成物理块号和物理块号对应的逻辑块号的映射关系，存储器的映射表包括物理块号和该物理块号对应的逻辑块号的映射关系的表项。
由于该存储器的映射表的表项的映射粒度是块，块对应的存储容量可以达到数百MB大小，这样可以将存储器的映射表的大小缩小到数KB级别，从而实现存储器的映射表常驻存储器的内存，在手机进行数据访问时可以减少访问存储器(如：闪存(Nand Flash))的次数，缩短了读写数据访问延迟。
第二方面，本申请提供了一种数据处理方法，该方法可应用于处理器，或者该方法可应用于可以支持处理器实现该方法的通信装置，例如该通信装置包括芯片系统。该方法包括：在接收到逻辑地址后，根据逻辑地址生成文件与逻辑地址的映射关系，其中，逻辑地址用于指示物理块号对应的逻辑块号和物理块号指示的存储空间内的偏移值，文件系统的映射表包括文件与逻辑地址的映射关系的表项。
本申请提供的数据处理方法，存储器的映射表中只需要存储与块粒度划分存储空间的相关表项，文件系统的映射表中存储块粒度和块内页粒度的存储空间的相关表项，使文件系统的映射表和存储器的映射表关联，基于映射粒度不同的存储器的映射表和文件系统的映射表进行数据读写操作。
第三方面，本申请提供了一种数据处理方法，该方法可应用于存储器，或者该方法可应用于可以支持存储器实现该方法的通信装置，例如该通信装置包括芯片系统。该方法包括：获取到文件信息后，根据文件信息查询文件系统的映射表，得到文件对应的逻辑地址，发送读请求，读请求包括逻辑地址和数据长度。其中，文件信息包括文件名称、文件地址和数据长度，逻辑地址用于指示物理块号对应的逻辑块号和物理块号指示的存储空间内的偏移值。
本申请提供的数据处理方法，存储器的映射表中只需要存储与块粒度划分存储空间的相关表项，使文件系统的映射表中存储块粒度和块内页粒度的存储空间的相关表项，从而，文件系统的映射表和存储器的映射表关联，基于映射粒度不同的存储器的映射表和文件系统的映射表进行数据读写操作。
第四方面，本申请提供了一种数据处理方法，该方法可应用于处理器，或者该方法可应用于可以支持处理器实现该方法的通信装置，例如该通信装置包括芯片系统。该方法包括：接收到包括逻辑地址和数据长度的读请求后，根据逻辑地址确定逻辑块号和偏移值；查询存储器的映射表，得到逻辑块号对应的物理块号；从物理块号指示的存储空间内依据偏移值指示的地址开始读取数据长度的数据。其中，逻辑地址用于指示物理块号对应的逻辑块号和物理块号指示的存储空间内的偏移值。
本申请提供的数据处理方法，存储器的映射表中只需要存储与块粒度划分存储空间的相关表项，使文件系统的映射表中存储块粒度和块内页粒度的存储空间的相关表项，从而，文件系统的映射表和存储器的映射表关联，基于映射粒度不同的存储器的映射表和文件系统的映射表进行数据读写操作。
第五方面，本申请还提供了一种通信装置，用于实现上述第一方面描述的方法。所述通信装置为支持存储器实现该第一方面描述的方法的通信装置，例如该通信装置包括芯片系统。例如该通信装置包括至少一个处理单元和收发单元，其中，所述收发 单元用于接收写请求，写请求包括文件的数据；所述处理单元用于分配物理块号指示的存储空间；所述处理单元还用于在物理块号指示的存储空间内的偏移值指示的地址开始写入文件的数据；所述处理单元还用于根据物理块号和物理块号指示的存储空间内的偏移值生成逻辑地址；所述收发单元还用于向处理器反馈逻辑地址。
在一种可能的设计中，所述处理单元还用于生成物理块号和物理块号对应的逻辑块号的映射关系，存储器的映射表包括物理块号和物理块号对应的逻辑块号的映射关系的表项。
第六方面，本申请还提供了一种通信装置，用于实现上述第二方面描述的方法。所述通信装置为支持处理器实现该第二方面描述的方法的通信装置，例如该通信装置包括芯片系统。例如所述通信装置包括至少一个处理单元和收发单元，其中，所述收发单元用于接收逻辑地址，逻辑地址用于指示物理块号对应的逻辑块号和物理块号指示的存储空间内的偏移值；所述处理单元用于根据存储器反馈的逻辑地址生成文件与逻辑地址的映射关系，文件系统的映射表包括文件与逻辑地址的映射关系的表项。
第七方面，本申请还提供了一种通信装置，用于实现上述第三方面描述的方法。所述通信装置为支持处理器实现该第三方面描述的方法的通信装置，例如该通信装置包括芯片系统。例如所述通信装置包括至少一个处理单元和收发单元，其中，所述处理单元用于获取文件信息，文件信息包括文件名称、文件地址和数据长度；所述处理单元还用于根据文件信息查询文件系统的映射表，得到文件对应的逻辑地址，逻辑地址用于指示物理块号对应的逻辑块号和物理块号指示的存储空间内的偏移值；所述收发单元用于向存储器发送读请求，读请求包括逻辑地址和数据长度。
第八方面，本申请还提供了一种通信装置，用于实现上述第四方面描述的方法。所述通信装置为支持存储器实现该第四方面描述的方法的通信装置，例如该通信装置包括芯片系统。例如该通信装置包括至少一个处理单元和收发单元，其中，所述收发单元用于接收包括逻辑地址和数据长度的读请求；所述处理单元用于根据处理器反馈的逻辑地址确定逻辑块号和偏移值，逻辑地址用于指示物理块号对应的逻辑块号和物理块号指示的存储空间内的偏移值；所述处理单元还用于查询存储器的映射表，得到逻辑块号对应的物理块号；所述处理单元还用于从物理块号指示的存储空间内依据偏移值指示的地址开始读取数据长度的数据。
需要说明的是，上述第五方面和第八方面的功能模块可以通过硬件实现，也可以通过硬件执行相应的软件实现。硬件或软件包括一个或多个与上述功能相对应的模块。例如，收发器，用于完成收发单元的功能，处理器，用于完成处理单元的功能，存储器，用于处理器处理本申请的方法的程序指令。处理器、收发器和存储器通过总线连接并完成相互间的通信。具体的，可以参考第一方面所述的方法至第四方面所述的方法中描述的功能。
第九方面，本申请还提供了一种存储器，用于实现上述第一方面或第四方面描述的方法。所述存储器为计算机设备实现该第一方面或第四方面描述的方法的通信装置，例如该通信装置包括芯片系统。在一种可能的设备中，该存储器包括：接口电路和处理器。接口电路用于执行上述第五方面或第八方面中收发单元的功能，处理器用于执行上述第五方面或第八方面中处理单元的功能。
可选地，具体的数据处理方法同第一方面或第四方面中相应的描述，这里不再赘述。
第十方面，本申请还提供了一种处理器，用于实现上述第二方面或第三方面描述的方法。所述处理器为计算机设备实现该第二方面或第三方面描述的方法的通信装置，例如该通信装置包括芯片系统。在一种可能的设备中，该处理器包括：接口电路和处理单元。接口电路用于执行上述第六方面或第七方面中收发单元的功能，处理单元用于执行上述第六方面或第七方面中处理单元的功能。
可选地，具体的数据处理方法同第二方面或第三方面中相应的描述，这里不再赘述。
第十一方面，本申请提供了一种计算机设备，用于实现上述第一方面和第二方面描述的方法。所述计算机设备为支持终端实现该第一方面和第二方面描述的方法的通信装置，例如该通信装置包括芯片系统。例如所述计算机设备包括处理器，用于实现上述第一方面和第二方面描述的方法的功能。所述计算机设备还可以包括存储器，用于存储程序指令和数据。所述存储器与所述处理器耦合，所述处理器可以调用并执行所述存储器中存储的程序指令，用于实现上述第一方面和第二方面描述的方法中的功能。所述计算机设备还可以包括通信接口，所述通信接口用于该通信装置与其它设备进行通信。示例性地，若所述计算机设备为终端，该其它设备为网络设备。
具体的，存储器用于接收到写请求后，分配物理块号指示的存储空间，写请求包括文件的数据；存储器还用于在物理块号指示的存储空间内的偏移值指示的地址开始写入文件的数据；存储器还用于根据物理块号和物理块号指示的存储空间内的偏移值生成逻辑地址，逻辑地址用于指示物理块号对应的逻辑块号和物理块号指示的存储空间内的偏移值；存储器还用于向处理器反馈逻辑地址；处理器用于根据存储器反馈的逻辑地址生成文件与逻辑地址的映射关系，文件系统的映射表包括文件与逻辑地址的映射关系的表项。
在一种可能的设计中，存储器还用于生成物理块号和物理块号对应的逻辑块号的映射关系，存储器的映射表包括物理块号和物理块号对应的逻辑块号的映射关系的表项。
第十二方面，本申请提供了一种计算机设备，用于实现上述第三方面和第四方面描述的方法。所述计算机设备为支持终端实现该第三方面和第四方面描述的方法的通信装置，例如该通信装置包括芯片系统。例如所述计算机设备包括处理器，用于实现上述第三方面和第四方面描述的方法的功能。所述计算机设备还可以包括存储器，用于存储程序指令和数据。所述存储器与所述处理器耦合，所述处理器可以调用并执行所述存储器中存储的程序指令，用于实现上述第三方面和第四方面描述的方法中的功能。所述计算机设备还可以包括通信接口，所述通信接口用于该通信装置与其它设备进行通信。示例性地，若所述计算机设备为终端，该其它设备为网络设备。
具体的，处理器用于获取文件信息，文件信息包括文件名称、文件地址和数据长度；处理器还用于根据文件信息查询文件系统的映射表，得到文件对应的逻辑地址，逻辑地址用于指示物理块号对应的逻辑块号和物理块号指示的存储空间内的偏移值；处理器还用于向存储器发送读请求，读请求包括逻辑地址和数据长度；存储器用于根 据处理器反馈的逻辑地址确定逻辑块号和偏移值；存储器还用于查询存储器的映射表，得到逻辑块号对应的物理块号；存储器还用于从物理块号指示的存储空间内依据偏移值指示的地址开始读取数据长度的数据。
在一种可能的设计中，物理块号指示了物理块，物理块的大小为闪存的擦除块的大小的整数倍。物理块的大小可以是指物理块号指示的存储空间的大小。
在另一种可能的设计中，偏移值为物理块号指示的存储空间内的页的起始地址。
第十三方面，本申请还提供了一种计算机可读存储介质，包括：计算机软件指令；当计算机软件指令在计算机设备中运行时，使得计算机设备执行上述第一方面至第四方面中任一方面所述的方法。
第十四方面，本申请还提供了一种包含指令的计算机程序产品，当计算机程序产品在计算机设备中运行时，使得计算机设备执行上述第一方面至第四方面中任一方面所述的方法。
第十五方面，本申请提供了一种芯片系统，该芯片系统包括处理器，还可以包括存储器，用于实现上述方法中计算机设备的功能。该芯片系统可以由芯片构成，也可以包含芯片和其他分立器件。
另外，上述任意方面的设计方式所带来的技术效果可参见第一方面至第四方面中不同设计方式所带来的技术效果，此处不再赘述。
本申请中，计算机设备、存储器和处理器的名字对设备本身不构成限定，在实际实现中，这些设备可以以其他名称出现。只要各个设备的功能和本申请类似，属于本申请权利要求及其等同技术的范围之内。
附图说明
图1为本申请一实施例提供的电子设备的结构示意图；
图2为本申请实施例提供的一种数据处理方法的流程图；
图3为本申请实施例提供一种写操作的地址转换流程图；
图4为本申请实施例提供的另一种数据处理方法的流程图；
图5为本申请实施例提供一种读操作的地址转换流程图；
图6为本申请提供的一种通信装置的组成示意图；
图7为本申请提供的另一种通信装置的组成示意图。
具体实施方式
本申请说明书和权利要求书及上述附图中的术语“第一”、“第二”和“第三”等是用于区别不同对象，而不是用于限定特定顺序。
在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
为了下述各实施例的描述清楚简洁，首先给出相关技术的简要介绍：
文件系统是一种存储和组织用户数据的方法，其使用文件和树形目录的抽象逻辑概念代替了硬盘、光盘等存储设备使用数据块的概念，为用户访问和查找文件提供了方便。为了管理目录下的子文件和子目录，目录的数据需要保存该目录下所有子文件 的名字和索引(inode)号。其中，文件名是用户可见的，用户通过文件名来管理和访问文件；inode号是文件系统中文件的内部索引，用于关联该文件的元数据与该文件的数据。由于文件系统会记录文件所属的目录和文件名，因此，在文件系统的应用场景中，用户不需要关心文件中的数据存储在存储设备的哪些数据块上，只需要记住文件所属的目录和文件名就可以完成对文件中的数据的访问。
文件系统是计算机的操作系统中的重要组成部分，用于控制对计算机的存储介质(如：闪存)所保存的数据的存取。在计算机中，文件系统对应用程序呈现出一段连续的逻辑存储空间，应用程序可以在所述连续的逻辑空间中进行随机访问。
在Linux操作系统中，文件的访问均需要通过inode来索引，每个文件唯一对应一个inode。文件的inode包括文件的基本信息(例如文件名称、文件大小、文件创建时间、文件修改时间等)、以及直接或间接指向存储文件数据的数据块的指针信息。因此，读取到文件的inode后即可根据该inode获取到该文件的数据。不同文件系统中的inode索引结构不同。
一般的，存储器(存储介质)所提供的存储空间包括多个分区(partition)，如：系统分区和用户分区，系统分区用于存储系统文件，用户分区用于存储用户数据。所述多个分区均被挂载在一个或多个文件系统。每个文件的数据均被存入到存储介质的某个分区中。
计算机中存储有文件系统的映射表和存储器的映射表。文件系统的映射表用于存储文件与逻辑地址的映射关系，所述逻辑地址是由文件系统分配的。存储器的映射表用于存储物理页号和该物理页号指示的存储空间的起始地址的映射关系。应用访问的数据需要经过文件系统的映射表和存储器的映射表的两次地址转换。
通常，存储器容量大小从几十GB到几百GB，存储器的映射表的映射粒度是页粒度(4KB)，一个表项可以管理4B的存储空间，因此，存储器的容量一般是存储器的映射表的大小的1000倍，存储器的映射表大小是从几十MB到几百MB。但是，存储器的内存一般只几个MB大小，导致只能有极小一部分的存储器的映射表的表项加载到内存中，这些表项覆盖的地址范围通常不到1个GB，如果应用访问的数据在这个地址范围之外，则会导致存储器首先要从闪存(Nand Flash)中获取数据对应的存储器的映射表的表项，加载到内存之后，才能通过查询存储器的映射表的表项获得数据的真正存放地址，再根据这个地址第二次访问闪存获得数据内容，从而产生多次访问闪存，造成较大的延时。
传统技术中，可以通过增大存储器的映射表的映射粒度，从当前的页粒度(4KB)扩大到数百MB的块(block)粒度，从而，大大减小了存储器的映射表的大小，能够实现将存储器的映射表全部表项加载到存储器的内存中，解决了在读写数据的过程中，可能需要多次访问闪存存取存储器的映射表表项的问题，降低了读写数据的延迟。例如，存储介质的每个分区被划分为多个块(block)。对于同一文件系统，每个block的大小相同。典型的，每个block的大小是1024字节(byte)或者4096字节。
但是，文件系统的映射表的映射粒度通常是页粒度。由于存储器的映射表的映射粒度与文件系统的映射表的映射粒度不同，无法根据文件系统的映射表和存储器的映射表来获取访问闪存的物理地址。因此，如何将存储器的映射表与文件系统的映射表 关联，基于映射粒度不同的存储器的映射表和文件系统的映射表进行数据读写操作还没有一个确定的方案。
为了解决上述问题，本申请实施例提供了一种数据处理方法，在存储器确定了物理块号后，根据物理块号和物理块号指示的存储空间内的页粒度的起始地址生成逻辑地址，向处理器反馈逻辑地址，使处理器生成逻辑地址和文件的映射关系，在文件系统的映射表中存储文件与逻辑地址的映射关系的表项。从而，存储器的映射表中只需要存储与块粒度划分存储空间的相关表项，文件系统的映射表中存储块粒度和块内页粒度的存储空间的相关表项，使得文件系统的映射表和存储器的映射表关联，可以基于映射粒度不同的存储器的映射表和文件系统的映射表进行数据读写操作。
下面将结合附图对本申请实施例的实施方式进行详细描述。
在本申请一实施例中，计算机设备可以是电子设备100。电子设备100的结构可以如图1所示。
电子设备100可以包括处理器110，外部存储器接口120，内部存储器121，通用串行总线(universal serial bus，USB)接口130，充电管理模块140，电源管理模块141，电池142，天线1，天线2，移动通信模块150，无线通信模块160，音频模块170，扬声器170A，受话器170B，麦克风170C，耳机接口170D，传感器模块180，按键190，马达191，指示器192，摄像头193，显示屏194，以及用户标识模块(subscriber identification module，SIM)卡接口195等。其中传感器模块180可以包括压力传感器180A，陀螺仪传感器180B，气压传感器180C，磁传感器180D，加速度传感器180E，距离传感器180F，接近光传感器180G，指纹传感器180H，温度传感器180J，触摸传感器180K，环境光传感器180L，骨传导传感器180M等。
可以理解的是，本实施例示意的结构并不构成对电子设备100的具体限定。在另一些实施例中，电子设备100可以包括比图示更多或更少的部件，或者组合某些部件，或者拆分某些部件，或者不同的部件布置。图示的部件可以以硬件，软件或软件和硬件的组合实现。
处理器110可以包括一个或多个处理单元，例如：处理器110可以包括应用处理器(application processor，AP)，调制解调处理器，图形处理器(graphics processing unit，GPU)，图像信号处理器(image signal processor，ISP)，控制器，视频编解码器，数字信号处理器(digital signal processor，DSP)，基带处理器，和/或神经网络处理器(neural-network processing unit，NPU)等。其中，不同的处理单元可以是独立的器件，也可以集成在一个或多个处理器中。
处理器110中还可以设置存储器，用于存储指令和数据。在一些实施例中，处理器110中的存储器为高速缓冲存储器。该存储器可以保存处理器110刚用过或循环使用的指令或数据。如果处理器110需要再次使用该指令或数据，可从所述存储器中直接调用。避免了重复存取，减少了处理器110的等待时间，因而提高了系统的效率。
在一些实施例中，处理器110可以包括一个或多个接口。接口可以包括集成电路(inter-integrated circuit，I2C)接口，集成电路内置音频(inter-integrated circuit sound，I2S)接口，脉冲编码调制(pulse code modulation，PCM)接口，通用异步收发传输器(universal asynchronous receiver/transmitter，UART)接口，移动产业处理器接口(mobile  industry processor interface，MIPI)，通用输入输出(general-purpose input/output，GPIO)接口，用户标识模块(subscriber identity module，SIM)接口，和/或通用串行总线(universal serial bus，USB)接口等。
可以理解的是，本实施例示意的各模块间的接口连接关系，只是示意性说明，并不构成对电子设备100的结构限定。在本申请另一些实施例中，电子设备100也可以采用上述实施例中不同的接口连接方式，或多种接口连接方式的组合。
充电管理模块140用于从充电器接收充电输入。其中，充电器可以是无线充电器，也可以是有线充电器。在一些有线充电的实施例中，充电管理模块140可以通过USB接口130接收有线充电器的充电输入。在一些无线充电的实施例中，充电管理模块140可以通过电子设备100的无线充电线圈接收无线充电输入。充电管理模块140为电池142充电的同时，还可以通过电源管理模块141为电子设备供电。
电子设备100的无线通信功能可以通过天线1，天线2，移动通信模块150，无线通信模块160，调制解调处理器以及基带处理器等实现。
天线1和天线2用于发射和接收电磁波信号。电子设备100中的每个天线可用于覆盖单个或多个通信频带。不同的天线还可以复用，以提高天线的利用率。例如：可以将天线1复用为无线局域网的分集天线。在另外一些实施例中，天线可以和调谐开关结合使用。
移动通信模块150可以提供应用在电子设备100上的包括2G/3G/4G/5G等无线通信的解决方案。移动通信模块150可以包括至少一个滤波器，开关，功率放大器，低噪声放大器(low noise amplifier，LNA)等。移动通信模块150可以由天线1接收电磁波，并对接收的电磁波进行滤波，放大等处理，传送至调制解调处理器进行解调。移动通信模块150还可以对经调制解调处理器调制后的信号放大，经天线1转为电磁波辐射出去。在一些实施例中，移动通信模块150的至少部分功能模块可以被设置于处理器110中。在一些实施例中，移动通信模块150的至少部分功能模块可以与处理器110的至少部分模块被设置在同一个器件中。
调制解调处理器可以包括调制器和解调器。其中，调制器用于将待发送的低频基带信号调制成中高频信号。解调器用于将接收的电磁波信号解调为低频基带信号。随后解调器将解调得到的低频基带信号传送至基带处理器处理。低频基带信号经基带处理器处理后，被传递给应用处理器。应用处理器通过音频设备(不限于扬声器170A，受话器170B等)输出声音信号，或通过显示屏194显示图像或视频。在一些实施例中，调制解调处理器可以是独立的器件。在另一些实施例中，调制解调处理器可以独立于处理器110，与移动通信模块150或其他功能模块设置在同一个器件中。
无线通信模块160可以提供应用在电子设备100上的包括无线局域网(wireless local area networks，WLAN)(如无线保真(wireless fidelity，Wi-Fi)网络)，蓝牙(bluetooth，BT)，全球导航卫星系统(global navigation satellite system，GNSS)，调频(frequency modulation，FM)，近距离无线通信技术(near field communication，NFC)，红外技术(infrared，IR)等无线通信的解决方案。无线通信模块160可以是集成至少一个通信处理模块的一个或多个器件。无线通信模块160经由天线2接收电磁波，将电磁波信号调频以及滤波处理，将处理后的信号发送到处理器110。无线通信模块160还可以从 处理器110接收待发送的信号，对其进行调频，放大，经天线2转为电磁波辐射出去。
在一些实施例中，电子设备100的天线1和移动通信模块150耦合，天线2和无线通信模块160耦合，使得电子设备100可以通过无线通信技术与网络以及其他设备通信。所述无线通信技术可以包括全球移动通讯系统(global system for mobile communications，GSM)，通用分组无线服务(general packet radio service，GPRS)，码分多址接入(code division multiple access，CDMA)，宽带码分多址(wideband code division multiple access，WCDMA)，时分码分多址(time-division code division multiple access，TD-SCDMA)，长期演进(long term evolution，LTE)，BT，GNSS，WLAN，NFC，FM，和/或IR技术等。所述GNSS可以包括全球卫星定位系统(global positioning system，GPS)，全球导航卫星系统(global navigation satellite system，GLONASS)，北斗卫星导航系统(beidou navigation satellite system，BDS)，准天顶卫星系统(quasi-zenith satellite system，QZSS)和/或星基增强系统(satellite based augmentation systems，SBAS)。
电子设备100通过GPU，显示屏194，以及应用处理器等实现显示功能。GPU为图像处理的微处理器，连接显示屏194和应用处理器。GPU用于执行数学和几何计算，用于图形渲染。处理器110可包括一个或多个GPU，其执行程序指令以生成或改变显示信息。
其中，内部存储器121可以用于存储计算机可执行程序代码，所述可执行程序代码包括指令。处理器110通过运行存储在内部存储器121的指令，从而执行电子设备100的各种功能应用以及数据处理。例如，在本实施例中，处理器110可以通过执行存储在内部存储器121中的指令，实现地址映射功能。内部存储器121可以包括存储程序区和存储数据区。其中，存储程序区可存储操作系统，至少一个功能所需的应用程序(比如声音播放功能，图像播放功能等)等。存储数据区可存储电子设备100使用过程中所创建的数据(比如音频数据，电话本等)等。此外，内部存储器121可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个闪存器件，通用闪存存储器(universal flash storage，UFS)，eMMC等。处理器110通过运行存储在内部存储器121的指令，和/或存储在设置于处理器中的存储器的指令，执行电子设备100的各种功能应用以及数据处理。在本申请中，内部存储器121可以是闪存器件，闪存器件中存储有存储器的映射表。
其中，触摸传感器180K，也称“触控器件”。触摸传感器180K可以设置于显示屏194，由触摸传感器180K与显示屏194组成触摸屏，也称“触控屏”。触摸传感器180K用于检测作用于其上或附近的触摸操作。触摸传感器可以将检测到的触摸操作传递给应用处理器，以确定触摸事件类型。可以通过显示屏194提供与触摸操作相关的视觉输出。在另一些实施例中，触摸传感器180K也可以设置于电子设备100的表面，与显示屏194所处的位置不同。
另外，在上述部件之上，运行有操作系统和文件系统。例如苹果公司所开发的iOS操作系统，谷歌公司所开发的Android开源操作系统，微软公司所开发的Windows操作系统等。在该操作系统上可以安装运行应用程序和文件系统。电子设备100的操作系统可以采用分层架构，事件驱动架构，微核架构，微服务架构，或云架构等。
图2为本申请实施例提供的一种数据处理方法的流程图。这里以电子设备是手机 为例进行说明。手机包括处理器和存储器。如图2所示，该方法可以包括：
S201、存储器接收写请求。
S202、存储器分配物理块号指示的存储空间。
在一些实施例中，存储器的存储容量可以根据块粒度预先划分为多个存储空间，可以采用一个物理块号指示一个存储空间。该多个存储空间包括存储热数据的数据存储空间和存储冷数据的数据存储空间。写请求包括数据和数据属性，该数据属性包括热数据属性和冷数据属性中至少一个。存储器可以根据数据属性分配存储空间，将热数据存储到可存储热数据的存储空间，以及将冷数据存储到可存储冷数据的存储空间。对于相同数据属性的数据可以存储到至少一个存储空间中。写请求还包括文件数据和数据长度等信息。
S203、存储器在物理块号指示的存储空间内的偏移值指示的地址开始写入文件的数据。
在一些实施例中，物理块号指示的存储空间内以页粒度进行划分，在对存储器进行读写时是以页粒度对存储器进行读写。因此，存储器在物理块号指示的存储空间内的偏移值指示的地址开始写入数据。具体的，对存储器写入写请求包括的数据长度的数据。这里的偏移值可以是指物理块号指示的存储空间内的页的起始地址。
需要说明的是，若物理块号指示的存储空间是一个未存储任何数据的空的存储空间，偏移值指示的地址可以是物理块号指示的存储空间的起始地址。若物理块号指示的存储空间已存储有其他数据，偏移值指示的地址可以是物理块号指示的存储空间的起始地址之后的页的起始地址。
S204、存储器根据物理块号和物理块号指示的存储空间内的偏移值生成逻辑地址。
S205、存储器向处理器反馈逻辑地址。
S206、处理器接收逻辑地址。
S207、处理器根据存储器反馈的逻辑地址生成文件与逻辑地址的映射关系。
在一些实施例中，存储器写入文件的数据后，根据写入文件的数据的存储空间的物理块号和该物理块号指示的存储空间内的偏移值生成逻辑地址，向处理器反馈该逻辑地址，逻辑地址用于指示该物理块号对应的逻辑块号和物理块号指示的存储空间内的偏移值。处理器接收到逻辑地址后，根据存储器反馈的逻辑地址生成文件与逻辑地址的映射关系。处理器更新文件系统的映射表，文件系统的映射表包括文件与逻辑地址的映射关系的表项。文件包括文件名称、文件地址、索引号和数据等。
本申请实施例提供的数据处理方法，在存储器确定了物理块号对应的逻辑块号和偏移值之后，向处理器反馈逻辑块号和偏移值，使得文件系统的映射表存储的文件对应的逻辑地址是存储器告知的，通过偏移值将文件系统的映射表和存储器的映射表关联，从而，可以基于映射粒度不同的存储器的映射表和文件系统的映射表进行数据写操作。
进一步的，存储器还需要更新存储器的映射表，如步骤S208的阐述。
S208、存储器生成物理块号和物理块号对应的逻辑块号的映射关系。
存储器可以存储一个存储器的映射表，该存储器的映射表用于记录物理块号和该物理块号对应的逻辑块号的映射关系。“物理块号和该物理块号对应的逻辑块号的映 射关系”也可以描述为物理块号和该物理块号指示的存储空间的起始地址的映射关系。两个存储空间的起始地址之间的存储容量表示一个物理块的大小。
由于该存储器的映射表的表项的映射粒度是块，块对应的存储容量可以达到数百MB大小，这样可以将存储器的映射表的大小缩小到数KB级别，从而实现存储器的映射表常驻存储器的内存，在手机进行数据访问时可以减少访问存储器(如：闪存(Nand Flash))的次数，缩短了读写数据访问延迟。
存储器在确定了物理块号和物理块号对应的逻辑块号后，生成物理块号和物理块号对应的逻辑块号的映射关系。存储器更新存储器的映射表，存储器的映射表包括物理块号和物理块号对应的逻辑块号的映射关系的表项。以便于存储器接收到读请求时，根据该表项读取物理块号指示的存储空间内的数据。
需要说明的是，本申请实施例提供的数据处理方法步骤的先后顺序可以进行适当调整，步骤也可以根据情况进行相应增减。示例的，如S208和S205之间的前后顺序可以互换，即存储器可以先生成物理块号和物理块号对应的逻辑块号的映射关系，以及再向处理器反馈逻辑地址，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化的方法，都应涵盖在本申请的保护范围之内，因此不再赘述。
需要说明的是，在手机向存储器中写入数据时，将数据写入存储器中的具体的位置是存储器确定的。但是，为了符合协议的规定，处理器可以根据文件信息包括的文件名称先分配一个临时的逻辑地址。该临时的逻辑地址可以是文件系统的映射表中任意一个逻辑地址。
示例的，图3为本申请实施例提供一种写操作的地址转换流程图。如图所示，在应用启动后，需要写入数据时，处理器可以获取到存储该应用的文件地址(如：应用逻辑区块地址(Logical Block Address，LBA)-application)。处理器根据文件系统的映射表进行地址转换，即将文件地址转换为逻辑地址。由于在处理器向存储器中写入数据时，将数据写入存储器中的具体的位置是存储器确定的。为了符合协议的规定，此时，处理器分配的逻辑地址为临时的逻辑地址。例如，将LBA-application转换为LBA-blockt+paget，其中，blockt为块粒度的逻辑块号，paget为逻辑块号对应的物理块号指示的存储空间内的偏移地址。需要说明的是，偏移地址可以是存储空间内页粒度的地址信息。
然后，处理器将逻辑地址(如：LBA-blockt+paget)发送给存储器。存储器的控制器根据存储器的映射表重新分配一个存储空间，得到新的物理块号和偏移值，在新的物理块号指示的存储空间中从偏移值指示的地址开始写入数据，并将新的逻辑地址反馈给处理器。例如，将LBA-blockn+pagex反馈给处理器。其中，blockn表示新的逻辑块号，pagex表示新的逻辑块号对应的物理块号指示的存储空间内的偏移值。blockn’为新的物理块号。
存储器生成新的物理块号和新的逻辑块号的映射关系，更新存储器的映射表，存储器的映射表包括新的物理块号和新的逻辑块号的映射关系的表项。
处理器生成新的逻辑地址和文件的映射关系，更新文件系统的映射表，文件系统的映射表包括新的逻辑地址和文件的映射关系的表项。
图4为本申请实施例提供的一种数据处理方法的流程图。这里以电子设备是手机 为例进行说明。手机包括处理器和存储器。如图4所示，该方法可以包括：
S401、处理器获取文件信息。
在应用启动后，需要读取数据时，处理器可以获取到文件信息包括的文件名称、文件地址、文件内的偏移值和数据长度等信息。
S402、处理器根据文件信息查询文件系统的映射表，得到文件对应的逻辑地址。
文件系统的映射表用于存储文件系统管理的文件与存储文件的逻辑地址的对应关系。处理器接收到读请求后，将文件系统的映射表加载到处理器的内存(缓存)中，处理器根据文件系统的映射表得到文件对应的逻辑地址。逻辑地址用于指示物理块号对应的逻辑块号和该物理块号指示的存储空间内的偏移值。该偏移值为物理块号指示的存储空间内的页的起始地址。处理器向存储器发送读请求，将逻辑地址和文件信息传输给存储器。
S403、处理器发送读请求，读请求包括逻辑地址和数据长度。
S404、存储器接收读请求。
S405、存储器根据逻辑地址确定逻辑块号和偏移值。
在一些实施例中，存储器先确定从存储器的起始地址到逻辑地址之间的存储容量，然后，用该存储容量除以物理块的大小，得到商和余数。其中，商表示逻辑块号，余数表示偏移值。若余数为0，偏移值表示该逻辑块号对应的物理块号指示的存储空间内的第一个页的起始地址。物理块的大小为闪存的擦除块的大小的整数倍。
S406、存储器查询存储器的映射表，得到逻辑块号对应的物理块号。
存储器的控制器根据逻辑块号查询存储器的内存中存储器的映射表，得到逻辑块号对应的物理块号。存储器的映射表包括物理块号和物理块号对应的逻辑块号的映射关系的表项。
S407、存储器从物理块号指示的存储空间内依据偏移值指示的地址开始读取数据长度的数据。
本申请实施例提供的数据处理方法，在存储器确定了物理块号对应的逻辑块号和偏移值之后，向处理器反馈逻辑块号和偏移值，使得文件系统的映射表存储的文件对应的逻辑地址是存储器告知的，通过偏移值将文件系统的映射表和存储器的映射表关联，从而，在处理器读取数据时，存储器根据处理器反馈的逻辑地址确定逻辑块号和偏移值，查询存储器的映射表，得到逻辑块号对应的物理块号，以便于存储器从物理块号指示的存储空间内依据偏移值指示的地址开始读取数据长度的数据。
示例的，图5为本申请实施例提供一种读操作的地址转换流程图。如图所示，在应用启动后，需要读数据时，处理器可以获取到存储该应用的文件地址(如：LBA-application)，处理器根据文件系统的映射表将文件地址转换为逻辑地址(如：LBA-blockn+pagex)，其中，其中，blockn为块粒度的逻辑块号，pagex为逻辑块号对应的物理块号指示的存储空间内的偏移地址。需要说明的是，偏移地址可以是存储空间内页粒度的地址信息。
然后，处理器将逻辑地址传输给存储器，存储器解析逻辑地址，得到逻辑块号和偏移值。存储器查询存储器的映射表，得到逻辑块号对应的物理块号(如：blockn’)，映射后的地址为LBA-blockn’+pagex，此地址指向存储数据的实际闪存的地址。存储器 从映射后的物理块号(blockn’)指示的存储空间内依据偏移值(pagex)指示的地址开始读取数据长度的数据。
可以理解的是，为了实现上述实施例中功能，存储器和处理器包括了执行各个功能相应的硬件结构和/或软件模块。本领域技术人员应该很容易意识到，结合本申请中所公开的实施例描述的各示例的单元及方法步骤，本申请能够以硬件或硬件和计算机软件相结合的形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用场景和设计约束条件。
图6和图7为本申请的实施例提供的可能的通信装置的结构示意图。这些通信装置可以用于实现上述方法实施例中存储器或处理器的功能，因此也能实现上述方法实施例所具备的有益效果。在本申请的实施例中，该通信装置可以是如图1所示的电子设备100，也可以是应用于电子设备的模块(如芯片)。
如图6所示，通信装置600包括处理单元601和收发单元602。通信装置600用于实现上述图2或图4中所示的方法实施例中存储器或处理器的功能。
当通信装置600用于实现图2所示的方法实施例中存储器的功能时：收发单元602用于支持通信装置执行S201和S205；处理单元601用于支持通信装置执行S202、S203、S204和S208。
当通信装置600用于实现图2所示的方法实施例中处理器的功能时：收发单元602用于支持通信装置执行S206；处理单元601用于支持通信装置执行S207。
当通信装置600用于实现图4所示的方法实施例中存储器的功能时：收发单元602用于支持通信装置执行S404；处理单元601用于支持通信装置执行S405～S407。
当通信装置600用于实现图4所示的方法实施例中处理器的功能时：收发单元602用于支持通信装置执行S401和S403；处理单元601用于支持通信装置执行S402。
有关上述处理单元601和收发单元602更详细的描述可以直接参考图2或图4所示的方法实施例中相关描述直接得到，这里不加赘述。
需要说明的是，上述方法实施例涉及的各步骤的所有相关内容均可以援引到对应功能模块的功能描述，在此不再赘述。
本申请实施例提供的通信装置，用于执行上述任意实施例的方法，因此可以达到与上述实施例的方法相同的效果。
如图7所示，通信装置700包括处理器701和接口电路702。处理器701和接口电路702之间相互耦合。可以理解的是，接口电路702可以为收发器或输入输出接口。可选的，通信装置700还可以包括存储器703用于存储处理器701执行的指令或存储处理器701运行指令所需要的输入数据或存储处理器701运行指令后产生的数据。
当通信装置700用于实现图2或图4所示的方法时，处理器701用于执行上述处理单元601的功能，接口电路702用于执行上述收发单元602的功能。
可以理解的是，本申请的实施例中的处理器可以是中央处理单元(Central Processing Unit，CPU)，还可以是其它通用处理器、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现场可编程门阵列(Field Programmable Gate Array，FPGA)或者其它可编程逻辑器件、晶体管逻辑器件，硬件部件或者其任意组合。通用处理器可以是微处理器，也可以是 任何常规的处理器。
本申请的实施例中的方法步骤可以通过硬件的方式来实现，也可以由处理器执行软件指令的方式来实现。软件指令可以由相应的软件模块组成，软件模块可以被存放于随机存取存储器(Random Access Memory，RAM)、闪存、只读存储器(Read-Only Memory，ROM)、可编程只读存储器(Programmable ROM，PROM)、可擦除可编程只读存储器(Erasable PROM，EPROM)、电可擦除可编程只读存储器(Electrically EPROM，EEPROM)、寄存器、硬盘、移动硬盘、CD-ROM或者本领域熟知的任何其它形式的存储介质中。一种示例性的存储介质耦合至处理器，从而使处理器能够从该存储介质读取信息，且可向该存储介质写入信息。当然，存储介质也可以是处理器的组成部分。处理器和存储介质可以位于ASIC中。另外，该ASIC可以位于网络设备或终端设备中。当然，处理器和存储介质也可以作为分立组件存在于网络设备或终端设备中。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机程序或指令。在计算机上加载和执行所述计算机程序或指令时，全部或部分地执行本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、网络设备、用户设备或者其它可编程装置。所述计算机程序或指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机程序或指令可以从一个网站站点、计算机、服务器或数据中心通过有线或无线方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是集成一个或多个可用介质的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，例如，软盘、硬盘、磁带；也可以是光介质，例如，数字视频光盘(digital video disc，DVD)；还可以是半导体介质，例如，固态硬盘(solid state drive，SSD)。
在本申请的各个实施例中，如果没有特殊说明以及逻辑冲突，不同的实施例之间的术语和/或描述具有一致性、且可以相互引用，不同的实施例中的技术特征根据其内在的逻辑关系可以组合形成新的实施例。
本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A,B可以是单数或者复数。在本申请的文字描述中，字符“/”，一般表示前后关联对象是一种“或”的关系；在本申请的公式中，字符“/”，表示前后关联对象是一种“相除”的关系。
可以理解的是，在本申请的实施例中涉及的各种数字编号仅为描述方便进行的区分，并不用来限制本申请的实施例的范围。上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定。

Claims (19)

  1. 一种数据处理方法，其特征在于，包括：
    接收写请求，所述写请求包括文件的数据；
    分配物理块号指示的存储空间；
    在所述物理块号指示的存储空间内的偏移值指示的地址开始写入所述文件的数据；
    根据所述物理块号和所述物理块号指示的存储空间内的偏移值生成逻辑地址，所述逻辑地址用于指示所述物理块号对应的逻辑块号和所述物理块号指示的存储空间内的偏移值；
    反馈所述逻辑地址。
  2. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    生成所述物理块号和所述物理块号对应的逻辑块号的映射关系，存储器的映射表包括所述物理块号和所述物理块号对应的逻辑块号的映射关系的表项。
  3. 一种数据处理方法，其特征在于，包括：
    接收逻辑地址，所述逻辑地址用于指示物理块号对应的逻辑块号和所述物理块号指示的存储空间内的偏移值；
    根据所述逻辑地址生成文件与逻辑地址的映射关系，文件系统的映射表包括所述文件与所述逻辑地址的映射关系的表项。
  4. 一种数据处理方法，其特征在于，包括：
    获取文件信息，所述文件信息包括文件名称、文件地址和数据长度；
    根据所述文件信息查询文件系统的映射表，得到文件对应的逻辑地址，所述逻辑地址用于指示物理块号对应的逻辑块号和所述物理块号指示的存储空间内的偏移值；
    发送读请求，所述读请求包括所述逻辑地址和所述数据长度。
  5. 一种数据处理方法，其特征在于，包括：
    接收读请求，所述读请求包括逻辑地址和数据长度，所述逻辑地址用于指示物理块号对应的逻辑块号和所述物理块号指示的存储空间内的偏移值；
    根据所述逻辑地址确定逻辑块号和偏移值；
    查询存储器的映射表，得到所述逻辑块号对应的物理块号；
    从所述物理块号指示的存储空间内依据所述偏移值指示的地址开始读取所述数据长度的数据。
  6. 一种通信装置，其特征在于，包括：
    收发单元用于接收写请求，所述写请求包括文件的数据；
    处理单元用于分配物理块号指示的存储空间；
    所述处理单元还用于在所述物理块号指示的存储空间内的偏移值指示的地址开始写入所述文件的数据；
    所述处理单元还用于根据所述物理块号和所述物理块号指示的存储空间内的偏移值生成逻辑地址，所述逻辑地址用于指示所述物理块号对应的逻辑块号和所述物理块号指示的存储空间内的偏移值；
    所述收发单元还用于向处理器反馈所述逻辑地址。
  7. 根据权利要求6所述的通信装置，其特征在于，
    所述处理单元还用于生成所述物理块号和所述物理块号对应的逻辑块号的映射关系，存储器的映射表包括所述物理块号和所述物理块号对应的逻辑块号的映射关系的表项。
  8. 一种通信装置，其特征在于，包括：
    收发单元用于接收逻辑地址，所述逻辑地址用于指示物理块号对应的逻辑块号和所述物理块号指示的存储空间内的偏移值；
    处理单元用于根据存储器反馈的所述逻辑地址生成文件与逻辑地址的映射关系，文件系统的映射表包括所述文件与所述逻辑地址的映射关系的表项。
  9. 一种通信装置，其特征在于，包括：
    处理单元用于获取文件信息，所述文件信息包括文件名称、文件地址和数据长度；
    所述处理单元还用于根据所述文件信息查询文件系统的映射表，得到文件对应的逻辑地址，所述逻辑地址用于指示物理块号对应的逻辑块号和所述物理块号指示的存储空间内的偏移值；
    收发单元用于向存储器发送读请求，所述读请求包括所述逻辑地址和所述数据长度。
  10. 一种通信装置，其特征在于，包括：
    收发单元用于接收读请求，所述读请求包括逻辑地址和数据长度，所述逻辑地址用于指示物理块号对应的逻辑块号和所述物理块号指示的存储空间内的偏移值；
    处理单元用于根据处理器反馈的所述逻辑地址确定逻辑块号和偏移值；
    所述处理单元还用于查询存储器的映射表，得到所述逻辑块号对应的物理块号；
    所述处理单元还用于从所述物理块号指示的存储空间内依据所述偏移值指示的地址开始读取所述数据长度的数据。
  11. 一种计算机设备，其特征在于，所述计算机设备包括处理器和存储器，其中，
    所述存储器用于接收到写请求后，分配物理块号指示的存储空间，所述写请求包括文件的数据；
    所述存储器还用于在所述物理块号指示的存储空间内的偏移值指示的地址开始写入所述文件的数据；
    所述存储器还用于根据所述物理块号和所述物理块号指示的存储空间内的偏移值生成逻辑地址，所述逻辑地址用于指示所述物理块号对应的逻辑块号和所述物理块号指示的存储空间内的偏移值；
    所述存储器还用于向所述处理器反馈所述逻辑地址；
    所述处理器用于根据所述存储器反馈的逻辑地址生成所述文件与所述逻辑地址的映射关系，文件系统的映射表包括所述文件与所述逻辑地址的映射关系的表项。
  12. 根据权利要求11所述的计算机设备，其特征在于，
    所述存储器还用于生成所述物理块号和所述物理块号对应的逻辑块号的映射关系，所述存储器的映射表包括所述物理块号和所述物理块号对应的逻辑块号的映射关系的表项。
  13. 一种计算机设备，其特征在于，所述计算机设备包括处理器和存储器，其中，
    所述处理器用于获取文件信息，所述文件信息包括文件名称、文件地址和数据长 度；
    所述处理器还用于根据所述文件信息查询文件系统的映射表，得到文件对应的逻辑地址，所述逻辑地址用于指示物理块号对应的逻辑块号和所述物理块号指示的存储空间内的偏移值；
    所述处理器还用于向所述存储器发送读请求，所述读请求包括所述逻辑地址和所述数据长度；
    所述存储器用于根据所述处理器反馈的所述逻辑地址确定逻辑块号和偏移值；
    所述存储器还用于查询存储器的映射表，得到所述逻辑块号对应的物理块号；
    所述存储器还用于从所述物理块号指示的存储空间内依据所述偏移值指示的地址开始读取所述数据长度的数据。
  14. 根据权利要求1至5中任一项所述的方法、或者权利要求6至10中任一项所述的通信装置、或者权利要求11至13中任一项所述的计算机设备，其特征在于，物理块的大小为闪存的擦除块的大小的整数倍。
  15. 根据权利要求1、3至5中任一项所述的方法、或者权利要求6、8至10中任一项所述的通信装置、或者权利要求11或13所述的计算机设备，其特征在于，所述偏移值为所述物理块号指示的存储空间内的页的起始地址。
  16. 一种存储器，其特征在于，用于实现如权利要求1和2中任一项所述的数据处理方法，或者用于实现如权利要求5所述的数据处理方法。
  17. 一种处理器，其特征在于，用于实现如权利要求3所述的数据处理方法，或者用于实现如权利要求4所述的数据处理方法。
  18. 一种计算机可读存储介质，其特征在于，包括：计算机软件指令；
    当所述计算机软件指令在计算机设备或内置在计算机设备的芯片中运行时，使得所述计算机设备执行如权利要求1至3中任一项所述数据处理方法，或者实现如权利要求4至5中任一项所述的数据处理方法。
  19. 一种包含指令的计算机程序产品，其特征在于，当所述计算机程序产品在计算机设备或内置在计算机设备的芯片中运行时，使得所述计算机设备执行如权利要求1至3中任一项所述数据处理方法，或者实现如权利要求4至5中任一项所述的数据处理方法。
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