WO2021036359A1 - 提高系统dram可靠性的方法、装置和存储介质 - Google Patents

提高系统dram可靠性的方法、装置和存储介质 Download PDF

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WO2021036359A1
WO2021036359A1 PCT/CN2020/091023 CN2020091023W WO2021036359A1 WO 2021036359 A1 WO2021036359 A1 WO 2021036359A1 CN 2020091023 W CN2020091023 W CN 2020091023W WO 2021036359 A1 WO2021036359 A1 WO 2021036359A1
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dram
voltage
reliability
value
power supply
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PCT/CN2020/091023
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English (en)
French (fr)
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刘凤鹏
刘冬梅
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中兴通讯股份有限公司
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Priority to EP20859130.5A priority Critical patent/EP3965108A4/en
Priority to US17/610,718 priority patent/US11837274B2/en
Publication of WO2021036359A1 publication Critical patent/WO2021036359A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/021—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50004—Marginal testing, e.g. race, voltage or current testing of threshold voltage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5004—Voltage

Definitions

  • This article relates to the field of electronic devices, and in particular to a method, device and computer-readable storage medium for improving the reliability of system DRAM.
  • DRAM Dynamic Random Access Memory
  • DRAM Dynamic Random Access Memory
  • the main function of dynamic random access memory is to use the amount of internal storage to represent whether a bit is 1 or 0.
  • the DRAM mainly achieves the purpose of ensuring the reliability of the DRAM by providing voltage coupling/decoupling devices in the DRAM device to improve the bias sensing of the sense amplifier.
  • the degree of improvement of this control method is limited, making the DRAM reliability still unstable.
  • the main purpose of this article is to provide a method, device and computer-readable storage medium for improving the reliability of system DRAM, aiming to achieve higher reliability of system DRAM.
  • this article provides a method for improving the reliability of the system DRAM.
  • the method for improving the reliability of the system DRAM includes the following steps: obtaining the performance voltage of the DRAM, and performing reliability verification on the voltage value of the performance voltage; Calculate the voltage deviation value of the power supply voltage under the ideal model of the DRAM according to the verification result of the reliability check; adjust the power supply voltage of the DRAM according to the voltage deviation value.
  • this article also provides a device for improving the reliability of the system DRAM.
  • the device for improving the reliability of the system DRAM includes a memory, a processor, and a memory, a processor, and storage on the memory and on the processor.
  • this article also provides a computer-readable storage medium that stores a program for improving the reliability of the system DRAM when the program for improving the reliability of the system DRAM is executed by the processor. The steps of the method for improving the reliability of the system DRAM are implemented.
  • FIG. 1 is a schematic diagram of the device structure of the hardware operating environment involved in the solution of the embodiments of this document;
  • FIG. 3 is a schematic flowchart of a second embodiment of the method for improving system DRAM reliability in this article
  • FIG. 5 is a schematic flowchart of a fourth embodiment of a method for improving system DRAM reliability in this article
  • FIG. 6 is a schematic flowchart of a fifth embodiment of the method for improving system DRAM reliability in this article
  • FIG. 7 is a schematic flowchart of a sixth embodiment of a method for improving system DRAM reliability in this article
  • FIG. 8 is a schematic diagram of the logic output of the first embodiment of the method for improving the reliability of the system DRAM in this article;
  • FIG. 9 is a schematic diagram of the voltage calculation process of the third embodiment of the method for improving the reliability of the system DRAM in this article.
  • FIG. 10 is a schematic diagram of the capacitance calculation process of the sixth embodiment of the method for improving the reliability of the system DRAM in this paper.
  • FIG. 1 is a schematic diagram of the device structure of the hardware operating environment involved in the solution of the embodiments herein.
  • the terminal in the embodiments herein may be a PC, or a terminal device with a data processing function, such as a smart phone, a tablet computer, or a portable computer.
  • the terminal may include: a processor 1001, such as a CPU, a network interface 1004, a user interface 1003, a memory 1005, and a communication bus 1002.
  • the communication bus 1002 is used to implement connection and communication between these components.
  • the user interface 1003 may include a display screen (Display) and an input unit such as a keyboard (Keyboard).
  • the user interface 1003 may also include a standard wired interface and a wireless interface.
  • the network interface 1004 may include a standard wired interface and a wireless interface (such as a WI-FI interface).
  • the memory 1005 may be a high-speed RAM memory, or a non-volatile memory (non-volatile memory), such as a magnetic disk memory.
  • the memory 1005 may also be a storage device independent of the aforementioned processor 1001.
  • the terminal may also include a camera, an RF (Radio Frequency, radio frequency) circuit, a sensor, an audio circuit, a Wi-Fi module, and so on.
  • sensors such as light sensors, motion sensors and other sensors.
  • the light sensor may include an ambient light sensor and a proximity sensor, where the ambient light sensor can adjust the brightness of the display screen according to the brightness of the ambient light, and the proximity sensor can turn off the display screen when the mobile terminal is moved to the ear And/or backlight.
  • the gravity acceleration sensor can detect the magnitude of acceleration in various directions (usually three-axis), and can detect the magnitude and direction of gravity when it is stationary, and can be used to identify the application of the mobile terminal's posture (such as horizontal and vertical screen switching, Related games, magnetometer posture calibration), vibration recognition related functions (such as pedometer, percussion), etc.; of course, the mobile terminal can also be equipped with other sensors such as gyroscope, barometer, hygrometer, thermometer, infrared sensor, etc. No longer.
  • terminal structure shown in FIG. 1 does not constitute a limitation on the terminal, and may include more or fewer components than shown in the figure, or combine some components, or arrange different components.
  • the memory 1005 which is a computer storage medium, may include an operating system, a network communication module, a user interface module, and programs to improve the reliability of the system DRAM.
  • the network interface 1004 is mainly used to connect to a back-end server and communicate with the back-end server;
  • the user interface 1003 is mainly used to connect to a client (user side) to communicate with the client;
  • the processor 1001 can be used to call a program stored in the memory 1005 to improve the reliability of the system DRAM, and perform the following operations: obtain the performance voltage of the DRAM, and perform a reliability check on the voltage value of the performance voltage; and verify according to the reliability check As a result, the voltage deviation value of the power supply voltage under the ideal model of the DRAM is calculated; the power supply voltage of the DRAM is adjusted according to the voltage deviation value.
  • the processor 1001 may call a program stored in the memory 1005 to improve the reliability of the system DRAM, and further perform the following operations: the step of adjusting the power supply voltage of the DRAM according to the voltage deviation value includes: After adjusting the power supply voltage of the DRAM, re-check the reliability of the voltage value of the performance voltage; if the check result is a failure, return to the step: calculate the DRAM ideal model according to the verification result of the reliability check The voltage deviation value below.
  • the processor 1001 may call a program stored in the memory 1005 to improve the reliability of the system DRAM, and also perform the following operations: the voltage deviation of the supply voltage under the ideal model of the DRAM is calculated according to the verification result of the reliability check
  • the value steps include:
  • a preset voltage increment value is added to the voltage test value of the power supply voltage to obtain a new voltage test value of the power supply voltage.
  • the processor 1001 may call a program stored in the memory 1005 to improve the reliability of the system DRAM, and also perform the following operations: the voltage deviation of the supply voltage under the ideal model of the DRAM is calculated according to the verification result of the reliability check
  • the value step further includes: if the verification result is successful, reducing the voltage test value of the power supply voltage by a preset voltage reduction value to obtain a new voltage test value of the power supply voltage.
  • the processor 1001 may call a program stored in the memory 1005 to improve the reliability of the system DRAM, and also perform the following operations:
  • the method for improving the reliability of the system DRAM further includes: obtaining the power supply capacitance value of the DRAM, adjusting the power supply capacitance value of the DRAM according to a preset rule to obtain the adjusted DRAM capacitance value, until the performance voltage corresponding to the adjusted DRAM capacitance is greater than or equal to Preset threshold voltage.
  • the processor 1001 may call a program stored in the memory 1005 to improve the reliability of the system DRAM, and also perform the following operations: the power supply capacitance value of the DRAM is obtained, and the power supply capacitance value of the DRAM is adjusted according to a preset rule.
  • the step includes: determining whether the power supply voltage value of the DRAM changes according to the voltage deviation value; If the voltage value changes, the capacitance value of the DRAM is reduced by a preset capacitance reduction value, the adjusted capacitance test value is obtained, and the reliability of the adjusted capacitance is verified; if the reliability verification result is all If the performance voltage is less than the preset threshold voltage, then return to the step: reduce the capacitance value of the DRAM by a preset capacitance reduction value, obtain the adjusted capacitance test value, and perform a reliability check on the adjusted capacitance until the adjustment The performance voltage corresponding to the subsequent DRAM capacitor is greater than or equal to the preset threshold voltage.
  • the processor 1001 may call a program stored in the memory 1005 to improve the reliability of the system DRAM, and also perform the following operations: the power supply capacitance value of the DRAM is obtained, and the power supply capacitance value of the DRAM is adjusted according to a preset rule. After the DRAM capacitance value, until the performance voltage corresponding to the adjusted DRAM capacitance is greater than or equal to the preset threshold voltage, the step further includes: if the power supply voltage value of the DRAM does not change, increasing the capacitance value of the DRAM by a preset value.
  • the capacitance value of the DRAM is increased by a preset capacitance increase value, the adjusted capacitance test value is obtained, and the reliability of the adjusted capacitance is checked until the performance voltage corresponding to the adjusted DRAM capacitance is less than the preset threshold voltage .
  • the processor 1001 may call a program stored in the memory 1005 to improve the reliability of the system DRAM, and also perform the following operations: the capacitor is a variable capacitor.
  • FIG. 2 is a schematic flowchart of a first embodiment of a method for improving system DRAM reliability in this article.
  • the method for improving system DRAM reliability includes:
  • Step S100 Obtain the performance voltage of the DRAM, and perform reliability verification on the voltage value of the performance voltage;
  • This implementation method aims at the problem of system load, environmental degradation and other factors after the DRAM package is integrated into the system, which causes the reliability of the DRAM system to deteriorate or even the system crashes.
  • This article proposes a system to ensure the speed and power consumption. DRAM has a higher reliability method.
  • the DRAM chip output is "0".
  • the performance voltage output can be any of V1, V2 or V3.
  • V1 because V1 is lower than the threshold voltage value Vtrip of the DRAM chip, the DRAM chip will have an output error according to the logic, and the output will be "0", which affects the reliability of the output result of the DRAM chip, resulting in low system DRAM reliability.
  • this paper proposes a method to make the system DRAM more reliable, by adjusting the voltage value of the performance voltage to always keep above the threshold voltage value, so that the performance voltage can always be output correctly according to the logic, thereby improving the reliability of the system DRAM Sex.
  • the performance voltage fluctuates on the basis of the power supply voltage, and the power supply voltage is the voltage value provided by the design system power supply
  • this solution is to adjust the power supply voltage so that the performance voltage based on the power supply voltage fluctuation can be stabilized within a reasonable range , So that the performance voltage can be output correctly, and the reliability of the system DRAM is improved.
  • the performance voltage of the DRAM is obtained, and the reliability check is performed on the voltage value of the performance voltage.
  • the reliability check is to perform output logic verification to determine whether the logic output result of the performance voltage is correct.
  • Step S200 Calculate the voltage deviation value of the power supply voltage under the DRAM ideal model according to the verification result of the reliability check; after the reliability check, calculate the voltage of the power supply voltage under the DRAM ideal model according to the verification result of the reliability check Deviation. That is, according to the verification result of the reliability check, the voltage deviation value of the power supply voltage under the ideal model of the DRAM is calculated.
  • the DRAM ideal model is the optimal performance voltage for the logic output of the system DRAM, such as V2.
  • the voltage deviation value is the difference between the power supply voltage corresponding to the optimal performance voltage of the DRAM ideal model and the real-time power supply voltage.
  • the performance voltage under the ideal DRAM model is V2
  • the reliability check cannot be passed at this time, and the power supply voltage corresponding to the performance voltage V1 and the DRAM ideal model can be obtained through calculation.
  • the difference between the supply voltages corresponding to the expression voltage V2 is used as the voltage deviation value.
  • the performance voltage is V3 in this embodiment, the reliability verification has been passed, but DRAM is also ideal
  • the model calculates the ideal power supply voltage value when the performance voltage is V3, and calculates the difference between the actual voltage when the performance voltage is V3 and the ideal power supply voltage value when the performance voltage is V3, as the voltage deviation value,
  • V3 may not be processed or adjusted in any way.
  • step S300 the power supply voltage of the DRAM is adjusted according to the voltage deviation value.
  • the power supply voltage of the DRAM is adjusted according to the voltage deviation value, so that the adjusted performance voltage stable output is in an ideal state such as V2.
  • the power supply voltage is adjusted to the state under the ideal DRAM model, that is, the performance voltage is adjusted to the logical output optimal voltage, so that the performance voltage is in the optimal output state, and the reliability of the system DRAM is improved.
  • This article provides a method, device and computer storage medium for improving system DRAM reliability.
  • the performance voltage of the DRAM is obtained, and the reliability check is performed on the voltage value of the performance voltage; the voltage deviation value of the power supply voltage under the ideal model of the DRAM is calculated according to the verification result of the reliability check; The deviation value adjusts the power supply voltage of the DRAM.
  • this article can perform reliability verification on the performance voltage, and according to the results of the reliability verification, obtain the voltage deviation value of the power supply voltage corresponding to the performance voltage and the performance voltage under the ideal model, so as to adjust the power supply according to the voltage deviation value.
  • the voltage makes the performance voltage based on the power supply voltage in the optimal logical output state, so that the performance voltage can be logically output, thereby improving the reliability of the system DRAM.
  • FIG. 3 is a schematic flowchart of a second embodiment of a method for improving system DRAM reliability in this article.
  • step S300 after step S300, it includes: step S310, after adjusting the power supply voltage of the DRAM, re-check the reliability of the voltage value of the performance voltage; if the check result is If it fails, return to step S200: Calculate the voltage deviation value under the ideal model of the DRAM according to the verification result of the reliability check.
  • the reliability check is performed on the voltage value of the performance voltage again, and the adjusted result is checked. If the check result is a failure, then return to step : Calculate the voltage deviation value under the ideal model of DRAM according to the verification result of the reliability check. Recalculate the voltage deviation between the power supply voltage corresponding to the performance voltage V1 and the power supply voltage corresponding to the DRAM ideal model performance voltage V2.
  • FIG. 4 is a schematic flowchart of a third embodiment of a method for improving system DRAM reliability in this article.
  • step S200 after step S200, it includes: if the verification result is a failure, perform step S210: add a preset voltage increment value to the voltage test value of the supply voltage to obtain a new The voltage test value of the supply voltage.
  • the voltage test value of the power supply voltage is increased by a preset voltage increase.
  • the voltage test value of the new power supply voltage is obtained, and the voltage test value can be used for further reliability verification.
  • the method further includes: if the verification result is successful, step S220 is performed: reducing the voltage test value of the power supply voltage by a preset voltage reduction value to obtain a new voltage test value of the power supply voltage.
  • the voltage test value of the power supply voltage is reduced by a preset voltage reduction value to obtain a new The voltage test value of the power supply voltage, which can be used for further reliability verification.
  • step ⁇ V adjust the power supply voltage to increase by a step ⁇ V, and verify again. If the verification is successful, determine the current power supply voltage and end. If the verification fails, repeat this step.
  • FIG. 5 is a schematic flowchart of a fourth embodiment of a method for improving system DRAM reliability in this article.
  • Step S400 Obtain the power supply capacitance value of the DRAM, and adjust the power supply capacitance value of the DRAM according to a preset rule to obtain the adjusted DRAM capacitance value until the adjusted DRAM capacitance corresponds to The performance voltage is greater than or equal to the preset threshold voltage.
  • the power supply capacitance value of the DRAM is adjusted to increase the response rate of the DRAM, thereby improving the reliability of the DRAM.
  • Proportion is the most important part of the time delay is the response time of the external power supply, that is, the transient response performance of the voltage supply power device.
  • the power supply capacitance value of the DRAM is obtained, and the power supply capacitance value of the DRAM is adjusted according to a preset rule to obtain the adjusted DRAM capacitance value until the performance voltage corresponding to the adjusted DRAM capacitance is greater than or equal to the preset threshold voltage.
  • the capacitor is a variable capacitor. Substituting variable capacitors for the decoupling capacitors and filter capacitors of the existing solution power supply can adjust the capacitance value of the capacitor while ensuring the decoupling and filter processing, so that the capacitor can ensure a good response rate.
  • the capacitance value of the DRAM is obtained, and the capacitance value of the DRAM is adjusted so that the performance voltage corresponding to the adjusted DRAM capacitance is greater than or equal to the preset threshold voltage, which can ensure the response speed of the voltage adjustment of the DRAM. Keep in a certain range of response rate, so as to ensure the transient response performance of the Vdevice power supply device.
  • FIG. 6 is a schematic flowchart of a fifth embodiment of a method for improving system DRAM reliability in this article.
  • step S400 includes: step S410, determining whether the power supply voltage value of the DRAM has changed according to the voltage deviation value; in this embodiment, adjusting the power supply capacitance value of the DRAM according to a preset rule To obtain the adjusted DRAM capacitance value, it is necessary to first determine whether the power supply voltage value of the DRAM changes according to the voltage deviation value.
  • step S420 reduce the capacitance value of the DRAM by a preset capacitance reduction value, obtain an adjusted capacitance test value, and perform a reliability check on the adjusted capacitance; If the power supply voltage value of the DRAM changes, the step is performed to reduce the capacitance value of the DRAM by a preset capacitance reduction value, obtain the adjusted capacitance test value, and perform a reliability check on the adjusted capacitance.
  • step S420 reduce the capacitance value of the DRAM by a preset capacitance reduction value, obtain the adjusted capacitance test value, and perform adjustment The reliability of the subsequent capacitor is checked until the performance voltage corresponding to the adjusted DRAM capacitor is greater than or equal to the preset threshold voltage.
  • the result of the reliability check is that the performance voltage is less than the preset threshold voltage, continue to reduce the capacitance value of the DRAM by a preset capacitance reduction value, obtain the adjusted capacitance test value, and perform the adjusted capacitance Reliability verification until the performance voltage corresponding to the adjusted DRAM capacitor is greater than or equal to the preset threshold voltage.
  • FIG. 7 is a schematic flowchart of a sixth embodiment of a method for improving system DRAM reliability in this article.
  • step S400 includes: if the power supply voltage value of the DRAM does not change, perform step S430: increase the capacitance value of the DRAM by a preset capacitance increase value to obtain an adjusted capacitance Test the value, and verify the reliability of the adjusted capacitor; in this embodiment, if the power supply voltage value of the DRAM does not change, perform the step of increasing the capacitance value of the DRAM by a preset capacitance increase value to obtain the adjustment After the capacitance test value, and verify the reliability of the adjusted capacitance.
  • step S430 increase the capacitance value of the DRAM by a preset capacitance increase value to obtain an adjusted capacitance test value, and The reliability of the adjusted capacitor is checked until the performance voltage corresponding to the adjusted DRAM capacitor is less than the preset threshold voltage.
  • the result of the reliability check is that the performance voltage is greater than or equal to the preset threshold voltage, continue to add a preset capacitance increase value to the capacitance value of the DRAM, obtain the adjusted capacitance test value, and perform the adjustment on the adjusted capacitance Reliability verification until the performance voltage corresponding to the adjusted DRAM capacitor is less than the preset threshold voltage.
  • variable capacitor is adjusted one step down based on the default capacitance value Cdefault, and the verification is performed. If the verification fails, repeat this process; if the verification succeeds, determine the current capacitance value Cdevice, and end.
  • variable capacitor is adjusted one step higher on the basis of the default capacitance value Cdefault, and the verification is performed. If the verification fails, the previous capacitance value Cdevice is restored, and the end; if the verification is successful, repeat the process .
  • a reasonable capacitance value ensures the response rate, while taking into account the filtering and decoupling functions.
  • the adjustment may not be made according to the change of the power supply voltage, for example, the capacitance value may be adjusted directly according to the current reliability check result.
  • embodiments herein also provide a computer-readable storage medium.
  • the computer-readable storage medium herein stores a program for improving the reliability of the system DRAM.
  • the program for improving the reliability of the system DRAM is executed by a processor, the steps of the method for improving the reliability of the system DRAM are implemented.
  • the method implemented when the program running on the processor to improve the reliability of the system DRAM is executed can refer to the various embodiments of the method for improving the reliability of the system DRAM in this document, which will not be repeated here.
  • This article provides a method, device and computer storage medium for improving system DRAM reliability.
  • the performance voltage of the DRAM is obtained, and the reliability check is performed on the voltage value of the performance voltage; the voltage deviation value of the power supply voltage under the ideal model of the DRAM is calculated according to the verification result of the reliability check; The deviation value adjusts the power supply voltage of the DRAM.
  • this article can perform reliability verification on the performance voltage, and according to the results of the reliability verification, obtain the voltage deviation value of the power supply voltage corresponding to the performance voltage and the performance voltage under the ideal model, so as to adjust the power supply according to the voltage deviation value.
  • the voltage makes the performance voltage based on the power supply voltage in the optimal logical output state, so that the performance voltage can be logically output, thereby improving the reliability of the system DRAM.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

一种提高系统DRAM可靠性的方法，装置及计算机可读存储介质。其中，该方法包括：获得DRAM的表现电压，对所述表现电压的电压值进行可靠性校验（S100）；根据可靠性校验的验证结果计算DRAM理想模型下的供电电压的电压偏差值（S200）；根据所述电压偏差值对所述DRAM的供电电压进行调整（S300）。

Description

提高系统DRAM可靠性的方法、装置和存储介质
本文要求享有2019年08月30日提交的名称为“提高系统DRAM可靠性的方法、装置和存储介质”的中国专利申请CN201910826187.3的优先权，其全部内容通过引用并入本文中。
技术领域
本文涉及电子器件领域，尤其涉及一种提高系统DRAM可靠性的方法、装置和计算机可读存储介质。
背景技术
DRAM(Dynamic Random Access Memory)，即动态随机存取存储器，是一种常见的系统内存。动态随机存取存储器(Dynamic Random Access Memory，DRAM)主要的作用原理是利用内存储的多寡来代表一个(bit)是1还是0。现阶段，随着互联网和智能设备的普及，用户对DRAM的速率、功耗和可靠性提出了更高的要求。
然而，现阶段，DRAM主要是通过在DRAM器件内设置电压耦合/去耦合器件，以改善感测放大器的偏置感测来达到保证DRAM可靠性的目的。然而，这种控制方式改善程度有限，使得DRAM可靠性还是存在不稳定的情况。
发明内容
本文的主要目的在于提供一种提高系统DRAM可靠性的方法、装置和计算机可读存储介质，旨在实现使系统DRAM具有更高的可靠性。
为实现上述目的，本文提供一种提高系统DRAM可靠性的方法，所述提高系统DRAM可靠性的方法包括以下步骤：获得DRAM的表现电压，对所述表现电压的电压值进行可靠性校验；根据可靠性校验的验证结果计算DRAM理想模型下的供电电压的电压偏差值；根据所述电压偏差值对所述DRAM的供电电压进行调整。
此外，为实现上述目的，本文还提供一种提高系统DRAM可靠性的装置，所述提高 系统DRAM可靠性的装置包括：存储器、处理器及存储在所述存储器上并可在所述处理器上运行的提高系统DRAM可靠性的程序，所述提高系统DRAM可靠性的程序被所述处理器执行时实现如上所述的提高系统DRAM可靠性的方法的步骤。
此外，为实现上述目的，本文还提供一种计算机可读存储介质，所述计算机可读存储介质上存储有提高系统DRAM可靠性的程序，所述提高系统DRAM可靠性的程序被处理器执行时实现上述的提高系统DRAM可靠性的方法的步骤。
附图说明
图1是本文实施例方案涉及的硬件运行环境的装置结构示意图；
图2为本文提高系统DRAM可靠性的方法第一实施例的流程示意图；
图3为本文提高系统DRAM可靠性的方法第二实施例的流程示意图；
图4为本文提高系统DRAM可靠性的方法第三实施例的流程示意图；
图5为本文提高系统DRAM可靠性的方法第四实施例的流程示意图；
图6为本文提高系统DRAM可靠性的方法第五实施例的流程示意图；
图7为本文提高系统DRAM可靠性的方法第六实施例的流程示意图；
图8为本文提高系统DRAM可靠性的方法第一实施例逻辑输出示意图；
图9为本文提高系统DRAM可靠性的方法第三实施例的电压计算过程示意图；
图10为本文提高系统DRAM可靠性的方法第六实施例的电容计算过程示意图。
本文目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
应当理解，此处所描述的具体实施例仅仅用以解释本文，并不用于限定本文。
如图1所示，图1是本文实施例方案涉及的硬件运行环境的装置结构示意图。
本文实施例终端可以是PC，也可以是智能手机、平板电脑、便携计算机等具有数据处理功能的终端设备。
如图1所示，该终端可以包括：处理器1001，例如CPU，网络接口1004，用户接口1003，存储器1005，通信总线1002。其中，通信总线1002用于实现这些组件之间的连接通信。用户接口1003可以包括显示屏(Display)、输入单元比如键盘(Keyboard)，在 一实施方式中用户接口1003还可以包括标准的有线接口、无线接口。在一实施方式中网络接口1004可以包括标准的有线接口、无线接口(如WI-FI接口)。存储器1005可以是高速RAM存储器，也可以是稳定的存储器(non-volatile memory)，例如磁盘存储器。在一实施方式中存储器1005还可以是独立于前述处理器1001的存储装置。
在一实施方式中，终端还可以包括摄像头、RF(Radio Frequency，射频)电路，传感器、音频电路、Wi-Fi模块等等。其中，传感器比如光传感器、运动传感器以及其他传感器。在一实施方式中，光传感器可包括环境光传感器及接近传感器，其中，环境光传感器可根据环境光线的明暗来调节显示屏的亮度，接近传感器可在移动终端移动到耳边时，关闭显示屏和/或背光。作为运动传感器的一种，重力加速度传感器可检测各个方向上(一般为三轴)加速度的大小，静止时可检测出重力的大小及方向，可用于识别移动终端姿态的应用(比如横竖屏切换、相关游戏、磁力计姿态校准)、振动识别相关功能(比如计步器、敲击)等；当然，移动终端还可配置陀螺仪、气压计、湿度计、温度计、红外线传感器等其他传感器，在此不再赘述。
本领域技术人员可以理解，图1中示出的终端结构并不构成对终端的限定，可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置。
如图1所示，作为一种计算机存储介质的存储器1005中可以包括操作系统、网络通信模块、用户接口模块以及提高系统DRAM可靠性的程序。
在图1所示的终端中，网络接口1004主要用于连接后台服务器，与后台服务器进行数据通信；用户接口1003主要用于连接客户端(用户端)，与客户端进行数据通信；而处理器1001可以用于调用存储器1005中存储的提高系统DRAM可靠性的程序，并执行以下操作：获得DRAM的表现电压，对所述表现电压的电压值进行可靠性校验；根据可靠性校验的验证结果计算DRAM理想模型下的供电电压的电压偏差值；根据所述电压偏差值对所述DRAM的供电电压进行调整。
在一实施方式中，处理器1001可以调用存储器1005中存储的提高系统DRAM可靠性的程序，还执行以下操作：所述根据所述电压偏差值对所述DRAM的供电电压进行调整的步骤包括：在对所述DRAM的供电电压进行调整后，重新对所述表现电压的电压值进行可靠性校验；若校验结果是失败，则返回步骤：根据可靠性校验的验证结果计算DRAM理想模型下的电压偏差值。
在一实施方式中，处理器1001可以调用存储器1005中存储的提高系统DRAM可靠性的程序，还执行以下操作：所述根据可靠性校验的验证结果计算DRAM理想模型下的 供电电压的电压偏差值的步骤包括：
若所述校验结果是失败，则对所述供电电压的电压测试值增加一个预设电压增量值，获得新的供电电压的电压测试值。
在一实施方式中，处理器1001可以调用存储器1005中存储的提高系统DRAM可靠性的程序，还执行以下操作：所述根据可靠性校验的验证结果计算DRAM理想模型下的供电电压的电压偏差值的步骤还包括：若所述校验结果是成功，则对所述供电电压的电压测试值减少一个预设电压减少值，获得新的供电电压的电压测试值。
在一实施方式中，处理器1001可以调用存储器1005中存储的提高系统DRAM可靠性的程序，还执行以下操作：
所述提高系统DRAM可靠性的方法还包括：获得DRAM的供电电容值，按照预设规则调整DRAM的供电电容值获得调整后的DRAM电容值，直到调整后的DRAM电容对应的表现电压大于或等于预设门限电压。
在一实施方式中，处理器1001可以调用存储器1005中存储的提高系统DRAM可靠性的程序，还执行以下操作：所述获得DRAM的供电电容值，按照预设规则调整DRAM的供电电容值获得调整后的DRAM电容值，直到调整后的DRAM电容对应的表现电压大于或等于预设门限电压的步骤包括：根据所述电压偏差值确定所述DRAM的供电电压值是否变化；若所述DRAM的供电电压值变化，则将所述DRAM的电容值减少一个预设电容减少值，获得调整后的电容测试值，并对调整后的电容进行可靠性校验；若所述可靠性校验结果为所述表现电压小于预设门限电压，则返回步骤：将所述DRAM的电容值减少一个预设电容减少值，获得调整后的电容测试值，并对调整后的电容进行可靠性校验，直到调整后的DRAM电容对应的表现电压大于或等于预设门限电压。
在一实施方式中，处理器1001可以调用存储器1005中存储的提高系统DRAM可靠性的程序，还执行以下操作：所述获得DRAM的供电电容值，按照预设规则调整DRAM的供电电容值获得调整后的DRAM电容值，直到调整后的DRAM电容对应的表现电压大于或等于预设门限电压的步骤还包括：若所述DRAM的供电电压值不变化，则将所述DRAM的电容值增加一个预设电容增加值，获得调整后的电容测试值，并对调整后的电容进行可靠性校验；若所述可靠性校验结果为所述表现电压大于或等于预设门限电压，则返回步骤：将所述DRAM的电容值增加一个预设电容增加值，获得调整后的电容测试值，并对调整后的电容进行可靠性校验，直到调整后的DRAM电容对应的表现电压小于预设门限电压。
在一实施方式中，处理器1001可以调用存储器1005中存储的提高系统DRAM可靠性的程序，还执行以下操作：所述电容为可变电容。
本文提高系统DRAM可靠性的设备的具体实施例与下述提高系统DRAM可靠性的方法各实施例基本相同，在此不作赘述。
参照图2，图2为本文提高系统DRAM可靠性的方法第一实施例的流程示意图，所述提高系统DRAM可靠性的方法包括：
步骤S100，获得DRAM的表现电压，对所述表现电压的电压值进行可靠性校验；
本实施方法为针对DRAM封装片集成到系统之后，系统负载、环境恶化等因素，造成DRAM系统可靠性恶化甚至系统崩溃的问题，本文在保证速率、保证功耗的前提下，提出一种使系统DRAM具有更高可靠性的方法。
为方便理解首先介绍下DRAM芯片的输出逻辑，请参见图8，当表现电压为0V时，DRAM芯片输出为“0”，当在供电电压稳定时，表现电压输出可以为V1，V2或V3任一一个电压值时，此时表现电压的电压值不为0时，DRAM芯片理论上应该输出为“1”，但受环境、工艺制程、老化程度众多因素影响可能会导致表现电压的电压值为V1时，V1因为低于DRAM芯片的门限电压值Vtrip，使得DRAM芯片按照逻辑会发生输出错误，输出为“0”，从而影响DRAM芯片输出结果的可靠性，造成系统DRAM可靠性低。因此，本文提出一种使系统DRAM具有更高可靠性的方法，通过调整使得表现电压的电压值一直保持门限电压值以上，从而使得表现电压按照逻辑能够保持一直输出正确，从而提高系统DRAM的可靠性。因为表现电压会在供电电压的基础上进行波动，且供电电压为设计系统电源提供的电压值，因此本方案为对供电电压进行调整，使得依据供电电压浮动的表现电压能够稳定在合理的范围内，从而使得表现电压能够输出正确，提高系统DRAM的可靠性。在本实施例中，获得DRAM的表现电压，对所述表现电压的电压值进行可靠性校验，可靠性校验即进行输出逻辑验证，以判断表现电压的逻辑输出结果是否正确。
步骤S200，根据可靠性校验的验证结果计算DRAM理想模型下的供电电压的电压偏差值；在进行可靠性校验后，根据可靠性校验的验证结果计算DRAM理想模型下的供电电压的电压偏差值。即根据可靠性校验的验证结果，计算DRAM理想模型下的供电电压的电压偏差值。DRAM理想模型为系统DRAM进行逻辑输出的最优的表现电压，如V2。电压偏差值为DRAM理想模型最优表现电压对应的供电电压与实时供电电压的差值。例如，如果DRAM理想模型下的表现电压为V2，当实际测得的表现电压为V1时，此时无 法通过可靠性校验，则通过计算，获得表现电压为V1对应的供电电压与DRAM理想模型表现电压V2对应的供电电压之间的差值，作为电压偏差值。
当实际测得的表现电压为V3时，由于V3过高会增加功耗，易发生振铃降低可靠性，因此本实施例中虽然表现电压为V3，已经通过可靠性验证，但也利用DRAM理想模型计算表现电压为V3时对应的理想供电电压值，并将表现电压为V3的实际电压与表现电压为V3时对应的理想供电电压值计算差值，作为电压偏差值，
当然在具体实施例中，因为V3通过了可靠性校验，也可以不对V3做任何处理和调整。
步骤S300，根据所述电压偏差值对所述DRAM的供电电压进行调整。
在获得DRAM理想模型下的供电电压的电压偏差值后，根据根据所述电压偏差值对所述DRAM的供电电压进行调整，以使得调整后的表现电压稳定输出为如V2的理想状态下。根据电压偏差值将供电电压调整到DRAM理想模型下的状态，即调整表现电压为逻辑输出最优电压，从而使得表现电压处于最优的输出状态，提高系统DRAM的可靠性。
本文提供一种提高系统DRAM可靠性的方法、装置和计算机存储介质。在该方法中，获得DRAM的表现电压，对所述表现电压的电压值进行可靠性校验；根据可靠性校验的验证结果计算DRAM理想模型下的供电电压的电压偏差值；根据所述电压偏差值对所述DRAM的供电电压进行调整。通过上述方式，本文能够对表现电压进行可靠性校验，并根据可靠性校验的结果，获得表现电压与理想模型下表现电压分别对应的供电电压的电压偏差值，从而根据电压偏差值调整供电电压，使得基于供电电压的表现电压处于最优的逻辑输出状态，使得表现电压能够被逻辑很好的输出，从而提高系统DRAM的可靠性。
请参阅图3，图3为本文提高系统DRAM可靠性的方法第二实施例的流程示意图。
基于上述实施例，本实施例中，步骤S300之后包括：步骤S310，在对所述DRAM的供电电压进行调整后，重新对所述表现电压的电压值进行可靠性校验；若校验结果是失败，则返回步骤S200：根据可靠性校验的验证结果计算DRAM理想模型下的电压偏差值。
在本实施例中，在对所述DRAM的供电电压进行调整后，重新对所述表现电压的电压值进行可靠性校验，校验调整后的结果，若校验结果为失败，则返回步骤：据可靠性校验的验证结果计算DRAM理想模型下的电压偏差值。重新计算表现电压为V1对应的 供电电压与DRAM理想模型表现电压V2对应的供电电压之间的电压偏差值。
请参阅图4，图4为本文提高系统DRAM可靠性的方法第三实施例的流程示意图。
基于上述实施例，本实施例中，步骤S200之后包括：若所述校验结果是失败，则执行步骤S210：对所述供电电压的电压测试值增加一个预设电压增量值，获得新的供电电压的电压测试值。
在本实施例中，根据可靠性校验的验证结果计算DRAM理想模型下的供电电压的电压偏差值的步骤中，若效果结果为失败，则对供电电压的电压测试值增加一个预设电压增量值，获得新的供电电压的电压测试值，该电压测试值可用于进一步进行可靠性校验。
在一实施方式中还包括：若所述校验结果是成功，则执行步骤S220：对所述供电电压的电压测试值减少一个预设电压减少值，获得新的供电电压的电压测试值。
根据可靠性校验的验证结果计算DRAM理想模型下的供电电压的电压偏差值的步骤中，若效果结果为成功，则对所述供电电压的电压测试值减少一个预设电压减少值，获得新的供电电压的电压测试值，该电压测试值可用于进一步进行可靠性校验。
在一实施方式中，参见图9，根据上述实施例的描述，作为一实施例，本文中整个电压计算过程可以如图9所示：首先，先用自学习算法计算并设计Vdevice曲线，在默认供电电压Vdevice-default下校验是否成功，如果校验失败，定义为欠压；如果校验成功，定义为过压。
其次，如果为欠压状态，例如V1状态，调整供电电压增加一个步进△V，再次校验，如果校验成功，确定当前供电电压，结束。如果校验失败，重复此步骤。
其次，如果为过压状态，例如V2或V3状态，调整供电电压减少一个步进△V，再次校验，如果校验失败，恢复上一个供电电压不做减少步进，结束；如果校验成功，重复此步骤。
最后，动态调整供电电压，保证表现电压刚好满足触发门限，保证逻辑1的稳定。
请参阅图5，图5为本文提高系统DRAM可靠性的方法第四实施例的流程示意图。
基于上述实施例，本实施例中还包括如下步骤：步骤S400，获得DRAM的供电电容值，按照预设规则调整DRAM的供电电容值获得调整后的DRAM电容值，直到调整后的DRAM电容对应的表现电压大于或等于预设门限电压。
DRAM芯片中设有电容，电容值越大，斜率越缓慢，那么，DRAM的电压调整的响 应时间越长，且供电电压是由算法实时计算出来的，存在时间延迟，因此为了进一步提高DRAM系统的可靠性，本实施例中通过调整DRAM的供电电容值以提高DRAM的响应速率，从而提高DRAM的可靠性。占比是时间延时最主要的部分是外部电源供应的响应时间，即表现电压供应电源器件的瞬态响应性能。在本实施例中，获得DRAM的供电电容值，按照预设规则调整DRAM的供电电容值获得调整后的DRAM电容值，直到调整后的DRAM电容对应的表现电压大于或等于预设门限电压。本实施例中，所述电容为可变电容。用可变电容替代现有方案电源的去耦电容和滤波电容，能在保证去耦和滤波处理的同时，可以调整电容的电容值，使得电容能保证很好的响应速率。
在本实施例中，获得DRAM的电容值，对DRAM的电容值进行调整，使得整后的DRAM电容对应的表现电压大于或等于预设门限电压，能很好的保证DRAM的电压调整的响应速度保持在一定的响应速率范围内，从而保证Vdevice供应电源器件的瞬态响应性能。
请参阅图6，图6为本文提高系统DRAM可靠性的方法第五实施例的流程示意图。
基于上述实施例，本实施例中，步骤S400包括：步骤S410，根据所述电压偏差值确定所述DRAM的供电电压值是否变化；在本实施例中，按照预设规则调整DRAM的供电电容值获得调整后的DRAM电容值，需先根据所述电压偏差值确定所述DRAM的供电电压值是否变化。
若所述DRAM的供电电压值变化，则执行步骤S420：将所述DRAM的电容值减少一个预设电容减少值，获得调整后的电容测试值，并对调整后的电容进行可靠性校验；若DRAM的供电电压值变化，则执行步骤对所述DRAM的电容值减少一个预设电容减少值，获得调整后的电容测试值，并对调整后的电容进行可靠性校验。
若所述可靠性校验结果为所述表现电压小于预设门限电压，则返回步骤S420：将所述DRAM的电容值减少一个预设电容减少值，获得调整后的电容测试值，并对调整后的电容进行可靠性校验，直到调整后的DRAM电容对应的表现电压大于或等于预设门限电压。
若可靠性校验的结果为所述表现电压小于预设门限电压，则继续对所述DRAM的电容值减少一个预设电容减少值，获得调整后的电容测试值，并对调整后的电容进行可靠性校验，直到调整后的DRAM电容对应的表现电压大于或等于预设门限电压。
请参阅图7，图7为本文提高系统DRAM可靠性的方法第六实施例的流程示意图。
基于上述实施例，本实施例中，步骤S400包括：若所述DRAM的供电电压值不变 化，则执行步骤S430：将所述DRAM的电容值增加一个预设电容增加值，获得调整后的电容测试值，并对调整后的电容进行可靠性校验；在本实施例中，若DRAM的供电电压值不变化，则执行步骤将所述DRAM的电容值增加一个预设电容增加值，获得调整后的电容测试值，并对调整后的电容进行可靠性校验。
若所述可靠性校验结果为所述表现电压大于或等于预设门限电压，则返回步骤S430：将所述DRAM的电容值增加一个预设电容增加值，获得调整后的电容测试值，并对调整后的电容进行可靠性校验，直到调整后的DRAM电容对应的表现电压小于预设门限电压。
若可靠性校验的结果为表现电压大于或等于预设门限电压，则继续对所述DRAM的电容值增加一个预设电容增加值，获得调整后的电容测试值，并对调整后的电容进行可靠性校验，直到调整后的DRAM电容对应的表现电压小于预设门限电压。
在一实施方式中，参见图10，根据上述实施例的描述，作为一实施例，本文中整个电容计算过程可以如图10所示：
首先，如果供电电压变化，可变电容在默认电容值Cdefault基础上，调小一个步进，校验，如果校验失败，重复此过程；如果校验成功，确定当前电容值Cdevice，结束。
其次，如果供电电压不变，可变电容在默认电容值Cdefault基础上，调高一个步进，校验，如果校验失败，恢复上一个电容值Cdevice，结束；如果校验成功，重复此过程。
最后，合理的电容值保证响应速率，同时兼顾滤波和去耦功能。具体实施例中也可以不根据供电电压变化进行调整，比如将电容值直接根据当前的可靠性校验的效果结果进行调整。
此外，本文实施例还提出一种计算机可读存储介质。
本文计算机可读存储介质上存储有提高系统DRAM可靠性的程序，所述提高系统DRAM可靠性的程序被处理器执行时实现如上所述的提高系统DRAM可靠性的方法的步骤。
其中，在所述处理器上运行的提高系统DRAM可靠性的程序被执行时所实现的方法可参照本文提高系统DRAM可靠性的方法各个实施例，此处不再赘述。
本文提供一种提高系统DRAM可靠性的方法、装置和计算机存储介质。在该方法中，获得DRAM的表现电压，对所述表现电压的电压值进行可靠性校验；根据可靠性校验的验证结果计算DRAM理想模型下的供电电压的电压偏差值；根据所述电压偏差值对所述 DRAM的供电电压进行调整。通过上述方式，本文能够对表现电压进行可靠性校验，并根据可靠性校验的结果，获得表现电压与理想模型下表现电压分别对应的供电电压的电压偏差值，从而根据电压偏差值调整供电电压，使得基于供电电压的表现电压处于最优的逻辑输出状态，使得表现电压能够被逻辑很好的输出，从而提高系统DRAM的可靠性。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者系统不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者系统所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者系统中还存在另外的相同要素。
上述本文实施例序号仅仅为了描述，不代表实施例的优劣。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述实施例方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本文的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在如上所述的一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端设备(可以是手机，计算机，服务器，空调器，或者网络设备等)执行本文各个实施例所述的方法。
以上仅为本文的优选实施例，并非因此限制本文的专利范围，凡是利用本文说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本文的专利保护范围内。

Claims (10)

  1. 一种提高系统DRAM可靠性的方法，其中，所述提高系统DRAM可靠性的方法包括以下步骤：
    获得DRAM的表现电压，对所述表现电压的电压值进行可靠性校验；
    根据可靠性校验的验证结果计算DRAM理想模型下的供电电压的电压偏差值；
    根据所述电压偏差值对所述DRAM的供电电压进行调整。
  2. 如权利要求1所述的提高系统DRAM可靠性的方法，其中，所述根据所述电压偏差值对所述DRAM的供电电压进行调整的步骤之后包括：
    在对所述DRAM的供电电压进行调整后，重新对所述表现电压的电压值进行可靠性校验；
    若校验结果是失败，则返回步骤：根据可靠性校验的验证结果计算DRAM理想模型下的电压偏差值。
  3. 如权利要求1或2所述的提高系统DRAM可靠性的方法，其中，所述根据可靠性校验的验证结果计算DRAM理想模型下的供电电压的电压偏差值的步骤包括：
    若所述校验结果是失败，则对所述供电电压的电压测试值增加一个预设电压增量值，获得新的供电电压的电压测试值。
  4. 如权利要求1或2所述的提高系统DRAM可靠性的方法，其中，所述根据可靠性校验的验证结果计算DRAM理想模型下的供电电压的电压偏差值的步骤还包括：
    若所述校验结果是成功，则对所述供电电压的电压测试值减少一个预设电压减少值，获得新的供电电压的电压测试值。
  5. 如权利要求1所述的提高系统DRAM可靠性的方法，其中，所述提高系统DRAM可靠性的方法还包括：
    获得DRAM的供电电容值，按照预设规则调整DRAM的供电电容值获得调整后的DRAM电容值，直到与调整后的DRAM电容值对应的表现电压大于或等于预设门限电压。
  6. 如权利要求5所述的提高系统DRAM可靠性的方法，其中，所述获得DRAM的供电电容值，按照预设规则调整DRAM的供电电容值获得调整后的DRAM电容值，直到与调整后的DRAM电容值对应的表现电压大于或等于预设门限电压的步骤包括：
    根据所述电压偏差值确定所述DRAM的供电电压值是否变化；
    若所述DRAM的供电电压值变化，则将所述DRAM的电容值减少一个预设电容减少值，获得调整后的电容测试值，并对调整后的电容进行可靠性校验；
    若所述可靠性校验结果为所述表现电压小于预设门限电压，则返回步骤：将所述DRAM的电容值减少一个预设电容减少值，获得调整后的电容测试值，并对调整后的电容进行可靠性校验，直到调整后的DRAM电容对应的表现电压大于或等于预设门限电压。
  7. 如权利要求6所述的提高系统DRAM可靠性的方法，其中，所述获得DRAM的供电电容值，按照预设规则调整DRAM的供电电容值获得调整后的DRAM电容值，直到与调整后的DRAM电容值对应的表现电压大于或等于预设门限电压的步骤还包括：
    若所述DRAM的供电电压值不变化，则将所述DRAM的电容值增加一个预设电容增加值，获得调整后的电容测试值，并对调整后的电容进行可靠性校验；
    若所述可靠性校验结果为所述表现电压大于或等于预设门限电压，则返回步骤：将所述DRAM的电容值增加一个预设电容增加值，获得调整后的电容测试值，并对调整后的电容进行可靠性校验，直到调整后的DRAM电容对应的表现电压小于预设门限电压。
  8. 如权利要求5-7中任一项所述的提高系统DRAM可靠性的方法，其中，所述电容为可变电容。
  9. 一种提高系统DRAM可靠性的装置，其中，所述提高系统DRAM可靠性的装置包括：存储器、处理器及存储在所述存储器上并可在所述处理器上运行的提高系统DRAM可靠性的程序，所述提高系统DRAM可靠性的程序被所述处理器执行时，实现如权利要求1至8中任一项所述提高系统DRAM可靠性的方法的步骤。
  10. 一种计算机可读存储介质，其中，所述计算机可读存储介质上存储有提高系统DRAM可靠性的程序，所述提高系统DRAM可靠性的程序被处理器执行时，实现如权利要求1至8中任一项所述提高系统DRAM可靠性的方法的步骤。
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