WO2021032397A1 - Puce semi-conductrice optoélectronique - Google Patents

Puce semi-conductrice optoélectronique Download PDF

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Publication number
WO2021032397A1
WO2021032397A1 PCT/EP2020/070663 EP2020070663W WO2021032397A1 WO 2021032397 A1 WO2021032397 A1 WO 2021032397A1 EP 2020070663 W EP2020070663 W EP 2020070663W WO 2021032397 A1 WO2021032397 A1 WO 2021032397A1
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WO
WIPO (PCT)
Prior art keywords
layer
semiconductor chip
electrical connection
dielectric layers
optoelectronic semiconductor
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Application number
PCT/EP2020/070663
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German (de)
English (en)
Inventor
Brendan HOLLAND
Original Assignee
Osram Opto Semiconductors Gmbh
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Application filed by Osram Opto Semiconductors Gmbh filed Critical Osram Opto Semiconductors Gmbh
Publication of WO2021032397A1 publication Critical patent/WO2021032397A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor

Definitions

  • an optoelectronic semiconductor chip in which a first and a second electrical connection layer are arranged between a semiconductor body with an active region provided for generating radiation and a carrier element.
  • the first electrical connection layer can be provided to reflect radiation generated in the active area and thus to increase the total radiation power emitted.
  • the second electrical connection layer extends through at least one recess in a first semiconductor layer and the active region into a second semiconductor layer.
  • the optoelectronic semiconductor chip has a Semiconductor layer sequence which has a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type and an active region arranged between the first semiconductor region and the second semiconductor region.
  • the active area is preferably provided for generating radiation.
  • the optoelectronic semiconductor chip can in particular be a light-emitting diode chip.
  • the active area can have, for example, a pn junction, a double heterostructure, a single quantum well structure (SQW structure) or a multiple quantum well structure (MQW structure).
  • the semiconductor layer sequence can comprise further functional layers and functional areas, for example p- or n-doped charge carrier transport layers, undoped or p- or n-doped confinement, cladding or waveguide layers, barrier layers, planarization layers, buffer layers, protective layers and / or Electrodes and combinations thereof.
  • the optoelectronic semiconductor chip can have a semiconductor layer sequence based on different semiconductor material systems.
  • a semiconductor layer sequence based on In x Ga y Al 1-xy As is suitable for long-wave, infrared to red radiation, for example, a semiconductor layer sequence based on In x Ga y Al 1-xy P is suitable for red to green radiation and for Short-wave visible radiation, in particular for green to blue radiation, and / or for UV radiation, for example, a semiconductor layer sequence based on InxGayAl1-x-yN is suitable, where 0 £ x £ 1 and 0 £ y £ 1 apply.
  • the optoelectronic semiconductor chip has a carrier on which the semiconductor layer sequence is arranged.
  • the first semiconductor region is preferably a p-type semiconductor region and is arranged on the side of the semiconductor layer sequence facing the carrier.
  • the second semiconductor region is preferably an n-type semiconductor region and is arranged on the side of the semiconductor layer sequence facing away from the carrier.
  • the p-type semiconductor region and the n-type semiconductor region may each include one or more semiconductor layers. It is also not excluded that the p-type semiconductor region and / or the n-type semiconductor region contain one or more undoped layers.
  • the optoelectronic semiconductor chip has a first electrical connection layer and a second electrical connection layer, the first electrical connection layer and the second electrical connection layer being arranged in regions between the carrier and the semiconductor layer sequence.
  • the first electrical connection layer is electrically conductively connected to the first semiconductor region and can, for example, directly adjoin the first semiconductor region.
  • the second electrical connection layer is led through at least one opening or preferably a plurality of openings in the first semiconductor region and the active region into the second semiconductor region and in this way is electrically conductively connected to the second semiconductor region.
  • the optoelectronic semiconductor chip has an insulation layer which is between the first electrical connection layer and the second electrical connection layer is arranged.
  • the insulation layer has the function in particular of preventing an electrical short circuit between the first electrical connection layer and the second electrical connection layer.
  • the insulation layer comprises a reflection-increasing dielectric layer sequence which has alternating first dielectric layers with a refractive index n 1 and second dielectric layers with a refractive index n 2 > n 1 .
  • the insulation layer advantageously has an additional functionality, namely to reflect radiation from the active region which strikes the insulation layer and in this way to increase the radiation yield of the optoelectronic semiconductor chip.
  • the reflection-increasing effect of the dielectric layer sequence is advantageously achieved by constructive interference at the boundary surfaces of the alternating first layers and second layers.
  • the reflection-increasing dielectric layer sequence is a dielectric interference layer system.
  • Such a reflection-increasing dielectric layer system based on constructive interference is often referred to as a Bragg mirror.
  • the reflection-increasing dielectric layer sequence has a reflection maximum in the emission wavelength range of the radiation emitted by the active region.
  • the reflection-increasing dielectric layer sequence has a reflection maximum at a wavelength IR, max and the radiation emitted by the active region has an intensity maximum at a wavelength l I, max , where l R, max is adapted to l I, max .
  • the wavelength l R, max can in particular be set by the materials and layer thicknesses of the first dielectric layers and second dielectric layers. For this purpose, for example, simulation programs known per se to the person skilled in the art can be used to calculate the reflection of thin-film systems.
  • the first dielectric layers have a refractive index n 1 ⁇ 1.7.
  • the refractive index of the first dielectric layers is preferably n 1 ⁇ 1.6, particularly preferably n 1 ⁇ 1.5.
  • a low refractive index of the first layers has the advantage that a high refractive index difference from the second layers with the higher refractive index can be achieved. This is advantageous in order to achieve a high reflection of the reflection-increasing dielectric layer sequence.
  • the second dielectric layers have a refractive index n 2 > 1.8.
  • the refractive index of the second dielectric layers is preferably n 2 > 2.0.
  • a high refractive index of the second dielectric layers has the advantage that there is a high refractive index difference from the first dielectric layers with the lower refractive index can be achieved. This is advantageous in order to achieve a high reflection of the reflection-increasing dielectric layer sequence.
  • the first dielectric layers have SiO 2 .
  • the second dielectric layers have Nb 2 O 5, TiO 2 , HfO 2 , Ta 2 O 5 or ZrO 2 .
  • the materials mentioned are characterized in particular by a comparatively high refractive index.
  • the reflection-increasing dielectric layer sequence comprises at least three layer pairs of the first dielectric layers and second dielectric layers.
  • the reflection-increasing dielectric layer sequence particularly preferably comprises at least four layer pairs of the first dielectric layers and second dielectric layers. With a number of at least three or preferably at least four pairs of layers, a comparatively high reflection can be achieved with a still low manufacturing cost.
  • the second electrical connection layer comprises aluminum or titanium or consists thereof. It is possible for the second electrical connection layer to have a plurality of partial layers, with a first partial layer being able to function, for example, as an adhesion promoter layer.
  • the dielectric as reflection-increasing The insulation layer formed in a layer sequence can in particular directly adjoin the second electrical connection layer. Viewed from the active area, the second electrical connection layer is arranged at least in some areas behind the insulation layer. When calculating the reflection of the reflection-increasing dielectric layer sequence, the second electrical connection layer can be viewed as a metallic substrate which has aluminum or titanium, for example.
  • the first electrical connection layer comprises or consists of silver. Silver is characterized by a particularly high reflectivity in the visible spectral range.
  • the first connection layer can contain another material with a high reflectivity, in particular a metal such as aluminum, platinum, titanium or palladium.
  • FIG. 1 shows a schematic view of an optoelectronic semiconductor chip according to an exemplary embodiment in a top view
  • FIG. 2 shows a schematic view of the optoelectronic semiconductor chip according to FIG. 1 in a cross section along the line AA '
  • 3 shows a schematic detailed view of an example of the insulation layer in a cross section
  • FIG. 4 shows a graphical representation of the calculated reflectivity R as a function of the wavelength l for two exemplary embodiments of the insulation layer and a comparative example
  • FIG. 5 shows a schematic detailed view of a further example of the insulation layer in a cross section
  • FIGS. 1 and 2 show an exemplary embodiment of the optoelectronic semiconductor chip 1, which is a light-emitting diode chip.
  • the optoelectronic semiconductor chip 1 contains a semiconductor layer sequence 2 which has a first semiconductor region 21 of a first conductivity type and a second semiconductor region 22 of a second conductivity type.
  • the first semiconductor region 21 is a p-type semiconductor region and the second semiconductor region 22 is an n-type semiconductor region.
  • An active region 20 is arranged between the first semiconductor region 21 and the second semiconductor region 22.
  • the active area 20 of the optoelectronic semiconductor chip 1 is particularly suitable for emitting radiation.
  • the active region 20 can be designed, for example, as a pn junction, a double heterostructure, a single quantum well structure or a multiple quantum well structure.
  • the term quantum well structure includes any structure in which charge carriers experience a quantization of their energy states through confinement.
  • the term quantum well structure does not contain any information about the dimensionality of the quantization.
  • the semiconductor layer sequence 2 of the semiconductor chip 1 is preferably based on a III-V compound semiconductor material, in particular on a nitride, phosphide or arsenide compound semiconductor material.
  • the III-V compound semiconductor material does not necessarily have to have a mathematically exact composition according to one of the above formulas. Rather, it can have one or more dopants and additional components.
  • the semiconductor chip 1 is connected to a carrier 10 with a connection layer 7, which can in particular be a solder layer made of a metal or a metal alloy of a solder layer or an electrically conductive adhesive layer.
  • the carrier 10 is formed from an electrically conductive material, for example a doped semiconductor material such as silicon or germanium.
  • the carrier 10 can be formed from an electrically insulating material in which electrically conductive plated-through holes are formed for electrical contacting.
  • a ceramic, for example aluminum nitride or boron nitride, or a plastic is suitable as the electrically insulating material.
  • the carrier 10 can be different from the growth substrate of the semiconductor layer sequence 2.
  • the optoelectronic semiconductor chip 1 can be a semiconductor chip from which the growth substrate is detached. Such a semiconductor chip is often referred to as a thin-film semiconductor chip.
  • the functional semiconductor layer sequence 2 which in particular comprises a radiation-emitting active layer 20, is first grown epitaxially on a growth substrate, then a new carrier 10 is applied to the surface of the semiconductor layer sequence 2 opposite the growth substrate, and the growth substrate is subsequently separated .
  • the main area of the semiconductor layer sequence 2 opposite the carrier 10 serves as a radiation exit area 11 of the optoelectronic semiconductor chip 1 and is advantageously free of electrical contact layers.
  • the radiation exit surface 11 can be provided with a coupling out structure 9 or a roughening.
  • the coupling-out structure 9 can be regular or irregular.
  • the structuring can be formed by means of pyramid-shaped or truncated pyramid-shaped depressions or a roughening.
  • the semiconductor chip 1 has a first electrical connection layer 31 and a second electrical connection layer 32.
  • the first electrical connection layer 31 is electrically conductively connected to the first semiconductor region 21 and the second electrical connection layer 32 is connected to the second semiconductor region 22.
  • the first electrical connection layer 31 follows the first semiconductor region 21 on the side facing the carrier 10 and can in particular directly adjoin the first semiconductor region 21 of the semiconductor layer sequence 2. It is also possible for at least one intermediate layer to be arranged between the first semiconductor region 21 and the first electrical connection layer 31, for example a thin adhesion promoter layer or a current spreading layer, for example a layer made of a transparent one conductive oxide.
  • the first electrical connection layer 31 contains in particular silver, aluminum or a metal alloy with silver or aluminum.
  • the first electrical connection layer 31 advantageously has the function of a mirror layer which reflects radiation emitted by the active region 20 in the direction of the carrier 10 towards the radiation exit surface 11.
  • the second electrical connection layer 32 is connected in an electrically conductive manner to the second semiconductor region 22 through a plurality of openings 25 which extend through the first semiconductor region 21 and the active region 20.
  • the second electrical connection layer 32 functions in the areas in which it directly adjoins the semiconductor layer sequence 2, advantageously not only as a contact layer, but also as a reflective layer that reflects radiation towards the second main surface of the semiconductor layer sequence 2 serving as radiation exit surface 11.
  • the semiconductor chip 1 has a first contact 41 and a second contact 42, the first contact 41 being connected to the first electrical connection layer 31 and the second contact, for example, via the carrier 10 and the connection layer 7 to the second electrical connection layer 32 is electrically conductively connected, so that during operation of the semiconductor chip, charge carriers from different sides of the active region 20 are in them are injected and can recombine there with emission of radiation.
  • an encapsulation layer 6 adjoins the first electrical connection layer 31.
  • the encapsulation layer 6 has in particular the function of protecting the first electrical connection layer, which has silver, for example, and can also be provided to electrically connect the first electrical connection layer 31 to the first contact 41.
  • the encapsulation layer 6 can have a plurality of partial layers and / or be structured (not shown).
  • the encapsulation layer 6 can in particular comprise metals such as titanium, platinum, gold, tungsten or metal alloys such as TiW. It is also possible for the encapsulation layer 6 to have one or more dielectric layers such as Al 2 O 3 , at least in regions.
  • the optoelectronic semiconductor chip 1 has a transparent dielectric protective layer 8.
  • the transparent dielectric protective layer 8 covers, in particular, the side surfaces and the main surface of the semiconductor layer sequence 2 that serves as the radiation exit surface 11.
  • the semiconductor layer sequence 2 is advantageously completely covered by the transparent protective layer 8.
  • the transparent protective layer 8 is preferably an aluminum oxide layer, in particular an Al 2 O 3 layer, or a silicon oxide layer, in particular an SiO 2 layer.
  • the transparent encapsulation layer is advantageously deposited by means of atomic layer deposition or as spin-on glass. Such by means of ALD or as a spin-on Silicon oxide layer deposited on glass advantageously has a high resistance to corrosion and the ingress of moisture.
  • the transparent protective layer 8 can advantageously close any fine cracks present on the surfaces of the semiconductor layer sequence 2. The complete encapsulation of the semiconductor layer sequence 2 is therefore advantageous for the long-term stability of the semiconductor chip.
  • the transparent protective layer 8 has an opening in which the first contact 41 is arranged, which is connected to the first electrical contact layer 31 via the conductive encapsulation layer 6.
  • the first contact 41 can in particular be a bond pad, which is provided for connecting a bond wire.
  • the first contact 41 is preferably arranged outside the center of the semiconductor chip 1, in particular in the region of a corner of the semiconductor chip 1.
  • Both the first electrical connection layer 31 and the second electrical connection layer 32 are at least regionally between a main surface of the semiconductor layer sequence 2 and facing the carrier 10 the carrier 10 arranged.
  • the first electrical connection layer 31 and the second electrical connection layer 32 are electrically insulated from one another by means of an insulation layer 5.
  • the insulation layer 5 is a reflection-increasing dielectric in the optoelectronic semiconductor chip 1 Sequence of layers.
  • FIGS. 3 and 4 Detailed views of possible designs of the insulation layer 5 are shown in FIGS. 3 and 4.
  • the insulation layer 5 has alternating first dielectric layers 51 and second dielectric layers 52.
  • the first dielectric layers 51 have a refractive index n 1 , for which advantageously n 1 ⁇ 1.7, preferably n 1 ⁇ 1.6 and particularly preferably n 1 ⁇ 1.5 applies.
  • the second dielectric layers 52 have a refractive index n 2 > n 1 , preferably n 2 > 1.8 and particularly preferably n 2 > 2.
  • the first dielectric layers 51 are low refractive index layers and the second dielectric layers 52 are high refractive index layers.
  • the first dielectric layers 51 preferably contain or consist of SiO 2.
  • Suitable materials for the second dielectric layers 52 are, for example, Nb 2 O 5, TiO 2 , HfO 2 , Ta 2 O 5 or ZrO 2 . These materials are characterized by a high refractive index n 2 > 2. It is not necessary for the dielectric layers 51, 52 to form a periodic layer sequence in which all first dielectric layers 51 and all second dielectric layers 52 each have the same layer thickness.
  • the layer thicknesses of the plurality of first dielectric layers 51 and second dielectric layers can differ from one another.
  • Computer simulations can be used to optimize the layer thicknesses in order to achieve the highest possible reflectivity at a given wavelength or in a given wavelength range.
  • the optimization is preferably carried out in such a way that the reflection-increasing dielectric layer sequence 5 has a reflection maximum at a wavelength l R, max and the radiation emitted by the active area has an intensity maximum at a wavelength l I, max , where l R, max is adapted to l I, max is.
  • the wavelength l R, max can in particular be set by the materials and layer thicknesses of the first dielectric layers 51 and second dielectric layers 52.
  • the insulation layer 5 adjoins the second electrical contact layer 32 on a side facing away from the semiconductor layer sequence.
  • the second electrical contact layer which contains a metal such as aluminum or titanium, can be viewed as a substrate when calculating the reflectivity of the dielectric layer sequence.
  • the insulation layer 5 can adjoin the encapsulation layer 6 or the transparent dielectric protective layer 8 in regions.
  • the insulation layer 5 has a reflection-increasing dielectric layer sequence, which, starting from the second electrical contact layer 32, has three layer pairs of alternating first dielectric layers 51 and second dielectric layers 52 and a further first dielectric layer 51.
  • the production outlay for the insulation layer 5 embodied as a reflection-increasing dielectric layer sequence is therefore advantageously low.
  • the second electrical connection layer 32 is a titanium layer, the insulation layer 5, starting from the second electrical connection layer 32, being an SiO 2 layer 51 with a thickness of 67.0 nm, an Nb 2 O 5 Layer 52 with a thickness of 53.5 nm, an SiO 2 layer 51 with a thickness of 94.6 nm, an Nb 2 O 5 layer 52 with a thickness of 60.7 nm, an SiO 2 layer 51 with a thickness of 92.3 nm, an Nb 2 O 5 layer 52 with a thickness of 52.6 nm and an SiO 2 layer 51 with a thickness of 94.3 nm.
  • the layer thicknesses have been optimized by means of a computer simulation in such a way that a maximum reflection is achieved at a wavelength of 450 nm.
  • the second electrical connection layer 32 is an aluminum layer, the insulation layer 5, starting from the second electrical connection layer 32, being an SiO 2 layer 51 with a thickness of 64.4 nm, an Nb 2 O 5 Layer 52 with a thickness of 57.2 nm, an SiO 2 layer 51 with a thickness of 90.2 nm, an Nb 2 O 5 layer 52 with a thickness of 63.4 nm, an SiO 2 layer 51 with a thickness of 94.9 nm, an Nb 2 O 5 layer 52 with a thickness of 52.3 nm and an SiO 2 layer 51 with a thickness of 93.0 nm.
  • the layer thicknesses have been optimized by means of a computer simulation in such a way that a maximum reflection is achieved at a wavelength of 450 nm.
  • the reflection R is a function of the wavelength l for the first example according to Figure 3 (curve 61), the second example according to Figure 3 (curve 62) and a comparative example not according to the invention (curve 63), in which the insulation layer only is formed by a 600 nm thick SiO 2 layer. It has been shown that with the insulation layer 5 designed as a reflection-increasing dielectric layer sequence, a significantly higher reflection can be achieved than when using an SiO 2 layer as the insulation layer.
  • the insulation layer 5 designed as a reflection-increasing dielectric layer sequence
  • the insulation layer 5 has a reflection-increasing dielectric layer sequence, which, starting from the second electrical contact layer 32, has four layer pairs of alternating first dielectric layers 51 and second dielectric layers 52 and a further first dielectric layer 51.
  • the manufacturing outlay for the insulation layer 5 is still advantageously low in this case.
  • the second electrical connection layer 32 is a titanium layer, the insulation layer 5, starting from the second electrical connection layer 32, being an SiO 2 layer 51 with a thickness of 63.0 nm, an Nb 2 O 5 - Layer 52 with a thickness of 54.0 nm, an SiO 2 layer 51 with a thickness of 90.0 nm, an Nb 2 O 5 layer 52 with a thickness of 54.0 nm, an SiO 2 layer 51 with a thickness of 90.0 nm, an Nb 2 O 5 layer 52 with a thickness of 54.0 nm, an SiO 2 layer 51 with a thickness of 90.0 nm, an Nb 2 O 5 layer 52 with a thickness of 54.0 nm, an SiO 2 layer 51 with a thickness of 90.0 nm, an Nb 2 O 5 layer 52 with a Thickness of 54.0 nm and an SiO2 layer 51 with a thickness of 90.0 nm.
  • the reflection R is shown as a function of the wavelength l for the example according to FIG.
  • the high reflectivity of the insulation layer 5 designed as a reflection-increasing dielectric layer sequence is advantageous in the optoelectronic semiconductor chip 1 described here in order to improve the radiation yield, particularly in the edge regions of the optoelectronic semiconductor chip 1, in which the insulation layer 5 can be arranged directly under a transparent protective layer 8 to achieve.
  • the optoelectronic semiconductor chip 1 described herein is therefore advantageous for all applications in which a high level of brightness and a light image that is as homogeneous as possible is desirable.
  • the optoelectronic semiconductor chip 1 can be used, for example, as a light-emitting diode chip for vehicle headlights, in particular in the automotive sector, in lamps for general lighting or for other special lighting purposes.
  • the design of the insulation layer as a reflection-increasing dielectric layer sequence also contributes to protecting the optoelectronic semiconductor chip from external influences such as moisture or corrosive substances.
  • the alternating dielectric layers have a good barrier effect, which increases the long-term stability of the optoelectronic semiconductor chip.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

L'invention porte sur une puce semi-conductrice optoélectronique (1) comprenant : - une séquence de couches semi-conductrices (2), laquelle est agencée sur un substrat (10) et a une zone active (20), - une première couche de connexion électrique (31) et une deuxième couche de connexion électrique (32), lesquelles sont agencées, au moins dans des zones, entre le substrat (10) et la séquence de couches semi-conductrices (2), la première couche de connexion électrique (31) étant connectée de manière électriquement conductrice à une première zone semi-conductrice (21), la deuxième couche de connexion électrique (32) étant conduite, à travers au moins un trou traversant (25) dans la première zone semi-conductrice (21) et dans la zone active (20), dans la deuxième zone semi-conductrice (22) et étant connectée de manière électriquement conductrice à ladite deuxième zone semi-conductrice, et - une couche d'isolation (5) entre la première couche de connexion électrique (31) et la deuxième couche de connexion électrique (32), la couche d'isolation (5) étant une séquence de couches diélectriques augmentant la réflexion qui comprend, en alternance, des premières couches diélectriques (51) dont l'indice de réfraction est n1 et des deuxièmes couches diélectriques (52) dont l'indice de réfraction est n2 > n1.
PCT/EP2020/070663 2019-08-22 2020-07-22 Puce semi-conductrice optoélectronique WO2021032397A1 (fr)

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DE102019122593.0A DE102019122593A1 (de) 2019-08-22 2019-08-22 Optoelektronischer Halbleiterchip
DE102019122593.0 2019-08-22

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008034708A1 (de) * 2008-07-25 2010-02-04 Osram Opto Semiconductors Gmbh Optoelektronischer Halbleiterchip und Verfahren zur Herstellung eines optoelektronischen Halbleiterchips
US20120074441A1 (en) * 2010-09-24 2012-03-29 Seoul Semiconductor Co., Ltd. Wafer-level light emitting diode package and method of fabricating the same
WO2012110364A1 (fr) 2011-02-14 2012-08-23 Osram Opto Semiconductors Gmbh Puce semi-conductrice optoélectronique et procédé de fabrication d'une puce semi-conductrice optoélectronique
US20180108704A1 (en) * 2012-08-07 2018-04-19 Seoul Viosys Co., Ltd. Wafer level light-emitting diode array
EP3454372A1 (fr) * 2016-05-03 2019-03-13 Seoul Viosys Co., Ltd. Diode électroluminescente

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3926698B1 (fr) * 2011-09-16 2023-01-04 Seoul Viosys Co., Ltd. Diode électroluminescente
KR102471102B1 (ko) * 2015-10-23 2022-11-25 서울바이오시스 주식회사 분포 브래그 반사기를 가지는 발광 다이오드 칩

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008034708A1 (de) * 2008-07-25 2010-02-04 Osram Opto Semiconductors Gmbh Optoelektronischer Halbleiterchip und Verfahren zur Herstellung eines optoelektronischen Halbleiterchips
US20120074441A1 (en) * 2010-09-24 2012-03-29 Seoul Semiconductor Co., Ltd. Wafer-level light emitting diode package and method of fabricating the same
WO2012110364A1 (fr) 2011-02-14 2012-08-23 Osram Opto Semiconductors Gmbh Puce semi-conductrice optoélectronique et procédé de fabrication d'une puce semi-conductrice optoélectronique
US20180108704A1 (en) * 2012-08-07 2018-04-19 Seoul Viosys Co., Ltd. Wafer level light-emitting diode array
EP3454372A1 (fr) * 2016-05-03 2019-03-13 Seoul Viosys Co., Ltd. Diode électroluminescente

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