WO2021028723A3 - Memory-based processors - Google Patents

Memory-based processors Download PDF

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Publication number
WO2021028723A3
WO2021028723A3 PCT/IB2020/000665 IB2020000665W WO2021028723A3 WO 2021028723 A3 WO2021028723 A3 WO 2021028723A3 IB 2020000665 W IB2020000665 W IB 2020000665W WO 2021028723 A3 WO2021028723 A3 WO 2021028723A3
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
substrate
memory
memory banks
based processors
Prior art date
Application number
PCT/IB2020/000665
Other languages
French (fr)
Other versions
WO2021028723A2 (en
Inventor
Elad SITY
Eliad HILLEL
Shany BRAUDO
David Shamir
Gal DAYAN
Original Assignee
Neuroblade Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Neuroblade Ltd. filed Critical Neuroblade Ltd.
Priority to EP20852497.5A priority Critical patent/EP4010808A4/en
Priority to CN202080071415.1A priority patent/CN114586019A/en
Priority to KR1020227008116A priority patent/KR20220078566A/en
Publication of WO2021028723A2 publication Critical patent/WO2021028723A2/en
Publication of WO2021028723A3 publication Critical patent/WO2021028723A3/en
Priority to US17/668,260 priority patent/US20220269645A1/en
Priority to US17/668,240 priority patent/US11860782B2/en
Priority to US17/669,642 priority patent/US20220164294A1/en
Priority to US17/669,649 priority patent/US20220164297A1/en
Priority to US17/669,657 priority patent/US20220164284A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7821—Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
    • G06F12/1441—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block for a range
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45—Caching of specific data in cache memory
    • G06F2212/454—Vector or matrix data
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Computer Security & Cryptography (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Software Systems (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Storage Device Security (AREA)
  • Semiconductor Memories (AREA)

Abstract

In some embodiments, an integrated circuit may include a substrate and a memory array disposed on the substrate, where the memory array includes a plurality of discrete memory banks. The integrated circuit may also include a processing array disposed on the substrate, where the processing array includes a plurality of processor subunits, each one of the plurality of processor subunits being associated with one or more discrete memory banks among the plurality of discrete memory banks. The integrated circuit may also include a controller configured to implement at least one security measure with respect to an operation of the integrated circuit and take one or more remedial actions if the at least one security measure is triggered.
PCT/IB2020/000665 2019-08-13 2020-08-13 Memory-based processors WO2021028723A2 (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
EP20852497.5A EP4010808A4 (en) 2019-08-13 2020-08-13 Memory-based processors
CN202080071415.1A CN114586019A (en) 2019-08-13 2020-08-13 Memory-based processor
KR1020227008116A KR20220078566A (en) 2019-08-13 2020-08-13 memory-based processor
US17/668,260 US20220269645A1 (en) 2019-08-13 2022-02-09 Memory mat as a register file
US17/668,240 US11860782B2 (en) 2019-08-13 2022-02-09 Compensating for DRAM activation penalties
US17/669,642 US20220164294A1 (en) 2019-08-13 2022-02-11 Cyber security and tamper detection techniques with a distributed processor memory chip
US17/669,649 US20220164297A1 (en) 2019-08-13 2022-02-11 Distributed processor memory chip with multi-port processor subunits
US17/669,657 US20220164284A1 (en) 2019-08-13 2022-02-11 In-memory zero value detection

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
US201962886328P 2019-08-13 2019-08-13
US62/886,328 2019-08-13
US201962907659P 2019-09-29 2019-09-29
US62/907,659 2019-09-29
US201962930593P 2019-11-05 2019-11-05
US62/930,593 2019-11-05
US202062971912P 2020-02-07 2020-02-07
US62/971,912 2020-02-07
US202062983174P 2020-02-28 2020-02-28
US62/983,174 2020-02-28

Related Child Applications (5)

Application Number Title Priority Date Filing Date
US17/668,260 Continuation US20220269645A1 (en) 2019-08-13 2022-02-09 Memory mat as a register file
US17/668,240 Continuation US11860782B2 (en) 2019-08-13 2022-02-09 Compensating for DRAM activation penalties
US17/669,657 Continuation US20220164284A1 (en) 2019-08-13 2022-02-11 In-memory zero value detection
US17/669,649 Continuation US20220164297A1 (en) 2019-08-13 2022-02-11 Distributed processor memory chip with multi-port processor subunits
US17/669,642 Continuation US20220164294A1 (en) 2019-08-13 2022-02-11 Cyber security and tamper detection techniques with a distributed processor memory chip

Publications (2)

Publication Number Publication Date
WO2021028723A2 WO2021028723A2 (en) 2021-02-18
WO2021028723A3 true WO2021028723A3 (en) 2021-07-08

Family

ID=74570549

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2020/000665 WO2021028723A2 (en) 2019-08-13 2020-08-13 Memory-based processors

Country Status (5)

Country Link
EP (1) EP4010808A4 (en)
KR (1) KR20220078566A (en)
CN (1) CN114586019A (en)
TW (1) TW202122993A (en)
WO (1) WO2021028723A2 (en)

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KR102638791B1 (en) * 2018-09-03 2024-02-22 에스케이하이닉스 주식회사 Semiconductor device and semiconductor system
EP4341934A1 (en) * 2021-05-18 2024-03-27 Silicon Storage Technology, Inc. Split array architecture for analog neural memory in a deep learning artificial neural network
US11327771B1 (en) * 2021-07-16 2022-05-10 SambaNova Systems, Inc. Defect repair circuits for a reconfigurable data processor
US20230051863A1 (en) * 2021-08-10 2023-02-16 Micron Technology, Inc. Memory device for wafer-on-wafer formed memory and logic
US11914532B2 (en) 2021-08-31 2024-02-27 Apple Inc. Memory device bandwidth optimization
US11947940B2 (en) * 2021-10-11 2024-04-02 International Business Machines Corporation Training data augmentation via program simplification
CN116264085A (en) * 2021-12-14 2023-06-16 长鑫存储技术有限公司 Storage system and data writing method thereof
TWI819480B (en) * 2022-01-27 2023-10-21 緯創資通股份有限公司 Acceleration system and dynamic configuration method thereof
TWI776785B (en) * 2022-04-07 2022-09-01 點序科技股份有限公司 Die test system and die test method thereof
WO2023227945A1 (en) * 2022-05-25 2023-11-30 Neuroblade Ltd. Processing systems and methods
US20230393849A1 (en) * 2022-06-01 2023-12-07 Advanced Micro Devices, Inc. Method and apparatus to expedite system services using processing-in-memory (pim)
WO2024027937A1 (en) * 2022-08-05 2024-02-08 Synthara Ag Memory-mapped compact computing array
CN115237036B (en) * 2022-09-22 2023-01-10 之江实验室 Full-digitalization management device for wafer-level processor system
CN115599025B (en) * 2022-12-12 2023-03-03 南京芯驰半导体科技有限公司 Resource grouping control system, method and storage medium of chip array
CN116962176B (en) * 2023-09-21 2024-01-23 浪潮电子信息产业股份有限公司 Data processing method, device and system of distributed cluster and storage medium

Citations (8)

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US20120102576A1 (en) * 2010-10-22 2012-04-26 Yen Hsiang Chew Scalable Memory Protection Mechanism
US20120255018A1 (en) * 2011-03-31 2012-10-04 Mcafee, Inc. System and method for securing memory and storage of an electronic device with a below-operating system security agent
US20120291133A1 (en) * 2011-05-11 2012-11-15 International Business Machines Corporation Security compliant data storage management
US20140040622A1 (en) * 2011-03-21 2014-02-06 Mocana Corporation Secure unlocking and recovery of a locked wrapped app on a mobile device
US20140136915A1 (en) * 2012-11-15 2014-05-15 Elwha LLC, a limited liability corporation of the State of Delaware Error correction with non-volatile memory on an integrated circuit
US20140143470A1 (en) * 2012-11-21 2014-05-22 Coherent Logix, Incorporated Processing System With Interspersed Processors DMA-FIFO
WO2019025864A2 (en) * 2017-07-30 2019-02-07 Sity Elad A memory-based distributed processor architecture
US20190102325A1 (en) * 2017-09-29 2019-04-04 Intel Corporation Memory control management of a processor

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JP2002063069A (en) * 2000-08-21 2002-02-28 Hitachi Ltd Memory controller, data processing system, and semiconductor device

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120102576A1 (en) * 2010-10-22 2012-04-26 Yen Hsiang Chew Scalable Memory Protection Mechanism
US20140040622A1 (en) * 2011-03-21 2014-02-06 Mocana Corporation Secure unlocking and recovery of a locked wrapped app on a mobile device
US20120255018A1 (en) * 2011-03-31 2012-10-04 Mcafee, Inc. System and method for securing memory and storage of an electronic device with a below-operating system security agent
US20120291133A1 (en) * 2011-05-11 2012-11-15 International Business Machines Corporation Security compliant data storage management
US20140136915A1 (en) * 2012-11-15 2014-05-15 Elwha LLC, a limited liability corporation of the State of Delaware Error correction with non-volatile memory on an integrated circuit
US20140143470A1 (en) * 2012-11-21 2014-05-22 Coherent Logix, Incorporated Processing System With Interspersed Processors DMA-FIFO
WO2019025864A2 (en) * 2017-07-30 2019-02-07 Sity Elad A memory-based distributed processor architecture
US20190102325A1 (en) * 2017-09-29 2019-04-04 Intel Corporation Memory control management of a processor

Also Published As

Publication number Publication date
CN114586019A (en) 2022-06-03
EP4010808A2 (en) 2022-06-15
KR20220078566A (en) 2022-06-10
EP4010808A4 (en) 2023-11-15
TW202122993A (en) 2021-06-16
WO2021028723A2 (en) 2021-02-18

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