WO2021026712A1 - 滤波器电路以及用于发射通道的集成电路 - Google Patents

滤波器电路以及用于发射通道的集成电路 Download PDF

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Publication number
WO2021026712A1
WO2021026712A1 PCT/CN2019/100161 CN2019100161W WO2021026712A1 WO 2021026712 A1 WO2021026712 A1 WO 2021026712A1 CN 2019100161 W CN2019100161 W CN 2019100161W WO 2021026712 A1 WO2021026712 A1 WO 2021026712A1
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Prior art keywords
differential
inductor
input terminal
output terminal
differential inductor
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PCT/CN2019/100161
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English (en)
French (fr)
Inventor
缪卫明
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华为技术有限公司
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Priority to PCT/CN2019/100161 priority Critical patent/WO2021026712A1/zh
Priority to CN201980098393.5A priority patent/CN114097176A/zh
Publication of WO2021026712A1 publication Critical patent/WO2021026712A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/04—Frequency selective two-port networks

Definitions

  • the present application relates to the field of electricity, and more specifically, to a filter circuit and an integrated circuit for a transmission channel.
  • both the filter and the modulator adopt a passive architecture to meet the requirements of low power consumption.
  • the filter circuit and the modulator circuit are all in a differential form.
  • the input signal is usually in-phase (in-phase, I) differential circuit and the input signal is quadrature (quadrature, Q)
  • I in-phase
  • Q quadrature
  • the single transmitting channel composed of the differential circuit is set up next to each other, and each transmitting channel is set next to each other in the multiple transmitting channels. This will cause the intermediate frequency isolation of the adjacent IQ channels in the single transmitting channel or the adjacent IQ channels in the adjacent channels in the multi-channel
  • the IF isolation is limited and cannot meet the requirements of the system, so that the image suppression performance required by the system cannot be achieved through algorithm correction.
  • the present application provides a filter circuit and an integrated circuit for transmitting channels, which can improve the isolation between two adjacent differential inductors in a single transmitting channel or multiple transmitting channels when the chip area is limited.
  • the isolation between two adjacent differential inductors in two adjacent channels can improve the isolation between two adjacent differential inductors in two adjacent channels.
  • a filter circuit including a first differential circuit and a second differential circuit, the first differential circuit includes a first differential inductor, and the second differential circuit includes a second differential inductor; The direction of the magnetic field lines of a differential inductor and the second differential inductor are opposite to each other.
  • the first differential circuit and the second differential circuit may be two differential circuits arranged in parallel in a single transmission channel.
  • the first differential circuit and the second differential circuit may also be two differential circuits arranged in parallel in adjacent channels in a multi-transmission channel.
  • the magnetic field lines formed by the first differential inductor and the second differential inductor will cancel each other out, thereby reducing the first differential inductor and the second differential inductor pair.
  • the influence of and the influence on peripheral circuit devices can improve the isolation between the first differential inductor and the second differential inductor, that is, the isolation between two adjacent differential inductors in a single channel, or multi-channel The isolation between two adjacent differential inductors in two adjacent channels.
  • the first differential circuit includes a first positive input terminal and a first negative input terminal
  • the second differential circuit includes a second positive input terminal and a second negative input terminal.
  • Terminal, the first differential inductor and the second differential inductor are spiral inductors with the same winding method, and both the first differential inductor and the second differential inductor include the same first input terminal and the same second input terminal ,
  • the first positive input terminal is coupled to the second input terminal of the first differential inductor
  • the first negative input terminal is coupled to the first input terminal of the first differential inductor
  • the second positive The input terminal is coupled to the first input terminal of the second differential inductor
  • the second negative input terminal is coupled to the second input terminal of the second differential inductor.
  • the first differential inductor and the second differential inductor are within the magnetic field range of each other, so that the first differential inductor and the second differential inductor work The magnetic fields generated at time cancel each other out.
  • the first differential inductance and the second differential inductance are within the magnetic field range of each other, so that the magnetic fields generated by the first differential inductance and the second differential inductance during operation cancel each other, thereby reducing the difference between the first and second differential inductance pairs.
  • the impact on the peripheral circuit devices and the impact on the peripheral circuit components, which can improve the isolation between the first differential inductor and the second differential inductor, that is, the isolation between two adjacent differential inductors in a single channel can be improved, or more The isolation between two adjacent differential inductors in two adjacent channels in a channel.
  • the direction of the signal in the first differential inductor is first Direction
  • the direction of the signal in the second differential inductor is the second direction, the second direction and the first The direction is opposite.
  • the first differential circuit further includes a first positive output terminal and a first negative output terminal; the second differential circuit further includes a second positive output terminal and a second positive output terminal. Negative output terminal; the first differential inductor and the second differential inductor both include the same first output terminal and second output terminal; wherein the first output terminal of the first differential inductor is coupled to the first A negative output terminal, the second output terminal of the first differential inductor is coupled to the first positive output terminal, the first output terminal of the second differential inductor is coupled to the second positive output terminal, so The second output terminal of the second differential inductor is coupled to the second negative output terminal; the connection between the first positive input terminal and the first negative output port is parallel to the first negative input terminal The connection between the second positive input terminal and the second negative output terminal is parallel to the second negative input terminal and the second positive output Connection between terminals.
  • the direction of the output signal of the first differential circuit can be guaranteed Consistency with the direction of the output signal of the second differential circuit.
  • the distance between the first differential inductor and the second differential inductor is less than or equal to a target distance.
  • the signal input by the first differential circuit and the signal input by the second differential circuit are orthogonal signals.
  • the signal input by the first differential circuit and the signal input by the second differential circuit are quadrature signals, which can be understood as a phase difference between the signal input by the first differential circuit and the signal input by the second differential circuit. °.
  • an integrated circuit for a transmission channel which includes: a digital-to-analog converter; a modulator; and a filter circuit.
  • the filter circuit includes a first differential circuit and a second differential circuit.
  • a differential circuit includes a first differential inductance
  • the second differential circuit includes a second differential inductance; when the first differential inductance and the second differential inductance work in opposite directions, the second input terminal of the first differential inductance The first input terminal of the two differential inductors, the second input terminal of the second differential inductor, the second input terminal of the first differential inductor, the first input terminal of the second differential inductor, the second input terminal of the second differential inductor.
  • the first differential circuit and the second differential circuit may be two differential circuits arranged in parallel in a single transmission channel.
  • the first differential circuit and the second differential circuit may also be two differential circuits arranged in parallel in adjacent channels in a multi-transmission channel.
  • the above-mentioned integrated circuit includes a digital-to-analog converter, a modulator, and a filter circuit.
  • the first differential inductor and the second differential inductor in the filter circuit work in opposite directions of magnetic force, and the first differential inductor and the second differential inductor The formed magnetic fields will cancel each other out, thereby reducing the influence of the first differential inductor and the second differential inductor on each other and on the peripheral circuit devices, thereby improving the isolation between the first differential inductor and the second differential inductor , Which can improve the isolation between two adjacent differential inductors in a single channel, or between two adjacent differential inductors in two adjacent channels in a multi-channel.
  • the first differential circuit includes a first positive input terminal and a first negative input terminal
  • the second differential circuit includes a second positive input terminal and a second negative input terminal.
  • Terminal, the first differential inductor and the second differential inductor are spiral inductors with the same winding method, and both the first differential inductor and the second differential inductor include the same first input terminal and the same second input terminal ,
  • the first positive input terminal is coupled to the second input terminal of the first differential inductor
  • the first negative input terminal is coupled to the first input terminal of the first differential inductor
  • the second positive The input terminal is coupled to the first input terminal of the second differential inductor
  • the second negative input terminal is coupled to the second input terminal of the second differential inductor.
  • the first differential inductor and the second differential inductor are within the magnetic field range of each other, so that the first differential inductor and the second differential inductor work The magnetic fields generated at time cancel each other out.
  • the direction of the signal in the first differential inductor is first Direction
  • the direction of the signal in the second differential inductor is the second direction, the second direction and the first The direction is opposite.
  • the first differential circuit further includes a first positive output terminal and a first negative output terminal; the second differential circuit further includes a second positive output terminal and a second positive output terminal. Negative output terminal; the first differential inductor further includes a first output terminal of the first differential inductor and a second output terminal of the first differential inductor; the second differential inductor also includes a first output terminal of the second differential inductor and The second output terminal of the second differential inductor; the first differential inductor and the second differential inductor both include the same first output terminal and the second output terminal; wherein, the first output terminal of the first differential inductor Is coupled to the first negative output terminal, the second output terminal of the first differential inductor is coupled to the first positive output terminal, and the first output terminal of the second differential inductor is coupled to the first Two positive output terminals, the second output terminal of the second differential inductor is coupled to the second negative output terminal; the connection between the first positive input terminal and the first negative output port is parallel
  • the direction of the output signal of the first differential circuit can be guaranteed Consistency with the direction of the output signal of the second differential circuit.
  • the distance between the first differential inductor and the second differential inductor is less than or equal to a target distance.
  • the signal input by the first differential circuit and the signal input by the second differential circuit are orthogonal signals.
  • the signal input by the first differential circuit and the signal input by the second differential circuit are quadrature signals, which can be understood as a phase difference between the signal input by the first differential circuit and the signal input by the second differential circuit. °.
  • a chip system including the first aspect and the filter circuit in any possible implementation manner of the first aspect.
  • a chip system including the second aspect and the integrated circuit for the emission channel in any possible implementation manner of the second aspect.
  • Figure 1 shows a schematic diagram of the launch architecture in a single-channel chip.
  • Figure 2 shows a schematic diagram of a transmitter internal circuit module in a single-channel chip.
  • FIG. 3 shows a schematic structural diagram of a filter circuit 300.
  • FIG. 4 shows a schematic structural diagram of another filter circuit 400.
  • FIG. 5 is a schematic structural diagram of a filter circuit 500 provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of another filter circuit 600 provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of another filter circuit 700 provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of another filter circuit 800 provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of another filter circuit 900 provided by an embodiment of the present application.
  • the filter circuit or integrated circuit designed in the embodiment of the present application is mainly arranged in a single-channel or multi-channel network device chip.
  • the single channel in the chip can be a single transmitting channel or a single receiving channel.
  • the multiple channels in the chip can include N transmit channels and M receive channels, where N>1 and M>1.
  • the channels can be eight transmitting channels and eight receiving channels.
  • the filter circuit involved in the embodiments of the present application may be a filter circuit in a single channel or a filter circuit in multiple channels. Two adjacent channels in the multiple channels designed in the embodiment of the present application can be understood as no other channel arrangement between the two channels.
  • the equipment includes, but is not limited to: evolved Node B (eNB), Radio Network Controller (RNC), Node B (Node B, NB), Base Station Controller (BSC) , Base transceiver station (Base Transceiver Station, BTS), home base station (for example, Home evolved NodeB, or Home Node B, HNB), baseband unit (BaseBand Unit, BBU), wireless fidelity (Wireless Fidelity, WIFI) system Access point (Access Point, AP), wireless relay node, wireless backhaul node, transmission point (transmission point, TP) or transmission and reception point (transmission and reception point, TRP), etc., can also be 5G, such as NR ,
  • the gNB may include a centralized unit (CU) and a DU.
  • the gNB may also include an active antenna unit (AAU for short).
  • CU implements part of the functions of gNB
  • DU implements part of the functions of gNB.
  • the CU is responsible for processing non-real-time protocols and services, and implements radio resource control (radio resource control, RRC), packet data convergence protocol (packet data convergence protocol, PDCP) layer functions.
  • RRC radio resource control
  • PDCP packet data convergence protocol
  • the DU is responsible for processing physical layer protocols and real-time services, and realizes the functions of the radio link control (RLC) layer, media access control (MAC) layer, and physical (PHY) layer.
  • RLC radio link control
  • MAC media access control
  • PHY physical
  • the network device may be a device that includes one or more of a CU node, a DU node, and an AAU node.
  • the CU can be divided into network equipment in an access network (radio access network, RAN), or the CU can be divided into network equipment in a core network (core network, CN), which is not limited in this application.
  • Passive components resistance, inductance, and capacitance components. Their common feature is that they can work when there is a signal without adding power to the circuit.
  • Inductance is an attribute of a closed loop and a physical quantity.
  • a magnetic field is induced in the coil, and the induced magnetic field will generate an induced current to resist the current passing through the coil.
  • the interaction between this current and the coil is called electrical inductance.
  • the frequency can be divided into low frequency, intermediate frequency and high frequency, the low frequency frequency is generally 30 ⁇ 300kHz, the intermediate frequency frequency is generally 300 ⁇ 3000kHz, and the high frequency frequency is generally 3 ⁇ 30MHz.
  • Modulator refers to a device that modulates low-frequency signals into high-frequency signals through digital signal processing technology for signal transmission.
  • the modulator is generally used to modulate two input signals (for example, the signal to be modulated output by the positive phase (I) path and the signal to be modulated output by the quadrature (Q) path).
  • the frequency of the output signal of the modulator is equal to the sum or difference of the frequencies of the two input signals, or a circuit combining the two.
  • the general modulator also needs to receive the local oscillator signal from the voltage-controlled oscillator, and its circuit completely works in the radio frequency band.
  • the differential circuit is a circuit with the characteristics of "suppressing common mode signals and amplifying differential mode signals".
  • the input of the circuit is the input of two signals
  • the difference between the two signals is the effective input signal of the circuit
  • the output of the circuit is the amplification of the difference between the two input signals. If there is an interference signal, the same interference will be generated for the two input signals. Through the difference between the two, the effective input of the interference signal is zero, which achieves the purpose of anti-common mode interference.
  • a differential inductor is to wind two separate inductors together to form four ports.
  • the four ports of the differential inductor can be connected to other components.
  • a differential inductor has a smaller area.
  • FIG. 1 shows a schematic diagram of the launch architecture in a multi-channel chip.
  • each channel transmission structure in the multi-channel chip includes two input signals, namely, in-phase (I) and quadrature (Q).
  • one path may include a digital to analog converter (DAC) 101, a filter 102, and a modulator 103; the other path may include a DAC 101', a filter 102', and a modulator.
  • the transmission architecture may also include an oscillator 105 and an amplifier 104.
  • the following uses the same phase one as an example to introduce each component.
  • the DAC 101 converts a digital signal into an analog signal.
  • the analog signal can be a differential signal, so the DAC divides the analog signal into two paths (differential circuit) and sends the analog signal to the low-pass filter 102.
  • the filter 102 can allow the analog signal to be lower than the cutoff The signal of the frequency is passed, and the signal higher than the cutoff frequency is filtered out.
  • the modulator 103 mixes the output signal of the filter 102 and the local oscillator LO signal output by the oscillator 105 to obtain a mixed signal, and the modulator 103 realizes the conversion of the input differential signal into a mixed signal.
  • the mixed radio frequency signal enters the amplifier 104, and the amplifier 104 can amplify the mixed signal.
  • the filter 102 may be a passive filter.
  • the passive filter is generally composed of an inductor and a capacitor.
  • the passive filter In order to better suppress out-of-band noise and burrs generated by the pre-DAC, the passive filter generally uses multiple inductors and multiple capacitors. A capacitor to achieve multi-stage filtering.
  • the filter 102 may be composed of a differential circuit.
  • the differential circuit has two input terminals, for example, the input terminal 1 and the input terminal 2 shown in FIG. 2. One of the two input terminals is a positive input.
  • the other input terminal is a negative input terminal, and the input signals of the two input terminals may be the first signal to be processed and the second signal to be processed, respectively.
  • the filter 102 may be a fifth-order passive filter, that is, each path in the differential circuit of the fifth-order passive filter may include two inductors and three capacitors. As shown in Figure 2, the two inductors in one path of the differential circuit are L1 122 and L2 124, and the three capacitors are 121, 123, and 125. The two inductors in the other path of the differential circuit are L1', L2. ', the three capacitors are 121', 123', and 125' respectively. The signal to be processed is filtered by the passive filter 102.
  • the filter circuit 300 may include two differential circuits, namely a first differential circuit 310 and a second differential circuit 320. Each differential circuit may be as shown in FIG.
  • the internal circuit diagram of the filter 120 wherein, the first differential circuit 310 and the second differential circuit 320 can be two differential circuits in parallel in a single channel, or the first differential circuit 310 and the second differential circuit 320 can also be two differential circuits in parallel in multiple channels.
  • the filter shown in the filter circuit 300 may be a third-order passive filter, that is, each path in each differential circuit in the filter circuit 300 may include an inductor and two capacitors.
  • the first differential circuit includes 4 ports, namely the input terminal 1, the input terminal of the first differential circuit 2, the output terminal 5 of the first differential circuit, and the output terminal 6 of the first differential circuit.
  • the first differential circuit includes a first differential inductor 110, a capacitor C1, a capacitor C2, a capacitor C1', and a capacitor C2'.
  • the first differential inductor 110 may include 4 ports, namely port 1', port 2', port 5'and Port 6'.
  • the second differential circuit includes 4 ports, namely the input terminal 3 of the second differential circuit, the input terminal 4 of the second differential circuit, the output terminal 7 of the second differential circuit, and the output terminal 8 of the second differential circuit.
  • the second differential circuit includes a second differential inductor 120, a capacitor C3, a capacitor C4, a capacitor C3', and a capacitor C4'.
  • the second differential inductor 120 may include 4 ports, namely port 3', port 4', port 7'and port 8'.
  • the sign of the signal input at the input terminal 1 of the first differential circuit is the same as the sign of the signal input at the input terminal 3 of the second differential circuit, the sign of the signal input at the input terminal 2 of the first differential circuit and the input terminal of the second differential circuit 4
  • the sign of the input signal is the same
  • the sign of the signal output from the output terminal 5 of the first differential circuit is the same as the sign of the signal output from the output terminal 7 of the second differential circuit
  • the sign of the signal output from the output terminal 6 of the first differential circuit It has the same sign as the signal output from the output terminal 8 of the second differential circuit.
  • the input terminal 1 of the first differential circuit inputs a positive signal
  • the input terminal 2 of the first differential circuit inputs a negative signal
  • the input terminal 3 of the second differential circuit inputs a positive signal
  • the input terminal of the second differential circuit 4 The input is a negative signal.
  • the filter circuit 400 includes: a first differential circuit 410, a second differential circuit 420, and each differential circuit may be the filter shown in FIG. 120 internal circuit diagram.
  • the first differential circuit 410 and the second differential circuit 420 may be two differential circuits in parallel in a single channel, or the first differential circuit 410 and the second differential circuit 420 may also be two differential circuits in parallel in multiple channels.
  • the filter shown in the filter circuit 400 may be a fifth-order passive filter, that is, each differential circuit in the filter circuit 400 includes two inductors and three capacitors.
  • the first differential circuit includes 4 ports, namely the input terminal 1, the input terminal of the first differential circuit 2, the output terminal 5 of the first differential circuit, and the output terminal 6 of the first differential circuit.
  • the first differential circuit includes a first differential inductor 110, a third differential inductor 130, a capacitor C1, a capacitor C2, a capacitor C5, a capacitor C1', a capacitor C2', and a capacitor C5'.
  • the first differential inductor 110 may include 4 ports, That is, the input terminal 11, the input terminal 12, the output terminal 13 and the output terminal 14.
  • the third differential inductor 130 may include 4 ports, namely the input terminal 31, the input terminal 32, the output terminal 33 and the output terminal 34.
  • one end of the capacitor C1 is grounded, and the other end is connected to the input terminal 1 of the first differential circuit; one end of the capacitor C1' is grounded, and the other end is connected to the input terminal 2 of the first differential circuit; one end of the capacitor C2 Ground, the other end is connected to the output terminal 5 of the first differential circuit, one end of the capacitor C5 is grounded, the other end is connected to the output terminal 13 of the first differential inductor, one end of the capacitor C5' is grounded, and the other end is connected to the output of the first differential inductor
  • the input terminal 11 of the first differential inductor 110 is connected to the input terminal 1 of the first differential circuit, and the input terminal 12 of the first differential inductor 110 is connected to the input terminal 2 of the first differential circuit;
  • the output terminal 13 is connected to the input terminal 31 of the third differential inductor 130, the output terminal 14 of the first differential inductor 110 is connected to the input terminal 32 of the third differential inductor 130; the output terminal 33 of the third differential inductor 130 is connected to
  • the second differential circuit includes 4 ports, namely the input terminal 3 of the second differential circuit, the input terminal 4 of the second differential circuit, the output terminal 7 of the second differential circuit, and the output terminal 8 of the second differential circuit.
  • the second differential circuit includes a second differential inductor 120, a capacitor C3, a capacitor C4, a capacitor C6, a capacitor C3', a capacitor C4', and a capacitor C6'; the second differential inductor 120 may include 4 ports, namely the input terminal 21, the input terminal 22. The output terminal 23 and the output terminal 24.
  • the fourth differential inductor 140 may include 4 ports, namely the input terminal 41, the input terminal 42, the output terminal 43 and the output terminal 44; in the second differential circuit, one end of the capacitor C3 is grounded , The other end is connected to the input terminal 3 of the second differential circuit, one end of the capacitor C3' is grounded, the other end is connected to the input terminal 4 of the second differential circuit, one end of the capacitor C4 is grounded, and the other end is connected to the output terminal of the second differential circuit 7 is connected, one end of the capacitor C4' is grounded, the other end is connected to the output terminal 8 of the second differential circuit, one end of the capacitor C6 is grounded, and the other end is connected to the output terminal 23 of the second differential inductor; one end of the capacitor C6' is grounded, and the other One end is connected to the output terminal 24 of the second differential inductor; the input terminal 21 of the second differential inductor 120 is connected to the input terminal 3 of the second differential circuit, and the input terminal 22 of the second differential inductor 120 is connected to the input terminal
  • the output terminal 23 of the second differential inductor 120 is connected to the input terminal 41 of the fourth differential inductor 140, the output terminal 24 of the second differential inductor 120 is connected to the input terminal 42 of the fourth differential inductor 140, and the fourth differential inductor 140
  • the output terminal 43 is connected to the output terminal 7 of the second differential circuit, and the output terminal 44 of the fourth differential inductor 140 is connected to the output terminal 8 of the second differential circuit.
  • the sign of the signal input at the input terminal 1 of the first differential circuit is the same as the sign of the signal input at the input terminal 3 of the second differential circuit, the sign of the signal input at the input terminal 2 of the first differential circuit and the input terminal of the second differential circuit 4
  • the sign of the input signal is the same
  • the sign of the signal output from the output terminal 5 of the first differential circuit is the same as the sign of the signal output from the output terminal 7 of the second differential circuit
  • the sign of the signal output from the output terminal 6 of the first differential circuit It has the same sign as the signal output from the output terminal 8 of the second differential circuit.
  • the input terminal 1 of the first differential circuit inputs a positive signal
  • the input terminal 2 of the first differential circuit inputs a negative signal
  • the input terminal 3 of the second differential circuit inputs a positive signal
  • the input terminal of the second differential circuit 4 The input is a negative signal.
  • the multi-order filter contains more components, the multi-order filter occupies a larger area.
  • the first differential circuit and the second differential circuit are usually placed next to each other Setting, that is, two parallel differential circuits in a single transmission channel are set up next to each other or two parallel differential circuits between each single transmission channel in a multi-transmission channel are set next to each other.
  • the magnetic field and the magnetic field generated in the differential inductor in the second differential circuit will affect each other, which will cause the isolation of the two adjacent differential inductors in the adjacent IQ channels in the single transmission channel or the isolation of the adjacent two in the multi-channel
  • the isolation of the two adjacent differential inductors in the two adjacent IQ two paths in the channel cannot meet the requirements of the system, so that the image suppression performance required by the system cannot be achieved through algorithm correction.
  • the differential inductor involved in the embodiment of the present application is to wind two common inductors together to form 4 ports, which are connected to different input or output ports of the differential circuit.
  • the shape of the differential inductor may be an octagon, and the shape of the differential inductor may also be a square.
  • the present application does not limit the shape of the differential inductor.
  • FIGS. 5 to 9 The following takes FIGS. 5 to 9 as examples to describe in detail the filter circuit provided by the present application.
  • An embodiment of the present application provides a filter circuit.
  • the filter circuit includes a first differential circuit and a second differential circuit.
  • the first differential circuit includes a first differential inductor
  • the second differential circuit includes a second differential inductor; The direction of the magnetic field lines of the inductor and the second differential inductor are opposite.
  • the distance between the first differential inductor and the second differential inductor is less than or equal to the target distance.
  • the target distance is a preset distance value.
  • the distance between the first differential inductance and the second differential inductance is less than or equal to the target distance, which can be understood as the first differential inductance and the second differential inductance are two differential inductances that are sufficiently arranged adjacently.
  • the first differential inductance and the second differential inductance are sufficiently adjacent to each other, the first differential inductance and the second differential inductance are within the magnetic field range of each other, so that the first differential inductance and the second differential inductance work The generated magnetic fields cancel each other out.
  • the first differential circuit and the second differential circuit may be two differential circuits arranged adjacently in parallel in a single transmission channel (that is, the same transmission channel).
  • the first differential circuit and the second differential circuit may also be two differential circuits arranged adjacently and in parallel among adjacent channels in multiple transmission channels (that is, different transmission channels). It can be understood that the above two differential circuits arranged adjacently in parallel means that no other circuits or components are arranged between the two parallel differential circuits.
  • first differential inductor and the second differential inductor may be two differential inductors whose distance between two differential inductors in the same channel is less than or equal to the target distance.
  • first differential inductor and the second differential inductor may also be two differential inductors whose distance between two differential inductors in adjacent channels is less than or equal to the target distance.
  • the first differential circuit includes a first positive input terminal and a first negative input terminal
  • the second differential circuit includes a second positive input terminal and a second negative input terminal
  • the first differential inductor and the second differential inductor are windings In the same spiral inductor
  • the first differential inductor and the second differential inductor both include the same first input terminal and second input terminal.
  • the first positive input terminal is coupled to the second input terminal of the first differential inductor, and the first negative The input terminal is coupled to the first input terminal of the first differential inductor;
  • the second positive input terminal is coupled to the first input terminal of the second differential inductor, and the second negative input terminal is coupled to the second input terminal of the second differential inductor .
  • the first differential inductor and the second differential inductor are spiral inductors with the same winding method, and the directions of magnetic lines of force when the first differential inductor and the second differential inductor work are opposite.
  • the spiral inductor is formed by winding the differential inductor 110, 120, 130, or 140 as shown in FIG. 3 or FIG. 4.
  • the winding method of the differential inductor is not limited, as long as the first differential inductor and the second differential inductor are two identical spiral inductors.
  • the signal input by the first differential circuit and the signal input by the second differential circuit are orthogonal signals.
  • the signal input by the first differential circuit and the signal input by the second differential circuit are quadrature signals, which can be understood as the phase difference between the signal input by the first differential circuit and the signal input by the second differential circuit by 90°.
  • One of the input signal of the first differential circuit and the input signal of the second differential circuit is the I signal, and the other is the Q signal, that is, the phase of the input signal of one of the first differential circuit and the second differential circuit is 0° or 180°, the phase of the input signal of the other differential circuit is 90° or 270°.
  • the phase of the signal input from the first positive input terminal of the first differential circuit is 0°
  • the phase of the signal input from the first negative input terminal of the first differential circuit is 180°
  • the second positive input terminal of the second differential circuit is 180°
  • the phase of the input signal is 90°
  • the phase of the signal input from the second negative input terminal of the second differential circuit is 270°
  • the phase of the signal input from the first positive input terminal of the first differential circuit is 90°
  • the phase of the signal input from the first negative input terminal of the first differential circuit is 270°
  • the second positive input of the second differential circuit is The phase of the signal input from the terminal is 0°
  • the phase of the signal input from the second negative input terminal of the second differential circuit is 180°.
  • the direction of the signal in the first differential inductor is the first direction; when the signal is input from the second positive input terminal to the second differential circuit, The direction of the signal in the second differential inductor is the second direction, and the second direction is opposite to the first direction.
  • the aforementioned signal may be a current.
  • the first differential circuit further includes a first positive output terminal and a first negative output terminal;
  • the second differential circuit further includes a second positive output terminal and a second negative output terminal;
  • the first differential inductor further includes a first differential inductor The first output terminal of the first differential inductor and the second output terminal of the first differential inductor;
  • the second differential inductor also includes the first output terminal of the second differential inductor and the second output terminal of the second differential inductor; wherein the first output of the first differential inductor An output terminal is coupled to the first negative output terminal, the second output terminal of the first differential inductor is coupled to the first positive output terminal, the first output terminal of the second differential inductor is coupled to the second positive output terminal, the second The second output terminal of the differential inductor is coupled to the second negative output terminal; the connection between the first positive input terminal and the first negative output terminal is parallel to the connection between the first negative input terminal and the first positive output terminal ;
  • the connection between the second positive input terminal and the second negative output terminal is parallel to
  • the first differential circuit in the above filter circuit may further include a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor, wherein one end of the first capacitor is grounded, and the other end is connected to the first capacitor of the first differential circuit.
  • One positive input terminal is connected; one end of the second capacitor is grounded, and the other end is connected to the first negative input terminal; one end of the third capacitor is grounded, the other end is connected to the first negative output terminal, one end of the fourth capacitor is grounded, and the other end is connected to the The first positive output terminal is connected.
  • the second differential circuit in the above filter circuit may further include a fifth capacitor, a sixth capacitor, a seventh capacitor, and an eighth capacitor, wherein one end of the fifth capacitor is grounded, and the other end is connected to the second positive input terminal of the first differential circuit.
  • One end of the sixth capacitor is grounded, and the other end is connected to the second negative input terminal; one end of the seventh capacitor is grounded, the other end is connected to the second negative output terminal, one end of the eighth capacitor is grounded, and the other end is connected to the second positive output End connected.
  • FIG. 5 is a schematic structural diagram of the aforementioned filter circuit 500.
  • the first differential circuit can be 510.
  • the first positive input terminal can be 1, the first negative input terminal can be 2, the first positive output terminal can be 6, and the first negative output terminal can be It can be 5;
  • the first input terminal of the first differential inductor can be 1', the second input terminal of the first differential inductor can be 2', the first output terminal of the first differential inductor can be 5', the first differential inductor
  • the second output terminal can be 6';
  • the first capacitor can be C1, the second capacitor can be C1', the third capacitor can be C2, and the fourth capacitor can be C2';
  • the connection between the output ports 5 is parallel to the connection between the first negative input terminal 2 and the first positive output terminal 6; and one end of the first capacitor C1 is grounded, and the other end is connected to the first positive terminal of the first differential circuit 510
  • the input terminal 1 is connected; one end of the second
  • the fourth capacitor C2' One end is grounded, and the other end is connected to the first positive output terminal 6; the first positive input terminal 1 is connected to the second input terminal 2'of the first differential inductor, and the first negative input terminal 2 is connected to the first input terminal of the first differential inductor 1'is connected, the second output terminal 6'of the first differential inductor is connected to the first positive output terminal 6, and the first output terminal 5'of the first differential inductor is connected to the first negative output terminal 5.
  • the second differential circuit can be 520.
  • the second positive input terminal can be 3, the second negative input terminal can be 4, the second positive output terminal can be 8 and the second negative output terminal can be 7;
  • the first input terminal of the second differential inductor can be 3', the second input terminal of the second differential inductor can be 4', and the first output terminal of the second differential inductor can be 7'and the second differential inductor
  • the second output terminal can be 8'; the connection between the second positive input terminal 3 and the second negative output terminal 7 is parallel to the connection between the second negative input terminal 4 and the second positive output terminal 8; the fifth capacitor One end of C3 is grounded, and the other end is connected to the second positive input terminal 3; one end of the sixth capacitor C3' is grounded, and the other end is connected to the second negative input terminal 4; one end of the seventh capacitor C4 is grounded, and the other end is connected to the second negative electrode
  • the output terminal 7 is connected, one end of the eighth capacitor C4' is grounded, and the other end is connected to the second positive output terminal 8; the second positive input terminal 3 is
  • the flow direction of the current in the first differential inductor and the current in the second differential inductor is On the contrary, according to the right-hand rule, the direction of the magnetic field formed by the first differential inductor and the direction of the magnetic field formed by the second differential inductor are opposite, and the magnetic fields formed by the first differential inductor and the second differential inductor will cancel each other, thereby reducing the first
  • the influence of the differential inductance and the second differential inductance on each other and on the peripheral circuit devices can improve the isolation of the first differential circuit and the second differential circuit, and the isolation can exceed the first threshold. It can be 20 dB, that is, through the technical solution of the present
  • the first differential circuit in the above filter circuit may further include a third differential inductor, a ninth capacitor, and a tenth capacitor
  • the second differential circuit may further include a fourth differential inductor, an eleventh capacitor, and a twelfth capacitor.
  • the third differential inductor and the fourth differential inductor both include the same first input terminal and the second input terminal
  • both the third differential inductor and the fourth differential inductor include the same first output terminal and the same second output terminal.
  • the first differential inductor, the second differential inductor, the third differential inductor, and the fourth differential inductor are spiral inductors with the same winding method.
  • connection between the first positive input terminal and the first negative output port is parallel to the connection between the first negative input terminal and the first positive output terminal;
  • the connection line between the first output terminal and the first input terminal of the third differential inductor is parallel to the connection line between the second output terminal of the first differential inductor and the second input terminal of the third differential inductor;
  • the third differential inductor The connection between the first output terminal and the first negative output terminal is parallel to the connection between the second output terminal and the first positive output terminal of the third differential inductor; one end of the first capacitor is grounded, and the other end is connected to the first The first positive input terminal of a differential circuit is connected; one end of the second capacitor is grounded, the other end is connected to the first negative input terminal, one end of the third capacitor is grounded, the other end is connected to the first negative output terminal, and one end of the fourth capacitor Ground, the other end is connected to the first positive output terminal, one end of the ninth capacitor is grounded, the other end is connected to the first input end of the third differential inductor,
  • connection between the second positive input terminal and the second negative output terminal is parallel to the connection between the second negative input terminal and the second positive output terminal;
  • first output of the second differential inductor The connection line between the terminal and the first input terminal of the fourth differential inductor is parallel to the connection between the second output terminal of the second differential inductor and the second input terminal of the fourth differential inductor;
  • the connection between the output terminal and the first negative output terminal is parallel to the connection between the second output terminal of the fourth differential inductor and the first positive output terminal; one end of the fifth capacitor is grounded, and the other end is connected to the second positive input
  • One end of the sixth capacitor is grounded, the other end is connected to the second negative output terminal, one end of the seventh capacitor is grounded, the other end is connected to the second negative output terminal, one end of the eighth capacitor is grounded, and the other end is connected to the second anode
  • the output end is connected; one end of the eleventh capacitor is grounded, and the other end of the eleventh capacitor is connected to the first input end of the fourth differential inductor
  • the distance between the third differential inductor and the fourth differential inductor is less than or equal to the target distance.
  • the target distance is a preset distance value.
  • the distance between the third differential inductance and the fourth differential inductance is less than or equal to the target distance, which can be understood as the third differential inductance and the fourth differential inductance are two differential inductances that are sufficiently arranged adjacently.
  • the third differential inductance and the fourth differential inductance are sufficiently adjacent to each other, the third differential inductance and the fourth differential inductance are within the magnetic field range of each other, so that the third differential inductance and the fourth differential inductance work The generated magnetic fields cancel each other out.
  • the first differential circuit and the second differential circuit may be two differential circuits arranged adjacently in parallel in a single transmission channel (that is, the same transmission channel).
  • the first differential circuit and the second differential circuit may also be two differential circuits arranged adjacently and in parallel among adjacent channels in multiple transmission channels (that is, different transmission channels). It can be understood that the above two differential circuits arranged adjacently in parallel means that no other circuits or components are arranged between the two parallel differential circuits.
  • the third differential inductor and the fourth differential inductor may be two differential inductors whose distance between the two differential inductors in the same channel is less than or equal to the target distance.
  • the third differential inductor and the fourth differential inductor may also be two differential inductors whose distance between two differential inductors in adjacent channels is less than or equal to the target distance.
  • first differential inductance, the second differential inductance, the third differential inductance, and the fourth differential inductance are spiral inductors with the same winding method, and the directions of magnetic lines of force when the first differential inductance and the second differential inductance work are opposite.
  • the winding method of the differential inductor is not limited, as long as the first differential inductor, the second differential inductor, the third differential inductor, and the fourth differential inductor are the same spiral inductor.
  • the direction of the signal in the first differential inductor is the first direction A
  • the direction of the signal in the third differential inductor is the first direction A
  • the signal direction in the second differential inductor is the second direction B
  • the signal direction in the fourth differential inductor is the first direction A and the second direction B It is opposite to the first direction A.
  • the aforementioned signal may be a current.
  • FIG. 6 is a schematic diagram of another structure of the aforementioned filter circuit 600.
  • the first differential circuit can be 610.
  • the first differential inductance can be 110
  • the third differential inductance can be 130
  • the first positive input terminal can be 1
  • the first negative input terminal can be 2.
  • the first positive output terminal can be 6, the first negative output terminal can be 5; the first input terminal of the first differential inductor can be 11, the second input terminal of the first differential inductor can be 12, the first differential inductor The first output terminal of the first differential inductor can be 13 and the second output terminal of the first differential inductor can be 14, the first input terminal of the third differential inductor can be 31, the second input terminal of the third differential inductor can be 32, the third The first output terminal of the differential inductor can be 33, and the second output terminal of the third differential inductor can be 34; the first capacitor can be C1, the second capacitor can be C1', the third capacitor can be C2, and the fourth capacitor can be C2', the ninth capacitor can be C5, and the tenth capacitor can be C5'; the connection between the first positive input terminal 1 and the first negative output port 5 is parallel to the first negative input terminal 2 and the first positive output The connection between the terminals 6 and the connection between the second output terminal 14 of the first differential inductor and the second input terminal 32 of the
  • a connection between the positive output terminals 6, and one end of the first capacitor C1 is grounded, and the other end is connected to the first positive input terminal 1 of the first differential circuit 610; one end of the second capacitor C1' is grounded, and the other end is connected to the A negative input terminal 2 is connected; one end of the third capacitor C2 is grounded, the other end is connected to the first negative output terminal 5, one end of the fourth capacitor C2' is grounded, and the other end is connected to the first positive output terminal 6; a ninth capacitor C5 One end of the third differential inductor is grounded, the other end is connected to the first input terminal 31 of the third differential inductor, one end of the tenth capacitor C5' is grounded, and the other end is connected to the second input terminal 32 of the third differential circuit; the first positive input terminal 1 is connected to the The second input terminal 12 of the first differential inductor is connected, the first negative input terminal 2 is connected to the first input terminal 11 of the first differential inductor, and the first output terminal 13 of the first differential inductor is connected to the first input
  • the second output terminal 14 of the first differential inductor is connected to the second input terminal 32 of the third differential inductor, and the second output terminal 34 of the third differential inductor is connected to the first positive output terminal 6.
  • the third differential inductor The first output terminal 33 is connected to the first negative output terminal 5.
  • the second differential circuit can be 620.
  • the second differential inductance can be 120
  • the fourth differential inductance can be 140
  • the second positive input terminal can be 3
  • the second negative input terminal can be 4.
  • the second positive output terminal can be 8 and the second negative output terminal can be 7;
  • the first input terminal of the second differential inductor can be 21, the second input terminal of the second differential inductor can be 22, and the second input terminal of the second differential inductor can be 22.
  • One output terminal can be 23 and the second output terminal of the second differential inductor can be 24; the first input terminal of the fourth differential inductor can be 41, the second input terminal of the fourth differential inductor can be 42, and the fourth differential inductor
  • the first output terminal can be 43, the second output terminal of the fourth differential inductor can be 44;
  • the fifth capacitor can be C3, the sixth capacitor can be C3', the seventh capacitor can be C4, and the eighth capacitor can be C4 ', the eleventh capacitor can be C6, the twelfth capacitor can be C6';
  • the connection between the second positive input terminal 3 and the second negative output terminal 7 is parallel to the second negative input terminal 4 and the second positive output
  • the connection between the terminals 8 and the connection between the second output terminal 24 of the second differential inductor and the second input terminal 42 of the fourth differential inductor is parallel to the first output terminal 23 and the fourth output terminal of the second differential inductor.
  • connection between the first input terminal 41 of the differential inductor, and the connection between the first output terminal 43 of the fourth differential inductor and the first negative output terminal 7 are parallel to the second output terminal 44 and the first output terminal of the fourth differential inductor.
  • the connection between the two positive output terminals 8, and one end of the fifth capacitor C3 is grounded, and the other end is connected to the second positive input terminal 3; one end of the sixth capacitor C3' is grounded, and the other end is connected to the second negative input terminal 4
  • One end of the seventh capacitor C4 is grounded, the other end is connected to the second negative output terminal 7, one end of the eighth capacitor C4' is grounded, and the other end is connected to the second positive output terminal 8; one end of the eleventh capacitor C6 is grounded,
  • the other end of the eleventh capacitor C6 is connected to the first input terminal 41 of the fourth differential inductor; one end of the twelfth capacitor C6' is grounded, and the other end of the twelfth capacitor C6' is connected to the second input terminal 42 of the fourth
  • the terminal 8 is connected, and the first output terminal 43 of the fourth differential inductor is connected to the first negative output terminal 7.
  • the direction A of the signal in the first differential inductor 110 and the direction B of the signal in the second differential inductor 120 are opposite.
  • the magnetic fields formed by the first differential inductor 110 and the second differential inductor 120 will cancel each other, thereby reducing the impact of the first differential inductor 110 and the second differential inductor 120 on each other and on peripheral circuit devices, thereby improving the first
  • the isolation between a differential inductor 110 and the second differential inductor 120, and the isolation may exceed a first threshold, the first threshold may be 20dB, that is, through the technical solution of the application, the two differentials in a single channel can be improved.
  • Inductance isolation, or the isolation of two adjacent differential inductances in two adjacent channels in a multi-channel can be improved.
  • Method 2 In the first differential circuit, the connection between the first positive input terminal and the first positive output port is parallel to the connection between the first negative input terminal and the first negative output terminal;
  • the connection line between the first output terminal and the first input terminal of the third differential inductor is parallel to the connection line between the second output terminal of the first differential inductor and the second input terminal of the third differential inductor;
  • the third differential inductor The connection between the first output terminal and the first positive output terminal is parallel to the connection between the second output terminal and the first negative output terminal of the third differential inductor; one end of the first capacitor is grounded, and the other end is connected to the first The first positive input terminal of a differential circuit is connected; one end of the second capacitor is grounded, the other end is connected to the first negative input terminal, one end of the third capacitor is grounded, the other end is connected to the first positive output terminal, and one end of the fourth capacitor Ground, the other end is connected to the first negative output terminal, one end of the ninth capacitor is grounded, the other end is connected to the first input end of the third
  • connection between the second positive input terminal and the second positive output terminal is parallel to the connection between the second negative input terminal and the second negative output terminal;
  • first output of the second differential inductor The connection line between the terminal and the first input terminal of the fourth differential inductor is parallel to the connection between the second output terminal of the second differential inductor and the second input terminal of the fourth differential inductor;
  • the connection between the output terminal and the first negative output terminal is parallel to the connection between the second output terminal of the fourth differential inductor and the first positive output terminal; one end of the fifth capacitor is grounded, and the other end is connected to the second positive input
  • One end of the sixth capacitor is grounded, the other end is connected to the second negative output end, one end of the seventh capacitor is grounded, the other end is connected to the second positive output end, one end of the eighth capacitor is grounded, and the other end is connected to the second negative
  • the output terminal is connected; one end of the eleventh capacitor is grounded, the other end of the eleventh capacitor is connected to the second input end of the fourth differential inductor; one end
  • the distance between the third differential inductor and the fourth differential inductor is less than or equal to the target distance.
  • the target distance is a preset distance value.
  • the distance between the third differential inductance and the fourth differential inductance is less than or equal to the target distance, which can be understood as the third differential inductance and the fourth differential inductance are two differential inductances that are sufficiently arranged adjacently.
  • the third differential inductance and the fourth differential inductance are sufficiently adjacent to each other, the third differential inductance and the fourth differential inductance are within the magnetic field range of each other, so that the third differential inductance and the fourth differential inductance work The generated magnetic fields cancel each other out.
  • the first differential circuit and the second differential circuit may be two differential circuits arranged adjacently in parallel in a single transmission channel (that is, the same transmission channel).
  • the first differential circuit and the second differential circuit may also be two differential circuits arranged adjacently and in parallel among adjacent channels in multiple transmission channels (that is, different transmission channels). It can be understood that the above two differential circuits arranged adjacently in parallel means that no other circuits or components are arranged between the two parallel differential circuits.
  • the third differential inductor and the fourth differential inductor may be two differential inductors whose distance between the two differential inductors in the same channel is less than or equal to the target distance.
  • the third differential inductor and the fourth differential inductor may also be two differential inductors whose distance between two differential inductors in adjacent channels is less than or equal to the target distance.
  • the first differential inductance, the second differential inductance, the third differential inductance, and the fourth differential inductance are spiral inductances with the same winding method, and the direction of the magnetic lines of force when the first differential inductance and the second differential inductance work are opposite.
  • the direction of the magnetic field lines of the inductor and the fourth differential inductor are opposite.
  • the winding method of the differential inductor is not limited, as long as the first differential inductor, the second differential inductor, the third differential inductor, and the fourth differential inductor are the same spiral inductor.
  • the direction of the signal in the first differential inductor is the first direction A
  • the direction of the signal in the third differential inductor is the first direction A
  • the signal direction in the second differential inductor is the second direction B
  • the signal direction in the fourth differential inductor is the first direction B and the second direction B It is opposite to the first direction A.
  • the aforementioned signal may be a current.
  • FIG. 7 is another structural schematic diagram of the aforementioned filter circuit 700.
  • the first differential circuit can be 710.
  • the first differential inductance can be 110
  • the third differential inductance can be 130
  • the first positive input terminal can be 1
  • the first negative input terminal can be 2.
  • the first positive output terminal can be 5, the first negative output terminal can be 6; the first input terminal of the first differential inductor can be 11, the second input terminal of the first differential inductor can be 12, the first differential inductor The first output terminal of the first differential inductor can be 13 and the second output terminal of the first differential inductor can be 14, the first input terminal of the third differential inductor can be 31, the second input terminal of the third differential inductor can be 32, the third The first output terminal of the differential inductor can be 33, and the second output terminal of the third differential inductor can be 34; the first capacitor can be C1, the second capacitor can be C1', the third capacitor can be C2, and the fourth capacitor can be C2', the ninth capacitor can be C5, and the tenth capacitor can be C5'; the connection between the first positive input terminal 1 and the first positive output terminal 5 is parallel to the first negative input terminal 2 and the first negative output The connection between the ports 6, the connection between the first output terminal 13 of the first differential inductor and the first input terminal 31 of the third differential
  • a connection between the negative output terminals 6, and one end of the first capacitor C1 is grounded, and the other end is connected to the first positive input terminal 1; one end of the second capacitor C1' is grounded, and the other end is connected to the first negative input terminal 2 ;
  • One end of the third capacitor C2 is grounded, the other end is connected to the first positive output terminal 5, one end of the fourth capacitor C2' is grounded, and the other end is connected to the first negative output terminal 6;
  • one end of the ninth capacitor C5 is grounded, and the other end Connected to the first input terminal 31 of the third differential inductor, one end of the tenth capacitor C5' is grounded, and the other end is connected to the second input terminal 32 of the third differential circuit;
  • the first positive input terminal 1 is connected to the first input terminal of the first differential inductor.
  • the two input terminals 12 are connected, the first negative input terminal 2 is connected to the first input terminal 11 of the first differential inductor, the first output terminal 13 of the first differential inductor is connected to the first input terminal 31 of the third differential inductor, the first The second output terminal 14 of the differential inductor is connected to the second input terminal 32 of the third differential inductor, the second output terminal 34 of the third differential inductor is connected to the first positive output terminal 5, and the first output terminal 33 of the third differential inductor is connected. Connected to the first negative output terminal 6.
  • the second differential circuit can be 720.
  • the second differential inductance can be 120
  • the fourth differential inductance can be 140
  • the second positive input terminal can be 3
  • the second negative input terminal can be 4.
  • the second positive output terminal can be 7 and the second negative output terminal can be 8; the first input terminal of the second differential inductor can be 21, the second input terminal of the second differential inductor can be 22, and the second input terminal of the second differential inductor can be 22.
  • One output terminal can be 23 and the second output terminal of the second differential inductor can be 24; the first input terminal of the fourth differential inductor can be 41, the second input terminal of the fourth differential inductor can be 42, and the fourth differential inductor
  • the first output terminal can be 43, the second output terminal of the fourth differential inductor can be 44;
  • the fifth capacitor can be C3, the sixth capacitor can be C3', the seventh capacitor can be C4, and the eighth capacitor can be C4 ', the eleventh capacitor can be C6, the twelfth capacitor can be C6';
  • the connection between the second positive input terminal 3 and the second positive output terminal 7 is parallel to the second negative input terminal 4 and the second negative output
  • connection between the second input terminal 42 of the inductor, and the connection between the first output terminal 43 and the second positive output terminal 7 of the fourth differential inductor is parallel to the second output terminal 44 and the second output terminal of the fourth differential inductor.
  • the connection between the negative output terminals 8, and one end of the fifth capacitor C3 is grounded, and the other end is connected to the second positive input terminal 3; one end of the sixth capacitor C3' is grounded, and the other end is connected to the second negative input terminal 4;
  • One end of the seventh capacitor C4 is grounded, the other end is connected to the second positive output terminal 7, one end of the eighth capacitor C4' is grounded, and the other end is connected to the second negative output terminal 8;
  • one end of the eleventh capacitor C6 is grounded, and the tenth
  • the other end of a capacitor C6 is connected to the second input terminal 42 of the fourth differential inductor; one end of the twelfth capacitor C6' is grounded, and the other end of the twelfth capacitor C6' is connected to the first input
  • the output terminal 8 is connected, and the first output terminal 43 of the fourth differential inductor is connected to the second positive output terminal 7.
  • the signal is input to the first differential circuit 710 and the second differential circuit 720, the direction A of the signal in the first differential inductor 110 and the direction B of the signal in the second differential inductor 120 are opposite, and the signal is in the third The direction A in the differential inductor 130 and the direction B of the signal in the fourth differential inductor 140 are opposite.
  • the first differential inductor 110 When the first positive input terminal 1 and the first negative input terminal 2 of the first differential circuit 710, and the second positive input terminal 3 and the second negative input terminal 4 of the second differential circuit 720 input signals respectively, the first differential inductor 110
  • the direction of the current in the second differential inductor 120 is opposite, so that the direction of the magnetic field formed by the first differential inductor 110 and the direction of the magnetic field formed by the second differential inductor 120 are opposite, and the first differential inductor 110 and the second differential inductor 120 have opposite directions.
  • the magnetic fields formed by the inductors 120 cancel each other out, thereby reducing the impact of the first differential inductor 110 and the second differential inductor 120 on each other and on peripheral circuit devices.
  • the third differential inductor 130 and the input and output terminals of the first differential circuit 710, and the connection between the fourth differential inductor 140 and the input and output terminals of the second differential circuit 720 the third The direction of the current in the differential inductor 130 and the current in the fourth differential inductor 140 are opposite, so that the direction of the magnetic field formed by the third differential inductor 130 and the direction of the magnetic field formed by the fourth differential inductor 140 are opposite, and the third differential inductor 130 and The magnetic fields formed by the fourth differential inductor 140 cancel each other, thereby reducing the influence of the third differential inductor 130 and the fourth differential inductor 140 on each other and on peripheral circuit devices.
  • a threshold can be 20dB, that is, through the technical solution of this application, the isolation between two adjacent differential inductors in a single channel can be improved, or the intermediate frequency of two adjacent adjacent differential inductors in two adjacent channels in a multi-channel can be increased Isolation.
  • Mode 3 In the first differential circuit, the connection between the first positive input terminal and the first positive output port is parallel to the connection between the first negative input terminal and the first negative output terminal;
  • the connection line between the first output terminal and the first input terminal of the third differential inductor is parallel to the connection line between the second output terminal of the first differential inductor and the second input terminal of the third differential inductor;
  • the third differential inductor The connection between the first output terminal and the first positive output terminal is parallel to the connection between the second output terminal and the first negative output terminal of the third differential inductor; one end of the first capacitor is grounded, and the other end is connected to the first The first positive input terminal of a differential circuit is connected; one end of the second capacitor is grounded, the other end is connected to the first negative input terminal, one end of the third capacitor is grounded, the other end is connected to the first positive output terminal, and one end of the fourth capacitor Ground, the other end is connected to the first negative output terminal, one end of the ninth capacitor is grounded, the other end is connected to the second input end of the third
  • connection between the second positive input terminal and the second positive output terminal is parallel to the connection between the second negative input terminal and the second negative output terminal;
  • first output of the second differential inductor The connection line between the terminal and the first input terminal of the fourth differential inductor is parallel to the connection between the second output terminal of the second differential inductor and the second input terminal of the fourth differential inductor;
  • the connection between the output terminal and the first positive output terminal is parallel to the connection between the second output terminal and the first negative output terminal of the fourth differential inductor; one end of the fifth capacitor is grounded, and the other end is connected to the second positive input One end of the sixth capacitor is grounded, the other end is connected to the second negative output end, one end of the seventh capacitor is grounded, the other end is connected to the second positive output end, one end of the eighth capacitor is grounded, and the other end is connected to the second negative The output end is connected; one end of the eleventh capacitor is grounded, and the other end of the eleventh capacitor is connected to the first input end of the fourth differential inductor; one end end of the
  • the distance between the third differential inductor and the fourth differential inductor is less than or equal to the target distance.
  • the target distance is a preset distance value.
  • the distance between the third differential inductance and the fourth differential inductance is less than or equal to the target distance, which can be understood as the third differential inductance and the fourth differential inductance are two differential inductances that are sufficiently arranged adjacently.
  • the third differential inductance and the fourth differential inductance are sufficiently adjacent to each other, the third differential inductance and the fourth differential inductance are within the magnetic field range of each other, so that the third differential inductance and the fourth differential inductance work The generated magnetic fields cancel each other out.
  • the first differential circuit and the second differential circuit may be two differential circuits arranged adjacently in parallel in a single transmission channel (that is, the same transmission channel).
  • the first differential circuit and the second differential circuit may also be two differential circuits arranged adjacently and in parallel among adjacent channels in multiple transmission channels (that is, different transmission channels). It can be understood that the above two differential circuits arranged adjacently in parallel means that no other circuits or components are arranged between the two parallel differential circuits.
  • the third differential inductor and the fourth differential inductor may be two differential inductors whose distance between the two differential inductors in the same channel is less than or equal to the target distance.
  • the third differential inductor and the fourth differential inductor may also be two differential inductors whose distance between two differential inductors in adjacent channels is less than or equal to the target distance.
  • the first differential inductance, the second differential inductance, the third differential inductance, and the fourth differential inductance are spiral inductances with the same winding method, and the direction of the magnetic lines of force when the first differential inductance and the second differential inductance work are opposite.
  • the direction of the magnetic field lines of the inductor and the fourth differential inductor are opposite.
  • the winding method of the differential inductor is not limited, as long as the first differential inductor, the second differential inductor, the third differential inductor, and the fourth differential inductor are the same spiral inductor.
  • the direction of the signal in the first differential inductor is the first direction A
  • the direction of the signal in the third differential inductor is the first direction B
  • the signal direction in the second differential inductor is the second direction B
  • the signal direction in the fourth differential inductor is the first direction A and the second direction B It is opposite to the first direction A.
  • the aforementioned signal may be a current.
  • FIG. 8 is a schematic diagram of another structure of the filter circuit 800 described above.
  • the first differential circuit can be 810.
  • the first differential inductance can be 110
  • the third differential inductance can be 130
  • the first positive input terminal can be 1
  • the first negative input terminal can be 2.
  • the first positive output terminal can be 5, the first negative output terminal can be 6; the first input terminal of the first differential inductor can be 11, the second input terminal of the first differential inductor can be 12, the first differential inductor The first output terminal of the first differential inductor can be 13 and the second output terminal of the first differential inductor can be 14, the first input terminal of the third differential inductor can be 31, the second input terminal of the third differential inductor can be 32, the third The first output terminal of the differential inductor can be 33, and the second output terminal of the third differential inductor can be 34; the first capacitor can be C1, the second capacitor can be C1', the third capacitor can be C2, and the fourth capacitor can be C2', the ninth capacitor can be C5, and the tenth capacitor can be C5'; the connection between the first positive input terminal 1 and the first positive output terminal 5 is parallel to the first negative input terminal 2 and the first negative output The connection between the ports 6, the connection between the first output terminal 13 of the first differential inductor and the first input terminal 31 of the third differential
  • a connection between the negative output terminals 6, and one end of the first capacitor C1 is grounded, and the other end is connected to the first positive input terminal 1; one end of the second capacitor C1' is grounded, and the other end is connected to the first negative input terminal 2 ;
  • One end of the third capacitor C2 is grounded, the other end is connected to the first positive output terminal 5, one end of the fourth capacitor C2' is grounded, and the other end is connected to the first negative output terminal 6;
  • one end of the ninth capacitor C5 is grounded, and the other end Connected to the second input terminal 32 of the third differential inductor, one end of the tenth capacitor C5' is grounded, and the other end is connected to the first input terminal 31 of the third differential circuit;
  • the first positive input terminal 1 is connected to the first input terminal of the first differential inductor.
  • the two input terminals 12 are connected, the first negative input terminal 2 is connected to the first input terminal 11 of the first differential inductor, and the first output terminal 13 of the first differential inductor is connected to the second input terminal 32 of the third differential inductor.
  • the second output terminal 14 of the differential inductor is connected to the first input terminal 31 of the third differential inductor, the second output terminal 34 of the third differential inductor is connected to the first negative output terminal 6, and the first output terminal 33 of the third differential inductor is connected. Connected to the first positive output terminal 5.
  • the second differential circuit can be 820. In the second differential circuit 820, the second differential inductance can be 120, the fourth differential inductance can be 140, the second positive input terminal can be 3, and the second negative input terminal can be 4.
  • the second positive output terminal can be 7 and the second negative output terminal can be 8; the first input terminal of the second differential inductor can be 21, the second input terminal of the second differential inductor can be 22, and the second input terminal of the second differential inductor can be 22.
  • One output terminal can be 23 and the second output terminal of the second differential inductor can be 24; the first input terminal of the fourth differential inductor can be 41, the second input terminal of the fourth differential inductor can be 42, and the fourth differential inductor
  • the first output terminal can be 43, the eighth output signal can be 44; the fifth capacitor can be C3, the sixth capacitor can be C3', the seventh capacitor can be C4, the eighth capacitor can be C4', and the eleventh
  • the capacitor can be C6 and the twelfth capacitor can be C6'; the connection between the second positive input terminal 3 and the second positive output terminal 7 is parallel to the connection between the second negative input terminal 4 and the second negative output terminal 8.
  • connection the connection line between the first output terminal 23 of the second differential inductor and the first input terminal 41 of the fourth differential inductor is parallel to the second output terminal 24 of the second differential inductor and the second input of the fourth differential inductor
  • the connection between the terminals 42 and the connection between the first output terminal 43 and the second positive output terminal 7 of the fourth differential inductor is parallel to the second output terminal 44 of the fourth differential inductor and the second negative output terminal 8
  • One end of the fifth capacitor C3 is grounded, and the other end is connected to the second positive input terminal 3; one end of the sixth capacitor C3' is grounded, and the other end is connected to the second negative input terminal 4; One end is grounded, the other end is connected to the second positive output terminal 7, one end of the eighth capacitor C4' is grounded, and the other end is connected to the second negative output terminal 8; one end of the eleventh capacitor C6 is grounded, and the other end of the eleventh capacitor C6 One end is connected to the first input terminal 41 of the fourth differential inductor; one end of the twel
  • the second input terminal 42 is connected, the second output terminal 24 of the second differential inductor is connected to the first input terminal 41 of the fourth differential inductor, and the second output terminal 44 of the fourth differential inductor is connected to the second positive output terminal 7.
  • the first output terminal 43 of the four-differential inductor is connected to the second negative output terminal 8.
  • the first differential inductor 110 Through the connection between the first differential inductor 110 and the input and output terminals of the first differential circuit 810 as shown in FIG. 8, and the connection between the second differential inductor 120 and the input and output terminals of the second differential circuit 820, when When the first positive input terminal 1 and the first negative input terminal 2 of the first differential circuit 810, and the second positive input terminal 3 and the second negative input terminal 4 of the second differential circuit 820 input signals respectively, the first differential inductor 110
  • the direction of the current in the second differential inductor 120 is opposite, so that the direction of the magnetic field formed by the first differential inductor 110 and the direction of the magnetic field formed by the second differential inductor 120 are opposite, and the first differential inductor 110 and the second differential inductor 120 have opposite directions.
  • the magnetic fields formed by the inductors 120 cancel each other out, thereby reducing the impact of the first differential inductor 110 and the second differential inductor 120 on each other and on peripheral circuit devices.
  • the third differential inductor 130 and the input and output terminals of the first differential circuit 810 in the foregoing implementation manner, and the connection between the fourth differential inductor 140 and the input and output terminals of the second differential circuit 820, when the first When the first positive input terminal 1 and the first negative input terminal 2 of a differential circuit 810, and the second positive input terminal 3 and the second negative input terminal 4 of the second differential circuit 820 input signals respectively, the third differential inductor 130
  • the direction of the current in the fourth differential inductor 140 is opposite, so that the direction of the magnetic field formed by the third differential inductor 130 and the direction of the magnetic field formed by the fourth differential inductor 140 are opposite, and the third differential inductor 130 and the fourth differential inductor 140
  • the magnetic fields formed by 140 will cancel each other, thereby reducing the influence of the third
  • a threshold may be 20dB, that is, through the technical solution of the present application, the isolation of two differential inductors in a single channel can be improved, or the isolation of two adjacent differential inductors in two adjacent channels in a multi-channel can be improved.
  • the filter circuit includes a first differential circuit and a second differential circuit.
  • the first differential circuit includes a fifth differential inductor and a seventh differential inductor
  • the second differential circuit includes a sixth differential inductor.
  • the eighth differential inductor is opposite to each other.
  • the distance between the fifth differential inductor and the sixth differential inductor is less than or equal to the target distance, and the distance between the seventh differential inductor and the eighth differential inductor is less than or equal to the target distance.
  • the target distance is a preset distance value.
  • the distance between the fifth differential inductance and the sixth differential inductance is less than or equal to the target distance, which can be understood as the fifth differential inductance and the sixth differential inductance are two differential inductances that are sufficiently arranged adjacently.
  • the distance between the seventh differential inductance and the eighth differential inductance is less than or equal to the target distance, and it can be understood that the seventh differential inductance and the eighth differential inductance are two differential inductances that are sufficiently adjacent to each other.
  • the seventh differential inductor and the eighth differential inductor are sufficiently adjacent to each other, the seventh differential inductor and the eighth differential inductor are within the magnetic field range of each other, so that the seventh differential inductor and the eighth differential inductor work The generated magnetic fields cancel each other out.
  • the first differential circuit and the second differential circuit may be two differential circuits arranged adjacently in parallel in a single transmission channel (that is, the same transmission channel).
  • the first differential circuit and the second differential circuit may also be two differential circuits arranged adjacently and in parallel among adjacent channels in multiple transmission channels (that is, different transmission channels). It can be understood that the above two differential circuits arranged adjacently in parallel means that no other circuits or components are arranged between the two parallel differential circuits.
  • the fifth differential inductor and the sixth differential inductor may be two differential inductors whose distance between two differential inductors in the same channel is less than or equal to the target distance.
  • the fifth differential inductor and the sixth differential inductor may also be two differential inductors whose distance between two differential inductors in adjacent channels is less than or equal to the target distance.
  • the seventh differential inductor and the eighth differential inductor may be two differential inductors whose distance between two differential inductors in the same channel is less than or equal to the target distance.
  • the seventh differential inductor and the eighth differential inductor may also be two differential inductors whose distance between two differential inductors in adjacent channels is less than or equal to the target distance.
  • the first differential circuit includes a first positive input terminal and a first negative input terminal
  • the second differential circuit includes a second positive input terminal and a second negative input terminal
  • a fifth differential inductor is spiral inductors with the same winding method.
  • the fifth differential inductor, the sixth differential inductor, the seventh differential inductor, and the eighth differential inductor include the same first input terminal and second input terminal.
  • the positive input terminal is coupled to the second input terminal of the fifth differential inductor, the first negative input terminal is coupled to the first input terminal of the fifth differential inductor; the second positive input terminal is coupled to the first input of the sixth differential inductor The second negative input terminal is coupled to the second input terminal of the sixth differential inductor.
  • the winding method of the differential inductor is not limited, as long as the fifth differential inductor, the sixth differential inductor, the seventh differential inductor, and the eighth differential inductor are the same spiral inductors.
  • the signal input by the first differential circuit and the signal input by the second differential circuit are orthogonal signals.
  • the signal input by the first differential circuit and the signal input by the second differential circuit are quadrature signals, which can be understood as the phase difference between the signal input by the first differential circuit and the signal input by the second differential circuit by 90°.
  • One of the input signal of the first differential circuit and the input signal of the second differential circuit is the I signal and the other is the Q signal, that is, the phase of the input signal of one of the first differential circuit and the second differential circuit is 0 ° or 180°, the phase of the input signal of the other differential circuit is 90° or 270°.
  • the phase of the signal input from the first positive input terminal of the first differential circuit is 0°
  • the phase of the signal input from the first negative input terminal of the first differential circuit is 180°
  • the second positive input terminal of the second differential circuit is 180°
  • the phase of the input signal is 90°
  • the phase of the signal input from the second negative input terminal of the second differential circuit is 270°
  • the phase of the signal input from the first positive input terminal of the first differential circuit is 90°
  • the phase of the signal input from the first negative input terminal of the first differential circuit is 270°
  • the second positive input of the second differential circuit is The phase of the signal input from the terminal is 0°
  • the phase of the signal input from the second negative input terminal of the second differential circuit is 180°.
  • the first differential circuit may further include a thirteenth capacitor, a fourteenth capacitor, a fifteenth capacitor, a sixteenth capacitor, a twenty-first capacitor, and a twenty-second capacitor.
  • the second differential circuit also includes a seventeenth capacitor, an eighteenth capacitor, a nineteenth capacitor, a twentieth capacitor, a twenty-third capacitor, and a twenty-fourth capacitor.
  • connection between the first positive input terminal and the first negative output port is parallel to the connection between the first negative input terminal and the first positive output terminal;
  • the fifth differential inductor The connection line between the first output terminal of the fifth differential inductor and the first input terminal of the seventh differential inductor is parallel to the connection line between the second output terminal of the fifth differential inductor and the second input terminal of the seventh differential inductor;
  • the connection between the first output terminal and the first negative output terminal of the inductor is parallel to the connection between the second output terminal and the first positive output terminal of the seventh differential inductor; one end of the thirteenth capacitor is grounded and the other end Connected to the first positive input terminal of the first differential circuit; one end of the fourteenth capacitor is grounded, the other end is connected to the first negative input terminal, one end of the fifteenth capacitor is grounded, and the other end is connected to the first negative output terminal.
  • One end of the sixteen capacitor is grounded, the other end is connected to the first positive output terminal, one end of the twenty-first capacitor is grounded, the other end is connected to the first input end of the seventh differential inductor, one end of the twenty-second capacitor is grounded, and the other One end is connected to the second input terminal of the seventh differential inductor; the first positive input terminal is coupled to the first input terminal of the fifth differential inductor, and the first negative input terminal is coupled to the second input terminal of the fifth differential inductor. , The first output terminal of the fifth differential inductor is coupled to the first input terminal of the seventh differential inductor, and the second output terminal of the fifth differential inductor is coupled to the second input terminal of the seventh differential inductor.
  • the second output terminal is coupled to the first negative output terminal, and the first output terminal of the seventh differential inductor is coupled to the first positive output terminal.
  • the connection between the second positive input terminal and the second negative output terminal is parallel to the connection between the second negative input terminal and the second positive output terminal;
  • the first output of the sixth differential inductor The connection line between the terminal and the first input terminal of the eighth differential inductor is parallel to the connection line between the second output terminal of the sixth differential inductor and the second input terminal of the eighth differential inductor;
  • the connection between the output terminal and the first negative output terminal is parallel to the connection between the second output terminal of the eighth differential inductor and the first positive output terminal; one end of the seventeenth capacitor is grounded, and the other end is connected to the second positive electrode
  • One end of the eighteenth capacitor is grounded, the other end is connected to the second negative output terminal, one end of the nineteenth capacitor is grounded, the other end is connected to the second negative output terminal, one end of the twentieth capacitor is grounded, and the other end Connect to the
  • the direction of the signal in the fifth differential inductor is the first direction B
  • the direction of the signal in the seventh differential inductor is the first direction B
  • the signal direction in the sixth differential inductor is the second direction B
  • the signal direction in the eighth differential inductor is the first direction A and the second direction B It is opposite to the first direction A.
  • the aforementioned signal may be a current.
  • FIG. 9 is a schematic diagram of another structure of the filter circuit 900 described above.
  • the first differential circuit can be 910.
  • the fifth differential inductance can be 110'
  • the seventh differential inductance can be 130'
  • the first positive input terminal can be 1, the first negative input terminal It can be 2, the first positive output terminal can be 6, and the first negative output terminal can be 5
  • the first input terminal of the fifth differential inductor can be 11'
  • the second input terminal of the fifth differential inductor can be 12'
  • the first output terminal of the fifth differential inductor may be 13'
  • the second output terminal of the fifth differential inductor may be 14'
  • the first input terminal of the seventh differential inductor may be 31'
  • the terminal can be 32', the first output terminal of the seventh differential inductor can be 33', the second output terminal of the seventh differential inductor can be 34';
  • the thirteenth capacitor can be C1, the fourteenth capacitor can be C1'
  • the fifteenth capacitor can be
  • connection between the output terminals 5 is parallel to the connection between the second output terminal 34' of the seventh differential inductor and the first positive output terminal 6, and one end of the thirteenth capacitor C1 is grounded, and the other end is connected to the first positive electrode.
  • the input terminal 1 is connected; one end of the fourteenth capacitor C1' is grounded, and the other end is connected to the first negative input terminal 2; one end of the fifteenth capacitor C2 is grounded, and the other end is connected to the first negative output terminal 5.
  • the sixteenth capacitor One end of C2' is grounded, and the other end is connected to the first positive output terminal 6; one end of the twenty-first capacitor C5 is grounded, and the other end is connected to the first input terminal 31' of the seventh differential inductor, and the twenty-second capacitor C5' One end of is grounded, and the other end is connected to the second input terminal 32' of the third differential circuit; the first positive input terminal 1 is connected to the first input terminal 11 of the fifth differential inductor, and the first negative input terminal 2 is connected to the fifth differential inductor
  • the second input terminal 12' of the fifth differential inductor is connected, the first output terminal 13' of the fifth differential inductor is connected to the first input terminal 31' of the seventh differential inductor, and the second output terminal 14' of the fifth differential inductor is connected to the seventh differential inductor.
  • the second input terminal 32' of the seventh differential inductor is connected, the second output terminal 34' of the seventh differential inductor is connected to the first negative output terminal 5, and the first output terminal 33' of the seventh differential inductor is connected to the first positive output terminal 6.
  • the second differential circuit can be 920.
  • the sixth differential inductance can be 120'
  • the eighth differential inductance can be 140'
  • the second positive input terminal can be 3
  • the second negative input terminal can be 4.
  • the second positive output terminal can be 8, and the second negative output terminal can be 7;
  • the first input terminal of the sixth differential inductor can be 21', the second input terminal of the sixth differential inductor can be 22', and the sixth The first output terminal of the differential inductor can be 23', and the second output terminal of the sixth differential inductor can be 24';
  • the first input terminal of the eighth differential inductor can be 41', and the second input terminal of the eighth differential inductor can be Is 42', the first output terminal of the eighth differential inductor can be 43', the eighth output signal can be 44';
  • the seventeenth capacitor can be C3, the eighteenth capacitor can be C3', and the nineteenth capacitor can be C4, the twentieth capacitor can be C4', the twenty-third capacitor can be C6, and the twenty-fourth capacitor can be C6';
  • the connection between the second positive input terminal 3 and the second negative output terminal 7 is parallel to The connection between the second negative input terminal 4 and the second positive output terminal 8, and the connection between the first output
  • the output terminal 24' is connected to the first input terminal 41' of the eighth differential inductor, the second output terminal 44' of the eighth differential inductor is connected to the second positive output terminal 8, and the first output terminal 43' of the eighth differential inductor is connected to The second negative output terminal 7 is connected.
  • the direction B of the signal in the seventh differential inductor 130' is opposite to the direction A of the signal in the eighth differential inductor 140'.
  • the seventh differential inductor 130' With the input and output of the first differential circuit 910 as shown in FIG. 9, and the connection of the eighth differential inductor 140' with the input and output of the second differential circuit 920 ,
  • the seventh differential The direction of the current in the inductor 130' and the current in the eighth differential inductor 140' are opposite, so that the direction of the magnetic field formed by the seventh differential inductor 130' is opposite to the direction of the magnetic field formed by the eighth differential inductor 140', and the seventh differential The magnetic fields formed by the inductor 130' and the eighth differential inductor 140' cancel each other out, thereby reducing the influence of the seventh differential inductor 130' and the eighth differential inductor 140' on each other and on peripheral circuit devices.
  • the isolation between the seventh differential inductor 130' and the eighth differential inductor 140' can be improved, and the isolation can exceed the first threshold.
  • the first threshold can be 20dB. That is, through the technical solution of the present application, the The isolation of two adjacent differential inductors in a single channel, or the isolation of two adjacent differential inductors in two adjacent channels in a multi-channel can be improved.
  • the embodiment of the present application also provides an integrated circuit, which includes the above-mentioned filter circuit, and the filter circuit is as described above, and will not be described in detail here.

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Abstract

一种滤波器电路（500），该滤波器电路（500）包括：第一差分电路（510）和第二差分电路（520），该第一差分电路（510）包括第一差分电感（110），该第二差分电路（520）包括第二差分电感（120）；第一差分电感（110）和所述第二差分电感（120）工作时的磁力线方向相反，进而第一差分电感（110）和第二差分电感（120）形成的磁场会互相抵消，进而减小第一差分电感（110）和第二差分电感（120）对彼此之间的影响以及对周边电路器件的影响，从而可以提高第一差分电感（110）和第二差分电感（120）之间的隔离度。

Description

滤波器电路以及用于发射通道的集成电路 技术领域
本申请涉及电学领域，并且更具体地，涉及一种滤波器电路以及用于发射通道的集成电路。
背景技术
随着第五代移动通信(5th Generation，5G)技术的不断发展，运营商能够提供大带宽、多通道基站芯片来解决大规模多输入多输出的应用需求。在多通道芯片中的发射通道的架构中，滤波器和调制器均采用无源架构来满足低功耗要求，为了提高共模抑制，滤波器电路和调制器电路等均采用差分形式。
由于片上系统中的多阶滤波器电路的面积较大，为了节省芯片的面积，通常会将由输入信号为同相(in-phase，I)的差分电路和输入信号为正交(quadrature，Q)的差分电路组成的单发射通道紧邻设置，多发射通道中将每个发射通道紧邻设置，这样会造成单发射通道中的相邻IQ路的中频隔离度或多通道中相邻通道中相邻IQ路的中频隔离度受限，不能够满足系统的要求，从而无法通过算法校正来实现系统所要求的镜像抑制性能。
发明内容
本申请提供了一种滤波器电路以及用于发射通道的集成电路，可以在芯片面积受限的情况下，能够提高单发射通道中相邻的两个差分电感之间的隔离度或者多发射通道中相邻两个通道中相邻的两个差分电感之间的隔离度。
第一方面，提供了一种滤波器电路，包括第一差分电路和第二差分电路，所述第一差分电路包括第一差分电感，所述第二差分电路包括第二差分电感；所述第一差分电感和所述第二差分电感工作时的磁力线方向相反。
其中，第一差分电路和第二差分电路可以是单发射通道中并行设置的两个差分电路。或者，该第一差分电路和第二差分电路也可以是多发射通道中相邻通道中并行设置的两个差分电路。
通过第一差分电感和第二差分电感工作时的磁力线方向相反，进而第一差分电感和第二差分电感形成的磁场会互相抵消，进而减小第一差分电感和第二差分电感对彼此之间的影响以及对周边电路器件的影响，从而可以提高第一差分电感和第二差分电感之间的隔离度，即可以提高单通道中两个相邻的差分电感之间的隔离度，或者多通道中相邻两个通道中的两个相邻的差分电感之间的隔离度。
结合第一方面，在一种可能的实现方式中，所述第一差分电路包括第一正极输入端和第一负极输入端，所述第二差分电路包括第二正极输入端和第二负极输入端，所述第一差分电感和所述第二差分电感为绕线方式相同的螺旋电感，所述第一差分电感和所述第二差分电感均包括相同的第一输入端和第二输入端，所述第一正极输入端被耦合至所述第一差 分电感的第二输入端，所述第一负极输入端被耦合至所述第一差分电感的第一输入端；所述第二正极输入端被耦合至所述第二差分电感的第一输入端，所述第二负极输入端被耦合至所述第二差分电感的第二输入端。
结合第一方面，在一种可能的实现方式中，所述第一差分电感和所述第二差分电感处于彼此的磁场范围内，以使得所述第一差分电感和所述第二差分电感工作时产生的磁场互相抵消。
第一差分电感和第二差分电感处于彼此的磁场范围内，以使得第一差分电感和第二差分电感工作时产生的磁场互相抵消，进而减小第一差分电感和第二差分电感对彼此之间的影响以及对周边电路器件的影响，从而可以提高第一差分电感和第二差分电感之间的隔离度，即可以提高单通道中两个相邻的差分电感之间的隔离度，或者多通道中相邻两个通道中的两个相邻的差分电感之间的隔离度。
结合第一方面，在一种可能的实现方式中，当所述信号由所述第一正极输入端输入至第一差分电路时，所述信号在所述第一差分电感中的走向为第一方向；当所述信号由所述第二正极输入端输入至第二差分电路时，所述信号在所述第二差分电感中的走向为第二方向，所述第二方向和所述第一方向是相反的。
结合第一方面，在一种可能的实现方式中，所述第一差分电路还包括第一正极输出端和第一负极输出端；所述第二差分电路还包括第二正极输出端和第二负极输出端；所述第一差分电感和所述第二差分电感均包括相同的第一输出端和第二输出端；其中，所述第一差分电感的第一输出端被耦合至所述第一负极输出端，所述第一差分电感的第二输出端被耦合至所述第一正极输出端，所述第二差分电感的第一输出端被耦合至所述第二正极输出端，所述第二差分电感的第二输出端被耦合至所述第二负极输出端；所述第一正极输入端与所述第一负极输出端口之间的连线平行于所述第一负极输入端与所述第一正极输出端之间的连线；所述第二正极输入端与所述第二负极输出端之间的连线平行于所述第二负极输入端与所述第二正极输出端之间的连线。
通过第一差分电感的输出端和第一差分电路的输出端的连接方式，以及第二差分电感的输出端和第二差分电路的输出端的连接方式，从而可以保证第一差分电路的输出信号的方向与第二差分电路的输出信号的方向的一致性。
结合第一方面，在一种可能的实现方式中，所述第一差分电感与所述第二差分电感之间的距离小于或等于目标距离。
结合第一方面，在一种可能的实现方式中，由所述第一差分电路输入的信号和由所述第二差分电路输入的信号为正交信号。
其中，由所述第一差分电路输入的信号和由所述第二差分电路输入的信号为正交信号可以理解为由第一差分电路输入的信号和由第二差分电路输入的信号相位相差90°。
第二方面，提供了一种用于发射通道的集成电路，包括：数字模拟转换器；调制器；滤波器电路，所述滤波器电路包括：第一差分电路和第二差分电路，所述第一差分电路包括第一差分电感，所述第二差分电路包括第二差分电感；所述第一差分电感和所述第二差分电感工作时的磁力线方向相反第一差分电感的第二输入端第二差分电感的第一输入端第二差分电感的第二输入端第一差分电感的第二输入端第二差分电感的第一输入端第二差分电感的第二输入端。
其中，第一差分电路和第二差分电路可以是单发射通道中并行设置的两个差分电路。或者，该第一差分电路和第二差分电路也可以是多发射通道中相邻通道中并行设置的两个差分电路。
上述集成电路中，包括数字模拟转换器、调制器和滤波器电路，该滤波器电路中的第一差分电感和第二差分电感工作时的磁力线方向相反，进而第一差分电感和第二差分电感形成的磁场会互相抵消，进而减小第一差分电感和第二差分电感对彼此之间的影响以及对周边电路器件的影响，从而可以提高第一差分电感和第二差分电感之间的隔离度，即可以提高单通道中两个相邻的差分电感之间的隔离度，或者多通道中相邻两个通道中的两个相邻的差分电感之间的隔离度。
结合第二方面，在一种可能的实现方式中，所述第一差分电路包括第一正极输入端和第一负极输入端，所述第二差分电路包括第二正极输入端和第二负极输入端，所述第一差分电感和所述第二差分电感为绕线方式相同的螺旋电感，所述第一差分电感和所述第二差分电感均包括相同的第一输入端和第二输入端，所述第一正极输入端被耦合至所述第一差分电感的第二输入端，所述第一负极输入端被耦合至所述第一差分电感的第一输入端；所述第二正极输入端被耦合至所述第二差分电感的第一输入端，所述第二负极输入端被耦合至所述第二差分电感的第二输入端。
结合第二方面，在一种可能的实现方式中，所述第一差分电感和所述第二差分电感处于彼此的磁场范围内，以使得所述第一差分电感和所述第二差分电感工作时产生的磁场互相抵消。
结合第二方面，在一种可能的实现方式中，当信号由所述第一正极输入端输入至所述第一差分电路时，所述信号在所述第一差分电感中的走向为第一方向；当所述信号由所述第二正极输入端输入至第二差分电路时，所述信号在所述第二差分电感中的走向为第二方向，所述第二方向和所述第一方向是相反的。
结合第二方面，在一种可能的实现方式中，所述第一差分电路还包括第一正极输出端和第一负极输出端；所述第二差分电路还包括第二正极输出端和第二负极输出端；所述第一差分电感还包括第一差分电感的第一输出端和第一差分电感的第二输出端；所述第二差分电感还包括第二差分电感的第一输出端和第二差分电感的第二输出端；所述第一差分电感和所述第二差分电感均包括相同的第一输出端和第二输出端；其中，所述第一差分电感的第一输出端被耦合至所述第一负极输出端，所述第一差分电感的第二输出端被耦合至所述第一正极输出端，所述第二差分电感的第一输出端被耦合至所述第二正极输出端，所述第二差分电感的第二输出端被耦合至所述第二负极输出端；所述第一正极输入端与所述第一负极输出端口之间的连线平行于所述第一负极输入端与所述第一正极输出端之间的连线；所述第二正极输入端与所述第二负极输出端之间的连线平行于所述第二负极输入端与所述第二正极输出端之间的连线。
通过第一差分电感的输出端和第一差分电路的输出端的连接方式，以及第二差分电感的输出端和第二差分电路的输出端的连接方式，从而可以保证第一差分电路的输出信号的方向与第二差分电路的输出信号的方向的一致性。
结合第二方面，在一种可能的实现方式中，所述第一差分电感与所述第二差分电感之间的距离小于或等于目标距离。
结合第二方面，在一种可能的实现方式中，由所述第一差分电路输入的信号和由所述第二差分电路输入的信号为正交信号。
其中，由所述第一差分电路输入的信号和由所述第二差分电路输入的信号为正交信号可以理解为由第一差分电路输入的信号和由第二差分电路输入的信号相位相差90°。
第三方面，提供了一种芯片系统，包括第一方面以及第一方面任一种可能的实现方式中的滤波器电路。
第四方面，提供了一种芯片系统，包括第二方面以及第二方面任一种可能的实现方式中的用于发射通道的集成电路。
附图说明
图1示出了单通道芯片中的发射架构示意图。
图2示出了单通道芯片中的发射内部电路模块示意图。
图3示出了一种滤波器电路300的结构示意图。
图4示出了另一种滤波器电路400的结构示意图。
图5是本申请实施例提供的一种滤波器电路500的结构示意图。
图6是本申请实施例提供的另一种滤波器电路600的结构示意图。
图7是本申请实施例提供的又一种滤波器电路700的结构示意图。
图8是本申请实施例提供的又一种滤波器电路800的结构示意图。
图9是本申请实施例提供的又一种滤波器电路900的结构示意图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
本申请实施例设计的滤波器电路或集成电路主要设置在单通道或多通道网络设备芯片中。其中，该芯片中的单通道可以是单发射通道，也可以是单接收通道。该芯片中的多通道可以包括N路发射通道和M路接收通道，其中，N>1，M>1。例如，当N＝4，且M＝4时，该芯片中的多通道可以是四路发射通道和四路接收通道；又例如，当N＝8，且M＝8时，该芯片中的多通道可以是八路发射通道和八路接收通道。
本申请实施例中涉及的滤波器电路可以是单通道中的滤波器电路，也可以是多通道中的滤波器电路。本申请实施例设计的多通道中相邻两个通道可以理解为两个通道之间无其他通道设置。
应理解，上述网络设备可以是任意一种具有无线收发功能的设备。该设备包括但不限于：演进型节点B(evolved Node B，eNB)、无线网络控制器(Radio Network Controller，RNC)、节点B(Node B，NB)、基站控制器(Base Station Controller，BSC)、基站收发台(Base Transceiver Station，BTS)、家庭基站(例如，Home evolved NodeB，或Home Node B，HNB)、基带单元(BaseBand Unit，BBU)，无线保真(Wireless Fidelity，WIFI)系统中的接入点(Access Point，AP)、无线中继节点、无线回传节点、传输点(transmission point，TP)或者发送接收点(transmission and reception point，TRP)等，还可以为5G，如，NR，系统中的gNB，或，传输点(TRP或TP)，5G系统中的基站的一个或一组(包括多个天线面板)天线面板，或者，还可以为构成gNB或传输点的网络节点，如基带单 元(BBU)，或，分布式单元(distributed unit，DU)等。
在一些部署中，gNB可以包括集中式单元(centralized unit，CU)和DU。gNB还可以包括有源天线单元(active antenna unit，简称AAU)。CU实现gNB的部分功能，DU实现gNB的部分功能。比如，CU负责处理非实时协议和服务，实现无线资源控制(radio resource control，RRC)，分组数据汇聚层协议(packet data convergence protocol，PDCP)层的功能。DU负责处理物理层协议和实时服务，实现无线链路控制(radio link control，RLC)层、媒体接入控制(media access control，MAC)层和物理(physical，PHY)层的功能。AAU实现部分物理层处理功能、射频处理及有源天线的相关功能。由于RRC层的信息最终会变成PHY层的信息，或者，由PHY层的信息转变而来，因而，在这种架构下，高层信令，如RRC层信令，也可以认为是由DU发送的，或者，由DU+AAU发送的。可以理解的是，网络设备可以为包括CU节点、DU节点、AAU节点中一项或多项的设备。此外，可以将CU划分为接入网(radio access network，RAN)中的网络设备，也可以将CU划分为核心网(core network，CN)中的网络设备，本申请对此不做限定。
为便于理解本申请实施例，首先对下文中涉及的几个概念做简单说明。
1、无源元件：电阻类、电感类、电容类元件，它们共同的特点是在电路中无需加电源即可在有信号时工作。
2、电感是闭合回路的一种属性，是一个物理量。当线圈通过电流后，在线圈中形成磁场感应，感应磁场又会产生感应电流来抵制通过线圈中的电流。这种电流与线圈的相互作用关系称为电的感抗。感抗XL的计算公式为：XL＝ωL＝2πfL，其中，ω是角频率，L是线圈电感，f是工作频率。从感抗的计算公式可以看到，随着频率的增大，电感的感抗也不断增大，即电感对高频信号的阻力增大。换言之，电感在高频电路中可起到阻碍高频信号的作用，频率越高阻力就越大。
其中，频率可以分为低频、中频和高频，低频频率一般为30～300kHz，中频频率一般为300～3000kHz，高频频率一般为3～30MHz。
3、调制器是指通过数字信号处理技术，将低频信号调制到高频信号中，进行信号传输的一种设备。调制器一般用于将两路输入信号(例如，正相(I)路输出的待调制信号和正交(Q)路输出的待调制信号)进行调制。调制器的输出信号的频率等于两个输入信号频率之和、差或为两者其他组合的电路。一般调制器还需要接收来自压控振荡器的本振信号，其电路完全工作在射频频段。
4、差分电路是具有“对共模信号抑制，对差模信号放大”特征的电路。该电路的输入端是两个信号的输入，这两个信号的差值，为电路有效输入信号，电路的输出是对两个输入信号之差的放大。如果存在干扰信号，会对两个输入信号产生相同的干扰，通过二者之差，干扰信号的有效输入为零，这就达到了抗共模干扰的目的。
5、一个差分电感是将两个单独的电感绕在一起形成四个端口，该差分电感的四个端口可以与其他元件连接。一个差分电感相比组成一个差分电感的两个单独电感而言，一个差分电感的面积较小。
图1示出了多通道芯片中的发射架构示意图。如图1所示，该多通道芯片中的每个通道发射架构包括两路输入信号，即同相(I)和正交(Q)两路。例如，如图1所示，其中，一路可以分别包括数字模拟转换器(digital to analog converter，DAC)101、滤波器102 和调制器103；另一路可以分别包括DAC101’、滤波器102’和调制器103’；其中，该滤波器102可以是一种带通滤波器，用来允许一定频率范围内的信号通过。在某些场合下，该滤波器102也可以是低通滤波器，用来允许信号中低于截止频率的信号通过。该发射架构还可以包括振荡器105和放大器104。下面以同相一路为例，介绍各个元件。DAC 101将数字信号转换为模拟信号，该模拟信号可以是差分信号，从而DAC分两路(差分电路)将该模拟信号发送至低通滤波器102，滤波器102可以允许模拟信号中低于截止频率的信号通过，过滤掉高于截止频率的信号。调制器103将滤波器102的输出的信号和振荡器105输出的本振LO信号混合得到混频信号，调制器103实现了将输入该差分信号转化为混频信号。该混频射频信号进入放大器104，放大器104可以对该混频信号进行放大。
如图2所示，是单通道芯片中的发射内部电路模块示意图。如图2虚线部分所示，可以是图1中滤波器102的一种可能实现方式。其中，滤波器102可以是无源滤波器，该无源滤波器一般由电感和电容组成，为了更好的抑制带外噪音和前级DAC产生的毛刺，一般无源滤波使用多个电感和多个电容来实现多阶滤波。该滤波器102可以由差分电路组成，该差分电路有两个输入端，例如，图2中所示的输入端①和输入端②，该两个输入端中一个输入端为正极(Positive)输入端，另外一个输入端为负极(negative)输入端，两个输入端的输入的信号可以分别为第一待处理的信号和第二待处理的信号。该滤波器102可以为五阶无源滤波器，即该五阶无源滤波器的差分电路中的每一路中可以包括两个电感和三个电容。如图2所示，差分电路中的一路中两个电感分别是L1 122、L2 124，三个电容分别是121、123、125；差分电路中的另一路中两个电感分别是L1’、L2’，三个电容分别是121’、123’、125’。待处理的信号经过无源滤波器102实现滤波。
如图3所示，是一种滤波器电路300，该滤波器电路300可以包括两个差分电路，即第一差分电路310，第二差分电路320，每个差分电路可以是图2中所示的滤波器120内部的电路图。其中，第一差分电路310和第二差分电路320可以是单通道中并行的两个差分电路，或者，第一差分电路310和第二差分电路320也可以是多通道中并行的两个差分电路。该滤波器电路300所示的滤波器可以是3阶无源滤波器，即该滤波器电路300中每一个差分电路中的每一路可以包括一个电感和两个电容，在一种实现的方式中，为了节省滤波器电路所占用的面积，可以将差分电路中的两路的电感绕在一起形成差分电感，如图3所示的110和120。其中，第一差分电路包括4个端口，即第一差分电路的输入端1、第一差分电路的输入端2、第一差分电路的输出端5和第一差分电路的输出端6。第一差分电路包括第一差分电感110、电容C1、电容C2、电容C1’和电容C2’，该第一差分电感110可以包括4个端口，即端口1’、端口2’、端口5’和端口6’。在第一差分电路中，电容C1的一端接地，另一端与第一差分电路的输入端1相连；电容C1’的一端接地，另一端与第一差分电路的输入端2相连；电容C2的一端接地，另一端与第一差分电路的输出端5相连；电容C2’的一端接地，另一端与第一差分电路的输出端6相连；第一差分电感110的端口1’与第一差分电路的输入端1相连，第一差分电感110的端口2’与第一差分电路的输入端2相连；第一差分电感110的端口5’与第一差分电路的输出端5相连，第一差分电感110的端口6’与第一差分电路的输出端6相连。第二差分电路包括4个端口，即第二差分电路的输入端3、第二差分电路的输入端4、第二差分电路的输出端7和第二差分电路的输出端8。第二差分电路包括第二差分电感120、电容C3、电容C4、电容C3’和电容 C4’，第二差分电感120可以包括4个端口，即端口3’、端口4’、端口7’和端口8’。在第二差分电路中，电容C3的一端接地，另一端与第二差分电路的输入端3相连；电容C3’的一端接地，另一端与第二差分电路的输入端4相连；电容C4的一端接地，另一端与第二差分电路的输出端7相连；电容C4’的一端接地，另一端与第二差分电路的输出端8相连；第二差分电感120的端口3’与第二差分电路的输入端3相连，第二差分电感120的端口4’与第二差分电路的输入端4相连；第二差分电感120的端口7’与第二差分电路的输出端7相连，第二差分电感120的端口8’与第二差分电路的输出端8相连。第一差分电路的输入端1输入的信号的符号和第二差分电路的输入端3输入的信号的符号相同、第一差分电路的输入端2输入的信号的符号和第二差分电路的输入端4输入的信号的符号相同、第一差分电路的输出端5输出的信号的符号和第二差分电路的输出端7输出的信号的符号相同、第一差分电路的输出端6输出的信号的符号和第二差分电路的输出端8输出的信号的符号相同。如果第一差分电路的输入端1输入的是正极信号，第一差分电路的输入端2输入的是负极信号，第二差分电路的输入端3输入的是正极信号，第二差分电路的输入端4输入的是负极信号，当信号分别输入至第一差分电路和第二差分电路时，第二差分电感120中的信号(电流)方向B与第一差分电感110中的信号(电流)方向B相同。
如图4所示，示出了另一种滤波器电路400，该滤波器电路400包括：第一差分电路410，第二差分电路420，每个差分电路可以是图2中所示的滤波器120内部的电路图。其中，第一差分电路410和第二差分电路420可以是单通道中并行的两个差分电路，或者，第一差分电路410和第二差分电路420也可以是多通道中并行的两个差分电路。该滤波器电路400所示的滤波器可以是5阶无源滤波器，即该滤波器电路400中每一个差分电路中包括两个电感和三个电容，同样，在一种实现的方式中，为了节省滤波器电路所占用的面积，可以将差分电路中的两路的电感绕在一起形成差分电感，如图4所示的110、120、130和140。其中，第一差分电路包括4个端口，即第一差分电路的输入端1、第一差分电路的输入端2、第一差分电路的输出端5和第一差分电路的输出端6。第一差分电路包括第一差分电感110、第三差分电感130、电容C1、电容C2、电容C5、电容C1’、电容C2’和电容C5’，该第一差分电感110可以包括4个端口，即输入端11、输入端12、输出端13和输出端14，第三差分电感130可以包括4个端口，即输入端31、输入端32、输出端33和输出端34。在第一差分电路中，电容C1的一端接地，另一端与第一差分电路的输入端1相连；电容C1’的一端接地，另一端与第一差分电路的输入端2相连；电容C2的一端接地，另一端与第一差分电路的输出端5相连，电容C5的一端接地，另一端与第一差分电感的输出端13相连，电容C5’的一端接地，另一端与第一差分电感的输出端14相连；第一差分电感110的输入端11与第一差分电路的输入端1相连，第一差分电感110的输入端12与第一差分电路的输入端2相连；第一差分电感110的输出端13与第三差分电感130的输入端31相连，第一差分电感110的输出端14与第三差分电感130的输入端32相连；第三差分电感130的输出端33与第一差分电路的输出端5相连，第三差分电感130的输出端34与第一差分电路的输出端6相连。第二差分电路包括4个端口，即第二差分电路的输入端3、第二差分电路的输入端4、第二差分电路的输出端7和第二差分电路的输出端8。第二差分电路包括第二差分电感120、电容C3、电容C4、电容C6、电容C3’、电容C4’和电容C6’；第二差分电感120可以包括4个端口，即输入端21、输入端 22、输出端23和输出端24，第四差分电感140可以包括4个端口，即输入端41、输入端42、输出端43和输出端44；在第二差分电路中，电容C3的一端接地，另一端与第二差分电路的输入端3相连，电容C3’的一端接地，另一端与第二差分电路的输入端4相连，电容C4的一端接地，另一端与第二差分电路的输出端7相连，电容C4’的一端接地，另一端与第二差分电路的输出端8相连，电容C6的一端接地，另一端与第二差分电感的输出端23相连；电容C6’的一端接地，另一端与第二差分电感的输出端24相连；第二差分电感120的输入端21与第二差分电路的输入端3相连，第二差分电感120的输入端22与第二差分电路的输入端4相连，第二差分电感120的输出端23与第四差分电感140的输入端41相连，第二差分电感120的输出端24与第四差分电感140的输入端42相连，第四差分电感140的输出端43与第二差分电路的输出端7相连，第四差分电感140的输出端44与第二差分电路的输出端8相连。第一差分电路的输入端1输入的信号的符号和第二差分电路的输入端3输入的信号的符号相同、第一差分电路的输入端2输入的信号的符号和第二差分电路的输入端4输入的信号的符号相同、第一差分电路的输出端5输出的信号的符号和第二差分电路的输出端7输出的信号的符号相同、第一差分电路的输出端6输出的信号的符号和第二差分电路的输出端8输出的信号的符号相同。如果第一差分电路的输入端1输入的是正极信号，第一差分电路的输入端2输入的是负极信号，第二差分电路的输入端3输入的是正极信号，第二差分电路的输入端4输入的是负极信号，当信号分别输入至第一差分电路和第二差分电路时，第二差分电感120中的信号(电流)方向B与第一差分电感110中的信号(电流)方向B相同的，且第三差分电感130中的信号(电流)方向B与第四差分电感140中的信号(电流)方向B是相同的。
由于多阶滤波器中包括的元件较多，因此，多阶滤波器占据的面积较大，为了节省多阶滤波器在芯片上占据的面积，通常会将第一差分电路和第二差分电路紧邻设置，即将单发射通道中并行的两路差分电路紧邻设置或者多发射通道中每个单发射通道之间并行的两路差分电路紧邻设置。但是，如上图3和图4所示，当信号输入至第一差分电路和第二差分电路时，第一差分电路中各个差分电感中的信号(电流)和第二差分电路中各个差分电感的信号(电流)的方向相同，即第一差分电路中的差分电感中产生的磁场方向和第二差分电路中的差分电感中产生的磁场方向相同，则第一差分电路中的差分电感中产生的磁场和第二差分电路中的差分电感中产生的磁场会相互影响，这样会造成单发射通道中相邻的IQ两路中相邻的两个差分电感的隔离度或多通道中相邻两个通道中的两个相邻的IQ两路中相邻的两个差分电感的隔离度不能够满足系统的要求，从而无法通过算法校正来实现系统所要求的镜像抑制性能。
因此，亟需提供一种滤波器电路，在芯片面积受限的情况下，能够提高单发射通道中相邻的IQ中相邻的两个差分电感的隔离度以及多通道中相邻两个通道中的两个相邻的IQ路中相邻的两个差分电感的隔离度。
本申请实施例涉及的差分电感是将两个普通的电感绕在一起，形成4个端口，这4个端口与差分电路的不同的输入或输出端口连接。该差分电感的形状可以是八边形，该差分电感的形状也可以是正方形，本申请对差分电感的形状并不作限定。
下面以图5至图9为例，详细介绍本申请提供的滤波器电路。
本申请实施例提供了一种滤波器电路，该滤波器电路包括第一差分电路和第二差分电 路，第一差分电路包括第一差分电感，第二差分电路包括第二差分电感；第一差分电感和第二差分电感工作时的磁力线方向相反。
可选地，第一差分电感与第二差分电感之间的距离小于或等于目标距离。
其中，该目标距离是预设定的距离值。
其中，第一差分电感与第二差分电感之间的距离小于或等于目标距离可以理解为第一差分电感和第二差分电感是足够相邻设置的两个差分电感。
在第一差分电感和第二差分电感是足够相邻设置的情况下，第一差分电感和第二差分电感处于彼此的磁场范围内，以使得第一差分电感和所述第二差分电感工作时产生的磁场互相抵消。
可选地，第一差分电路和第二差分电路可以是单发射通道(即相同的发射通道)中相邻并行设置的两个差分电路。或者，该第一差分电路和第二差分电路也可以是多发射通道(即不同的发射通道)中相邻通道中相邻并行设置的两个差分电路。可以理解的是，上述相邻并行设置的两个差分电路即为两个并行的差分电路之间无其他电路或元件设置。
可以理解的是，上述第一差分电感和第二差分电感可以是同一通道中的两个差分电感之间的距离小于或等于目标距离的两个差分电感。或者，上述第一差分电感和第二差分电感也可以是相邻通道中两个差分电感的之间的距离小于或等于目标距离的两个差分电感。
可选地，第一差分电路包括第一正极输入端和第一负极输入端，第二差分电路包括第二正极输入端和第二负极输入端，第一差分电感和第二差分电感为绕线方式相同的螺旋电感，第一差分电感和第二差分电感均包括相同的第一输入端和第二输入端，第一正极输入端被耦合至第一差分电感的第二输入端，第一负极输入端被耦合至第一差分电感的第一输入端；第二正极输入端被耦合至第二差分电感的第一输入端，第二负极输入端被耦合至第二差分电感的第二输入端。
其中，第一差分电感和第二差分电感为绕线方式相同的螺旋电感，则第一差分电感和第二差分电感工作时的磁力线方向相反。例如，如图3或图4中所示的差分电感110、120、130或140的缠绕方式形成的螺旋电感。
在本申请实施例中，对差分电感的绕线方式不做限定，只需第一差分电感和第二差分电感是两个一样的螺旋电感即可。
可选地，由第一差分电路输入的信号和由第二差分电路输入的信号为正交信号。
其中，由第一差分电路输入的信号和由第二差分电路输入的信号为正交信号可以理解为由第一差分电路输入的信号和由第二差分电路输入的信号相位相差90°，即第一差分电路的输入信号和第二差分电路的输入信号中一路为I路信号，另一路为Q路信号，也即第一差分电路和第二差分电路中有一条差分电路的输入信号的相位为0°或180°，另一条差分电路的输入信号的相位为90°或270°。例如，第一差分电路的第一正极输入端输入的信号的相位为0°，第一差分电路的第一负极输入端输入的信号的相位为180°，第二差分电路的第二正极输入端输入的信号的相位为90°，第二差分电路的第二负极输入端输入的信号的相位为270°。又例如，第一差分电路的第一正极输入端输入的信号的相位为90°，第一差分电路的第一负极输入端输入的信号的相位为270°，第二差分电路的第二正极输入端输入的信号的相位为0°，第二差分电路的第二负极输入端输入的信号的相位为180°。
可选地，当信号由第一正极输入端输入至第一差分电路时，信号在第一差分电感中的 走向为第一方向；当信号由第二正极输入端输入至第二差分电路时，信号在第二差分电感中的走向为第二方向，第二方向和第一方向是相反的。
可选地，上述信号可以是电流。
可选地，第一差分电路还包括第一正极输出端和第一负极输出端；第二差分电路还包括第二正极输出端和第二负极输出端；第一差分电感还包括第一差分电感的第一输出端和第一差分电感的第二输出端；第二差分电感还包括第二差分电感的第一输出端和第二差分电感的第二输出端；其中，第一差分电感的第一输出端被耦合至第一负极输出端，第一差分电感的第二输出端被耦合至第一正极输出端，第二差分电感的第一输出端被耦合至第二正极输出端，第二差分电感的第二输出端被耦合至第二负极输出端；第一正极输入端与第一负极输出端之间的连线平行于第一负极输入端与第一正极输出端之间的连线；第二正极输入端与第二负极输出端之间的连线平行于第二负极输入端与第二正极输出端之间的连线。
可选地，上述滤波器电路中第一差分电路还可以包括第一电容、第二电容、第三电容和第四电容，其中，第一电容的一端接地，另一端与第一差分电路的第一正极输入端相连；第二电容的一端接地，另一端与第一负极输入端相连；第三电容的一端接地，另一端与第一负极输出端相连，第四电容的一端接地，另一端与第一正极输出端相连。上述滤波器电路中第二差分电路还可以包括第五电容、第六电容、第七电容和第八电容，其中，第五电容的一端接地，另一端与第一差分电路的第二正极输入端相连；第六电容的一端接地，另一端与第二负极输入端相连；第七电容的一端接地，另一端与第二负极输出端相连，第八电容的一端接地，另一端与第二正极输出端相连。
例如，图5是上述滤波器电路500的一种结构示意图。其中，第一差分电路可以是510，在第一差分电路510中，第一正极输入端可以是1、第一负极输入端可以是2、第一正极输出端可以是6、第一负极输出端可以是5；第一差分电感的第一输入端可以是1’、第一差分电感的第二输入端可以是2’、第一差分电感的第一输出端可以是5’、第一差分电感的第二输出端可以是6’；第一电容可以是C1、第二电容可以是C1’、第三电容可以是C2、第四电容可以是C2’；第一正极输入端1与第一负极输出端口5之间的连线平行于第一负极输入端2与第一正极输出端6之间的连线；且第一电容C1的一端接地，另一端与第一差分电路510的第一正极输入端1相连；第二电容C1’的一端接地，另一端与第一负极输入端2相连；第三电容C2的一端接地，另一端与第一负极输出端5相连，第四电容C2’的一端接地，另一端与第一正极输出端6相连；第一正极输入端1与第一差分电感的第二输入端2’相连，第一负极输入端2与第一差分电感的第一输入端1’相连，第一差分电感的第二输出端6’与第一正极输出端6相连，第一差分电感的第一输出端5’与第一负极输出端5相连。第二差分电路可以是520，在第二差分电路520中，第二正极输入端可以是3、第二负极输入端可以是4、第二正极输出端可以是8和第二负极输出端可以是7；第二差分电感的第一输入端可以是3’、第二差分电感的第二输入端可以是4’、第二差分电感的第一输出端可以是7’和第二差分电感的第二输出端可以是8’；第二正极输入端3与第二负极输出端7之间的连线平行于第二负极输入端4与第二正极输出端8之间的连线；第五电容C3的一端接地，另一端与第二正极输入端3相连；第六电容C3’的一端接地，另一端与第二负极输入端4相连；第七电容C4的一端接地，另一端与第二负极输出端7相连， 第八电容C4’的一端接地，另一端与第二正极输出端8相连；第二正极输入端3与第二差分电感的第一输入端3’相连，第二负极输入端4与第二差分电感的第二输入端4’相连；第二差分电感的第一输出端7’与第二正极输出端8相连，第二差分电感的第二输出端8’与第二负极输出端7相连。当信号分别输入至第一差分电路510和第二差分电路520时，信号在第一差分电感110中的方向A与信号在第二差分电感120中的方向B是相反的。
通过上述第一差分电感的各端与第一差分电路的输入端和输出端的连接方式，以及第二差分电感与第二差分电路的输入端和输出端的连接方式，当第一差分电路的第一正极输入端和第一负极输入端，以及第二差分电路的第二正极输入端和第二负极输入端分别输入信号时，第一差分电感中电流和第二差分电感中的电流的流方向是相反的，从而根据右手定则，第一差分电感形成的磁场方向和第二差分电感形成的磁场方向相反，进而第一差分电感和第二差分电感形成的磁场会互相抵消，进而减小第一差分电感和第二差分电感对彼此之间的影响以及对周边电路器件的影响，从而可以提高第一差分电路和第二差分电路隔离度，且该隔离度可以超过第一阈值，该第一阈值可以是20dB，即通过本申请的技术方案，可以提高单通道中两个差分电感隔离度，或者可以提高多通道中相邻两个通道中的两个相邻差分电感隔离度。
可选地，上述滤波器电路中第一差分电路还可以包括第三差分电感、第九电容、第十电容，第二差分电路还包括第四差分电感、第十一电容、第十二电容。其中，第三差分电感和第四差分电感均包括相同的第一输入端和第二输入端，第三差分电感和第四差分电感均包括相同的第一输出端和第二输出端。第一差分电感、第二差分电感、第三差分电感和第四差分电感为绕线方式相同的螺旋电感。
以下，以上述滤波器电路中各元件之间的3种连接方式为例进行详细的描述。
方式1，在第一差分电路中，第一正极输入端与第一负极输出端口之间的连线平行于第一负极输入端与第一正极输出端之间的连线；第一差分电感的第一输出端与第三差分电感的第一输入端之间的连线平行于第一差分电感的第二输出端与第三差分电感的第二输入端之间的连线；第三差分电感的第一输出端与第一负极输出端之间的连线平行于第三差分电感的第二输出端与第一正极输出端之间的连线；第一电容的一端接地，另一端与第一差分电路的第一正极输入端相连；第二电容的一端接地，另一端与第一负极输入端相连，第三电容的一端接地，另一端与第一负极输出端相连，第四电容的一端接地，另一端与第一正极输出端相连，第九电容的一端接地，另一端与第三差分电感的第一输入端相连，第十电容的一端接地，另一端与第三差分电感的第二输入端相连；第一正极输入端被耦合至第一差分电感的第二输入端相连，第一负极输入端被耦合至第一差分电感的第一输入端相连，第一差分电感的第一输出端被耦合至第三差分电感的第一输入端，第一差分电感的第二输出端被耦合至第三差分电感的第二输入端，第三差分电感的第二输出端被耦合至第一正极输出端，第三差分电感的第一输出端被耦合至第一负极输出端。在第二差分电路中，第二正极输入端与第二负极输出端之间的连线平行于第二负极输入端与第二正极输出端之间的连线；第二差分电感的第一输出端与第四差分电感的第一输入端之间的连线平行于第二差分电感的第二输出端与第四差分电感的第二输入端之间的连线；第四差分电感的第一输出端与第一负极输出端之间的连线平行于第四差分电感的第二输出端与第一正极输出端之间的连线；第五电容的一端接地，另一端与第二正极输入端相连；第六电容的一端 接地，另一端与第二负极输出端相连，第七电容的一端接地，另一端与第二负极输出端相连，第八电容的一端接地，另一端与第二正极输出端相连；第十一电容的一端接地，第十一电容的另一端与第四差分电感的第一输入端相连；第十二电容的一端接地，第十二电容的另一端与第四差分电感的第二输入端相连；第二正极输入端被耦合至第二差分电感的第一输入端，第二负极输入端被耦合至第二差分电感的第二输入端；第二差分电感的第一输出端被耦合至第四差分电感的第二输入端，第二差分电感的第二输出端被耦合至第四差分电感的第一输入端，第四差分电感的第一输出端被耦合至第二负极输出端，第四差分电感的第二输出端被耦合至第二正极输出端。
可选地，第三差分电感与第四差分电感之间的距离小于或等于目标距离。
其中，该目标距离是预设定的距离值。
其中，第三差分电感与第四差分电感之间的距离小于或等于目标距离可以理解为第三差分电感和第四差分电感是足够相邻设置的两个差分电感。
在第三差分电感和第四差分电感是足够相邻设置的情况下，第三差分电感和第四差分电感处于彼此的磁场范围内，以使得第三差分电感和所述第四差分电感工作时产生的磁场互相抵消。
可选地，第一差分电路和第二差分电路可以是单发射通道(即相同的发射通道)中相邻并行设置的两个差分电路。或者，该第一差分电路和第二差分电路也可以是多发射通道(即不同的发射通道)中相邻通道中相邻并行设置的两个差分电路。可以理解的是，上述相邻并行设置的两个差分电路即为两个并行的差分电路之间无其他电路或元件设置。
可以理解的是，上述第三差分电感和第四差分电感可以是同一通道中的两个差分电感之间的距离小于或等于目标距离的两个差分电感。或者，上述第三差分电感和第四差分电感也可以是相邻通道中两个差分电感的之间的距离小于或等于目标距离的两个差分电感。
其中，第一差分电感、第二差分电感、第三差分电感和第四差分电感为绕线方式相同的螺旋电感，则第一差分电感和第二差分电感工作时的磁力线方向相反。
在本申请实施例中，对差分电感的绕线方式不做限定，只需第一差分电感、第二差分电感、第三差分电感和第四差分电感是一样的螺旋电感即可。
可选地，当信号由第一正极输入端输入至第一差分电路时，信号在第一差分电感中的走向为第一方向A，信号在第三差分电感中的走向为第一方向A；当信号由第二正极输入端输入至第二差分电路时，信号在第二差分电感中的走向为第二方向B，信号在第四差分电感中的走向为第一方向A，第二方向B和第一方向A是相反的。
可选地，上述信号可以是电流。
例如，图6是上述滤波器电路600的另一种结构示意图。其中，第一差分电路可以是610，在第一差分电路610中，第一差分电感可以是110、第三差分电感可以是130，第一正极输入端可以是1、第一负极输入端可以是2、第一正极输出端可以是6、第一负极输出端可以是5；第一差分电感的第一输入端可以是11、第一差分电感的第二输入端可以是12、第一差分电感的第一输出端可以是13和第一差分电感的第二输出端可以是14，第三差分电感的第一输入端可以是31、第三差分电感的第二输入端可以是32、第三差分电感的第一输出端可以是33、第三差分电感的第二输出端可以是34；第一电容可以是C1、第二电容可以是C1’、第三电容可以是C2、第四电容可以是C2’、第九电容可以是C5、第 十电容可以是C5’；第一正极输入端1与第一负极输出端口5之间的连线平行于第一负极输入端2与第一正极输出端6之间的连线，第一差分电感的第二输出端14与第三差分电感的第二输入端32相连之间的连线平行于第一差分电感的第二输出端13与第三差分电感的第一输入端31之间的连线，第三差分电感的第一输出端33与第一负极输出端5之间的连线平行于第三差分电感的第二输出端34与第一正极输出端6之间的连线，且第一电容C1的一端接地，另一端与第一差分电路610的第一正极输入端1相连；第二电容C1’的一端接地，另一端与第一负极输入端2相连；第三电容C2的一端接地，另一端与第一负极输出端5相连，第四电容C2’的一端接地，另一端与第一正极输出端6相连；第九电容C5的一端接地，另一端与第三差分电感的第一输入端31相连，第十电容C5’的一端接地，另一端与第三差分电路的第二输入端32相连；第一正极输入端1与第一差分电感的第二输入端12相连，第一负极输入端2与第一差分电感的第一输入端11相连，第一差分电感的第一输出端13与第三差分电感的第一输入端31相连，第一差分电感的第二输出端14与第三差分电感的第二输入端32相连，第三差分电感的第二输出端34与第一正极输出端6相连，第三差分电感的第一输出端33与第一负极输出端5相连。第二差分电路可以是620，在第二差分电路620中，第二差分电感可以是120、第四差分电感可以是140，第二正极输入端可以是3、第二负极输入端可以是4、第二正极输出端可以是8和第二负极输出端可以是7；第二差分电感的第一输入端可以是21、第二差分电感的第二输入端可以是22、第二差分电感的第一输出端可以是23和第二差分电感的第二输出端可以是24；第四差分电感的第一输入端可以是41、第四差分电感的第二输入端可以是42、第四差分电感的第一输出端可以是43、第四差分电感的第二输出端可以是44；第五电容可以是C3、第六电容可以是C3’、第七电容可以是C4、第八电容可以是C4’、第十一电容可以是C6、第十二电容可以是C6’；第二正极输入端3与第二负极输出端7之间的连线平行于第二负极输入端4与第二正极输出端8之间的连线，第二差分电感的第二输出端24与第四差分电感的第二输入端42相连之间的连线平行于第二差分电感的第一输出端23与第四差分电感的第一输入端41之间的连线，第四差分电感的第一输出端43与第一负极输出端7之间的连线平行于第四差分电感的第二输出端44与第二正极输出端8之间的连线，且第五电容C3的一端接地，另一端与第二正极输入端3相连；第六电容C3’的一端接地，另一端与第二负极输入端4相连；第七电容C4的一端接地，另一端与第二负极输出端7相连，第八电容C4’的一端接地，另一端与第二正极输出端8相连；第十一电容C6的一端接地，第十一电容C6的另一端与第四差分电感第一输入端41相连；第十二电容C6’的一端接地，第十二电容C6’的另一端与第四差分电感的第二输入端42相连；第二正极输入端3与第二差分电感的第一输入端21相连，第二负极输入端4与第二差分电感的第二输入端22相连，第二差分电感的第一输出端23与第四差分电感的第二输入端42相连，第二差分电感的第二输出端24与第四差分电感的第一输入端41相连，第四差分电感的第二输出端44与第一正极输出端8相连，第四差分电感的第一输出端43与第一负极输出端7相连。当信号分别输入至第一差分电路610和第二差分电路620时，信号在第一差分电感110中的方向A与信号在第二差分电感120中的方向B是相反的。
通过如图6中所示的第一差分电感110的各端与第一差分电路610的输入端和输出端的连接方式，以及第二差分电感120与第二差分电路620的输入端和输出端的连接方式， 当第一差分电路610的第一正极输入端1和第一负极输入端2，以及第二差分电路620的第二正极输入端3和第二负极输入端4分别输入信号时，第一差分电感110中的电流和第二差分电感120中的电流的流方向是相反的，从而根据右手定则，第一差分电感110形成的磁场方向和第二差分电感120形成的磁场方向相反，进而第一差分电感110和第二差分电感120形成的磁场会互相抵消，进而减小第一差分电感110和第二差分电感120对彼此之间的影响以及对周边电路器件的影响，从而可以提高第一差分电感110和第二差分电感120之间的隔离度，且该隔离度可以超过第一阈值，该第一阈值可以是20dB，即通过本申请的技术方案，可以提高单通道中两个差分电感隔离度，或者可以提高多通道中相邻两个通道中的两个相邻差分电感隔离度。
方式2，在第一差分电路中，第一正极输入端与第一正极输出端口之间的连线平行于第一负极输入端与第一负极输出端之间的连线；第一差分电感的第一输出端与第三差分电感的第一输入端之间的连线平行于第一差分电感的第二输出端与第三差分电感的第二输入端之间的连线；第三差分电感的第一输出端与第一正极输出端之间的连线平行于第三差分电感的第二输出端与第一负极输出端之间的连线；第一电容的一端接地，另一端与第一差分电路的第一正极输入端相连；第二电容的一端接地，另一端与第一负极输入端相连，第三电容的一端接地，另一端与第一正极输出端相连，第四电容的一端接地，另一端与第一负极输出端相连，第九电容的一端接地，另一端与第三差分电感的第一输入端相连，第十电容的一端接地，另一端与第三差分电感的第二输入端相连；第一正极输入端被耦合至第一差分电感的第二输入端相连，第一负极输入端被耦合至第一差分电感的第一输入端相连，第一差分电感的第一输出端被耦合至第三差分电感的第一输入端，第一差分电感的第二输出端被耦合至第三差分电感的第二输入端，第三差分电感的第二输出端被耦合至第一正极输出端，第三差分电感的第一输出端被耦合至第一负极输出端。在第二差分电路中，第二正极输入端与第二正极输出端之间的连线平行于第二负极输入端与第二负极输出端之间的连线；第二差分电感的第一输出端与第四差分电感的第一输入端之间的连线平行于第二差分电感的第二输出端与第四差分电感的第二输入端之间的连线；第四差分电感的第一输出端与第一负极输出端之间的连线平行于第四差分电感的第二输出端与第一正极输出端之间的连线；第五电容的一端接地，另一端与第二正极输入端相连；第六电容的一端接地，另一端与第二负极输出端相连，第七电容的一端接地，另一端与第二正极输出端相连，第八电容的一端接地，另一端与第二负极输出端相连；第十一电容的一端接地，第十一电容的另一端与第四差分电感的第二输入端相连；第十二电容的一端接地，第十二电容的另一端与第四差分电感的第一输入端相连；第二正极输入端被耦合至第二差分电感的第一输入端，第二负极输入端被耦合至第二差分电感的第二输入端；第二差分电感的第一输出端被耦合至第四差分电感的第一输入端，第二差分电感的第二输出端被耦合至第四差分电感的第二输入端，第四差分电感的第一输出端被耦合至第二正极输出端，第四差分电感的第二输出端被耦合至第二负极输出端。
可选地，第三差分电感与第四差分电感之间的距离小于或等于目标距离。
其中，该目标距离是预设定的距离值。
其中，第三差分电感与第四差分电感之间的距离小于或等于目标距离可以理解为第三差分电感和第四差分电感是足够相邻设置的两个差分电感。
在第三差分电感和第四差分电感是足够相邻设置的情况下，第三差分电感和第四差分电感处于彼此的磁场范围内，以使得第三差分电感和所述第四差分电感工作时产生的磁场互相抵消。
可选地，第一差分电路和第二差分电路可以是单发射通道(即相同的发射通道)中相邻并行设置的两个差分电路。或者，该第一差分电路和第二差分电路也可以是多发射通道(即不同的发射通道)中相邻通道中相邻并行设置的两个差分电路。可以理解的是，上述相邻并行设置的两个差分电路即为两个并行的差分电路之间无其他电路或元件设置。
可以理解的是，上述第三差分电感和第四差分电感可以是同一通道中的两个差分电感之间的距离小于或等于目标距离的两个差分电感。或者，上述第三差分电感和第四差分电感也可以是相邻通道中两个差分电感的之间的距离小于或等于目标距离的两个差分电感。
其中，第一差分电感、第二差分电感、第三差分电感和第四差分电感为绕线方式相同的螺旋电感，则第一差分电感和第二差分电感工作时的磁力线方向相反，第三差分电感和第四差分电感工作时的磁力线方向相反。
在本申请实施例中，对差分电感的绕线方式不做限定，只需第一差分电感、第二差分电感、第三差分电感和第四差分电感是一样的螺旋电感即可。
可选地，当信号由第一正极输入端输入至第一差分电路时，信号在第一差分电感中的走向为第一方向A，信号在第三差分电感中的走向为第一方向A；当信号由第二正极输入端输入至第二差分电路时，信号在第二差分电感中的走向为第二方向B，信号在第四差分电感中的走向为第一方向B，第二方向B和第一方向A是相反的。
可选地，上述信号可以是电流。
又例如，图7是上述滤波器电路700的又一种结构示意图。其中，第一差分电路可以是710，在第一差分电路710中，第一差分电感可以是110、第三差分电感可以是130，第一正极输入端可以是1、第一负极输入端可以是2、第一正极输出端可以是5、第一负极输出端可以是6；第一差分电感的第一输入端可以是11、第一差分电感的第二输入端可以是12、第一差分电感的第一输出端可以是13和第一差分电感的第二输出端可以是14，第三差分电感的第一输入端可以是31、第三差分电感的第二输入端可以是32、第三差分电感的第一输出端可以是33、第三差分电感的第二输出端可以是34；第一电容可以是C1、第二电容可以是C1’、第三电容可以是C2、第四电容可以是C2’、第九电容可以是C5、第十电容可以是C5’；第一正极输入端1与第一正极输出端5之间的连线平行于第一负极输入端2与第一负极输出端口6之间的连线，第一差分电感的第一输出端13与第三差分电感的第一输入端31相连之间的连线平行于第一差分电感的第二输出端14与第三差分电感的第二输入端32之间的连线，第三差分电感的第一输出端33与第一正极输出端5之间的连线平行于第三差分电感的第二输出端34与第一负极输出端6之间的连线，且第一电容C1的一端接地，另一端与第一正极输入端1相连；第二电容C1’的一端接地，另一端与第一负极输入端2相连；第三电容C2的一端接地，另一端与第一正极输出端5相连，第四电容C2’的一端接地，另一端与第一负极输出端6相连；第九电容C5的一端接地，另一端与第三差分电感的第一输入端31相连，第十电容C5’的一端接地，另一端与第三差分电路的第二输入端32相连；第一正极输入端1与第一差分电感的第二输入端12相连，第一负极输入端2与第一差分电感的第一输入端11相连，第一差分电感的第一输出端13 与第三差分电感的第一输入端31相连，第一差分电感的第二输出端14与第三差分电感的第二输入端32相连，第三差分电感的第二输出端34与第一正极输出端5相连，第三差分电感的第一输出端33与第一负极输出端6相连。第二差分电路可以是720，在第二差分电路720中，第二差分电感可以是120、第四差分电感可以是140，第二正极输入端可以是3、第二负极输入端可以是4、第二正极输出端可以是7、第二负极输出端可以是8；第二差分电感的第一输入端可以是21、第二差分电感的第二输入端可以是22、第二差分电感的第一输出端可以是23和第二差分电感的第二输出端可以是24；第四差分电感的第一输入端可以是41、第四差分电感的第二输入端可以是42、第四差分电感的第一输出端可以是43、第四差分电感的第二输出端可以是44；第五电容可以是C3、第六电容可以是C3’、第七电容可以是C4、第八电容可以是C4’、第十一电容可以是C6、第十二电容可以是C6’；第二正极输入端3与第二正极输出端7之间的连线平行于第二负极输入端4与第二负极输出端8之间的连线，第二差分电感的第一输出端23与第四差分电感的第一输入端41之间的连线平行于第二差分电感的第二输出端24与第四差分电感的第二输入端42之间的连线，第四差分电感的第一输出端43与第二正极输出端7之间的连线平行于第四差分电感的第二输出端44与第二负极输出端8之间的连线，且第五电容C3的一端接地，另一端与第二正极输入端3相连；第六电容C3’的一端接地，另一端与第二负极输入端4相连；第七电容C4的一端接地，另一端与第二正极输出端7相连，第八电容C4’的一端接地，另一端与第二负极输出端8相连；第十一电容C6的一端接地，第十一电容C6的另一端与第四差分电感的第二输入端42相连；第十二电容C6’的一端接地，第十二电容C6’的另一端与第四差分电感的第一输入端41相连；第二正极输入端3与第二差分电感的第一输入端21相连，第二负极输入端4与第二差分电感的第二输入端22相连，第二差分电感的第一输出端23与第十二电容C6’的非接地的一端相连，第二差分电感的第二输出端24与第十一电容C6的非接地的一端相连，第四差分电感的第二输出端44与第二负极输出端8相连，第四差分电感的第一输出端43与第二正极输出端7相连。当信号分别输入至第一差分电路710和第二差分电路720时，信号在第一差分电感110中的方向A与信号在第二差分电感120中的方向B是相反的，且信号在第三差分电感130中的方向A与信号在第四差分电感140中的方向B是相反的。
通过如图7中所示的第一差分电感110与第一差分电路710的输入端和输出端的连接方式，以及第二差分电感120与第二差分电路720的输入端和输出端的连接方式，当第一差分电路710的第一正极输入端1和第一负极输入端2，以及第二差分电路720的第二正极输入端3和第二负极输入端4分别输入信号时，第一差分电感110中的电流和第二差分电感120中的电流的方向是相反的，从而第一差分电感110形成的磁场方向和第二差分电感120形成的磁场方向相反，进而第一差分电感110和第二差分电感120形成的磁场会互相抵消，进而减小第一差分电感110和第二差分电感120对彼此之间的影响以及对周边电路器件的影响。同时，通过上述实现方式中第三差分电感130与第一差分电路710的输入端和输出端的连接方式，以及第四差分电感140与第二差分电路720的输入端和输出端的连接方式，第三差分电感130中的电流和第四差分电感140中的电流的方向是相反的，从而第三差分电感130形成的磁场方向和第四差分电感140形成的磁场方向相反，进而第三差分电感130和第四差分电感140形成的磁场会互相抵消，进而减小第三差分电感130和 第四差分电感140对彼此之间的影响以及对周边电路器件的影响。从而可以提高第一差分电感110和第二差分电路120之间的隔离度，以及第三差分电感130和第四差分电路140之间的隔离度，且该隔离度可以超过第一阈值，该第一阈值可以是20dB，即通过本申请的技术方案，可以提高单通道中两个相邻差分电感隔离度，或者可以提高多通道中相邻两个通道中的两个相邻相邻差分电感中频隔离度。
方式3，在第一差分电路中，第一正极输入端与第一正极输出端口之间的连线平行于第一负极输入端与第一负极输出端之间的连线；第一差分电感的第一输出端与第三差分电感的第一输入端之间的连线平行于第一差分电感的第二输出端与第三差分电感的第二输入端之间的连线；第三差分电感的第一输出端与第一正极输出端之间的连线平行于第三差分电感的第二输出端与第一负极输出端之间的连线；第一电容的一端接地，另一端与第一差分电路的第一正极输入端相连；第二电容的一端接地，另一端与第一负极输入端相连，第三电容的一端接地，另一端与第一正极输出端相连，第四电容的一端接地，另一端与第一负极输出端相连，第九电容的一端接地，另一端与第三差分电感的第二输入端相连，第十电容的一端接地，另一端与第三差分电感的第一输入端相连；第一正极输入端被耦合至第一差分电感的第二输入端相连，第一负极输入端被耦合至第一差分电感的第一输入端相连，第一差分电感的第一输出端被耦合至第三差分电感的第二输入端，第一差分电感的第二输出端被耦合至第三差分电感的第一输入端，第三差分电感的第二输出端被耦合至第一负极输出端，第三差分电感的第一输出端被耦合至第一正极输出端。在第二差分电路中，第二正极输入端与第二正极输出端之间的连线平行于第二负极输入端与第二负极输出端之间的连线；第二差分电感的第一输出端与第四差分电感的第一输入端之间的连线平行于第二差分电感的第二输出端与第四差分电感的第二输入端之间的连线；第四差分电感的第一输出端与第一正极输出端之间的连线平行于第四差分电感的第二输出端与第一负极输出端之间的连线；第五电容的一端接地，另一端与第二正极输入端相连；第六电容的一端接地，另一端与第二负极输出端相连，第七电容的一端接地，另一端与第二正极输出端相连，第八电容的一端接地，另一端与第二负极输出端相连；第十一电容的一端接地，第十一电容的另一端与第四差分电感的第一输入端相连；第十二电容的一端接地，第十二电容的另一端与第四差分电感的第二输入端相连；第二正极输入端被耦合至第二差分电感的第一输入端，第二负极输入端被耦合至第二差分电感的第二输入端；第二差分电感的第一输出端被耦合至第四差分电感的第二输入端，第二差分电感的第二输出端被耦合至第四差分电感的第一输入端，第四差分电感的第一输出端被耦合至第二负极输出端，第四差分电感的第二输出端被耦合至第二正极输出端。
可选地，第三差分电感与第四差分电感之间的距离小于或等于目标距离。
其中，该目标距离是预设定的距离值。
其中，第三差分电感与第四差分电感之间的距离小于或等于目标距离可以理解为第三差分电感和第四差分电感是足够相邻设置的两个差分电感。
在第三差分电感和第四差分电感是足够相邻设置的情况下，第三差分电感和第四差分电感处于彼此的磁场范围内，以使得第三差分电感和所述第四差分电感工作时产生的磁场互相抵消。
可选地，第一差分电路和第二差分电路可以是单发射通道(即相同的发射通道)中相 邻并行设置的两个差分电路。或者，该第一差分电路和第二差分电路也可以是多发射通道(即不同的发射通道)中相邻通道中相邻并行设置的两个差分电路。可以理解的是，上述相邻并行设置的两个差分电路即为两个并行的差分电路之间无其他电路或元件设置。
可以理解的是，上述第三差分电感和第四差分电感可以是同一通道中的两个差分电感之间的距离小于或等于目标距离的两个差分电感。或者，上述第三差分电感和第四差分电感也可以是相邻通道中两个差分电感的之间的距离小于或等于目标距离的两个差分电感。
其中，第一差分电感、第二差分电感、第三差分电感和第四差分电感为绕线方式相同的螺旋电感，则第一差分电感和第二差分电感工作时的磁力线方向相反，第三差分电感和第四差分电感工作时的磁力线方向相反。
在本申请实施例中，对差分电感的绕线方式不做限定，只需第一差分电感、第二差分电感、第三差分电感和第四差分电感是一样的螺旋电感即可。
可选地，当信号由第一正极输入端输入至第一差分电路时，信号在第一差分电感中的走向为第一方向A，信号在第三差分电感中的走向为第一方向B；当信号由第二正极输入端输入至第二差分电路时，信号在第二差分电感中的走向为第二方向B，信号在第四差分电感中的走向为第一方向A，第二方向B和第一方向A是相反的。
可选地，上述信号可以是电流。
又例如，图8是上述滤波器电路800的又一种结构示意图。其中，第一差分电路可以是810，在第一差分电路810中，第一差分电感可以是110、第三差分电感可以是130，第一正极输入端可以是1、第一负极输入端可以是2、第一正极输出端可以是5、第一负极输出端可以是6；第一差分电感的第一输入端可以是11、第一差分电感的第二输入端可以是12、第一差分电感的第一输出端可以是13和第一差分电感的第二输出端可以是14，第三差分电感的第一输入端可以是31、第三差分电感的第二输入端可以是32、第三差分电感的第一输出端可以是33、第三差分电感的第二输出端可以是34；第一电容可以是C1、第二电容可以是C1’、第三电容可以是C2、第四电容可以是C2’、第九电容可以是C5、第十电容可以是C5’；第一正极输入端1与第一正极输出端5之间的连线平行于第一负极输入端2与第一负极输出端口6之间的连线，第一差分电感的第一输出端13与第三差分电感的第一输入端31相连之间的连线平行于第一差分电感的第二输出端14与第三差分电感的第二输入端32之间的连线，第三差分电感的第一输出端33与第一正极输出端5之间的连线平行于第三差分电感的第二输出端34与第一负极输出端6之间的连线，且第一电容C1的一端接地，另一端与第一正极输入端1相连；第二电容C1’的一端接地，另一端与第一负极输入端2相连；第三电容C2的一端接地，另一端与第一正极输出端5相连，第四电容C2’的一端接地，另一端与第一负极输出端6相连；第九电容C5的一端接地，另一端与第三差分电感的第二输入端32相连，第十电容C5’的一端接地，另一端与第三差分电路的第一输入端31相连；第一正极输入端1与第一差分电感的第二输入端12相连，第一负极输入端2与第一差分电感的第一输入端11相连，第一差分电感的第一输出端13与第三差分电感的第二输入端32相连，第一差分电感的第二输出端14与第三差分电感的第一输入端31相连，第三差分电感的第二输出端34与第一负极输出端6相连，第三差分电感的第一输出端33与第一正极输出端5相连。第二差分电路可以是820，在第二差分电路820中，第二差分电感可以是120、第四差分电感可以是140，第二正极输入端可以 是3、第二负极输入端可以是4、第二正极输出端可以是7、第二负极输出端可以是8；第二差分电感的第一输入端可以是21、第二差分电感的第二输入端可以是22、第二差分电感的第一输出端可以是23和第二差分电感的第二输出端可以是24；第四差分电感的第一输入端可以是41、第四差分电感的第二输入端可以是42、第四差分电感的第一输出端可以是43、第八输出信号可以是44；第五电容可以是C3、第六电容可以是C3’、第七电容可以是C4、第八电容可以是C4’、第十一电容可以是C6、第十二电容可以是C6’；第二正极输入端3与第二正极输出端7之间的连线平行于第二负极输入端4与第二负极输出端8之间的连线，第二差分电感的第一输出端23与第四差分电感的第一输入端41之间的连线平行于第二差分电感的第二输出端24与第四差分电感的第二输入端42之间的连线，第四差分电感的第一输出端43与第二正极输出端7之间的连线平行于第四差分电感的第二输出端44与第二负极输出端8之间的连线，且第五电容C3的一端接地，另一端与第二正极输入端3相连；第六电容C3’的一端接地，另一端与第二负极输入端4相连；第七电容C4的一端接地，另一端与第二正极输出端7相连，第八电容C4’的一端接地，另一端与第二负极输出端8相连；第十一电容C6的一端接地，第十一电容C6的另一端与第四差分电感的第一输入端41相连；第十二电容C6’的一端接地，第十二电容C6’的另一端与第四差分电感的第二输入端42相连；第二正极输入端3与第二差分电感的第一输入端21相连，第二负极输入端4与第二差分电感的第二输入端22相连，第二差分电感的第一输出端23与第四差分电感的第二输入端42相连，第二差分电感的第二输出端24与第四差分电感的第一输入端41相连，第四差分电感的第二输出端44与第二正极输出端7相连，第四差分电感的第一输出端43与第二负极输出端8相连。当信号分别输入至第一差分电路810和第二差分电路820时，信号在第一差分电感110中的方向A与信号在第二差分电感120中的方向B是相反的，且信号在第三差分电感130中的方向B与信号在第四差分电感140中的方向A是相反的。
通过如图8中所示的第一差分电感110与第一差分电路810的输入端和输出端的连接方式，以及第二差分电感120与第二差分电路820的输入端和输出端的连接方式，当第一差分电路810的第一正极输入端1和第一负极输入端2，以及第二差分电路820的第二正极输入端3和第二负极输入端4分别输入信号时，第一差分电感110中的电流和第二差分电感120中的电流的方向是相反的，从而第一差分电感110形成的磁场方向和第二差分电感120形成的磁场方向相反，进而第一差分电感110和第二差分电感120形成的磁场会互相抵消，进而减小第一差分电感110和第二差分电感120对彼此之间的影响以及对周边电路器件的影响。同时，通过上述实现方式中第三差分电感130与第一差分电路810的输入端和输出端的连接方式，以及第四差分电感140与第二差分电路820的输入端和输出端的连接方式，当第一差分电路810的第一正极输入端1和第一负极输入端2，以及第二差分电路820的第二正极输入端3和第二负极输入端4分别输入信号时，第三差分电感130中的电流和第四差分电感140中的电流的方向是相反的，从而第三差分电感130形成的磁场方向和第四差分电感140形成的磁场方向相反，进而第三差分电感130和第四差分电感140形成的磁场会互相抵消，进而减小第三差分电感130和第四差分电感140对彼此之间的影响以及对周边电路器件的影响。从而可以提高第一差分电感110和第二差分电路120之间的隔离度，以及第三差分电感130和第四差分电路140之间的隔离度，且该隔离度可 以超过第一阈值，该第一阈值可以是20dB，即通过本申请的技术方案，可以提高单通道中两个差分电感隔离度，或者可以提高多通道中相邻两个通道中的两个相邻差分电感隔离度。
本申请还提供了另一种滤波电路，该滤波器电路包括第一差分电路和第二差分电路，第一差分电路包括第五差分电感和第七差分电感，第二差分电路包括第六差分电感和第八差分电感。其中，第七差分电感和所述第八差分电感工作时的磁力线方向相反。
可选地，第五差分电感与第六差分电感之间的距离小于或等于目标距离，以及第七差分电感与第八差分电感之间的距离小于或等于目标距离。
其中，该目标距离是预设定的距离值。
其中，第五差分电感与第六差分电感之间的距离小于或等于目标距离可以理解为第五差分电感和第六差分电感是足够相邻设置的两个差分电感。第七差分电感与第八差分电感之间的距离小于或等于目标距离可以理解为第七差分电感和第八差分电感是足够相邻设置的两个差分电感。
在第七差分电感和第八差分电感是足够相邻设置的情况下，第七差分电感和第八差分电感处于彼此的磁场范围内，以使得第七差分电感和所述第八差分电感工作时产生的磁场互相抵消。
可选地，第一差分电路和第二差分电路可以是单发射通道(即相同的发射通道)中相邻并行设置的两个差分电路。或者，该第一差分电路和第二差分电路也可以是多发射通道(即不同的发射通道)中相邻通道中相邻并行设置的两个差分电路。可以理解的是，上述相邻并行设置的两个差分电路即为两个并行的差分电路之间无其他电路或元件设置。
可以理解的是，上述第五差分电感和第六差分电感可以是同一通道中的两个差分电感之间的距离小于或等于目标距离的两个差分电感。或者，上述第五差分电感和第六差分电感也可以是相邻通道中两个差分电感的之间的距离小于或等于目标距离的两个差分电感。
可以理解的是，上述第七差分电感和第八差分电感可以是同一通道中的两个差分电感之间的距离小于或等于目标距离的两个差分电感。或者，上述第七差分电感和第八差分电感也可以是相邻通道中两个差分电感的之间的距离小于或等于目标距离的两个差分电感。
可选地，第一差分电路包括第一正极输入端和第一负极输入端，第二差分电路包括第二正极输入端和第二负极输入端，第五差分电感、第六差分电感、第七差分电感和第八差分电感为绕线方式相同的螺旋电感，第五差分电感第六差分电感、第七差分电感和第八差分电感均包括相同的第一输入端和第二输入端，第一正极输入端被耦合至第五差分电感的第二输入端，第一负极输入端被耦合至第五差分电感的第一输入端；第二正极输入端被耦合至第六差分电感的第一输入端，第二负极输入端被耦合至第六差分电感的第二输入端。
在本申请实施例中，对差分电感的绕线方式不做限定，只需第五差分电感、第六差分电感、第七差分电感和第八差分电感是一样的螺旋电感即可。
可选地，由第一差分电路输入的信号和由第二差分电路输入的信号为正交信号。
其中，由第一差分电路输入的信号和由第二差分电路输入的信号为正交信号可以理解为由第一差分电路输入的信号和由第二差分电路输入的信号相位相差90°，即第一差分电路的输入信号和第二差分电路的输入信号中一路为I路信号，另一路为Q路信号，也即第一差分电路和第二差分电路中有一条差分电路输入信号的相位为0°或180°，另一条差分 电路输入信号的相位为90°或270°。例如，第一差分电路的第一正极输入端输入的信号的相位为0°，第一差分电路的第一负极输入端输入的信号的相位为180°，第二差分电路的第二正极输入端输入的信号的相位为90°，第二差分电路的第二负极输入端输入的信号的相位为270°。又例如，第一差分电路的第一正极输入端输入的信号的相位为90°，第一差分电路的第一负极输入端输入的信号的相位为270°，第二差分电路的第二正极输入端输入的信号的相位为0°，第二差分电路的第二负极输入端输入的信号的相位为180°。
可选地，第一差分电路还可以包括第十三电容、第十四电容、第十五电容、第十六电容、第二十一电容和第二十二电容。第二差分电路还包括第十七电容、第十八电容、第十九电容、第二十电容、第二十三电容、第二十四电容。
可选地，在第一差分电路中，第一正极输入端与第一负极输出端口之间的连线平行于第一负极输入端与第一正极输出端之间的连线；第五差分电感的第一输出端与第七差分电感的第一输入端之间的连线平行于第五差分电感的第二输出端与第七差分电感的第二输入端之间的连线；第七差分电感的第一输出端与第一负极输出端之间的连线平行于第七差分电感的第二输出端与第一正极输出端之间的连线；第十三电容的一端接地，另一端与第一差分电路的第一正极输入端相连；第十四电容的一端接地，另一端与第一负极输入端相连，第十五电容的一端接地，另一端与第一负极输出端相连，第十六电容的一端接地，另一端与第一正极输出端相连，第二十一电容的一端接地，另一端与第七差分电感的第一输入端相连，第二十二电容的一端接地，另一端与第七差分电感的第二输入端相连；第一正极输入端被耦合至第五差分电感的第一输入端相连，第一负极输入端被耦合至第五差分电感的第二输入端相连，第五差分电感的第一输出端被耦合至第七差分电感的第一输入端，第五差分电感的第二输出端被耦合至第七差分电感的第二输入端，第七差分电感的第二输出端被耦合至第一负极输出端，第七差分电感的第一输出端被耦合至第一正极输出端。在第二差分电路中，第二正极输入端与第二负极输出端之间的连线平行于第二负极输入端与第二正极输出端之间的连线；第六差分电感的第一输出端与第八差分电感的第一输入端之间的连线平行于第六差分电感的第二输出端与第八差分电感的第二输入端之间的连线；第八差分电感的第一输出端与第一负极输出端之间的连线平行于第八差分电感的第二输出端与第一正极输出端之间的连线；第十七电容的一端接地，另一端与第二正极输入端相连；第十八电容的一端接地，另一端与第二负极输出端相连，第十九电容的一端接地，另一端与第二负极输出端相连，第二十电容的一端接地，另一端与第二正极输出端相连；第二十三电容的一端接地，第二十三电容的另一端与第八差分电感的第二输入端相连；第二十四电容的一端接地，第二十四电容的另一端与第八差分电感的第一输入端相连；第二正极输入端被耦合至第六差分电感的第一输入端，第二负极输入端被耦合至第六差分电感的第二输入端；第六差分电感的第一输出端被耦合至第八差分电感的第二输入端，第六差分电感的第二输出端被耦合至第八差分电感的第一输入端，第八差分电感的第一输出端被耦合至第二负极输出端，第八差分电感的第二输出端被耦合至第二正极输出端。
可选地，当信号由第一正极输入端输入至第一差分电路时，信号在第五差分电感中的走向为第一方向B，信号在第七差分电感中的走向为第一方向B；当信号由第二正极输入端输入至第二差分电路时，信号在第六差分电感中的走向为第二方向B，信号在第八差分电感中的走向为第一方向A，第二方向B和第一方向A是相反的。
可选地，上述信号可以是电流。
例如，图9是上述滤波器电路900的又一种结构示意图。其中，第一差分电路可以是910，在第一差分电路910中，第五差分电感可以是110'、第七差分电感可以是130'，第一正极输入端可以是1、第一负极输入端可以是2、第一正极输出端可以是6、第一负极输出端可以是5；第五差分电感的第一输入端可以是11'、第五差分电感的第二输入端可以是12'、第五差分电感的第一输出端可以是13'、第五差分电感的第二输出端可以是14'，第七差分电感的第一输入端可以是31'、第七差分电感的第二输入端可以是32'、第七差分电感的第一输出端可以是33'、第七差分电感的第二输出端可以是34'；第十三电容可以是C1、第十四电容可以是C1’、第十五电容可以是C2、第十六电容可以是C2’、第二十一电容可以是C5、第二十二电容可以是C5’；第一正极输入端1与第一负极输出端口5之间的连线平行于第一负极输入端2与第一正极输出端6之间的连线，第五差分电感的第一输出端13'与第七差分电感的第一输入端31'之间的连线平行于第五差分电感的第二输出端14'与第七差分电感的第二输入端32'之间的连线，第七差分电感的第一输出端33'与第一负极输出端5之间的连线平行于第七差分电感的第二输出端34'与第一正极输出端6之间的连线，且第十三电容C1的一端接地，另一端与第一正极输入端1相连；第十四电容C1’的一端接地，另一端与第一负极输入端2相连；第十五电容C2的一端接地，另一端与第一负极输出端5相连，第十六电容C2’的一端接地，另一端与第一正极输出端6相连；第二十一电容C5的一端接地，另一端与第七差分电感的第一输入端31'相连，第二十二电容C5’的一端接地，另一端与第三差分电路的第二输入端32'相连；第一正极输入端1与第五差分电感的第一输入端11相连，第一负极输入端2与第五差分电感的第二输入端12'相连，第五差分电感的第一输出端13'与第七差分电感的第一输入端31'相连，第五差分电感的第二输出端14'与第七差分电感的第二输入端32'相连，第七差分电感的第二输出端34'与第一负极输出端5相连，第七差分电感的第一输出端33'与第一正极输出端6相连。第二差分电路可以是920，在第二差分电路920中，第六差分电感可以是120'、第八差分电感可以是140'，第二正极输入端可以是3、第二负极输入端可以是4、第二正极输出端可以是8、第二负极输出端可以是7；第六差分电感的第一输入端可以是21'、第六差分电感的第二输入端可以是22'、第六差分电感的第一输出端可以是23'、第六差分电感的第二输出端可以是24'；第八差分电感的第一输入端可以是41'、第八差分电感的第二输入端可以是42'、第八差分电感的第一输出端可以是43'、第八输出信号可以是44'；第十七电容可以是C3、第十八电容可以是C3’、第十九电容可以是C4、第二十电容可以是C4’、第二十三电容可以是C6、第二十四电容可以是C6’；第二正极输入端3与第二负极输出端7之间的连线平行于第二负极输入端4与第二正极输出端8之间的连线，第六差分电感的第一输出端23'与第八差分电感的第一输入端41'之间的连线平行于第六差分电感的第二输出端24'与第八差分电感的第二输入端42'之间的连线，第八差分电感的第一输出端43'与第二负极输出端7之间的连线平行于第八差分电感的第二输出端44'与第二正极输出端8之间的连线，且第十七电容C3的一端接地，另一端与第二正极输入端3相连；第十八电容C3’的一端接地，另一端与第二负极输入端4相连；第十九电容C4的一端接地，另一端与第二负极输出端7相连，第二十电容C4’的一端接地，另一端与第二正极输出端8相连；第二十三电容C6的一端接地，第二十三电容C6的另一端与第八差分电感的第二输入端42'相连；第二十四 电容C6’的一端接地，第二十四电容C6’的另一端与第八差分电感的第一输入端41'相连；第二正极输入端3与第六差分电感的第一输入端21'相连，第二负极输入端4与第六差分电感的第二输入端22'相连，第六差分电感的第一输出端23'与第八差分电感的第二输入端42'相连，第六差分电感的第二输出端24'与第八差分电感的第一输入端41'相连，第八差分电感的第二输出端44'与第二正极输出端8相连，第八差分电感的第一输出端43'与第二负极输出端7相连。当信号分别输入至第一差分电路910和第二差分电路920时，信号在第七差分电感130'中的方向B与信号在第八差分电感140'中的方向A是相反的。
通过如图9中所示的第七差分电感130'与第一差分电路910的输入端和输出端的连接方式，以及第八差分电感140'与第二差分电路920的输入端和输出端的连接方式，当第一差分电路910的第一正极输入端1和第一负极输入端2，以及第二差分电路920的第二正极输入端3和第二负极输入端4分别输入信号时，第七差分电感130'中的电流和第八差分电感140'中的电流的方向是相反的，从而第七差分电感130'形成的磁场方向和第八差分电感140'形成的磁场方向相反，进而第七差分电感130'和第八差分电感140'形成的磁场会互相抵消，进而减小第七差分电感130'和第八差分电感140'对彼此之间的影响以及对周边电路器件的影响。从而可以提高第七差分电感130'和第八差分电感140'之间的隔离度，且该隔离度可以超过第一阈值，该第一阈值可以是20dB，即通过本申请的技术方案，可以提高单通道中相邻的两个差分电感隔离度，或者可以提高多通道中相邻两个通道中的两个相邻差分电感隔离度。
本申请实施例还提供了一种集成电路，该集成电路包括上述滤波器电路，该滤波器电路如上述所述，这里不再详细赘述。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种滤波器电路，其特征在于，包括第一差分电路和第二差分电路，
    所述第一差分电路包括第一差分电感，所述第二差分电路包括第二差分电感；
    所述第一差分电感和所述第二差分电感工作时的磁力线方向相反。
  2. 根据权利要求1所述的滤波器电路，其特征在于，所述第一差分电路包括第一正极输入端和第一负极输入端，所述第二差分电路包括第二正极输入端和第二负极输入端，
    所述第一差分电感和所述第二差分电感为绕线方式相同的螺旋电感，所述第一差分电感和所述第二差分电感均包括相同的第一输入端和第二输入端，
    所述第一正极输入端被耦合至所述第一差分电感的第二输入端，所述第一负极输入端被耦合至所述第一差分电感的第一输入端；
    所述第二正极输入端被耦合至所述第二差分电感的第一输入端，所述第二负极输入端被耦合至所述第二差分电感的第二输入端。
  3. 根据权利要求1或2所述的滤波器电路，其特征在于，所述第一差分电感和所述第二差分电感处于彼此的磁场范围内，以使得所述第一差分电感和所述第二差分电感工作时产生的磁场互相抵消。
  4. 根据权利要求2所述的滤波器电路，其特征在于，当信号由所述第一正极输入端输入至所述第一差分电路时，所述信号在所述第一差分电感中的走向为第一方向；
    当所述信号由所述第二正极输入端输入至第二差分电路时，所述信号在所述第二差分电感中的走向为第二方向，所述第二方向和所述第一方向是相反的。
  5. 根据权利要求1所述的滤波器电路，其特征在于，所述第一差分电路还包括第一正极输出端和第一负极输出端；
    所述第二差分电路还包括第二正极输出端和第二负极输出端；
    所述第一差分电感和所述第二差分电感均包括相同的第一输出端和第二输出端；
    其中，所述第一差分电感的第一输出端被耦合至所述第一负极输出端，所述第一差分电感的第二输出端被耦合至所述第一正极输出端，所述第二差分电感的第一输出端被耦合至所述第二正极输出端，所述第二差分电感的第二输出端被耦合至所述第二负极输出端；
    所述第一正极输入端与所述第一负极输出端口之间的连线平行于所述第一负极输入端与所述第一正极输出端之间的连线；
    所述第二正极输入端与所述第二负极输出端之间的连线平行于所述第二负极输入端与所述第二正极输出端之间的连线。
  6. 根据权利要求1至5中任一项所述的滤波器电路，其特征在于，所述第一差分电感与所述第二差分电感之间的距离小于或等于目标距离。
  7. 根据权利要求1或2所述的滤波器电路，其特征在于，由所述第一差分电路输入的信号和由所述第二差分电路输入的信号为正交信号。
  8. 一种用于发射通道的集成电路，其特征在于，包括：
    数字模拟转换器；
    调制器；
    滤波器电路，所述滤波器电路包括：第一差分电路和第二差分电路，
    所述第一差分电路包括第一差分电感，所述第二差分电路包括第二差分电感；
    所述第一差分电感和所述第二差分电感工作时的磁力线方向相反。
  9. 根据权利要求8所述的集成电路，其特征在于，所述第一差分电路包括第一正极输入端和第一负极输入端，所述第二差分电路包括第二正极输入端和第二负极输入端，
    所述第一差分电感和所述第二差分电感为绕线方式相同的螺旋电感，所述第一差分电感和所述第二差分电感均包括相同的第一输入端和第二输入端，
    所述第一正极输入端被耦合至所述第一差分电感的第二输入端，所述第一负极输入端被耦合至所述第一差分电感的第一输入端；
    所述第二正极输入端被耦合至所述第二差分电感的第一输入端，所述第二负极输入端被耦合至所述第二差分电感的第二输入端。
  10. 根据权利要求8或9所述的集成电路，其特征在于，所述第一差分电感和所述第二差分电感处于彼此的磁场范围内，以使得所述第一差分电感和所述第二差分电感工作时产生的磁场互相抵消。
  11. 根据权利要求9所述的集成电路，其特征在于，当信号由所述第一正极输入端输入至所述第一差分电路时，所述信号在所述第一差分电感中的走向为第一方向；
    当所述信号由所述第二正极输入端输入至第二差分电路时，所述信号在所述第二差分电感中的走向为第二方向，所述第二方向和所述第一方向是相反的。
  12. 根据权利要求8所述的集成电路，其特征在于，所述第一差分电路还包括第一正极输出端和第一负极输出端；
    所述第二差分电路还包括第二正极输出端和第二负极输出端；
    所述第一差分电感和所述第二差分电感均包括相同的第一输出端和第二输出端；
    其中，所述第一差分电感的第一输出端被耦合至所述第一负极输出端，所述第一差分电感的第二输出端被耦合至所述第一正极输出端，所述第二差分电感的第一输出端被耦合至所述第二正极输出端，所述第二差分电感的第二输出端被耦合至所述第二负极输出端；
    所述第一正极输入端与所述第一负极输出端口之间的连线平行于所述第一负极输入端与所述第一正极输出端之间的连线；
    所述第二正极输入端与所述第二负极输出端之间的连线平行于所述第二负极输入端与所述第二正极输出端之间的连线。
  13. 根据权利要求8至12中任一项所述的集成电路，其特征在于，所述第一差分电感与所述第二差分电感之间的距离小于或等于目标距离。
  14. 根据权利要求8或9所述的集成电路，其特征在于，由所述第一差分电路输入的信号和由所述第二差分电路输入的信号为正交信号。
  15. 一种芯片系统，其特征在于，包括如权利要求1至7中任一项所述的滤波器电路，或者，包括如权利要求8至14中任一项所述的用于发射通道的集成电路。
PCT/CN2019/100161 2019-08-12 2019-08-12 滤波器电路以及用于发射通道的集成电路 WO2021026712A1 (zh)

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