WO2021016939A1

WO2021016939A1 - Imaging device, method for supplying power to imaging device, and related device

Info

Publication number: WO2021016939A1
Application number: PCT/CN2019/098693
Authority: WO
Inventors: 郑健华; 黄婷婷
Original assignee: 华为技术有限公司
Priority date: 2019-07-31
Filing date: 2019-07-31
Publication date: 2021-02-04
Also published as: CN114127936A

Abstract

Provided are an imaging device, a method for supplying power to an imaging device, and a related device. The imaging device comprises a semiconductor substrate, wherein a first well and a second well are provided at two sides of the semiconductor substrate; and a first insulating dielectric layer and a control gate electrode are successively provided on a surface of the first well, and the magnitude of a voltage applied to the control gate electrode has a positive correlation with the number of charges stored in the first well. In environments having different illumination intensities, voltages of different magnitudes can be applied to the control gate electrode, and the greater the voltage applied to the control gate electrode is, the larger the capacity of a capacitor of the first well is, such that the full-well capacity of the imaging device can satisfy different illumination environments.

Description

Imaging device, method for powering imaging device, and related equipment

Technical field

This application relates to the technical field of electronic circuits, and in particular to an imaging device, a method for powering the imaging device, and related equipment.

Background technique

The image sensor is a device that converts photoelectrons into electrical signals. The partial structure of an imaging device provided in the prior art for forming a sensor will be described below in conjunction with FIG. 1.

The imaging device includes a semiconductor substrate 100. N-type impurities are injected into the outer edge of the semiconductor substrate 100 to form a shallow N buried layer 101. The N buried layer 101 and the semiconductor substrate 100 close to the N buried layer 101 form a photodiode ( photodiode (PD) 103, when external incident light irradiates the PD 103, the PD 103 generates photoelectrons corresponding to the incident light, and the photoelectrons can be transferred to the floating diffusion node 104 to generate electrical signals for obtaining corresponding images.

However, as the size of the image sensor continues to shrink, the area of the PD103 of a single imaging device is reduced, so that the reduced area of the N buried layer 101 cannot provide sufficient full well capacity (FWC) for the imaging device. The reduction of the full-well capacity leads to a decrease in the signal-to-noise ratio and sensitivity of the imaging device.

Summary of the invention

The present application provides an imaging device, a method for powering the imaging device, and related equipment, which have a full well capacity matching the light intensity, so that the full well capacity of the imaging device can meet different light intensities.

The first aspect of the embodiments of the present application provides an imaging device, including a semiconductor substrate, a first well and a second well are respectively provided on both sides of the semiconductor substrate by ion implantation doping, the semiconductor substrate and the The second well has a first doping type, and the first well has a second doping type; the surface of the first well is sequentially provided with a first insulating dielectric layer and a control gate electrode, and the control gate electrode is applied The magnitude of the voltage has a positive correlation with the amount of charge stored in the first well.

It can be understood that under different light intensity environments, different voltages can be applied to the control gate electrode, that is, the stronger the light in the light environment where the imaging device is located, the greater the voltage applied to the control gate electrode When a voltage is applied to the control gate electrode, the first well becomes a capacitor for storing charges, and the greater the voltage applied to the control gate electrode, the greater the capacitance of the first well That is, the magnitude of the voltage applied to the control gate electrode and the amount of charge that can be stored in the first well are in a positive correlation. It can be seen that when the light intensity is relatively high, a high voltage can be applied to the control gate electrode, so that the first well can hold more charges, which improves the full well capacity of the imaging device; when the light intensity is relatively weak, the control gate can be A weak voltage is applied to the electrodes, so that the full well capacity of the first well can meet the demand under low light and avoid waste of power consumption.

Based on the first aspect of the embodiments of the present application, in an optional implementation of the first aspect of the embodiments of the present application, a second insulating dielectric layer is provided on the surface of the control gate electrode facing the semiconductor substrate, and the first An accommodating cavity is formed between an insulating dielectric layer and the second insulating dielectric layer, and a floating gate for storing electric charges is arranged in the accommodating cavity.

It can be understood that in the imaging device, a floating gate for storing charges is added, thereby increasing the full well capacity of the imaging device and increasing the amount of charge that the imaging device can store.

Based on the first aspect of the embodiments of the present application, in an optional implementation manner of the first aspect of the embodiments of the present application, along the lateral direction of the imaging device, there is formed between the first well and the second well A channel region, in a direction away from the channel region, the surface of the channel region is sequentially provided with the first insulating dielectric layer and a charge transfer transistor, and the charge transfer transistor is used to enable the first well The charge inside is transferred to the floating diffusion node through the channel region, and the floating diffusion node is located in the second well.

Therefore, the floating diffusion node is arranged in the second well, so that the second well can effectively isolate the floating diffusion node, and effectively prevent the charge from entering the floating diffusion node during the exposure process. Internally, the interference of the charge on the floating diffusion node during the exposure process is avoided, thereby effectively improving the accuracy of the number of read charges, so as to improve the quality of the generated image.

Based on the first aspect of the embodiments of the present application, in an optional implementation of the first aspect of the embodiments of the present application, the first insulating dielectric layer is provided with at least one window, the floating gate and the first well Through the window connection, the charge transfer transistor is also used to enable the charge in the floating gate to be transferred to the floating diffusion node through the channel region.

Based on the first aspect of the embodiments of the present application, in an optional implementation of the first aspect of the embodiments of the present application, along a direction perpendicular to the imaging device, the window includes a first opening and a second opening that are arranged oppositely. The first opening is located on the surface of the first insulating dielectric layer facing the floating gate, the second opening is located on the surface of the first insulating dielectric layer facing the first well, and the first The opening and the second opening are connected.

Based on the first aspect of the embodiments of the present application, in an optional implementation of the first aspect of the embodiments of the present application, the floating gate extends to the second opening through the first opening along the guide of the window opening , And the floating gate located at the second opening is connected to the first well.

It can be understood that in the case where the first insulating dielectric layer is installed, the window can be directly penetrated through the first insulating dielectric layer, and then it can be directly deposited by means such as chemical vapor deposition (CVD). A floating gate is deposited on the surface of the first insulating dielectric layer, so that the floating gate deposited in the window is directly connected to the first well.

Based on the first aspect of the embodiments of the present application, in an optional implementation of the first aspect of the embodiments of the present application, the first well extends through the second opening along the guide of the window to the first At the opening, and the floating gate at the first opening is connected to the first well.

Based on the first aspect of the embodiments of the present application, in an optional implementation of the first aspect of the embodiments of the present application, the floating gate extends into the window through the first opening, and the first well passes through The second opening extends to the inside of the window, and the floating gate located inside the window is connected to the first well.

It can be understood that the direct connection between the first well and the floating gate is realized through the opening of the window, and the full well capacity of the imaging device is improved, thereby improving the efficiency of charge transfer and the quality of the acquired image. The transfer process will not cause damage to the first insulating dielectric layer, thereby reducing the requirements for the thickness of the first insulating dielectric layer. Because the damage of the first insulating dielectric layer is effectively avoided, the reading is effectively improved. The accuracy of the number of charges and the quality of the image, and in the process of use, increase the service life of the imaging device, so that the reliability of the imaging device is improved.

Based on the first aspect of the embodiments of the present application, in an optional implementation of the first aspect of the embodiments of the present application, in a direction perpendicular to the imaging device, the first well and the first insulating dielectric layer are arranged between The isolation medium layer is a high-density P ion implantation medium.

It can be understood that the isolation dielectric layer is provided between the first well and the first insulating dielectric layer, thereby effectively isolating the first well and the first insulating dielectric layer, reducing the generation of dark current and avoiding The influence of dark current on reading the amount of charge stored in the floating gate improves the accuracy of reading the amount of charge, thereby improving the quality of the image.

Based on the first aspect of the embodiments of the present application, in an optional implementation of the first aspect of the embodiments of the present application, along the lateral direction of the imaging device, the cross-sectional area of the first well is larger than that of the second well The cross-sectional area.

It can be understood that because the cross-sectional area of the first well is larger than the cross-sectional area of the second well, the photosensitive area used for sensitization to generate charges during the exposure period is effectively increased. It can be seen that the imaging device improves When the photosensitive area is increased, the photosensitive sensitivity of the imaging device is effectively increased.

Based on the first aspect of the embodiments of the present application, in an optional implementation of the first aspect of the embodiments of the present application, along the lateral direction of the imaging device, there is a first well between the first well and the second well. A distance, a second distance between the first insulating dielectric layer and the second well, and the first distance is smaller than the second distance.

It can be understood that because the first distance is smaller than the second distance, the success rate and transfer rate of the charge stored in the floating gate being transferred to the floating diffusion node through the first well are improved, and the floating gate is effectively avoided. The occurrence of a situation where the stored charge cannot be successfully transferred to the floating diffusion node.

Based on the first aspect of the embodiments of the present application, in an optional implementation of the first aspect of the embodiments of the present application, the first doping type is n-type impurity doping, and the second doping type is p-type Impurity doping; or, the first doping type is p-type impurity doping, and the second doping type is n-type impurity doping.

A second aspect of the embodiments of the present application provides a method for powering an imaging device, the method is used in a logic control circuit, and the logic control circuit is electrically connected to the imaging device, and the method includes:

The logic control circuit adjusts the voltage applied to the control gate electrode of the imaging device according to the charge stored in the imaging device, wherein the magnitude of the voltage applied to the control gate electrode and the amount of the charge stored in the imaging device The quantity is positively correlated.

It can be understood that the amount of charge that can be stored by the photosensitive transistor due to the photoelectric effect is positively correlated with the light intensity, that is, the greater the light intensity under the light environment in which the photosensitive transistor is located, the photosensitive transistor needs The greater the number of stored charges, the weaker the light intensity under the light environment in which the photosensitive transistor is located, and the smaller the amount of charge that the photosensitive transistor needs to store. The logic control circuit can be based on the position of the photosensitive transistor. In the lighting environment, the intensity of the light is adjusted correspondingly to the magnitude of the voltage applied to the control gate electrode, so that the method provided in this embodiment can enable the amount of charge that the imaging device can store to match different lighting environments Under demand.

Based on the second aspect of the embodiments of the present application, in an optional implementation of the second aspect of the embodiments of the present application, the method specifically includes:

The logic control circuit obtains the target quantity of the charge stored by the imaging device in the first exposure time period; adjusts the voltage applied to the control gate electrode of the imaging device in the second exposure time period according to the target quantity, Wherein, the magnitude of the voltage applied to the control gate electrode has a positive correlation with the target quantity, and the first exposure time period is earlier than the second exposure time period.

It can be understood that if the logic control circuit determines that the photosensitive transistor is in a strong light environment during the first exposure period, the logic control circuit can increase the voltage applied to the control gate electrode, thereby increasing The capacitance of the first well is increased, so that during the second exposure period, the first well can hold more charges, so that the full well capacity of the photosensitive transistor shown in this embodiment can meet the requirements of strong light. Demand; if the logic control circuit determines that the photosensitive transistor is in a weak light environment during the first exposure time period, the logic control circuit can reduce the voltage applied to the control gate electrode, thereby reducing The capacitance of the first well, so that in the second exposure time period, the capacity of the first well that can hold charges matches the current light, which effectively saves the power consumption of applying voltage to the control gate electrode Therefore, when the full well capacity of the photosensitive transistor can meet the current lighting environment, waste of power consumption is avoided.

Based on the second aspect of the embodiments of the present application, in an optional implementation of the second aspect of the embodiments of the present application, the control gate electrode of the imaging device is adjusted during the second exposure time period according to the target quantity. The applied voltage includes: if the target number is greater than or equal to a preset value, increasing the voltage applied to the control gate electrode of the imaging device during the second exposure time period.

It can be understood that when the logic control circuit determines that the target number is greater than or equal to the preset value, the logic control circuit can determine that the imaging device is in a strong light environment during the first exposure period, and the logic control circuit is The voltage applied to the control gate electrode can be increased, thereby increasing the capacitance of the first well, so that in the second exposure time period, the first well can hold more charges, thereby making the present embodiment The shown full-well capacity of the photosensitive transistor can meet the demand for strong light.

Based on the second aspect of the embodiments of the present application, in an optional implementation of the second aspect of the embodiments of the present application, the control gate electrode of the imaging device is adjusted during the second exposure time period according to the target quantity. The applied voltage includes: if the target number is less than a preset value, reducing the voltage applied to the control gate electrode of the imaging device during the second exposure time period.

It can be understood that when the logic control circuit determines that the target number is less than the preset value, the logic control circuit can determine that the imaging device is in a low-light environment during the first exposure period, and the logic control circuit That is, the voltage applied to the control gate electrode can be reduced, so that in the second exposure time period, the full well capacity of the first well can meet the demand in the low light environment, and waste of power consumption can be avoided.

Based on the second aspect of the embodiments of the present application, in an optional implementation of the second aspect of the embodiments of the present application, the method further includes: obtaining a preset voltage adjustment list, where the preset voltage adjustment list includes different charges The corresponding relationship between the number range and different voltage values; the adjusting the voltage applied to the control gate electrode of the imaging device in the second exposure time period according to the target number includes: adjusting the list according to the preset voltage, The target voltage corresponding to the target number is determined; in the second exposure time period, the target voltage is applied to the control gate electrode of the imaging device.

It can be understood that the dynamic adjustment of the target voltage applied to the control gate electrode is realized through the preset voltage adjustment list, so that the imaging device can match a wider variety of lighting environments, and the matching degree between the imaging device and the lighting environment is improved. After the control circuit applies the target voltage to the control gate electrode, the full well capacity of the imaging device can meet the requirements of the current lighting environment.

A third aspect of the embodiments of the present application provides a logic processing circuit, the logic control circuit is electrically connected to an imaging device, and the logic processing circuit includes: an adjustment unit configured to adjust the control circuit according to the charge stored in the imaging device. In the voltage applied to the control gate electrode of the imaging device, the magnitude of the voltage applied to the control gate electrode and the amount of charge stored in the imaging device have a positive correlation.

Based on the third aspect of the embodiments of the present application, in an optional implementation of the third aspect of the embodiments of the present application, the roadbed processing circuit further includes an acquiring unit configured to acquire that the imaging device is within the first exposure time period The target quantity of the stored charge; the adjustment unit is further configured to adjust the voltage applied to the control gate electrode of the imaging device in the second exposure time period according to the target quantity, wherein the control gate electrode is The magnitude of the applied voltage has a positive correlation with the target quantity, and the first exposure time period is earlier than the second exposure time period.

Based on the third aspect of the embodiments of the present application, in an optional implementation of the third aspect of the embodiments of the present application, the adjustment unit is specifically configured to: if the target quantity is greater than or equal to a preset value, During the second exposure time period, the voltage applied to the control gate electrode of the imaging device is increased.

Based on the third aspect of the embodiments of the present application, in an optional implementation of the third aspect of the embodiments of the present application, the adjustment unit is specifically configured to: if the target number is less than a preset value, perform During the exposure time period, the voltage applied to the control gate electrode of the imaging device is reduced.

Based on the third aspect of the embodiments of the present application, in an optional implementation of the third aspect of the embodiments of the present application, the adjustment unit is specifically configured to: obtain a preset voltage adjustment list, and the preset voltage adjustment list includes different The corresponding relationship between the charge quantity range and the different voltage values; according to the preset voltage adjustment list, determine the target voltage corresponding to the target quantity; in the second exposure time period, control the gate electrode of the imaging device The target voltage is applied.

A fourth aspect of the embodiments of the present application provides an image sensor. The image sensor includes a pixel array and a logic control circuit, the pixel array includes at least one imaging device, and the imaging device is electrically connected to the logic control circuit. The imaging device is as shown in the above-mentioned first aspect, and the logic control circuit is as shown in the above-mentioned third aspect, and details are not described in detail.

A fifth aspect of the embodiments of the present application provides an electronic device. The electronic device includes a processor and an image sensor. The image sensor is as shown in the above-mentioned fourth aspect, and the processor is configured to obtain all data from the image sensor.述图片。

The sixth aspect of the embodiments of the present application provides a storage medium in which computer instructions are stored, and when the computer instructions are called by a logic control circuit, the logic control circuit is caused to execute the method shown in the second aspect.

The seventh aspect of the embodiments of the present application provides a computer program product. The computer program product includes computer program code. When the computer program code is called by a logic control circuit, the logic control circuit executes the above-mentioned second aspect. method.

Description of the drawings

FIG. 1 is a diagram of an example structure of an imaging device provided by the prior art;

2 is a structural example diagram of an embodiment of the electronic device provided by this application;

3 is a structural example diagram of an embodiment of the pixel array provided by this application;

4 is a diagram showing another example of the structure of an imaging device provided by the prior art;

FIG. 5 is an example diagram of a side cross-sectional structure of an embodiment of a photosensitive transistor provided by this application;

FIG. 6 is a side view cross-sectional structure example diagram of an embodiment of the imaging device provided by this application;

FIG. 7 is an example diagram of a side cross-sectional structure of another embodiment of the imaging device provided by this application;

FIG. 8 is an example diagram of a side sectional structure of another embodiment of the imaging device provided by this application;

FIG. 9 is an example diagram of the transfer of an embodiment of optoelectronics provided by this application;

FIG. 10 is a flowchart of the steps of an embodiment of powering an imaging device provided by this application;

FIG. 11 is a flowchart of steps in another embodiment of supplying power to an imaging device provided by this application;

FIG. 12 is a flowchart of the steps of another embodiment for supplying power to the imaging device provided by this application;

FIG. 13 is a schematic structural diagram of an embodiment of a logic control circuit provided by this application.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work shall fall within the protection scope of the present invention.

The term "and/or" in this application can be an association relationship describing associated objects, indicating that there can be three types of relationships, for example, A and/or B, which can mean: A alone exists, and both A and B exist , There are three cases of B alone. In addition, the character "/" in this application generally indicates that the associated objects before and after are in an "or" relationship.

The terms "first", "second", etc. in the description and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific sequence or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments described herein can be implemented in an order other than the content illustrated or described herein. In addition, the terms "including" and "having" and any variations of them are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or modules is not necessarily limited to the clearly listed Those steps or modules may include other steps or modules that are not clearly listed or are inherent to these processes, methods, products, or equipment.

This application provides an imaging device. In order to better understand the imaging device provided in this application, the structure of an electronic device containing the imaging device is first described as follows:

As shown in FIG. 2, the electronic device 20 may be any electronic device equipped with a camera. The electronic device 20 includes, but is not limited to, a smart phone, a mobile computer, a tablet computer, a personal digital assistant (PDA), etc. As shown in FIG. 2, the electronic device 20 includes but is not limited to components such as an image sensor 200, a processor 210, a display 220, a communication unit 260, a storage unit 270, a radio frequency circuit 240, and a power supply 250.

Optionally, the processor 210 may be one or more of the following processors: a central processing unit (CPU), an image signal processor (ISP), and a graphics processor (graphics processor). Processing unit, GPU), and digital signal processor (digital signal processor, DSP).

The image sensor 200 may include a pixel array 201 and a logic control circuit 202. Specifically, the pixel array 201 may be composed of individual imaging devices, and each imaging device may correspond to one or more pixels in the image displayed by the display 230, wherein each imaging device in the pixel array 201 may be mutually Independently, specifically, when external light shines on the pixel array 201, the imaging devices located on the pixel array 201 will have a photoelectric effect, and a corresponding charge will be generated in each imaging device. The logic control circuit 202 is based on each imaging device. The corresponding charge is generated in the device to obtain the image. More specifically, the logic control circuit 202 is used to control the pixel array 201 and exchange data. For example, before the image sensor is exposed to light, the logic control circuit sends a command to reset each imaging device included in the pixel array. The logic control circuit 202 exposes the pixel array 201. After the exposure is finished, the logic control circuit 202 reads and analyzes the charge quantity of each imaging device of the pixel array 201 to obtain an image.

Wherein, the logic control circuit 202 may be provided with a processing device for controlling the pixel array to generate charges and generate corresponding images. The processing device may be one or more field-programmable gate arrays. , FPGA), application specific integrated circuit (ASIC), system on chip (SoC), central processor unit (CPU), network processor (NP), digital signal processing Circuit (digital signal processor, DSP), microcontroller (microcontroller unit, MCU), programmable controller (programmable logic device, PLD) or other integrated chips, or any combination of the above chips or processors, etc.

Specifically, the imaging device may be a three-tube active pixel (3T-APS), a clamp diode four-tube active pixel (4T-APS), a clamp diode five-tube active pixel (5T-APS), this application Take the imaging device as 4T-APS as an example for illustrative description.

The image sensor 200 may be controlled by the processor 210, and the processor 210 may output the image that the image sensor 200 has sensed and output to the display 230. The display 230 may be a display panel configured in the form of a liquid crystal display (LCD), an organic light-emitting diode (OLED), a field emission display (FED), etc.

The storage unit 270 is used to store code and data, and the code is for the processor 210 to run. In this embodiment, the storage unit 270 may include a volatile memory, and may also include a non-volatile memory.

The communication unit 260 is configured to establish a communication channel so that the electronic device can connect to a remote server through the communication channel and download media data from the remote server. The communication unit 260 may include communication modules such as a wireless local area network (wireless local area network, wireless LAN) module, a Bluetooth module, a baseband module, etc., and a radio frequency (RF) circuit corresponding to the communication module for performing wireless local area network Network communication, Bluetooth communication, infrared communication and/or cellular communication system communication.

The radio frequency circuit 240 is used to receive and send signals during information transmission and reception or during a call. For example, after receiving the downlink information of the base station, it is processed by the processor 210; in addition, the uplink data is sent to the base station. Generally, the radio frequency circuit 240 includes well-known circuits for performing these functions, including but not limited to antenna systems, radio frequency transceivers, one or more amplifiers, tuners, one or more oscillators, digital signal processors, Decoding (Codec) chipset, subscriber identification module (SIM) card, memory, etc. In addition, the radio frequency circuit 240 can also communicate with the network and other devices through wireless communication.

The power supply 250 is used to supply power to different components of the electronic device to maintain its operation. As a general understanding, the power supply 250 may be a built-in battery, such as a common lithium-ion battery, a nickel-metal hydride battery, etc., and also include an external power supply that directly supplies power to electronic devices, such as an alternating current (AC) adapter. In some embodiments of the present invention, the power supply 250 can also be defined more broadly, for example, it can also include a power management system, a charging system, a power failure detection circuit, a power converter or inverter, and a power status indicator. (Such as light-emitting diodes), and any other components associated with the generation, management and distribution of electrical energy in electronic devices.

The specific structure of the pixel array provided in the present application will be exemplarily described below with reference to FIG. 3, where FIG. 3 is a top view structure example of an embodiment of the pixel array provided in this application.

As shown in FIG. 3, the pixel array 300 includes a plurality of imaging devices 301. The pixel array 300 also includes a word line set 310, a bit line set 320, and a source line set. The source line set includes multiple source lines, and any One source line is perpendicular to the pixel array 300, and the source line is not shown in FIG. 3. The word line set 310 includes a plurality of word lines, as shown in FIG. 3, the word line 3101, the word line 3102, the word line 3103, and the word line 310y. The number of word lines included in the word line set 310 is y in this embodiment. It is not limited, as long as y is a positive integer greater than 1. The bit line set 320 includes a plurality of bit lines, such as the bit line 3201, the bit line 3202, and the bit line 320x as shown in FIG. The number x of bit lines included in the line set 320 is not limited, as long as x is a positive integer greater than one. Specifically, any one of the multiple source lines is connected to an imaging device included in the pixel array 300, and any word line included in the word line set 310 is connected to an imaging device included in the pixel array 300. Device connection. Any bit line in the bit line set 320 is connected to an imaging device included in the pixel array 300. It can be seen that any imaging device included in the pixel array 300 is connected to a bit line in the bit line set 302, respectively. One word line in the word line set 310 is connected, and any source line in the source line set is connected. Any imaging device is coupled to a logic control circuit through a bit line, a word line, and a source line. The logic control circuit can control the imaging device to generate charges through the bit line, word line, and source line, and obtain the corresponding charge according to the charge generated by the imaging device. image.

The structure of the existing imaging device will be exemplarily described below with reference to FIG. 4. FIG. 4a on the left side of FIG. 4 and FIG. 4b on the right side of FIG. 4 show two structures of the imaging device. As shown in FIG. 4a, N buried The longitudinal depth of layer 401 is L1, in order to increase the full well capacity of the imaging device, so that even if the area of the imaging device is reduced, the signal-to-noise ratio, sensitivity, etc. of the imaging device can also be improved, as shown in Figure 4b, N The vertical depth of the buried layer 402 is L2, and the length of L2 is greater than the length of L1. It can be seen that FIG. 4b increases the vertical depth of the N buried layer compared to FIG. 4a, so that the full well capacity of the imaging device of FIG. 4b is greater than that of FIG. 4a. The full well capacity of the imaging device.

However, the N buried layer 402 of FIG. 4b has a deeper longitudinal depth, which makes it more difficult for the photoelectrons in the N buried layer 402 to transfer to the floating diffusion node 404, so that the photoelectrons in the N buried layer 402 are transferred to the floating diffusion. The low efficiency of the node 404 may easily cause image deterioration, such as image tailing.

The structure of the imaging device provided by the present application will be exemplarily described below. The imaging device shown in the present application can increase the full well capacity of the imaging device while effectively guaranteeing the quality of the image and alleviating image smearing. Happening. The imaging device provided by the present application includes a photosensitive transistor and a reading unit. Specifically, the photosensitive transistor includes a semiconductor substrate, the semiconductor substrate is provided with a first well, and the surface of the first well is sequentially provided with a first well. The insulating dielectric layer and the control gate electrode, specifically, when incident light is irradiated on the semiconductor substrate and the first well, a photoelectric effect occurs to generate charges, and the first well is used to transfer the generated charges To the reading unit, the reading unit is configured to obtain a corresponding image according to the charge from the first well. Moreover, in this embodiment, when a voltage is applied to the control gate electrode, the first well becomes a capacitor capable of accommodating charges, and the greater the voltage applied to the control gate electrode, the greater the The larger the capacitance of the capacitor, the greater the amount of charge that the first well can hold. It can be seen that the expansion of the capacitance of the first well is achieved by applying a voltage to the control gate electrode, thereby making the photosensitive transistor The full well capacity can meet the demand of strong light.

For a better understanding, the following first specifically describes the structure of the imaging device with reference to FIGS. 5 and 6, where FIG. 5 is a cross-sectional structure example diagram of an embodiment of the imaging device provided by this application. 6 is an example diagram of a cross-sectional structure of an embodiment of the imaging device provided by this application.

Specifically, the process in which the photosensitive transistor 500 generates corresponding charges according to incident light is described below:

The photosensitive transistor 500 shown in this embodiment includes a photodiode (PD), and the photodiode included in the photosensitive transistor 500 is used to generate corresponding charges according to incident light. More specifically, the photodiode shown in this embodiment is used for The photosensitive photodiode includes a semiconductor substrate 501 and a first well 502.

The semiconductor substrate 501 will be described in detail below:

The semiconductor substrate 501 shown in this embodiment has a first doping type. Optionally, the first doping type is n-type impurity doping. Specifically, the material of the semiconductor substrate 501 is Pure silicon crystal, in which pentavalent elements (such as phosphorus) are doped, so that the doped phosphorus replaces the position of the silicon atoms in the semiconductor substrate 501 to form an n-type semiconductor substrate. The free electron concentration of the substrate is much higher than the hole concentration of impurity semiconductors, and the more impurities doped in the semiconductor substrate 501, the higher the free electron concentration of the semiconductor substrate 501 and the stronger the conductivity. Optionally, the first doping type is p-type impurity doping, which specifically means that the material of the semiconductor substrate 501 is pure silicon crystal, and the silicon crystal is doped with trivalent elements (such as boron). ), so that the doped boron replaces the position of the silicon atoms in the semiconductor substrate 501 to form a p-type semiconductor substrate. The hole concentration of the p-type semiconductor substrate is greater than that of the impurity semiconductor of free electrons, and the semiconductor substrate 501 The more impurities doped in the semiconductor substrate 501, the higher the hole concentration and the stronger the conductivity. In this embodiment, the material of the semiconductor substrate 501 is silicon as an example for illustrative description, and is not limited. In other examples, the material of the semiconductor substrate 501 may also be germanium. In this embodiment, the semiconductor The substrate 501 is a p-type semiconductor substrate as an example for illustration.

The first well 502 is exemplarily described below:

Optionally, if the semiconductor substrate 501 is a p-type semiconductor substrate, the charge generated by the photodiode is photoelectrons, and if the semiconductor substrate 501 is an n-type semiconductor substrate, the charge generated by the photodiode is The generated charges are holes. In this embodiment, the charge generated by the photodiode is photoelectrons as an example for illustration:

As shown in this embodiment, the first ion implantation and doping can be performed on the first side of the semiconductor substrate 501 to form a first well (WELL) 502. Taking the example shown in FIG. 6 as an example, the semiconductor substrate 501 The left side is the first side as an example for illustrative description, then first ion implantation and doping may be performed on the left side of the semiconductor substrate 501 to form the first well 502;

Specifically, if the first ion is a trivalent element (such as boron), the formed first well 502 is PWELL; if the first ion is a pentavalent element (such as phosphorus), the formed first well The well 502 is NWELL. In this embodiment, to form the photodiode capable of light-sensing, if the first doping type of the semiconductor substrate 501 is a p-type semiconductor substrate, the first ion is Boron ions, if the first doping type of the semiconductor substrate 501 is an n-type semiconductor substrate, the first ions are phosphorus ions. In this embodiment, the semiconductor substrate 501 is a p-type substrate as an example for illustration.

The position of the control gate electrode 504 included in the photosensitive transistor 500 shown in this embodiment will be exemplarily described below:

Specifically, above the semiconductor substrate 501, the first well 502, the first insulating dielectric layer 503 and the control gate electrode 504 are sequentially arranged;

The first insulating dielectric layer 503 shown in this embodiment has an insulating function. The specific material of the first insulating dielectric layer 503 is not limited in this embodiment, as long as it is a medium with a high dielectric constant, for example, The material of the first insulating dielectric layer 503 is one or a combination of silicon oxide, silicon oxynitride (SiON), silicon nitride, and aluminum oxide.

The material of the control gate electrode 504 shown in this embodiment may be a conductor with a conductive function such as polysilicon, metal, etc. The specific material is not limited in this embodiment. The control gate electrode 504 shown in this embodiment is used to connect to a logic control circuit, and the logic control circuit is used to apply a voltage to the control gate electrode 504. In this embodiment, the control gate electrode 504 is connected to the logic control circuit. The specific connection mode of the circuit is not limited. For example, the control gate electrode 504 may be connected to the logic control circuit through the word line or bit line shown in FIG. 3, and for another example, the control gate electrode 504 may be connected through an independent The wire is connected with the logic control circuit.

The function of the control gate electrode 504 provided in this embodiment is described below:

Specifically, the logic control circuit can apply a voltage within the exposure time period to the control gate electrode 504, so that the first well 502 becomes a capacitor for storing photoelectrons, and the voltage applied on the control gate electrode 504 becomes higher. Larger, the greater the capacitance of the first well 502, that is, the magnitude of the voltage applied to the control gate electrode 504 and the number of photoelectrons that can be stored in the first well 502 have a positive correlation.

The specific structure of the photosensitive transistor 500 of the imaging device is exemplarily described above. The specific structure of the reading unit 600 is exemplarily described below in conjunction with FIG. 6. It should be clarified that this embodiment describes the specific structure of the reading unit 600. The description of the structure of 600 is an optional example. For example, the reading unit shown in this embodiment may be a metal-oxide-semiconductor field-effect transistor (MOSFET) or a V-groove metal oxide. V-groove metal-oxide semiconductor (VMOS), vertical double-diffused metal-oxide semiconductor field effect transistor (vertical double-diffused MOSFET, VDMOSFET), or lateral double-diffused metal-oxide semiconductor field effect transistor (lateral double-dif fused MOSFET, LDMOSFET).

The specific structure of the reading unit 600 shown in this embodiment will be exemplarily described below in conjunction with FIG. 6:

The reading unit 600 includes a floating diffusion node 603, a charge transfer transistor 604, a reset transistor 605, a source follower transistor 606, and a row selection transistor 607. The specific location of the floating diffusion node 603 will be exemplarily described below. :

Optionally, the floating diffusion node 603 shown in this embodiment is disposed in the second well 602 of the semiconductor substrate 501. The second well 602 will be described below with reference to FIG. 6:

As shown in this embodiment, second ion implantation and doping can be performed on the second side of the semiconductor substrate 501 to form the second well 602. In the above example, the case where the first side is the left side of the semiconductor substrate 501 is taken as an example. Below, the second side shown in this example is the right side of the semiconductor substrate 501. Taking the example shown in FIG. 6 as an example, a second ion implantation doping is performed on the right side of the semiconductor substrate 501 to form a second well 602.

Specifically, the doping type of the first well 502 shown in this embodiment is different from the doping type of the second well 602. If the first ion is a trivalent element (such as boron), the formed first well 502 Is PWELL, the second ion is a pentavalent element (such as phosphorus), and the second well 602 formed is NWELL. Similarly, if the first ion is phosphorus, the first well 502 formed is NWELL. Then the second ion is boron, and the formed second well 502 is PWELL. Because the first well 502 is NWELL as an example in this embodiment, the second well 602 in this example is PWELL, because the first well 502 is PWELL. The doping type of the well 502 is different from the doping type of the second well 602, so that the photoelectrons generated by the photodiode will not enter the second well 602, so as to prevent the photoelectrons from flowing to the second well 602 for reading The accuracy of the number of photoelectrons read by the fetching unit 600 affects.

Continue to describe how the floating diffusion node 603 is specifically arranged in the second well 602 with reference to FIG. 6;

The surface of the second well 602 is doped by ion implantation to form the floating diffusion node 603, and the doping type of the floating diffusion node 603 is different from that of the second well 602. The doping type of the floating diffusion node 603 is the first doping type. For a specific description of the first doping type, please refer to the above description for details, and details are not repeated.

The electrical connection relationship between the components included in the reading unit 600 is described below as an example:

The drain of the reset transistor 605 and the drain of the source follower transistor 606 shown in this embodiment are respectively connected to the power supply voltage VDD to be connected to the logic control circuit. The source of the source follower transistor 606 and the row selection The drain of the transistor 607 is connected, the source of the row selection transistor 607 is connected to the logic control circuit, the source of the reset transistor 605 and the gate of the source follower transistor 606 are connected to the floating diffusion node 603, so The charge transfer transistor 604 is connected to the logic control circuit.

The specific working process of the reading unit 600 is exemplified below:

The logic control circuit shown in this embodiment presets the imaging period. An imaging period includes a reset time period, an exposure time period, a transfer time period, and a read time period that are arranged in sequence in sequence. The present embodiment compares the duration of each time period. Without limitation, the following is a specific description:

First, the first step is reset. The reset transistor 605 is used to reset the photodiode. Specifically, the logic control circuit turns on the charge transfer transistor 604 and the reset transistor 605 at the same time, so that the electrons in the first well 502 are depleted At this time, the first well 502 is in an empty well state, and the floating diffusion node 603 is at a high potential. At this time, the potential of the floating diffusion node 603 is read out through the source follower transistor 606 and the row selection transistor 607, as The first signal of correlated double sample (CDS) is output to the bus;

The second step is exposure. Specifically, the logic control circuit turns off the charge transfer transistor 604 and the reset transistor 605. The photosensitive transistor 500 generates photoelectrons under the excitation of incident light. After the exposure period, the photosensitive transistor 500 accumulates enough photoelectrons;

Specifically, during the exposure time period, a depletion layer is formed in the formation of the first well 502. When incident light from the outside irradiates the depletion layer, a photoelectric effect can occur in the depletion layer, that is, the photons of the incident light are Photoelectrons are absorbed; this embodiment does not limit the direction in which incident light from the outside illuminates the pixel array. Optionally, as shown in the arrow direction of the arrow 608 shown in FIG. 6, the light is sequentially passed through the control gate electrode 504, The first insulating medium layer 503 is irradiated on the photodiode; optionally, the direction of the arrow 609 shown in FIG. 6 is continued, that is, the light is directly irradiated on the photodiode. Wherein, the number of photoelectrons generated by the photodiode is in a positive correlation with the intensity of light irradiated by the external incident light on the photodiode and/or the irradiated time.

The third step is to transfer photoelectrons. In order to better understand the specific process of transferring photoelectrons, please refer to FIG. 6 below. Along the lateral direction of the imaging device, the first well 502 and the second well 602 A channel region 610 is formed therebetween. Along the direction away from the channel region 610, the surface of the channel region 610 is sequentially provided with the first insulating dielectric layer 503 and the charge transfer transistor 604;

Wherein, the logic control circuit turns on the charge transfer transistor 604 during the transfer period, and drops the voltage of the control gate electrode 504 to the reset voltage, so that the photoelectrons in the first well 502 can pass through the channel region 610 completely. Transfer to the floating diffusion node 603;

It can be seen that the charge transfer transistor 604 shown in this embodiment is used to transfer the photoelectrons in the first well 502 to the floating diffusion node 603 through the channel region 610. In the direction of the imaging device, the charge transfer transistor 604 is arranged above the channel region 610, so that when the charge transfer transistor 604 is turned on by the logic control circuit, the charge transfer transistor 604 can control the photoelectron It is completely transferred to the floating diffusion node 603 through the channel region 610.

The fourth step is reading. Specifically, because photoelectrons are transferred to the floating diffusion node 603, the potential of the floating diffusion node 603 is reduced, and the floating diffusion node 603 is used to convert the transferred photoelectrons Is the corresponding electrical signal, and sequentially outputs the optical signal to the logic control circuit through the source follower transistor 606 and the row selection transistor 607, the optical signal at this time is output to the logic control circuit as the second signal of the CDS, the logic control circuit Make difference between two CDS signals to get the corresponding image.

Optionally, along the lateral direction of the imaging device, the cross-sectional area of the first well 502 is larger than the cross-sectional area of the second well 602, thereby effectively improving the photosensitive of the imaging device shown in this embodiment. Since the cross-sectional area of the first well 502 is larger than the cross-sectional area of the second well 602, the full-well capacitance of the imaging device is not reduced, and the photosensitive sensitivity of the imaging device is increased.

The electrical connection relationship of the pixel array shown in this embodiment will be described below with reference to FIGS. 3 and 6:

All the reading units 600 included in the pixel array 300 shown in this embodiment are interconnected by flash memory NOR, so that the logic control circuit shown in this embodiment can control mutually perpendicular bit lines and word lines, so that the pixel array All imaging devices included in 300 perform XY address reading.

All the imaging devices included in the pixel array 300 shown in this embodiment have a common source. During the exposure time, the logic control circuit controls the common source of all the imaging devices included in the pixel array 300 to be grounded, which can effectively prevent sharing. The reading unit 600 of the source causes interference to the photosensitive transistor 500 during the exposure time period.

All photosensitive transistors included in the pixel array 300 shown in this embodiment are interconnected by flash memory NAND, so that the photosensitive transistors 500 of each imaging device are independent, so that even if one photosensitive transistor 500 fails, it will not affect the pixel array. The other photosensitive transistors 500 in the normal operation.

Optionally, continuing as shown in FIG. 6, isolation layers 511 are provided on both sides of the imaging device. The isolation layer 511 is used to realize isolation between the imaging device and surrounding imaging devices in the pixel array. It is formed by shallow trench isolation (STI), and the STI specifically refers to forming a shallow trench and filling the trench with oxide or nitride for isolation to ensure adjacent imaging devices They will not interfere with each other; optionally, the isolation layer 511 can also be formed according to local oxidation of silicon (locos) technology, which is not specifically limited in this embodiment.

The following is an exemplary description of how the imaging device provided in this embodiment can effectively reduce the influence of dark current with reference to FIG. 7:

First, the dark current will be described with reference to FIGS. 5 and 6. In the photosensitive transistor 500, in the state of no light irradiation, the current flowing between the first well 502 and the first insulating dielectric layer 503 is a dark current. The current will interfere with the process of the reading unit 600 obtaining the corresponding electrical signal according to the photoelectron. In order to reduce the influence of the dark current on the reading unit obtaining the electrical signal, as shown in FIG. 7, as shown in this embodiment, in the first An isolation dielectric layer 701 is arranged between a well 502 and the first insulating dielectric layer 503.

This embodiment does not limit the specific material of the isolation dielectric layer 701, as long as the isolation dielectric layer 701 can function to isolate the first well 502 and the first insulating dielectric layer 503, for example, The isolation dielectric layer 701 may be a high-density P ion implantation (high density of P ion implan) medium, and the first well 502 and the first insulating dielectric layer 503 can be effectively separated by the isolation dielectric layer 701, Therefore, the interference of the dark current between the first well 502 and the first insulating dielectric layer 503 on the reading unit 600 is effectively reduced.

In the following, another structure of the imaging device is exemplarily described in conjunction with FIG. 8:

In the photosensitive transistor 500 shown in this example, directly above the semiconductor substrate 501, the first well 502, the isolation dielectric layer 701, the first insulating dielectric layer 503, the floating gate 800, and the second The second insulating dielectric layer 801 and the control gate electrode 504. For specific descriptions of the first well 502, the isolation dielectric layer 701, the first insulating dielectric layer 503 and the control gate electrode 504, please refer to the above implementation for details As shown in the example, it is not specifically limited in this embodiment.

In this example, the material of the second insulating dielectric layer 801 and the material of the first insulating dielectric layer 503 may be the same or different, as long as the second insulating dielectric layer 801 is also a medium with a high dielectric constant. .

It can be seen from FIG. 8 that the floating gate 800 is located in the containing cavity formed between the first insulating dielectric layer 503 and the second insulating dielectric layer 801, so that the first insulating dielectric layer 503 and the The two insulating dielectric layers 801 can effectively isolate the floating gate 800, so that the photoelectrons are confined in the floating gate 800 to realize the storage function of the photoelectrons. The floating gate 800 shown in this embodiment can be a broadband semiconductor, such as polysilicon, silicon nitride ( Si3N4) or other electronic conductors or semiconductors, the floating gate 800 shown in this embodiment effectively guarantees that photoelectrons can enter the floating gate 800 and be stored in the floating gate 800. It can be seen that the structure shown in this embodiment is adopted. It can effectively increase the number of photoelectrons that the photosensitive transistor can store, and further increase the full well capacity of the imaging device.

In order to realize that the photoelectrons generated by the photodiode can be stored in the floating gate 800, an opening 803 is provided through the first insulating layer 503 in a direction perpendicular to the imaging device. The specific number of windows 803 is not limited, that is, the number of windows 803 can be one or more. This embodiment takes the example shown in FIG. 8 as an example, that is, an imaging device includes one window 803. Specifically, The window 803 includes a first opening 8031 and a second opening 8032 opposed to each other. The first opening 8031 is located at the end surface of the first insulating dielectric layer 503 facing the floating gate 800, and the second opening 8032 is located at the end of the floating gate 800. The first insulating dielectric layer 503 faces the end surface of the first well 502, and the first opening 8031 and the second opening 8032 are connected.

This embodiment is to realize that the photoelectrons generated by the photodiode can be stored in the floating gate 800 through the window 803, so that the photosensitive transistor can simultaneously store the photoelectrons through the first well 502 and the floating gate 800. In order to achieve the purpose of transmitting the photoelectrons generated by the photodiode to the floating gate 800, the first well 502 shown in this embodiment can be connected to the floating gate 800 through the window 803, as follows Illustrate the specific connection method:

Way 1

The medium of the floating gate 800 extends to the second opening 8032 through the first opening 8031 along the guide of the window 803, and realizes the floating gate 800 and the first well at the second opening 8032. 502 connections.

Way 2

The medium of the first well 502 extends through the second opening 8032 to the first opening 8031 along the guide of the window 803, and realizes the floating gate 800 and the first well 502 at the first opening 8031 Connection.

Way 3

The medium of the floating gate 800 extends to the inside of the window 803 along the guide of the window 803 through the first opening 8031, and the medium of the first well 502 passes through the second opening 8032 and extends along the window 803. The guide of the window 803 extends to the inside of the window 803, so that the floating gate 800 in the window 803 is connected to the first well 502. In this way, the thickness of the floating gate 800 in the window 803 and The thickness of the first well 502 is not limited, as long as the floating gate 800 and the first well 502 can be connected.

When the image sensor provided in this application is applied to a terminal, such as a smart phone, the imaging device can be less than 0.7um. It can be seen that the imaging device shown in this application can meet the requirements for full well capacity while also satisfying imaging The demand for device miniaturization.

The process of how the photoelectrons located in the photodiode are transmitted to the floating gate 800 is described below in conjunction with FIG. 9:

Specifically, during the exposure time period, a depletion layer 900 is formed in the photodiode. For a specific description of the depletion layer 900, please refer to the above-mentioned embodiment for details, which will not be repeated in this embodiment.

When the external incident light irradiates the depletion layer 900, a photoelectric effect can occur in the depletion layer 900, that is, the photons of the incident light from the outside are absorbed to generate photoelectrons 901; for specific instructions on generating photoelectrons 901, please refer to As shown in the foregoing embodiment, details are not repeated in this embodiment. The photoelectron 901 generated in the depletion layer 900 drifts in a direction toward the floating gate 800, and when the photoelectron 901 moves to the interface of the first well 502, it enters the floating gate 800 through the window 803;

During the transfer period, the logic control circuit turns on the charge transfer transistor 604 during the transfer period, and drops the voltage of the control gate electrode 504 to a reset voltage, so that the floating gate 800 stores Photoelectrons can flow to the channel region 610 through the window 803 so that the floating gate 800 completely transfers the photoelectrons to the floating diffusion node 603 through the channel region 610. A detailed description of the transfer period , Please refer to the above for details, and I won’t go into details.

Optionally, referring to FIG. 8, along the lateral direction of the imaging device, there is a first distance L1 between the first well 502 and the second well 602, and the first insulating dielectric layer 503 and There is a second distance L2 between the second wells 602, and the first distance L1 is less than the second distance L2. The structure shown in this embodiment is adopted, because the first distance L1 is less than the second distance L2 improves the success rate and transfer rate of the photoelectrons stored in the floating gate 800 to the floating diffusion node 603 via the first well 502, and effectively prevents the photoelectrons stored in the floating gate 800 from being successfully transferred to the floating diffusion node 603. The emergence of the floating diffusion node 603.

Based on the description of the structure of the imaging device in the foregoing embodiment, this application also provides a method for powering the imaging device. For a specific description of the imaging device, please refer to the foregoing embodiment for details, which is specifically in this embodiment. Do not repeat;

The method specifically includes: the logic control circuit adjusts the voltage applied to the control gate electrode of the imaging device according to the stored charge of the imaging device, wherein the magnitude of the voltage applied to the control gate electrode and the amount of The amount of charge stored in the imaging device is positively correlated.

Specifically, the amount of charge that can be stored by the phototransistor due to the photoelectric effect is positively correlated with the light intensity, that is, the greater the light intensity under the light environment in which the phototransistor is located, the phototransistor needs The greater the number of stored charges, the weaker the light intensity under the light environment in which the photosensitive transistor is located, and the smaller the amount of charge that the photosensitive transistor needs to store. The logic control circuit can be based on the position of the photosensitive transistor. The intensity of the light in the light environment corresponds to the adjustment of the voltage applied to the control gate electrode. Specifically, for example, if the light in the light environment where the photosensitive transistor is located is stronger, the light on the control gate electrode is The greater the applied voltage, the greater the amount of charge that the photosensitive transistor can store, and the weaker the light in the light environment in which the photosensitive transistor is located, the smaller the voltage applied to the control gate electrode Therefore, the smaller the amount of charge that can be stored by the photosensitive transistor, the method provided in this embodiment can enable the amount of charge that can be stored by the imaging device to match the requirements under different lighting environments.

In order to better understand the method provided by this application, the specific execution process of the method for supplying power to the imaging device provided by this application will be exemplarily described below in conjunction with FIG. 10, as shown in FIG. The methods shown include:

Step 1001: The logic control circuit obtains the target amount of charge stored by the imaging device in the first exposure time period;

For a specific description of the logic control circuit, please refer to the above description. The details are not repeated in this embodiment. The logic control circuit shown in this embodiment first determines the first exposure time period, where the The first exposure time period is the time period during which the imaging device has completed exposure, that is, the photosensitive transistor completes the exposure in the first exposure time period and acquires a target amount of charge in the first exposure time period, wherein, For a specific description of the target amount of charge acquired by the photosensitive transistor during the exposure time period, please refer to the above-mentioned embodiment for details, and details are not repeated in this embodiment.

Step 1002: The logic control circuit adjusts the voltage applied to the control gate electrode of the imaging device in the second exposure time period according to the target number.

In this embodiment, the voltage applied by the logic control circuit to the control gate electrode is dynamically adjusted. Specifically, the logic control circuit is based on the charge stored by the photosensitive transistor during the first exposure period. The target number is adjusted.

More specifically, the target amount of charge that can be stored by the photosensitive transistor due to the photoelectric effect is positively correlated with the light intensity, that is, the light intensity of the photosensitive transistor in the light environment during the first exposure period. The greater the value, the greater the target quantity of charge stored by the photosensitive transistor, and the weaker the light intensity of the photosensitive transistor in the light environment during the first exposure time period, the lower the target amount of charge stored by the photosensitive transistor The smaller the number, the logic control circuit determines the light condition of the photosensitive transistor during the first exposure time period, and can correspondingly adjust the control gate electrode of the imaging device during the second exposure time period. In the applied voltage, the first exposure time period is earlier than the second exposure time period, and the second exposure time period is the next time period during which the photosensitive transistor needs to be exposed to light.

The specific adjustment process may be: if the logic control circuit determines that the photosensitive transistor is in a strong light environment during the first exposure time period, the logic control circuit may increase the voltage applied to the control gate electrode , Thereby increasing the capacitance of the first well, so that in the second exposure period, the first well can hold more charges, so that the full well capacity of the photosensitive transistor shown in this embodiment can satisfy The need for strong light;

If the logic control circuit determines that the photosensitive transistor is in a weak light environment during the first exposure period, the logic control circuit can reduce the voltage applied to the control gate electrode, thereby reducing the first exposure time. The capacitance of the well, so that during the second exposure time period, the ability of the first well to hold charges matches the current light, which effectively saves the power consumption of applying voltage to the control gate electrode. The full well capacity of the photosensitive transistor can meet the current lighting environment and avoid waste of power consumption.

Hereinafter, in conjunction with FIG. 11, a specific process for the logic control circuit to adjust the magnitude of the voltage applied to the control gate electrode is exemplified:

Step 1101: The logic control circuit obtains the target amount of charge stored by the imaging device during the first exposure time period;

For the specific execution process of step 1101 shown in this embodiment, please refer to step 1001 shown in FIG. 10 for details, and the specific execution process will not be repeated in this embodiment.

Step 1102: The logic control circuit judges whether the target number is greater than or equal to a preset value, if yes, execute step 1103, if not, execute step 1104.

Specifically, the logic control circuit shown in this embodiment may set the preset value in advance. When the target amount of charge generated by the imaging device according to the photoelectric effect is greater than or equal to the preset value, the logic control The circuit determines that the first exposure time period is light-sensitive in a strong light environment, and when the target amount of charge generated by the imaging device according to the photoelectric effect is less than the preset value, the logic control circuit It is determined that the first exposure time period is photosensitive under a weak light environment.

Step 1103: The logic control circuit increases the voltage applied to the control gate electrode of the imaging device during the second exposure time period.

Step 1104: The logic control circuit reduces the voltage applied to the control gate electrode of the imaging device during the second exposure time period.

The method shown in this embodiment will be described below in conjunction with specific examples:

Taking the first exposure time period of 10 milliseconds as an example, the incident light under weak light irradiates the photosensitive transistor 500, which can generate 10,000 charges in the first well 502, and the incident light under strong light irradiates In the photosensitive transistor 500, one hundred thousand charges can be generated in the first well 502. If the capacitance of the first well 502 is fixed, the photosensitive transistor 500 cannot meet the demand for strong light;

However, as shown in this embodiment, the logic control circuit determines that the target number (100,000 charges) stored in the photosensitive transistor 500 is greater than the preset value (60,000 charges) during the first exposure time period. , The photosensitive transistor 500 is exposed under a strong light environment, then the next exposure time period (second exposure time period) of the first exposure time period, the photosensitive transistor 500 may be in a strong light environment The logic control circuit shown in this embodiment can reduce the voltage applied to the control gate electrode of the imaging device during the second exposure time period, so as to increase the fullness of the first well 502. The well capacity, so that the capacitance value of the photoelectrons that can be accommodated in the first well 502 is also increased, thereby realizing the expansion of the charge depletion area of the first well 502, thereby making the photosensitive transistor shown in this embodiment more effective The full well capacity can meet the demand of strong light.

Hereinafter, in conjunction with FIG. 12, another specific process for the logic control circuit to adjust the magnitude of the voltage applied to the control gate electrode is exemplified:

Step 1201: The logic control circuit obtains the target amount of charge stored by the imaging device in the first exposure time period;

For the specific execution process of step 1201 shown in this embodiment, please refer to step 1001 shown in FIG. 10 for details, and the specific execution process will not be repeated in this embodiment.

Step 1202, the logic control circuit obtains a preset voltage adjustment list.

The preset voltage adjustment list shown in this embodiment includes the correspondence between different charge quantity ranges and different voltage values. In order to realize that the stronger the light illuminating the imaging device, the larger the capacitance value of the first well to accommodate more For the purpose of more electric charges, in the preset voltage adjustment list, the larger the range of the electric charges, the larger the corresponding voltage value.

Step 1203: The logic control circuit determines a target voltage corresponding to the target number according to the preset voltage adjustment list.

Step 1204: The logic control circuit applies the target voltage to the control gate electrode of the imaging device in the second exposure time period.

As shown in this embodiment, the dynamic adjustment of the target voltage applied to the control gate electrode is realized through the preset voltage adjustment list, so that the method shown in this embodiment can match more diverse lighting environments and improve imaging The matching degree of the device and the lighting environment, after the logic control circuit applies the target voltage to the control gate electrode, can enable the full well capacity of the imaging device to meet the requirements of the current lighting environment.

The specific structure of the logic control circuit provided in this embodiment will be exemplarily described below in conjunction with FIG. 13, where the logic control circuit shown in this embodiment is used to perform the corresponding processing in any of the above method embodiments. And/or the processing device of the step, the specific process, please refer to the above method embodiment;

Specifically, the logic control circuit includes:

The adjusting unit 1301 is configured to adjust the voltage applied to the control gate electrode of the imaging device according to the charge stored in the imaging device, wherein the magnitude of the voltage applied to the control gate electrode is the same as that stored in the imaging device The number of charges is positively correlated.

Optionally, the logic control circuit further includes an obtaining unit 1302, configured to obtain a target quantity of charges stored by the imaging device in the first exposure time period;

The adjusting unit 1301 is further configured to adjust the voltage applied to the control gate electrode of the imaging device in the second exposure time period according to the target number, wherein the magnitude of the voltage applied to the control gate electrode is equal to The number of targets is in a positive correlation, and the first exposure time period is earlier than the second exposure time period.

Optionally, the adjustment unit 1301 is specifically configured to: if the target number is greater than or equal to a preset value, increase the voltage applied to the control gate electrode of the imaging device during the second exposure time period .

Optionally, the adjustment unit 1301 is specifically configured to: if the target number is less than a preset value, in the second exposure time period, reduce the voltage applied to the control gate electrode of the imaging device.

Optionally, the adjustment unit 1301 is specifically configured to: obtain a preset voltage adjustment list, where the preset voltage adjustment list includes the correspondence between different charge quantity ranges and different voltage values; and adjust the list according to the preset voltage , Determining the target voltage corresponding to the target number; applying the target voltage to the control gate electrode of the imaging device in the second exposure time period.

In a specific application process, the acquisition unit 1302 may be an input/output interface or a transceiver circuit. The input/output interface may include an input interface and an output interface, and the transceiver circuit may include an input interface circuit and an output interface circuit.

The adjustment unit 1301 may be a processing device, and the functions of the processing device may be partially or fully implemented by software. Optionally, the functions of the processing device may be partially or fully implemented by software. At this time, the processing device may include a memory and a processor, where the memory is used to store a computer program, and the processor reads and executes the computer program stored in the memory to perform corresponding processing and/or steps in any method embodiment. Optionally, the processing device may only include a processor. The memory for storing the computer program is located outside the processing device, and the processor is connected to the memory through a circuit/wire to read and execute the computer program stored in the memory. Optionally, the functions of the processing device may be partially or fully implemented by hardware, which is not specifically limited in this embodiment, as long as the processing device can execute the corresponding processing and/or steps in any one of the above method embodiments.

The embodiment of the present application also provides a storage medium that stores computer instructions, and when the computer instructions are called by the logic control circuit, the logic control circuit is caused to perform the corresponding processing and processing shown in any of the above method embodiments. / Or steps.

The embodiment of the present application also provides a computer program product. The computer program product includes computer program code. When the computer program code is called by a logic control circuit, the logic control circuit is executed as shown in any of the above method embodiments. The corresponding processing and/or steps.

Those skilled in the art can clearly understand that, for the convenience and conciseness of description, the specific working process of the above-described system, device, and unit can refer to the corresponding process in the foregoing method embodiment, which will not be repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed system, device, and method may be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or It can be integrated into another system, or some features can be ignored or not implemented. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.

In addition, the functional units in the various embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or software functional unit.

If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, the technical solution of the present invention essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , Including several instructions to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method in each embodiment of the present invention. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk and other media that can store program code .

As mentioned above, the above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions recorded in the embodiments are modified, or some of the technical features are equivalently replaced; these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

An imaging device is characterized by comprising a semiconductor substrate, a first well and a second well are respectively provided on both sides of the semiconductor substrate by ion implantation doping, and the semiconductor substrate and the second well have a first well A doping type, the first well has a second doping type;

The surface of the first well is sequentially provided with a first insulating dielectric layer and a control gate electrode, and the magnitude of the voltage applied to the control gate electrode is positively correlated with the amount of charge stored in the first well.
The imaging device according to claim 1, wherein a second insulating dielectric layer is provided on the surface of the control gate electrode facing the semiconductor substrate, the first insulating dielectric layer and the second insulating dielectric layer A accommodating cavity is formed therebetween, and a floating gate for storing electric charges is arranged in the accommodating cavity.
The imaging device according to claim 2, wherein a channel region is formed between the first well and the second well along the lateral direction of the imaging device, and a channel region is formed along a distance away from the channel region. Direction, the surface of the channel region is sequentially provided with the first insulating dielectric layer and a charge transfer transistor, and the charge transfer transistor is used to enable the charge in the first well to be transferred to the floating point via the channel region. In the empty diffusion node, the floating diffusion node is located in the second well.
The imaging device according to claim 3, wherein the first insulating dielectric layer is provided with at least one window, the floating gate and the first well are connected through the window, and the charge transfer transistor It is also used to enable the charge in the floating gate to be transferred to the floating diffusion node through the channel region.
The imaging device according to claim 3 or 4, wherein in a direction perpendicular to the imaging device, the window includes a first opening and a second opening that are oppositely disposed, and the first opening is located in the The first insulating dielectric layer faces the surface of the floating gate, the second opening is located on the surface of the first insulating dielectric layer facing the first well, and the first opening and the second opening are connected .
The imaging device according to any one of claims 1 to 5, wherein along a direction perpendicular to the imaging device, an isolation dielectric layer is provided between the first well and the first insulating dielectric layer, so The isolation medium layer is a high-density P ion implantation medium.
The imaging device according to any one of claims 1 to 6, wherein in the lateral direction of the imaging device, the cross-sectional area of the first well is larger than the cross-sectional area of the second well.
The imaging device according to any one of claims 1 to 7, wherein along the lateral direction of the imaging device, there is a first distance between the first well and the second well, and the first There is a second distance between the insulating dielectric layer and the second well, and the first distance is smaller than the second distance.
The imaging device according to claim 5, wherein the floating gate extends to the second opening through the first opening along the guide of the window, and the floating gate located at the second opening The gate is connected to the first well.
The imaging device of claim 5, wherein the first well extends to the first opening through the second opening along the guide of the window, and is located at the first opening. The floating gate is connected to the first well.
The imaging device according to claim 5, wherein the floating gate extends to the inside of the window through the first opening, and the first well extends to the inside of the window through the second opening , The floating gate located inside the window is connected to the first well.
The imaging device according to any one of claims 1 to 11, wherein the first doping type is n-type impurity doping, and the second doping type is p-type impurity doping; or, The first doping type is p-type impurity doping, and the second doping type is n-type impurity doping.
A method for powering an imaging device, characterized in that the method is used in a logic control circuit, the logic control circuit is electrically connected to the imaging device, and the method includes:

The voltage applied to the control gate electrode of the imaging device is adjusted according to the charge stored in the imaging device, wherein the magnitude of the voltage applied to the control gate electrode is positively related to the amount of charge stored in the imaging device relationship.
An image sensor, characterized in that the image sensor includes a pixel array and a logic control circuit, the pixel array includes at least one imaging device, the imaging device is electrically connected to the logic control circuit, and the imaging device is As shown in any one of claims 1 to 12, the logic control circuit is used to adjust the voltage applied to the control gate electrode of the imaging device according to the charge stored in the imaging device, wherein the control gate electrode is applied There is a positive correlation between the magnitude of the voltage and the amount of charge stored in the imaging device.
An electronic device, characterized in that the electronic device comprises a processor and an image sensor, the image sensor is as described in claim 14, and the processor is used to obtain the image from the image sensor.