WO2021015677A1 - Transition metal dichalcogenides and uses thereof - Google Patents

Transition metal dichalcogenides and uses thereof Download PDF

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Publication number
WO2021015677A1
WO2021015677A1 PCT/SG2020/050426 SG2020050426W WO2021015677A1 WO 2021015677 A1 WO2021015677 A1 WO 2021015677A1 SG 2020050426 W SG2020050426 W SG 2020050426W WO 2021015677 A1 WO2021015677 A1 WO 2021015677A1
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layer
tmd
alkali metal
transition metal
metals
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PCT/SG2020/050426
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French (fr)
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Wei Chen
Yue Zheng
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National University Of Singapore
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Priority to SG11202112907XA priority Critical patent/SG11202112907XA/en
Priority to CN202080050245.9A priority patent/CN114072926A/en
Publication of WO2021015677A1 publication Critical patent/WO2021015677A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
    • H01L21/441—Deposition of conductive or insulating materials for electrodes
    • H01L21/443—Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78681—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02568—Chalcogenide semiconducting materials not being oxides, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02576—N-type

Definitions

  • the present invention relates to transition metal dichalcogenides, particularly the use of transition metal dichalcogenides in electronic devices.
  • TMDs transition metal dichalcogenides
  • CMOS complementary metal oxide semiconductor field-effect transistors
  • ⁇ NSe2 tungsten diselenide
  • 2H phase semiconducting trigonal prismatic (2H phase)
  • I phase metallic octahedral
  • IT' phase distorted octahedral
  • WSe2 Semiconducting WSe2 demonstrates great advantages in complementary logic devices, arising from its ambipolar transport property with high current on/off ratio.
  • 2H WSe2-based transistors generally suffer from high Schottky barrier height and high contact resistance at the metal contact/WSe2 interface, which degrades the performance of WSe2 FETs, including the electrical conductance and carrier mobility.
  • a material comprising: a transition metal dichalcogenide (TMD) comprising a surface, a least a portion of the surface being surface-modified with one or more Group 1 metals, wherein the one or more Group 1 metals comprise Cs and/or Rb.
  • TMD transition metal dichalcogenide
  • a transition metal dichalcogenide has the general formula MX 2 , where M is a transition metal atom and X is a chalcogen atom.
  • the transition metal dichalcogenide may comprise one or more of M0S 2 , WS 2 , MoSe 2 and WSe 2 , MoTe 2 , alkali metal-doped MoTe 2 , alkali metal-doped MoSe 2 , alkali metal- doped M0S 2 , alkali metal-doped WSe 2 , and alkali metal-doped WS 2 .
  • the transition metal dichalcogenide may comprise one or more of WSe 2 and/or MoTe 2 .
  • the transition metal dichalcogenide may comprise WSe 2 .
  • the TMD may comprise one or more impurities.
  • the transition metal dichalcogenide may be substantially two-dimensional (2-D). A portion of the transition metal dichalcogenide may be substantially two-dimensional. A portion or all of the transition metal dichalcogenide may have a thickness of between 1 and 5 layers. A portion or all of the transition metal dichalcogenide may comprise a mono-layer or a bi-layer.
  • 'Surface modified' or 'surface modification' refers to a surface of a material being changed by bringing physical, chemical or biological characteristics different from the ones originally found on the surface of a material.
  • a surface is modified if it is functionalised by adding new functions, features, capabilities, or properties to a material.
  • the modification changes the surface chemistry of the material.
  • the modification or functionalisation resides only on the surface and does not penetrate the material.
  • 'doping' refers to the intentional introduction of impurities into an intrinsic semiconductor for the purpose of modulating its electrical, optical and structural properties.
  • the impurity resides within the semiconductor.
  • One portion of the surface of the TMD may be surface-modified and one portion may not be surface modified. All of the surface may be surface modified. A plurality of portions of the surface may be surface-modified. The surface may be modified by a mixture of two or more alkali metals. The surface may be modified only by Caesium and/or Rubidium. One portion of the TMD may be surface modified with Caesium and/or Rubidium and another portion may be surface modified with another alkali metal. The one or more alkali metals may comprise one or more impurities.
  • the one or more alkali metals may comprise Caesium and one or more element selected from Lithium, Sodium, Potassium and Rubidium.
  • the one or more alkali metals may comprise Rubidium and one or more element selected from Lithium, Sodium, Potassium and Caesium.
  • the alkali metal may be in direct contact with the surface of the TMD. There may be a direct interface between the alkali metal and the TMD.
  • the one or more Group 1 metals may form a layer on the surface of the TMD.
  • the layer of Group 1 metal may have a thickness of greater than or equal to 0.2nm.
  • the layer may have a thickness of less than or equal to 5.0nm.
  • the layer of Group 1 metal may have a thickness of between 0.4nm and 2.0nm.
  • O.Onm to O.Olnm O.Onm to 0.05nm, O.Onm to 0.07nm, O.Onm to 0.08nm, O.Onm to O.lnm, O.Onm to 0.19nm, O.Onm to 0.20nm, O.Onm to 0.4nm O.Onm to 0.5nm, O.Onm to 0.6nm O.Onm to l.Onm, O.Onm to 2.0nm, O.Onm to 5.0nm;
  • 0.2nm to 0.4nm 0.2nm to 0.5nm, 0.2nm to 0.6nm 0.2nm to l.Onm, 0.2nm to 2.0nm, 0.2nm to 5.0nm; 0.4nm to 0.5nm, 0.4nm to 0.6nm, 0.4nm to l.Onm, 0.4nm to 2.0nm, 0.4nm to 5.0nm;
  • the surface modified portion or portions of the TMD may be in a different phase to the portion or portions of the TMD that are not surface modified.
  • the surface-modified portion or portions may be in a IT or IT' phase and the portion or portions that are not surface-modified may be in a 2H phase.
  • an electronic device comprising a transition metal dichalcogenide (TMD) is provided, the TMD comprising first and second portions which are surface modified with one or more a Group 1 metals and a third portion which is not surface modified with one or more Group 1 metals; and first and second electrodes, wherein the first and second electrodes are in direct electrical contact with the first and second portions of the transition metal dichalcogenide, respectively, wherein the one or more Group 1 metals comprises Caesium and/or Rubidium.
  • TMD transition metal dichalcogenide
  • the transition metal dichalcogenide may comprise one or more of M0S 2 , WS 2 , MoSe 2 and WSe 2 , MoTe 2 , alkali metal-doped MoTe 2 , alkali metal-doped MoSe 2 , alkali metal- doped M0S 2 , alkali metal-doped WSe 2 , and alkali metal-doped WS 2 .
  • the transition metal dichalcogenide may comprise one or more of WSe 2 and/or MoTe 2 .
  • the transition metal dichalcogenide may comprise WSe 2 .
  • the one or more alkali metals may comprise Caesium and the transition metal dichalcogenide may comprise WSe 2 .
  • the TMD may comprise one or more impurities.
  • the transition metal dichalcogenide may be substantially two-dimensional (2-D). A portion of the transition metal dichalcogenide may be substantially two-dimensional. A portion or all of the transition metal dichalcogenide may have a thickness of between 1 and 5 layers. A portion or all of the transition metal dichalcogenide may comprise a mono-layer or a bi-layer.
  • the surface may be modified by a mixture of two or more alkali metals.
  • the surface may be modified only by Caesium and/or Rubidium.
  • One portion of the TMD may be surface modified with Caesium and/or Rubidium and another portion may be surface modified with another alkali metal.
  • the one or more alkali metals may comprise one or more impurities.
  • the one or more Group 1 metals may form a layer on the surface of the TMD.
  • the layer of Group 1 metal may have a thickness of greater than or equal to 0.2nm.
  • the layer may have a thickness of less than or equal to 5.0nm.
  • the layer of Group 1 metal may have a thickness of between 0.4nm and 2.0nm.
  • the thickness of the more or more alkali metals may fall into one of the following ranges: O.Onm to O.Olnm, O.Onm to 0.05nm, O.Onm to 0.07nm, O.Onm to 0.08nm, O.Onm to O.lnm, O.Onm to 0.19nm, O.Onm to 0.20nm, O.Onm to 0.4nm O.Onm to 0.5nm,
  • the surface modified portion or portions of the TMD may be in a different phase to the portion or portions of the TMD that are not surface modified.
  • the surface-modified portion or portions may be in a IT or IT' phase and the portion or portions that are not surface-modified may be in a 2H phase.
  • the device may exhibit substantially Ohmic contact behaviour with respect to the first and second electrodes.
  • Ohmic contact behaviour implies that the current between the two electrodes of the device has a substantially linear
  • the device may have a Schottky barrier height of less than or equal to lOmeV.
  • the device may have a Schottky barrier height of less than or equal to 9.4meV.
  • the device may have a Schottky barrier height of between 9meV and lOmeV or of between
  • the device may have a field effect electron mobility at room temperature (298K) of 35 cm 2 V 1 s 1 or greater, particularly 37.7cm 2 V 1 s 1 or greater, more particularly 70 cm 2 V
  • the device may have a field effect electron mobility at room
  • the device may have a current on/off ratio at room temperature (298K) of 10 6 or greater, particularly 10 7 or greater, further particularly 10 s or greater.
  • the device may have a current on/off ratio of approximately 10 9 .
  • the device may have a current on/off ratio at room temperature falling in one of the following ranges: 10 6 to 10 7 , 10 6 to 10 s , 10 6 to 10 9 ; 10 7 to 10 s , 10 7 to 10 9 ; and 10 8 to 10 9 .
  • the device may have a subthreshold swing at room temperature (298K) of 85mV dec 1 or less, particularly 75mV dec 1 or less, further particularly in the range 60 mV dec 1 to 75 mV dec -1 .
  • the device may have a subthreshold swing of 61 mV dec 1 .
  • the device may have a subthreshold swing falling in one of the following ranges: 60 mV dec 1 to 61 mV dec 1 , 60 mV dec 1 to 75 mV dec 1 , 60 mV dec 1 to 85 mV dec 1 ; 61 mV dec 1 to
  • the electronic device may be a field-effect transistor.
  • the electronic device may be a logic inverter.
  • the inverter may be capable of a gain greater than 100.
  • the inverter may be capable of a gain of greater than 5 with a power consumption less than 10 pW.
  • the material and/or device may be held under substantially vacuum conditions.
  • the device may be operated under substantially vacuum conditions.
  • the device may further comprise a vacuum chamber configured to contain the surface-modified TMD under substantially vacuum conditions. By substantially vacuum conditions, it is intended to mean pressures of lO 7 mbar or less.
  • the material and/or device may be held under a nitrogen atmosphere.
  • the material and/or device may be packaged with a nitrogen atmosphere.
  • the nitrogen atmosphere may be a substantially 100% nitrogen environment.
  • the material and/or device may comprise a package configured or arranged to exclude oxygen and water from contact with the surface-modified TMD.
  • the package may be configured to maintain the surface-modified TMD under vacuum.
  • the package may be configured to maintain the surface-modified TMD in a Nitrogen (N2) or other inert atmosphere.
  • a method of producing a material comprising: a transition metal dichalcogenide (TMD) comprising a surface, a least a portion of the surface being surface-modified with one or more Group 1 metals, wherein the one or more Group 1 metals comprise Cs and/or Rb, the method comprising: providing a transition metal dichalcogenide; and evaporating one or more Group 1 metals onto at least a portion of a surface of the transition metal dichalcogenide, wherein the one or more group 1 metals comprises Cs and/or Rb.
  • TMD transition metal dichalcogenide
  • a method of producing an electronic device comprising: a transition metal dichalcogenide (TMD), the TMD comprising first and second portions which are surface modified with one or more a Group 1 metals and a third portion which is not surface modified with one or more Group 1 metals; and first and second electrodes, wherein the first and second electrodes are in direct electrical contact with the first and second portions of the transition metal dichalcogenide, respectively, wherein the one or more Group 1 metals comprises Caesium and/or Rubidium, the method comprising: providing a layer of transition metal dichalcogenide and first and second electrodes on the surface of a substrate, such that the first and second electrodes are in electrical contact with the layer of transition metal dichalcogenide; evaporating one or more Group 1 metals onto a surface of first and second portions of the layer of transition metal dichalcogenide such that the one or more Group 1 metals has a thickness of at least 0.2nm, wherein the first and second portions of the layer of
  • Figure 1 shows a material according to an embodiment
  • Figure 2 shows a material according to an embodiment
  • Figures 3a and 3b show the 2H and IT' phases of WSe 2 , respectively;
  • Figure 4 shows a device according to an embodiment
  • Figure 5 shows a device according to an embodiment
  • Figure 6 shows a device according to an embodiment
  • Figure 7 shows a method of producing a material according to an embodiment
  • Figure 8a shows the line profile derived from the Atomic Force Microscope (AFM) image of a bilayer WSe 2 device
  • Figure 8b shows Raman measurements for the bilayer WSe 2 device
  • Figure 8c shows photoluminescence (PL) measurements for the bilayer WSe 2 device
  • Figure 9a shows a schematic representation of a bilayer WSe 2 device with surface modification
  • Figure 9b and Figure 9c show transport characteristics (l Sd -V g ) of a pristine bilayer WSe 2 FET;
  • Figure 9d shows transfer characteristic evolution of the WSe 2 FET as a function of Cs thickness
  • Figure 9f shows output curves (l Sd -V Sd ) for the pristine and 1.0 nm Cs-modified WSe 2
  • Figures 9g and 9h show temperature-dependent transport measurements for the Cs- modified WSe2 FET
  • Figure 9i shows the electrical conductance evolution of the bilayer WSe2 device after 1.0 nm Cs functionalization with respect to temperature at different Vg;
  • Figure 10 (a)-(d) show the results of in situ XPS and UPS of the bilayer WSe2 device;
  • Figure 11a shows the Photoluminescence (PL) spectra for a bilayer WSe2 flake before and after 0.1 nm Cs modification;
  • Figure lib shows Raman measurements for a bilayer WSe2 flake before and after 0.1 nm Cs modification
  • Figure 12a shows the evolution of transfer characteristics of a device according to an embodiment as a function of Cs thickness
  • Figure 12b shows the evolution of field-effect electron mobility for the device
  • Figures 12c and Figure 12d illustrate the output curves of the device under a range of gate voltages after and before Cs modification, respectively;
  • Figure 13a shows the Schottky barrier height of a hetero-phase transistor according to an embodiment
  • Figure 14a shows the transfer characteristic evolution of the device as a function of Cs thickness for a sandwich framework device according to an embodiment
  • Figure 14b shows the corresponding electron mobility versus Cs thickness
  • Figures 14c and 14d show output curves for the device before and after 1.0 nm Cs contact doping at different gate voltages ranging from 1 V to 5 V, respectively;
  • Figure 14e shows the transfer characteristic evolution of the device as a function of Cs thickness for another sandwich framework device according to an embodiment
  • Figure 15a shows transfer characteristics for a logic inverter according to an embodiment
  • Figure 15b shows output characteristics of the inverter
  • Figure 15c shows the extracted gain as a function of V IN at three different V DD for the inverter
  • Figure 15d shows the evolution of the power consumption of the inverter versus VDD
  • Figure 16 (a) shows output characteristics of a homogeneous WSe2 inverter according to an embodiment
  • Figure 16 (b) shows the output curve and corresponding voltage gain as a function of Vi N for the inverter.
  • references to "an embodiment / example”, “another embodiment / example”, “some embodiments / examples”, “some other embodiments / examples”, and so on, indicate that the embodiment(s) / example(s) so described may include a particular feature, structure, characteristic, property, element, or limitation, but that not every embodiment / example necessarily includes that particular feature, structure, characteristic, property, element or limitation. Furthermore, repeated use of the phrase “in an embodiment / example” or “in another embodiment / example” does not necessarily refer to the same embodiment / example.
  • Figure 1 shows a schematic representation of a material 1 according to an
  • the material comprises a layer 101 of a transmission metal dichalcogenide (TMD).
  • TMD transmission metal dichalcogenide
  • a layer 103 of one or more alkali metals i.e. the surface of the TMD is surface-modified with one or more alkali metals.
  • alkali metal is provided on the surface of two portions 105 of the TMD 101.
  • a portion 107 of the TMD, positioned between the regions 105 is not surface modified by alkali metal 103.
  • all of the TMD may be surface modified or only one or a greater number of portions of the TMD may be surface modified.
  • the thickness of the TMD is not particularly limited.
  • the TMD may be provided as a monolayer, a bilayer or as a multilayer, for example with a thickness of 3- 5 layers.
  • monolayer, bilayer or otherwise substantially two-dimensional forms of TMD may be advantageous for use in electronic devices, enabling low-profile devices to be provided.
  • the thickness of a TMD layer may be approximately determined by using a high- resolution optical microscope (e.g. the Nikon Eclipse LV100D), and further confirmed by Atomic Force Microscopy (AFM).
  • a high- resolution optical microscope e.g. the Nikon Eclipse LV100D
  • AFM Atomic Force Microscopy
  • the layer of alkali metal comprises Caesium and/or Rubidium. In an embodiment, the layer of alkali metal comprises a mixture of more than one alkali metal.
  • the layer of alkali metal may comprise Caesium and one or more element selected from Lithium, Sodium, Potassium and Rubidium.
  • the layer of alkali metal may comprise Rubidium and one or more element selected from Lithium, Sodium, Potassium and Caesium.
  • the thickness of the alkali metal layer is in the range 0.2nm to 5nm.
  • the thickness of the alkali metal may be in the range 0.4nm to 2nm.
  • the thickness of Caesium and/or Rubidium is in the range 0.2nm to
  • the thickness of Caesium and/or Rubidium may be in the range 0.4nm to 2nm. Thicknesses lying in this range may convey advantageous electronic properties to the surface-modified portions 105 of the TMD. These properties will be discussed further below.
  • the thickness of the alkali metal layer may be determined by weight, for example, using a quartz crystal microbalance.
  • X-ray photoelectron spectroscopy can also be employed to determine the thickness of the alkali metal.
  • XPS X-ray photoelectron spectroscopy
  • One such protocol suitable for determining the thickness of the alkali metal is given in the reference: Seah, M. P., & Dench, W. A. (1979), Quantitative electron spectroscopy of surfaces: A standard data base for electron inelastic mean free paths in solids. Surf. Interface Anal., 1(1), 2-11.
  • the TMD may be selected from M0S 2 , WS 2 , MoSe 2 and WSe 2 ,
  • the TMD may be selected from WSe 2 and MoTe 2 . More particularly, the TMD may be WSe 2 .
  • the alkali metal may comprise Caesium and/or Rubidium and the TMD may be selected from M0S 2 , WS 2 , MoSe 2 and WSe 2 , MoTe 2 , alkali metal-doped MoTe 2 , alkali metal-doped MoSe 2 , alkali metal-doped MoS 2 , alkali metal-doped WSe 2 , and alkali metal-doped WS 2 .
  • the alkali metal may comprise Caesium and/or Rubidium and the TMD may be selected from WSe 2 and MoTe 2 .
  • alkali metal may comprise Caesium and/or Rubidium and the TMD may comprise tungsten diselenide (WSe 2 ).
  • WSe 2 tungsten diselenide
  • Figure 2 is a schematic representation of WSe2 surface modified with Cs.
  • WSe2 is provided as a monolayer.
  • WSe2 may be provided as a bilayer or as a multilayer (for example, between 3 and 5 layers) material.
  • the portion 107 of TMD 101 which is not surface modified (if present) may have a 2H crystal structure.
  • the surface modification of the portion or portions 105 of TMD 101 may result in these portions having a different phase from the portion 107 which is not surface modified.
  • the portion or portions 105 may have a IT or IT' crystal structure, particularly a IT' crystal structure.
  • Figures 3a and 3b show the 2H and IT' crystal structures of WSe2 , respectively, with Tungsten atoms denoted by 301 and the Selenium atoms denoted by 303.
  • HRTEM High-resolution transmission electron microscope
  • the crystal structure of the TMD in the surface modified portions may depend on the thickness of the alkali metal layer 103 present on the surface.
  • the thickness of the alkali metal 103 may be chosen such that the surface-modified portions 105 of the TMD have a substantially IT or IT' crystal structure.
  • the TMD will exhibit IT or IT' behaviour at larger thicknesses of alkali metal, as shown in the experimental results discussed below.
  • the portion 107 of TMD 101 that is not surface modified may be a semi-conductor.
  • the surface modification of the portion or portions 105 may result in these portions exhibiting different electrical behaviour than the portion 107 of TMD that is not surface modified.
  • the portion, or portions 105 may exhibit metallic behaviour.
  • the portion, or portions 105 may exhibit n-type doping behaviour.
  • the electrical behaviour of the surface-modified and unmodified portions can be determined by examining the electrical transport properties of the material in accordance with methods well known in the art.
  • the electrical behaviour of surface modified portions of the TMD may depend on the thickness of the layer of alkali metal 103 on their respective surfaces.
  • the thickness of the layer of alkali metal may be selected such that the surface modified portions of the TMD 105 exhibit metallic or substantially metallic behaviour.
  • the surface-modified portions of TMD will exhibit metallic behaviour at larger thicknesses of alkali metal.
  • the thickness of the alkali metal may be selected in order to obtain other electrical behaviours, such as n-type doping behaviour relative to the non-surface modified TMD.
  • the thickness of the alkali metal is in the range 0.2nm to 5nm. In an embodiment, the thickness of the alkali metal may be in the range 0.4nm to 2nm. In this embodiment, the TMD may exhibit metallic behaviour and Ohmic contact behaviour.
  • the thickness of the alkali metal layer may be less than 0.4nm. In an embodiment, the thickness of the alkali metal layer may be between 0.2nm and 0.4nm. In this embodiment, the TMD may exhibit n-type doping behaviour of the surface-modified portions 105 of the TMD relative to the non-surface modified portions 107.
  • the thickness of Caesium and/or Rubidium is in the range 0.2nm to 5nm. In an embodiment, the thickness of Caesium and/or Rubidium may be in the range 0.4nm to 2nm. In this embodiment, the TMD may exhibit metallic behaviour and
  • the thickness of Caesium and/or Rubidium may be less than 0.4nm. In an embodiment, the thickness of Caesium and/or Rubidium may be between 0.2nm and 0.4nm. In this embodiment, the TMD may exhibit n-type doping behaviour of the surface-modified portions 105 of the TMD relative to the non-surface modified portions 107.
  • the material of Figure 1 may comprise a hetero-phase contact within the TMD layer at the interface 111 between the surface- modified and unmodified portions.
  • the hetero-phase contact is between a 2H phase in the portions which are not surface modified and a IT' phase in the portions which are surface modified.
  • materials according to these embodiments above may enable the exploitation of the both the semiconducting and metallic properties of two phases of TMD within the same material, namely both the advantageous ambipolar transport properties of the
  • materials according to embodiments described above may be advantageously deployed in electronic devices such as transistors by employing the metallic 11 /IT phased TMD as a buffer contact layer, thereby achieving 2H-1T/1T' hetero-phase transistors with low contact resistance and Ohmic behaviour.
  • 2H-1T/1T' heterophase contact in materials according to embodiments described above can i) avoid the lattice mismatch between the metal electrodes and the channel materials, which significantly enhances the carrier injection efficiency; ii) eliminate the Fermi level pinning effect originating from the surface states; iii) and create an atomically sharp interface, to avoid the chemical bond formation at the metal/semiconductor interface which can generate large strain in the crystal lattice.
  • alkali metals particularly Caesium and/or Rubidium
  • surface modification using alkali metals, particularly Caesium and/or Rubidium provides a facile, non-destructive method to achieve Ohmic contact for 2D materials, while maintaining ambipolar behaviour.
  • the alkali metal surface functionalization, particularly surface functionalization using Caesium and/or Rubidium can be performed in situ as will be discussed further below. Phase transition performed in this way also enables a high degree of control over the area of TMD which undergoes the phase transition.
  • the material according to the above described embodiments is employed in electronic device.
  • the material according to Figure 1 is employed in a Field effect transistor (FET).
  • FET Field effect transistor
  • FIG. 4 A schematic of a n-type FET device according to this embodiment is shown in Figure 4.
  • the transistor comprises a monolayer of TMD 101 arranged on a substrate 401.
  • the substrate is a p-type Silicon wafer with SiC>2 layer.
  • suitable substrates with insulating properties may be employed according to embodiments.
  • Source and drain electrodes 40S are provided on the substrate at either end of the TMD layer 101. The reason for this arrangement will become apparent from the discussion below. In the embodiment of Figure 4, the electrodes 40S comprise
  • a layer of photoresist material 405 is arranged on a portion the surface of the TMD layer 101.
  • a photoresist such as PMMA is employed due to its photoresist properties which are advantageously employed during the manufacturing process (see below).
  • the top layer of 405 may be any insulating material capable of encapsulating the TMD layer 101 to avoid modification with one or more alkali metals including Cs and/or Rb modification.
  • the photoresist or other insulating layer 405 may be omitted partially or completely.
  • the ends 105 of the TMD layer adjacent to the source and drain electrodes 403 are not covered by the dielectric 405, i.e. they are exposed.
  • a back-gate electrode (not shown) is arranged on the Silicon substrate.
  • an alkali metal layer 103 is present on the portion of the surface at either end of the TMD layer 101 which is not covered by the photoresist 405.
  • the TMD layer 101 is therefore surface modified at each end 105 but is unmodified in the centre.
  • the alkali metal layer comprises Caesium and/or Rubidium.
  • the TMD may be selected from MoS 2 , WS 2 , MoSe 2 and WSe 2 , MoTe2, alkali metal-doped MoTe2, alkali metal-doped MoSe2, alkali metal-doped M0S2, alkali metal-doped WSe2, and alkali metal-doped WS2.
  • the TMD may be selected from WSe2 and MoTe2. More particularly, the TMD may be WSe 2 .
  • the width of each of the portions of the TMD layer on which alkali metal is present is in the range 0.2-5 pm. In an embodiment, they have a width in the range 0.2-0.3 pm.
  • the TMD layer may be metallic at each end 105 but behave as a semiconductor towards the centre of the layer 107, in the region 107 positioned under the photoresist 405.
  • the TMD is employed as a n-type unipolar semiconductor.
  • the TMD has a IT or IT' phase at each end 105 adjacent to the source and drain electrodes 403 and a 2H phase in the portion 107 beneath the gate electrode which is not surface modified with alkali metal.
  • the TMD is therefore comprises a hetero-phase contact 111 and the device 4 is therefore a hetero-phase transistor.
  • the thickness of the alkali metal lies in the range 0.2nm to 5nm. In an embodiment, it lies in the range 0.4nm-2nm as this ensures good ohmic contact between the source and drain electrodes and the TMD, as will be shown in the Examples discussed below. In an embodiment, the thickness of the alkali metal is approximately l.Onm.
  • the alkali metal comprises Caesium and/or Rubidium and the thickness of the Caesium and/or Rubidium lies in the range 0.2nm to 5nm. In an embodiment, it lies in the range 0.4nm-2nm. In an embodiment, the thickness of the Caesium and/or Rubidium is approximately l.Onm. In an embodiment, the thickness of the alkali metal is chosen according to the desired properties of the device.
  • the thickness of the alkali metal is chosen such that there is substantially ohmic contact between the electrodes and the TMD layer, i.e. the current between the source and drain electrodes 403 has a substantially linear dependence on voltage.
  • the alkali metal comprises Caesium and/or Rubidium and the thickness of the alkali metal is such that the current on/off ratio of the device 4 at room temperature (298K) is at least 10 6 .
  • the current on/off ratio of the device is defined by the ratio of the on state current and off state current, i.e. it is the ratio of the current maximum and the current minimum in the transfer characteristic curve.
  • the alkali metal comprises Caesium and/or Rubidium and the thickness of the alkali metal is such that the field-effect electron mobility in the device at room temperature (298K) is at least 30 cm 2 V _1 s _1 .
  • the field effect electron mobility m of the device is derived from the linear regime of a transfer plot of current between source and drain electrodes (l Sd ) against potential difference across the source and drain electrodes (V Sd ) using the equation:
  • L and W denote the length and width of the conduction channel between source and drain electrodes 403, respectively, denotes the capacitance per unit area of the dielectric (i.e. Si0 2., in the present embodiment) and dl Sd /dV Sd represents the slope of the linear region in the transfer plot.
  • the electrodes 403 interface with the portions 105 of the TMD 101 which are surface modified, i.e. they are in direct electrical contact with these portions. However, the majority of the channel remains unmodified.
  • This arrangement therefore provides a field effect transistor based on the semi- conductor behaviour of the TMD, while simultaneously ensuring that the source and drain electrodes are in direct electrical contact with metallic portions of the TMD, thereby ensuring Ohmic contact between the with low contact resistance and avoiding a Schottky barrier at the contact between the electrodes and the semiconducting material.
  • the alkali metal functionalization described above according to embodiments, particularly functionalization using Caesium and/or Rubidium provides a simple method of achieving a high-performance transistor with high mobility, high current on/off ratio, low subthreshold swing.
  • the device of Figure 4 therefore is a high-quality device which has a fast on/off speed and is cost-efficient.
  • Figure 5 shows a sandwich framework FET according to an embodiment of the invention.
  • the transistor 5 comprises a mono-layer of TMD 101 with source and drain electrodes 403 provided on the substrate 401 at either end of the TMD layer 101 and a layer of photoresist material 405 arranged on a portion the surface of the TMD layer 101.
  • the photoresist 405 is PMMA, however, the person skilled in the art will appreciate that other materials could be employed according to embodiments.
  • the photoresist or other insulating layer 405 may be omitted partially or completely.
  • the TMD and source and drain electrodes are arranged on a dielectric layer 501.
  • the dielectric layer comprises a sheet of hexagonal boron nitride (h-BN).
  • h-BN hexagonal boron nitride
  • the thickness of the dielectric layer 501 may particularly be in the range 10-20nm. Thinner dielectric layers may induce undesirable quantum tunnelling into the device.
  • the dielectric layer is arranged on a bottom gate electrode layer 503.
  • the bottom gate electrode comprises a layer of Graphene.
  • the thickness of the bottom gate electrode layer may particularly be less than lOnm.
  • the sandwich arrangement described above is arranged on a silicon-based substrate 401 as described above in relation to the embodiment of Figure 4.
  • a layer of alkali metal is present on the portions 105 of the surface of the TMD at either end of the TMD layer 101 which are not covered by the photoresist 405.
  • the TMD layer 101 is therefore surface modified at each end 105 but is unmodified in its central portion 107.
  • the width of each of the portions 105 of the TMD layer on which alkali metal is present is in the range 0.2-5 pm. In an embodiment, they have a width in the range 0.2-0.3 pm.
  • the alkali metal layer employed in the embodiment of Figure 5 comprises Caesium and/or Rubidium.
  • the TMD may be selected from MoS 2 , WS 2 , MoSe 2 and WSe 2 , MoTe 2 , alkali metal-doped MoTe 2 , alkali metal-doped MoSe 2 , alkali metal-doped MOS 2 , alkali metal-doped WSe 2 , and alkali metal-doped WS 2 .
  • the TMD may be selected from WSe 2 and MoTe 2 . More particularly, the TMD may be WSe 2 .
  • the TMD layer may be metallic at each end 105 but behave as a semiconductor towards the centre of the layer 107, in the region 107 positioned under the photoresist 405.
  • the TMD is employed as a n-type unipolar semiconductor.
  • the TMD has a IT or IT' phase at each end 105 adjacent to the source and drain electrodes 403 and a 2H phase in the portion 107 beneath the photoresist 405 which is not surface modified with alkali metal.
  • the TMD is therefore comprises a hetero-phase contact 111 and the device 5 is therefore a hetero-phase transistor.
  • the thickness of the alkali metal lies in the range 0.2nm to 5nm. In an embodiment, the thickness of the alkali metal lies in the range 0.4nm to 2nm. In an embodiment, the thickness of the alkali metal is approximately l.Onm.
  • the thickness of the alkali metal is chosen according to the desired properties of the device.
  • the alkali metal comprises Caesium and/or Rubidium and the thickness of the alkali metal is such that there is ohmic contact between the electrodes and the TMD layer.
  • the alkali metal comprises Caesium and/or Rubidium and the thickness of the alkali metal is such that the current on/off ratio at room temperature (298K) of the device 5 is at least 10 7 , in particular in the range from 10 7 to 10 9 .
  • the current on/off ratio of the device is defined by the ratio of the on state current and off state current, i.e. it is the ratio of the current maximum and the current minimum in the transfer characteristic curve.
  • the alkali metal comprises Caesium and/or Rubidium and the thickness of the alkali metal is such that the field effect electron mobility in the surface modified potions of the TMD is at least 70 cm 2 V _1 s _1 .
  • the field effect electron mobility m of the device is derived from the linear regime of a transfer plot of current between source and drain electrodes (l Sd ) against potential difference across the source and drain electrodes (V Sd ) using the equation:
  • L and W denote the length and width of the conduction channel between source and drain electrodes 403, respectively
  • Q denotes the capacitance per unit area of the dielectric 501 (i.e. BN in the embodiment of Figure 5)
  • dl Sd /dV Sd represents the slope of the linear region in the transfer plot.
  • the alkali metal comprises Caesium and/or Rubidium and the thickness of the alkali metal is chosen such that subthreshold swing is less than 85 mV dec -1 , particularly in the range 60 to 85 mV dec -1 .
  • the subthreshold swing of the device is determined from d ⁇ / g /d ( log/ Sd ), where V g is the gate voltage and l Sd is the current between source and drain electrodes.
  • Figure 6 shows a transistor-based logic inverter according to an embodiment.
  • the device comprises a back-gate electrode 503 providing the input signal (Vm) and a dielectric layer 501 arranged on a substrate 401 as described in association with the device of Figure 4.
  • the device further comprises three parallel electrodes 605, 607, 609 arranged on the dielectric layer 501, serving as the power supply (VDD; 605), output signal (VOUT; 607), and ground (GND; 609), respectively, between which a layer of TMD 101 forms two channels 601 and 603 in series.
  • VDD power supply
  • VOUT output signal
  • GND ground
  • a Photoresist 405 is arranged to completely cover the TMD of one channel, 601 such that no surface modification of the TMD is present in this channel therefore enabling this channel to retain the p-type dominated ambipolar behaviour of the TMD.
  • the other channel 603 is only partially covered by the PMMA photoresist 405 with alkali-metal surface modification at each end, adjacent to the corresponding electrodes 605.
  • this channel behaves as an n-type transistor as described above in relation to Figures 4 and 5.
  • the photoresist layers 405 may be completely or partially omitted from either or both of the channels.
  • the embodiment of Figure 6 corresponds to a TMD inverter with two channels in series.
  • unipolar hetero-phase n-type transistor can be obtained.
  • another channel is fully covered by the PMMA photoresist, where the p-type dominated ambipolar transport behaviour is retained.
  • multilayer h-BN and graphene are used as the dielectric layer and bottom gate electrode, respectively, however the skilled person will appreciate that other suitable materials could be employed according to embodiments.
  • the graphene provides the input signal (VI N ), and the three parallel electrodes on the TMD flake serve as the power supply (VDD), output signal (VOUT), and ground (GND), respectively.
  • the thickness of the alkali metal layer is chosen according to the desired properties of the n-type channel. In an embodiment, the thickness of the alkali metal is in the range 0.2nm to 5nm, particularly 0.4nm to 2nm. In an embodiment, the thickness of the alkali metal is approximately l.Onm.
  • the alkali metal comprises Caesium and/or Rubidium and the thickness of the alkali metal may be such that the gain (-d ⁇ /ou T /d ⁇ /i N ) achievable by the inverter 6 is greater than 100 when VDD 2.5 V.
  • inverters according to this embodiment have high voltage gain, thereby enabling fast logic state inversion, high accuracy and low power consumption.
  • Figure 7 shows a method of producing the material of Figure 1 according to an embodiment. It is also suitable for producing the relevant layers in the devices in Figures 4, 5 and 6.
  • the TMD 101 is provided.
  • the layer may be a monolayer, a bilayer, or comprise three or more layers according requirements of the final material.
  • Bulk TMD crystals are commercially available, for example from HQ-Graphene.
  • Monolayer and bilayer TMD can be produced from bulk TMD via, for example, mechanical exfoliation using Scotch tape.
  • the TMD may be transferred to a suitable substrate such as Silicon dioxide prior to performing step S70S.
  • electrodes may be patterned onto the TMD using electron beam lithography prior to performing step S703.
  • steps S703 to S707 may be performed in situ in an electronic device, such as those described above in relation to Figures 4, 5 and 6.
  • the electrodes may be thermally evaporated onto the substrate, for example by thermally evaporating Pd and/or Au. Excess metal may then be removed from the sample, for example by soaking in acetone according to procedures well known in the art. The method then proceeds to step S703.
  • step S703 the surface 109 of the TMD layer is coated with a barrier layer 405 of photoresist such as PMMA.
  • the barrier layer is applied to the TMD layer using spin-coating.
  • step S705 electron beam lithography (EBL) is employed to remove the photoresist on the portions 105 of the TMD layer to be surface modified. In the embodiment of Figure S705, these are the portions at the edge of the layer.
  • EBL electron beam lithography
  • step S707 a layer of one or more alkali metals 103 is evaporated directly onto the
  • the TMD layer In an embodiment, this is done under vacuum from one or more alkali metal getters. Suitable getters are commercially available, for example from SAES.
  • the one or more alkali metals comprise Caesium and/or Rubidium and a layer of Caesium and/or Rubidium is evaporated onto the TMD layer from, for example, a Caesium and/or Rubidium getter.
  • the alkali metal getter is heated in a high-vacuum chamber with the TMD in order to achieve evaporation of the alkali metal onto the exposed surfaces of the TMD.
  • Evaporation of the alkali metal from the getter may be achieved, for example by supplying a DC current to a feedthrough into the vacuum chamber.
  • the vacuum chamber should be under a high vacuum condition of less than 10 7 mbar.
  • Such pressures can be achieved by pumping a suitable chamber with a turbopump.
  • Turbopumps suitable for achieving a high vacuum are commercially available, for example from Pfeiffer Vacuum GmbH.
  • Components for a chamber suitable for supporting such a vacuum are also commercially available, for example, from UHV Design.
  • the photoresist 405 acting as a barrier layer, film growth of the alkali metal is restricted to the exposed portions 105 and 105 of the TMD layer.
  • the thickness of the alkali metal can be monitored by monitoring the weight of the material during evaporation, for example using a quartz crystal microbalance (QCM), thereby enabling it to be controlled according to the desired properties of the material or device, as appropriate.
  • QCM quartz crystal microbalance
  • Quartz crystal microbalances (and corresponding feedthroughs) suitable for use in accordance with embodiments are commercially available, for example from
  • the vacuum chamber is configured such that the QCM is positioned so as to protect the sample from alkali metal deposition while the evaporation rate from the alkali metal getter is brought to required levels. Once it achieves the desired rate, the QCM is moved out of the way in order to enable alkali metal deposition. Once the desired evaporation onto the sample is complete, the QCM is moved back into position to protect the sample from further deposition.
  • a suitable in situ vacuum characterization system for use in accordance with embodiments is given in Lei, B., et al. (2017). Nano Research, 10(4), 1282-1291.
  • the photoresist layer may or may not be removed following the application, according to desired use.
  • the method of Figure 7 provides a method of producing the materials and devices according to embodiments which may be performed in situ and easily integrated with conventional CMOS processes, thereby enabling straightforward integration into the fabrication process.
  • This method provides an effective, damage- free and non-volatile procedure for realizing phase transitions in TMDs such as WSe2.
  • Scotch tape was used to mechanically exfoliate WSe2 flakes from bulk WSe2 crystals (commercially obtained from HQ-graphene), and then quickly transferred onto a degenerately p-type doped silicon substrate with S00 nm SiC>2.
  • Monolayer and bilayer WSe2 were found by utilizing a high-resolution optical microscope (Nikon Eclipse LV100D), and further confirmed by AFM and Raman measurements.
  • PMMA photoresist commercially obtained from PMMA
  • MicroChem was subsequently spin coated on the silicon substrate for the conventional e-beam lithography (EBL) process. After patterning the source and drain electrodes on WSe2, 5 nm Pd and 60 nm Au were thermally evaporated onto the substrate. The sample was then soaked in acetone for about 1 hour to lift off excess metal.
  • EBL e-beam lithography
  • Figures 8a-c show results for the bilayer WSe2 device, where the WSe2 flakes were mechanically exfoliated onto a degenerately p-type doped silicon wafer with a 300 nm SiC>2 layer. Standard lithography was then carried out to define the WSe2 channel followed by the metal deposition of Pd/Au.
  • Fig. 8a shows the line profile derived from the Atomic Force Microscope (AFM) image of the device. It reveals that the thickness of the WSe2 flake is around ⁇ 1.7 nm, indicating its bilayer nature.
  • Raman and photoluminescence (PL) measurements ( Figures 8b and 8c, respectively) were employed for further verification.
  • An Agilent 2912A precision source/measure unit was utilized to perform the related electrical measurements.
  • Caesium was evaporated in situ from a SAES Getter directly to the devices and a quartz crystal microbalance (QCM) (commercially obtained from Testbourne Ltd) was employed to calibrate the nominal thickness.
  • QCM quartz crystal microbalance
  • the sample was loaded onto the sample stage through a flexible fast entry door. After several hours' pumping, the sample was pulled back to a particular position for in situ deposition, where a thermal effusion cell was equipped to evaporate dopant.
  • the quartz crystal microbalance (QCM) was placed in front of the sample stage to precisely monitor the deposition rate. Once the Cs evaporate rate was confirmed, the QCM was shifted upwards to allow Cs to deposit onto the sample. After the evaporation, the QCM was shifted downward to block Cs. The Cs was evaporated via a DC current (3.8
  • Figure 9a shows a schematic representation of the bilayer WSe2 923 device in a FET structure with Pd/Au (5nm/60 nm) as the metal contacts 921 and 300 nm S1O2 layer as the dielectric.
  • Figure 9b and Figure 9c show the transport characteristics (l Sd -V g ) of the pristine bilayer WSe 2 FET in high vacuum condition (10 7 mbar). The results clearly reveal a hole- dominated ambipolar transport behaviour, where gate voltage sweeps from -80 V to
  • Figure 9d shows Transfer characteristic evolution of the WSe 2 FET as a function of Cs thickness following in situ deposition of Cs on the device as described above.
  • the thicknesses shown are Onm (901), O.Olnm (903), 0.07nm (905), 0.19nm (907), 0.4nm (909) and 1.0 nm (911).
  • Two distinct stages can be observed, including i) a significant n-type doping stage with strongly enhanced on-current in the electron transport regime under the low Cs doping level (Cs nominal thickness ⁇ 0.2 nm); and ii) the WSe 2 device exhibits a nearly gate independent transport behaviour when the Cs nominal thickness is above 0.4 nm, indicating a semiconductor to metal phase transition.
  • Figure 9f shows output curves (l Sd -V Sd ) for the pristine (915) and 1.0 nm (913) Cs- modified WSe2 FET at different gate voltage, V g , from 0 to 50 V.
  • V g gate voltage
  • the pristine WSe2 device exhibits a Schottky contact behaviour, while ohmic contact feature is identified after 1.0 nm Cs decoration.
  • the large enhancement of l Sd reveals the reduction of contact and channel resistances, originating from the semiconductor to metal phase transition.
  • the semiconductor to metal phase transition in the bilayer WSe2 device was further characterised by temperature-dependent transport measurements.
  • Figure 9i shows the electrical conductance evolution of the bilayer WSe2 device after 1.0 nm Cs functionalization with respect to temperature at different Vg from -80 V to 50 V. The conductance progressively decreases as the temperature increases under all gate voltages, clearly revealing the metallic feature of the Cs-modified WSe2 flake and further corroborating the semiconductor to metal phase transition induced by Cs surface functionalization.
  • Figure 10 shows UPS spectra evolution at low kinetic energy region
  • Figure 10(b) shows XPS core level spectra of W 4f as a function of Cs thickness on WSe2
  • Figure 10(c) shows XPS core level spectra of Se 3d as a function of Cs thickness on WSe2
  • Figure 10(d) shows UPS valence band spectra near the Fermi level region.
  • Pristine WSe2 is denoted by 1001, O.Olnm Cs by 1003, O.lOnm Cs by 1005, 0.20nm Cs by 1007, 0.40nm Cs by 1009, and l.OOnm Cs by 1011 in all figures.
  • f denotes the work function
  • DE denotes the energy difference.
  • the work function (WF) of the pristine WSe2 is measured to be ⁇ 4.02 eV, which sharply dropped to ⁇ 2.2 eV after 1.0 nm Cs decoration.
  • the decrease of WF implies the significant electron transfer from Cs to WSe2 at the Cs/WSe2 interface, resulting from the ultralow WF of Cs ( ⁇ 2.14 eV).
  • Figures 10(b) and 10(c) show the evolution of W 4f and Se 3d core level binding energy as a function of Cs thickness, respectively.
  • the electron doping effect of Cs on WSe2 makes the Fermi level of WSe2 move towards its conduction band and hence the binding energy of W 4f and Se 3d slightly increases by 0.1 eV and 0.15 eV, respectively.
  • the W 4f and Se 3d core levels move towards the lower binding energy by ⁇ 0.3 eV and ⁇ 0.35 eV, respectively. This is consistent with previous reports of K-functionalization and hence electron-doping induced
  • the valence band spectra shown in Figure 10(d) can further validate the metallization of the heavily doped WSe2.
  • Cs thickness ⁇ 0.4 nm At low surface modification levels (Cs thickness ⁇ 0.4 nm), a downward band bending of the valence band is observed due to the electron doping.
  • Cs thickness is above 0.4 nm, a sharp peak emerges around the Fermi level, clearly revealing the metal-like features, further confirming the semiconductor to metal phase transition.
  • Figure 11a shows the Photoluminescence (PL) spectra for the bilayer WSe2 flake before
  • Figure lib shows the Raman spectra of the pristine, 0.1 nm and 1.0 nm Cs-modified WSe2.
  • IT and IT' are metallic.
  • Previous reports suggest that the IT phase of group VI TMDs is unstable and spontaneously transforms to IT' phase with energy relaxation. Therefore, without wishing to be bound by theory, it is proposed that the metallic phase of the WSe2 after Cs doping is IT'.
  • phase transition of the bilayer WSe2 from the semiconducting 2H phase to IT' metallic phase.
  • the B 1 2g peak totally vanishes, and five new peaks emerge in the low wavenumber regime, at around ⁇ 93, 114, 227, 242 and 260 cm . These new peaks correspond to the characteristic peaks of the WSe2 in IT' phase. Therefore, without wishing to be bound by theory, the phase transition of Cs-modified WSe2 observed here can be assigned to a 2H to IT' phase transition.
  • the pristine WSe2 device was first fabricated in accordance with the method described above.
  • PMMA photoresist was spin-coated again and a second EBL process was performed to expose desired area around the contact after the lift off of the excess metal.
  • the device was then loaded into a vacuum system as previously described for Caesium evaporation for electrical characterization.
  • Fig. 12a exhibits the evolution of the transfer characteristics as a function of Cs thickness, with thicknesses of Onm (1301), 0.05nm (1303), 0.20nm (1305), 0.50nm (1307) and l.OOnm (1309).
  • the WSe2 flake is n-type doped at low Cs deposition level. Further increasing Cs thickness to a high level induces the phase transition in the exposed region, leading to the IT' contact.
  • the saturation current with IT' phase contact is approximately 2 orders of magnitude higher than that of the pristine device with Pd contact, leading to a giant gate modulation effect as well as a high current on/off ratio of ⁇ 10 7 .
  • the field-effect electron mobility is also dramatically improved from 0.6 to
  • Figures 12c and Figure 12d illustrate the output curves of the device under gate voltages 0V (1311), 20V (1313), 40V (1315) and 50V (1317) before ( Figure 12d) and after ( Figure 12c) 1.0 nm Cs functionalization.
  • the pristine transistor exhibits a clear
  • the Schottky barrier height of the hetero-phase transistor was further investigated, and the results are shown in Figure ISa as a function of gate voltage V g .
  • the SB in the hetero-phase transistor is determined to be as low as ⁇ 9.4 meV for the electron-transport.
  • Such negligible SB can significantly enhance the electron injection into the semiconductor, resulting in true Ohmic contact behaviour under high electrostatic doping.
  • the width normalized contact resistance (R c ) was extracted via the transfer length method (TLM).
  • TLM transfer length method
  • a series of WSe 2 (5-layer) transistors with different channel lengths were employed for the measurement. To ensure accuracy, it was assumed that the channel segments covered by the metal contact have no contribution to the overall channel length.
  • a very small bias ⁇ 10 mV was employed in order to avoid an underestimation of the R c .
  • the R tot is linearly fitted, where the y intercept yields the total contact resistance (2R C ) and the slope represents the sheet resistance (R Sh ) of the channel.
  • Figure 14a shows the transfer characteristic evolution of the device as a function of Cs thickness. Results for Cs thicknesses of O.Onm (1401), O.Olnm (1403), 0.08nm (1405),
  • Figures 14c and 14d show output curves for the device before ( Figure 14c) and after 1.0 nm (Figure 14d) Cs contact doping at different gate voltages 0V (1415), IV (1417), 2V (1419), 3V (1421), 4V (1423) and 5V (1425).
  • the output curves of the pristine WSe device are nonlinear even at a high electrostatically doping level (Vg ⁇ 5V), illustrating a clear Schottky contact behaviour.
  • Vg ⁇ 5V electrostatically doping level
  • the current is largely improved by over 2 orders of magnitude at each gate voltage.
  • the output curves are almost linear especially at the low V Sd regime, suggesting a nearly-ideal ohmic contact.
  • FIG. 14e shows the transfer characteristic evolution as a function of Cs thickness for this second device.
  • the current on/off ratio of the Cs doped device was found to be even higher at ⁇ 10 9 .
  • the subthreshold swing (SS) defined was measured to be 61 mV dec -1 .
  • a device according to the embodiment of Figure 6 was fabricated as described above with regard to the FET sandwich device but modified to obtain a contact exposure channel and a full PMMA covered channel. As before, the device was loaded into a high vacuum chamber for further measurements.
  • Figure 15a shows transfer characteristics for N-FET 1501 and P-FET 1503
  • unipolar hetero-phase n-type transistor can be obtained through spatially controlling the exposed regions near the metal electrodes of one WSe2 channel, while p-type dominated ambipolar transport behaviour is retained in the other channel which is fully covered by the PMMA photoresist.
  • V DD 1 V (1505), 2 V (1507), and 2.5 V (1509) respectively.
  • the inverter experiences a 'high state' (high VOUT), 'steep slope' (sharp decrease of VOUT), and a 'low state' (low VOUT) sequentially.
  • Figure 15c shows the extracted gain as a function of VIN at three different VDD
  • Figure 15d shows the evolution of the power consumption of the device versus ⁇ / DD from 0.5 V to 2.5 V.
  • the results above show the realisation of a semiconducting-to-metallic (2H to IT') phase transition in WSe2 via in situ Cs surface functionalization.
  • the phase transition is firstly revealed by the in situ electrical characterization of the WSe2 FET.
  • the Cs- functionalized WSe2 transistor exhibits gate-independent transport behaviour with nearly 7 orders of magnitude enhancement in electrical conductance.
  • the 2H to IT' phase transition originates from the giant electron doping from Cs to WSe2.
  • a 2H-1T' hetero-phase WSe2 transistor is obtained with remarkably enhanced field-effect electron mobility, increased by nearly 50 times, reaching up to ⁇ 70 cm 2 V _1 s _1 .
  • the device demonstrates an ultrahigh current on/off ratio ⁇ 10 8 and low SS ⁇ 75 mV dec -1 , enabling the realization of high performance WSe2 logic inverter with ultralow power consumption of ⁇ 5 pW and a high voltage gain of ⁇ 106, higher than all the 2D-material- based homo-inverters.
  • alkali metal functionalization induced phase transition particularly Cs metal functionalization induce phase transition in TMDs provides a simple method to achieve high performance TMD hetero-phase transistor and logic inverter.
  • in situ alkali-metal surface modification particularly in situ Cs surface modification, has been demonstrated as an effective approach to induce the semiconducting to metallic phase transition in 2H TMDs, which offers the opportunity to realize a high performance 2H-1T' hetero-phase TMD transistor via spatially controlling the phase transition region.
  • TMD transition metal dichalcogenide
  • TMD of 1 or 2 wherein the Group 1 alkali metal is selected from lithium, sodium, potassium, rubidium, caesium or francium.
  • TMD any of 1 to 3, further including a second portion, wherein the first portion has a different phase structure to the second portion.
  • TMD any of 1 to 4, wherein the first portion has a metallic octahedral (IT') phase structure.
  • TMD any of 1 to 5, wherein a thickness of the Group 1 alkali metal in the first portion is from about 0.2 nm to about 10 nm.
  • the TMD of any of 1 to 6, the TMD is selected from M0S2, WS2, MoSe2 and WSe2,
  • An electronic device including: a layer of a transition metal dichalcogenide (TMD) including a first portion, wherein the first portion is surface modified with a Group 1 alkali metal; and a pair of electrodes connected to the layer of the TMD.
  • TMD transition metal dichalcogenide
  • the electronic device of 8 having an electrical conductance of at least 4 times to that of a control.
  • SS subthreshold swing
  • the electronic device of any of 8 to 15, the electronic device is a logic inverter or a field effect transistor.
  • An electronic circuit comprising the electronic device of any of 8 to 16.

Abstract

A material (1) comprising: a transition metal dichalcogenide (107) comprising a surface (109), a least a portion of the surface being surface-modified with one or more Group 1 metals (103), wherein the one or more Group 1 metals comprise Caesium and/or Rubidium.

Description

TRANSITION METAL DICHALCOGENIDES AND USES THEREOF
Cross Reference to Related Application(s)
The present disclosure claims the benefit of Singapore Patent Application No.
10201906808T, which is incorporated in its entirety by reference herein.
Technical Field
The present invention relates to transition metal dichalcogenides, particularly the use of transition metal dichalcogenides in electronic devices.
Background
Two-dimensional (2D) transition metal dichalcogenides (TMDs) have been established as promising building blocks for the next-generation nano electronic devices, showing great potential to extend the scaling limits in silicon-based complementary metal oxide semiconductor (CMOS) field-effect transistors (FETs). As one of the most studied TMD materials, tungsten diselenide (\NSe2) possesses three dominant polymorphs, including the semiconducting trigonal prismatic (2H phase), metallic octahedral (IT phase), and distorted octahedral (IT' phase). 2H
semiconducting WSe2 demonstrates great advantages in complementary logic devices, arising from its ambipolar transport property with high current on/off ratio. However, similar to other TMDs, 2H WSe2-based transistors generally suffer from high Schottky barrier height and high contact resistance at the metal contact/WSe2 interface, which degrades the performance of WSe2 FETs, including the electrical conductance and carrier mobility.
To reduce contact resistance in WSe2-based FETs, various methods are currently being explored, such as metal contact engineering, ionic liquid gating, photo-doping, and surface charge transfer doping.
Several approaches have also been employed to induce 2H to 1T/1T' phase transition in TMDs, such as alkali metal intercalation, strain engineering, ionic liquid gating and laser irradiation. However, alkali metal intercalation requires soaking the TMD in a chemical liquid such as n-butyllithium (n-BuLi) or tert-butyl lithium (t-BuLi) which is both complicated and time-consuming. Strain engineering and ionic liquid gating require harsh conditions to be successful. High energy laser irradiation results in undesirable and irreversible damage to samples. There is a continuing need to improve the performance of electronic devices based on
TMD materials.
Summary
In a first aspect, a material is provided, the material comprising: a transition metal dichalcogenide (TMD) comprising a surface, a least a portion of the surface being surface-modified with one or more Group 1 metals, wherein the one or more Group 1 metals comprise Cs and/or Rb.
A transition metal dichalcogenide (TMD) has the general formula MX2, where M is a transition metal atom and X is a chalcogen atom.
The transition metal dichalcogenide may comprise one or more of M0S2, WS2, MoSe2 and WSe2, MoTe2, alkali metal-doped MoTe2, alkali metal-doped MoSe2, alkali metal- doped M0S2, alkali metal-doped WSe2, and alkali metal-doped WS2. The transition metal dichalcogenide may comprise one or more of WSe2 and/or MoTe2. The transition metal dichalcogenide may comprise WSe2.
The TMD may comprise one or more impurities. The transition metal dichalcogenide may be substantially two-dimensional (2-D). A portion of the transition metal dichalcogenide may be substantially two-dimensional. A portion or all of the transition metal dichalcogenide may have a thickness of between 1 and 5 layers. A portion or all of the transition metal dichalcogenide may comprise a mono-layer or a bi-layer.
'Surface modified' or 'surface modification' refers to a surface of a material being changed by bringing physical, chemical or biological characteristics different from the ones originally found on the surface of a material. For example, a surface is modified if it is functionalised by adding new functions, features, capabilities, or properties to a material. The modification changes the surface chemistry of the material. In this regard, the modification or functionalisation resides only on the surface and does not penetrate the material. In contrast, 'doping' refers to the intentional introduction of impurities into an intrinsic semiconductor for the purpose of modulating its electrical, optical and structural properties. In this regard, the impurity resides within the semiconductor.
One portion of the surface of the TMD may be surface-modified and one portion may not be surface modified. All of the surface may be surface modified. A plurality of portions of the surface may be surface-modified. The surface may be modified by a mixture of two or more alkali metals. The surface may be modified only by Caesium and/or Rubidium. One portion of the TMD may be surface modified with Caesium and/or Rubidium and another portion may be surface modified with another alkali metal. The one or more alkali metals may comprise one or more impurities.
The one or more alkali metals may comprise Caesium and one or more element selected from Lithium, Sodium, Potassium and Rubidium.
The one or more alkali metals may comprise Rubidium and one or more element selected from Lithium, Sodium, Potassium and Caesium.
The alkali metal may be in direct contact with the surface of the TMD. There may be a direct interface between the alkali metal and the TMD.
The one or more Group 1 metals may form a layer on the surface of the TMD. The layer of Group 1 metal may have a thickness of greater than or equal to 0.2nm. The layer may have a thickness of less than or equal to 5.0nm. The layer of Group 1 metal may have a thickness of between 0.4nm and 2.0nm. For the avoidance of doubt, it is explicitly contemplated that where a number of numerical ranges related to the same feature are cited herein, that the end points for each range are intended to be combined in any order to provide further contemplated (and implicitly disclosed) ranges. Thus, in relation to the above related numerical ranges, there is disclosed:
O.Onm to O.Olnm, O.Onm to 0.05nm, O.Onm to 0.07nm, O.Onm to 0.08nm, O.Onm to O.lnm, O.Onm to 0.19nm, O.Onm to 0.20nm, O.Onm to 0.4nm O.Onm to 0.5nm, O.Onm to 0.6nm O.Onm to l.Onm, O.Onm to 2.0nm, O.Onm to 5.0nm;
O.Olnm to 0.05nm, O.Olnm to 0.07nm, O.Olnm to 0.08nm, O.Olnm to O.lnm, O.Olnm to 0.19nm, O.Olnm to 0.20nm, O.Olnm to 0.4nm O.Olnm to 0.5nm, O.Olnm to 0.6nm O.Olnm to l.Onm, O.Olnm to 2.0nm, O.Olnm to 5.0nm;
0.05nm to 0.07nm, 0.05nm to 0.08nm, 0.05nm to O.lnm, 0.05nm to 0.19nm, 0.05nm to 0.20nm, 0.05nm to 0.4nm 0.05nm to 0.5nm, 0.05nm to 0.6nm 0.05nm to l.Onm, 0.05nm to 2.0nm, 0.05nm to 5.0nm; 0.07nm to 0.08nm, 0.07nm to O.lnm, 0.07nm to 0.19nm, 0.07nm to 0.20nm, 0.07nm to 0.4nm 0.07nm to 0.5nm, 0.07nm to 0.6nm 0.07nm to l.Onm, 0.07nm to 2.0nm, 0.07nm to 5.0nm;
0.08nm to O.lnm, 0.08nm to 0.19nm, 0.08nm to 0.20nm, 0.08nm to 0.4nm 0.08nm to 0.5nm, 0.08nm to 0.6nm 0.08nm to l.Onm, 0.08nm to 2.0nm, 0.08nm to 5.0nm; O.lOnm to 0.19nm, O.lOnm to 0.20nm, O.lOnm to 0.4nm, O.lOnm to 0.5nm, O.lOnm to
0.6nm O.lOnm to l.Onm, O.lOnm to 2.0nm, O.lOnm to 5.0nm; 0.19nm to 0.20nm, 0.19nm to 0.4nm, 0.19nm to 0.5nm, 0.19nm to 0.6nm 0.19nm to l.Onm, 0.19nm to 2.0nm, 0.19nm to 5.0nm;
0.2nm to 0.4nm, 0.2nm to 0.5nm, 0.2nm to 0.6nm 0.2nm to l.Onm, 0.2nm to 2.0nm, 0.2nm to 5.0nm; 0.4nm to 0.5nm, 0.4nm to 0.6nm, 0.4nm to l.Onm, 0.4nm to 2.0nm, 0.4nm to 5.0nm;
0.5nm to 0.6nm, 0.5nm to l.Onm, 0.5nm to 2.0nm, 0.5nm to 5.0nm;
0.6nm to l.Onm, 0.6nm to 2.0nm, 0.6nm to 5.0nm; l.Onm to 2.0nm, l.Onm to 5.0nm; and
2.0nm to 5.0nm.
The surface modified portion or portions of the TMD may be in a different phase to the portion or portions of the TMD that are not surface modified. The surface-modified portion or portions may be in a IT or IT' phase and the portion or portions that are not surface-modified may be in a 2H phase.
As is known in the art, 7H' refers to the hexagonal phase structure and ΊT" refers to the metallic monoclinic or octahedral phase structure. In an aspect, an electronic device comprising a transition metal dichalcogenide (TMD) is provided, the TMD comprising first and second portions which are surface modified with one or more a Group 1 metals and a third portion which is not surface modified with one or more Group 1 metals; and first and second electrodes, wherein the first and second electrodes are in direct electrical contact with the first and second portions of the transition metal dichalcogenide, respectively, wherein the one or more Group 1 metals comprises Caesium and/or Rubidium.
The transition metal dichalcogenide may comprise one or more of M0S2, WS2, MoSe2 and WSe2, MoTe2, alkali metal-doped MoTe2, alkali metal-doped MoSe2, alkali metal- doped M0S2, alkali metal-doped WSe2, and alkali metal-doped WS2. The transition metal dichalcogenide may comprise one or more of WSe2 and/or MoTe2. The transition metal dichalcogenide may comprise WSe2.
The one or more alkali metals may comprise Caesium and the transition metal dichalcogenide may comprise WSe2.
The TMD may comprise one or more impurities. The transition metal dichalcogenide may be substantially two-dimensional (2-D). A portion of the transition metal dichalcogenide may be substantially two-dimensional. A portion or all of the transition metal dichalcogenide may have a thickness of between 1 and 5 layers. A portion or all of the transition metal dichalcogenide may comprise a mono-layer or a bi-layer.
The surface may be modified by a mixture of two or more alkali metals. The surface may be modified only by Caesium and/or Rubidium. One portion of the TMD may be surface modified with Caesium and/or Rubidium and another portion may be surface modified with another alkali metal. The one or more alkali metals may comprise one or more impurities.
The one or more Group 1 metals may form a layer on the surface of the TMD. The layer of Group 1 metal may have a thickness of greater than or equal to 0.2nm. The layer may have a thickness of less than or equal to 5.0nm. The layer of Group 1 metal may have a thickness of between 0.4nm and 2.0nm.
The thickness of the more or more alkali metals may fall into one of the following ranges: O.Onm to O.Olnm, O.Onm to 0.05nm, O.Onm to 0.07nm, O.Onm to 0.08nm, O.Onm to O.lnm, O.Onm to 0.19nm, O.Onm to 0.20nm, O.Onm to 0.4nm O.Onm to 0.5nm,
O.Onm to 0.6nm O.Onm to l.Onm, O.Onm to 2.0nm, O.Onm to 5.0nm; O.Olnm to 0.05nm, O.Olnm to 0.07nm, O.Olnm to 0.08nm, O.Olnm to O.lnm, O.Olnm to 0.19nm, O.Olnm to 0.20nm, O.Olnm to 0.4nm O.Olnm to 0.5nm, O.Olnm to 0.6nm O.Olnm to l.Onm, O.Olnm to 2.0nm, O.Olnm to 5.0nm; 0.05nm to 0.07nm, 0.05nm to 0.08nm, 0.05nm to O.lnm, 0.05nm to 0.19nm, 0.05nm to 0.20nm, 0.05nm to 0.4nm 0.05nm to 0.5nm, 0.05nm to 0.6nm 0.05nm to l.Onm, 0.05nm to 2.0nm, 0.05nm to 5.0nm;
0.07nm to 0.08nm, 0.07nm to O.lnm, 0.07nm to 0.19nm, 0.07nm to 0.20nm, 0.07nm to 0.4nm 0.07nm to 0.5nm, 0.07nm to 0.6nm 0.07nm to l.Onm, 0.07nm to 2.0nm, 0.07nm to 5.0nm; 0.08nm to O.lnm, 0.08nm to 0.19nm, 0.08nm to 0.20nm, 0.08nm to 0.4nm 0.08nm to 0.5nm, 0.08nm to 0.6nm 0.08nm to l.Onm, 0.08nm to 2.0nm, 0.08nm to 5.0nm; O.lOnm to 0.19nm, O.lOnm to 0.20nm, O.lOnm to 0.4nm, O.lOnm to
0.5nm, O.lOnm to 0.6nm O.lOnm to l.Onm, O.lOnm to 2.0nm, O.lOnm to 5.0nm;
0.19nm to 0.20nm, 0.19nm to 0.4nm, 0.19nm to 0.5nm, 0.19nm to 0.6nm 0.19nm to l.Onm, 0.19nm to 2.0nm, 0.19nm to 5.0nm; 0.2nm to 0.4nm, 0.2nm to 0.5nm, 0.2nm to 0.6nm 0.2nm to l.Onm, 0.2nm to 2.0nm, 0.2nm to 5.0nm; 0.4nm to 0.5nm, 0.4nm to 0.6nm, 0.4nm to l.Onm, 0.4nm to 2.0nm, 0.4nm to 5.0nm; 0.5nm to 0.6nm, 0.5nm to l.Onm, 0.5nm to 2.0nm, 0.5nm to 5.0nm; 0.6nm to l.Onm, 0.6nm to 2.0nm, 0.6nm to 5.0nm; l.Onm to 2.0nm, l.Onm to 5.0nm; and 2.0nm to 5.0nm.
The surface modified portion or portions of the TMD may be in a different phase to the portion or portions of the TMD that are not surface modified. The surface-modified portion or portions may be in a IT or IT' phase and the portion or portions that are not surface-modified may be in a 2H phase.
The device may exhibit substantially Ohmic contact behaviour with respect to the first and second electrodes. In this context, Ohmic contact behaviour implies that the current between the two electrodes of the device has a substantially linear
dependence on voltage.
The device may have a Schottky barrier height of less than or equal to lOmeV. The device may have a Schottky barrier height of less than or equal to 9.4meV. The device may have a Schottky barrier height of between 9meV and lOmeV or of between
9.4meV and lOmeV.
The device may have a field effect electron mobility at room temperature (298K) of 35 cm2V1s 1 or greater, particularly 37.7cm2V1s 1 or greater, more particularly 70 cm2V
1s 1 or greater. The device may have a field effect electron mobility at room
temperature (298K) falling in one of the following ranges: 35 cm2V1s _ 1 to 37.7cm2V1s 35 cm2V1s 1 to 70 cm2V _1s _1, 35 cm2V1s _ 1 to 75 cm2V _1s _1; 37.5 cm^ 1 to 70 cm2V _1s _1, 37.5 cm2V1s _ 1 to 75 cm2V _1s _1; 70 cm2V1s _ 1 to 75 cm2V _1s _1. The device may have a current on/off ratio at room temperature (298K) of 106 or greater, particularly 107 or greater, further particularly 10s or greater. The device may have a current on/off ratio of approximately 109. The device may have a current on/off ratio at room temperature falling in one of the following ranges: 106to 107, 106 to 10s, 106to 109; 107 to 10s, 107 to 109; and 108to 109.
The device may have a subthreshold swing at room temperature (298K) of 85mV dec 1 or less, particularly 75mV dec 1 or less, further particularly in the range 60 mV dec 1 to 75 mV dec-1. The device may have a subthreshold swing of 61 mV dec1. The device may have a subthreshold swing falling in one of the following ranges: 60 mV dec 1 to 61 mV dec 1, 60 mV dec 1 to 75 mV dec 1, 60 mV dec 1 to 85 mV dec 1; 61 mV dec 1 to
75 mV dec 1, 61 mV dec 1 to 85 mV dec 1; and 75mV dec 1 to 85 mV dec 1.
The electronic device may be a field-effect transistor.
The electronic device may be a logic inverter. The inverter may be capable of a gain greater than 100. The inverter may be capable of a gain of greater than 5 with a power consumption less than 10 pW. The material and/or device may be held under substantially vacuum conditions. The device may be operated under substantially vacuum conditions. The device may further comprise a vacuum chamber configured to contain the surface-modified TMD under substantially vacuum conditions. By substantially vacuum conditions, it is intended to mean pressures of lO 7 mbar or less.
The material and/or device may be held under a nitrogen atmosphere. The material and/or device may be packaged with a nitrogen atmosphere. The nitrogen atmosphere may be a substantially 100% nitrogen environment.
The material and/or device may comprise a package configured or arranged to exclude oxygen and water from contact with the surface-modified TMD. The package may be configured to maintain the surface-modified TMD under vacuum. The package may be configured to maintain the surface-modified TMD in a Nitrogen (N2) or other inert atmosphere.
In an aspect, a method of producing a material is provided, the material comprising: a transition metal dichalcogenide (TMD) comprising a surface, a least a portion of the surface being surface-modified with one or more Group 1 metals, wherein the one or more Group 1 metals comprise Cs and/or Rb, the method comprising: providing a transition metal dichalcogenide; and evaporating one or more Group 1 metals onto at least a portion of a surface of the transition metal dichalcogenide, wherein the one or more group 1 metals comprises Cs and/or Rb.
In an aspect, a method of producing an electronic device is provided, the electronic device comprising: a transition metal dichalcogenide (TMD), the TMD comprising first and second portions which are surface modified with one or more a Group 1 metals and a third portion which is not surface modified with one or more Group 1 metals; and first and second electrodes, wherein the first and second electrodes are in direct electrical contact with the first and second portions of the transition metal dichalcogenide, respectively, wherein the one or more Group 1 metals comprises Caesium and/or Rubidium, the method comprising: providing a layer of transition metal dichalcogenide and first and second electrodes on the surface of a substrate, such that the first and second electrodes are in electrical contact with the layer of transition metal dichalcogenide; evaporating one or more Group 1 metals onto a surface of first and second portions of the layer of transition metal dichalcogenide such that the one or more Group 1 metals has a thickness of at least 0.2nm, wherein the first and second portions of the layer of transition metal dichalcogenide are adjacent to the first and second electrodes respectively, and wherein the one or more Group 1 metals comprises Cs and/or Rb.
Brief description of Figures Embodiments are described below in association with the Figures, in which:
Figure 1 shows a material according to an embodiment;
Figure 2 shows a material according to an embodiment;
Figures 3a and 3b show the 2H and IT' phases of WSe2, respectively;
Figure 4 shows a device according to an embodiment;
Figure 5 shows a device according to an embodiment;
Figure 6 shows a device according to an embodiment;
Figure 7 shows a method of producing a material according to an embodiment;
Figure 8a shows the line profile derived from the Atomic Force Microscope (AFM) image of a bilayer WSe2 device;
Figure 8b shows Raman measurements for the bilayer WSe2 device;
Figure 8c shows photoluminescence (PL) measurements for the bilayer WSe2 device; Figure 9a shows a schematic representation of a bilayer WSe2 device with surface modification;
Figure 9b and Figure 9c show transport characteristics (lSd-Vg) of a pristine bilayer WSe2 FET;
Figure 9d shows transfer characteristic evolution of the WSe2 FET as a function of Cs thickness;
Figure 9e shows the electrical conductance (G) versus Cs thickness at Vg = 0V of the WSe2 FET;
Figure 9f shows output curves (lSd-VSd) for the pristine and 1.0 nm Cs-modified WSe2
FET; Figures 9g and 9h show temperature-dependent transport measurements for the Cs- modified WSe2 FET;
Figure 9i shows the electrical conductance evolution of the bilayer WSe2 device after 1.0 nm Cs functionalization with respect to temperature at different Vg;
Figure 10 (a)-(d) show the results of in situ XPS and UPS of the bilayer WSe2 device; Figure 11a shows the Photoluminescence (PL) spectra for a bilayer WSe2 flake before and after 0.1 nm Cs modification;
Figure lib shows Raman measurements for a bilayer WSe2 flake before and after 0.1 nm Cs modification;
Figure 12a shows the evolution of transfer characteristics of a device according to an embodiment as a function of Cs thickness;
Figure 12b shows the evolution of field-effect electron mobility for the device;
Figures 12c and Figure 12d illustrate the output curves of the device under a range of gate voltages after and before Cs modification, respectively;
Figure 13a shows the Schottky barrier height of a hetero-phase transistor according to an embodiment;
Figure 13b shows the width-normalized total resistance (Rtot) as a function of the channel length at Vg = 5 V for the hetero-phase transistor;
Figure 14a shows the transfer characteristic evolution of the device as a function of Cs thickness for a sandwich framework device according to an embodiment;
Figure 14b shows the corresponding electron mobility versus Cs thickness; Figures 14c and 14d show output curves for the device before and after 1.0 nm Cs contact doping at different gate voltages ranging from 1 V to 5 V, respectively;
Figure 14e shows the transfer characteristic evolution of the device as a function of Cs thickness for another sandwich framework device according to an embodiment; Figure 15a shows transfer characteristics for a logic inverter according to an embodiment;
Figure 15b shows output characteristics of the inverter;
Figure 15c shows the extracted gain as a function of VIN at three different VDDfor the inverter;
Figure 15d shows the evolution of the power consumption of the inverter versus VDD Figure 16 (a) shows output characteristics of a homogeneous WSe2 inverter according to an embodiment; and
Figure 16 (b) shows the output curve and corresponding voltage gain as a function of ViN for the inverter.
Detailed Description
For purposes of brevity and clarity, descriptions of embodiments of the present disclosure are directed to a transition metal dichalcogenide and uses thereof, in accordance with the drawings. While aspects of the present disclosure will be described in conjunction with the embodiments provided herein, it will be understood that they are not intended to limit the present disclosure to these embodiments. On the contrary, the present disclosure is intended to cover alternatives, modifications and equivalents to the embodiments described herein, which are included within the scope of the present disclosure as defined by the appended claims. Furthermore, in the following detailed description, specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be recognized by an individual having ordinary skill in the art, i.e. a skilled person, that the present disclosure may be practiced without specific details, and/or with multiple details arising from combinations of aspects of particular embodiments. In a number of instances, well-known systems, methods, procedures, and components have not been described in detail so as to not unnecessarily obscure aspects of the embodiments of the present disclosure.
In embodiments of the present disclosure, depiction of a given element or
consideration or use of a particular element number in a particular figure or a reference thereto in corresponding descriptive material can encompass the same, an equivalent, or an analogous element or element number identified in another figure or descriptive material associated therewith.
References to "an embodiment / example", "another embodiment / example", "some embodiments / examples", "some other embodiments / examples", and so on, indicate that the embodiment(s) / example(s) so described may include a particular feature, structure, characteristic, property, element, or limitation, but that not every embodiment / example necessarily includes that particular feature, structure, characteristic, property, element or limitation. Furthermore, repeated use of the phrase "in an embodiment / example" or "in another embodiment / example" does not necessarily refer to the same embodiment / example.
The terms "comprising", "including", "having", and the like do not exclude the presence of other features / elements / steps than those listed in an embodiment, nor do they require the presence of other features. Recitation of certain features / elements / steps in mutually different embodiments does not indicate that a combination of these features / elements / steps cannot be used in an embodiment.
As used herein, the terms "a" and "an" are defined as one or more than one. The use of "/" in a figure or associated text is understood to mean "and/or" unless otherwise indicated. The recitation of a particular numerical value or value range herein is understood to include or be a recitation of an approximate numerical value or value range.
Figure 1 shows a schematic representation of a material 1 according to an
embodiment. In the embodiment of Figure 1, the material comprises a layer 101 of a transmission metal dichalcogenide (TMD). On the surface 109 of the TMD 101, is provided a layer 103 of one or more alkali metals, i.e. the surface of the TMD is surface-modified with one or more alkali metals. In the embodiment of Figure 1, alkali metal is provided on the surface of two portions 105 of the TMD 101. In the embodiment of Figure 1, a portion 107 of the TMD, positioned between the regions 105 is not surface modified by alkali metal 103. In other embodiments, all of the TMD may be surface modified or only one or a greater number of portions of the TMD may be surface modified.
The thickness of the TMD is not particularly limited. In embodiments, the TMD may be provided as a monolayer, a bilayer or as a multilayer, for example with a thickness of 3- 5 layers. However, monolayer, bilayer or otherwise substantially two-dimensional forms of TMD may be advantageous for use in electronic devices, enabling low-profile devices to be provided.
The thickness of a TMD layer may be approximately determined by using a high- resolution optical microscope (e.g. the Nikon Eclipse LV100D), and further confirmed by Atomic Force Microscopy (AFM).
In an embodiment, the layer of alkali metal comprises Caesium and/or Rubidium. In an embodiment, the layer of alkali metal comprises a mixture of more than one alkali metal.
The layer of alkali metal may comprise Caesium and one or more element selected from Lithium, Sodium, Potassium and Rubidium.
The layer of alkali metal may comprise Rubidium and one or more element selected from Lithium, Sodium, Potassium and Caesium.
In an embodiment, the thickness of the alkali metal layer is in the range 0.2nm to 5nm.
In an embodiment, the thickness of the alkali metal may be in the range 0.4nm to 2nm.
In an embodiment, the thickness of Caesium and/or Rubidium is in the range 0.2nm to
5nm. In an embodiment, the thickness of Caesium and/or Rubidium may be in the range 0.4nm to 2nm. Thicknesses lying in this range may convey advantageous electronic properties to the surface-modified portions 105 of the TMD. These properties will be discussed further below.
The thickness of the alkali metal layer may be determined by weight, for example, using a quartz crystal microbalance. X-ray photoelectron spectroscopy (XPS) can also be employed to determine the thickness of the alkali metal. One such protocol suitable for determining the thickness of the alkali metal is given in the reference: Seah, M. P., & Dench, W. A. (1979), Quantitative electron spectroscopy of surfaces: A standard data base for electron inelastic mean free paths in solids. Surf. Interface Anal., 1(1), 2-11.
In an embodiment, the TMD may be selected from M0S2, WS2, MoSe2 and WSe2,
MoTe2, alkali metal-doped MoTe2, alkali metal-doped MoSe2, alkali metal-doped M0S2, alkali metal-doped WSe2, and alkali metal-doped WS2.
In particular, the TMD may be selected from WSe2 and MoTe2. More particularly, the TMD may be WSe2.
In an embodiment, the alkali metal may comprise Caesium and/or Rubidium and the TMD may be selected from M0S2, WS2, MoSe2 and WSe2, MoTe2, alkali metal-doped MoTe2, alkali metal-doped MoSe2, alkali metal-doped MoS2, alkali metal-doped WSe2, and alkali metal-doped WS2. In particular, the alkali metal may comprise Caesium and/or Rubidium and the TMD may be selected from WSe2 and MoTe2. More particularly, alkali metal may comprise Caesium and/or Rubidium and the TMD may comprise tungsten diselenide (WSe2). A material according to this embodiment is shown in Figure 2, which is a schematic representation of WSe2 surface modified with Cs. In the embodiment of Figure 2, WSe2 is provided as a monolayer. However, in other embodiments, WSe2 may be provided as a bilayer or as a multilayer (for example, between 3 and 5 layers) material.
In an embodiment, the portion 107 of TMD 101 which is not surface modified (if present) may have a 2H crystal structure. In an embodiment the surface modification of the portion or portions 105 of TMD 101 may result in these portions having a different phase from the portion 107 which is not surface modified. In an embodiment, the portion or portions 105 may have a IT or IT' crystal structure, particularly a IT' crystal structure. Figures 3a and 3b show the 2H and IT' crystal structures of WSe2, respectively, with Tungsten atoms denoted by 301 and the Selenium atoms denoted by 303.
High-resolution transmission electron microscope (HRTEM) can be employed to directly observe the atomically sharp interface between the 2H and 11 /IT phases in materials according to embodiments. A protocol suitable for such characterisation is given in, for example, Kappera, R., et al. Nat. Mater. 13.12 (2014): 1128.
The crystal structure of the TMD in the surface modified portions may depend on the thickness of the alkali metal layer 103 present on the surface. In embodiments, the thickness of the alkali metal 103 may be chosen such that the surface-modified portions 105 of the TMD have a substantially IT or IT' crystal structure. Typically, the TMD will exhibit IT or IT' behaviour at larger thicknesses of alkali metal, as shown in the experimental results discussed below.
In an embodiment, the portion 107 of TMD 101 that is not surface modified may be a semi-conductor. In embodiments, the surface modification of the portion or portions 105 may result in these portions exhibiting different electrical behaviour than the portion 107 of TMD that is not surface modified. In an embodiment, the portion, or portions 105 may exhibit metallic behaviour. In an embodiment, the portion, or portions 105 may exhibit n-type doping behaviour.
The electrical behaviour of the surface-modified and unmodified portions can be determined by examining the electrical transport properties of the material in accordance with methods well known in the art.
In an embodiment, the electrical behaviour of surface modified portions of the TMD may depend on the thickness of the layer of alkali metal 103 on their respective surfaces. In an embodiment, the thickness of the layer of alkali metal may be selected such that the surface modified portions of the TMD 105 exhibit metallic or substantially metallic behaviour. Typically, the surface-modified portions of TMD will exhibit metallic behaviour at larger thicknesses of alkali metal.
In other embodiments, the thickness of the alkali metal may be selected in order to obtain other electrical behaviours, such as n-type doping behaviour relative to the non-surface modified TMD.
In an embodiment, the thickness of the alkali metal is in the range 0.2nm to 5nm. In an embodiment, the thickness of the alkali metal may be in the range 0.4nm to 2nm. In this embodiment, the TMD may exhibit metallic behaviour and Ohmic contact behaviour.
In an embodiment, the thickness of the alkali metal layer may be less than 0.4nm. In an embodiment, the thickness of the alkali metal layer may be between 0.2nm and 0.4nm. In this embodiment, the TMD may exhibit n-type doping behaviour of the surface-modified portions 105 of the TMD relative to the non-surface modified portions 107.
In an embodiment, the thickness of Caesium and/or Rubidium is in the range 0.2nm to 5nm. In an embodiment, the thickness of Caesium and/or Rubidium may be in the range 0.4nm to 2nm. In this embodiment, the TMD may exhibit metallic behaviour and
Ohmic contact behaviour.
In an embodiment, the thickness of Caesium and/or Rubidium may be less than 0.4nm. In an embodiment, the thickness of Caesium and/or Rubidium may be between 0.2nm and 0.4nm. In this embodiment, the TMD may exhibit n-type doping behaviour of the surface-modified portions 105 of the TMD relative to the non-surface modified portions 107.
According to embodiment described above the material of Figure 1 may comprise a hetero-phase contact within the TMD layer at the interface 111 between the surface- modified and unmodified portions. In embodiments, the hetero-phase contact is between a 2H phase in the portions which are not surface modified and a IT' phase in the portions which are surface modified.
Thus, materials according to these embodiments above may enable the exploitation of the both the semiconducting and metallic properties of two phases of TMD within the same material, namely both the advantageous ambipolar transport properties of the
2H phase and the advantageous ohmic electrical contact via surface-doped metallic IT' portions. In particular, materials according to embodiments described above may be advantageously deployed in electronic devices such as transistors by employing the metallic 11 /IT phased TMD as a buffer contact layer, thereby achieving 2H-1T/1T' hetero-phase transistors with low contact resistance and Ohmic behaviour.
In contrast to the metal contacts in existing 2D TMD transistors, 2H-1T/1T' heterophase contact in materials according to embodiments described above can i) avoid the lattice mismatch between the metal electrodes and the channel materials, which significantly enhances the carrier injection efficiency; ii) eliminate the Fermi level pinning effect originating from the surface states; iii) and create an atomically sharp interface, to avoid the chemical bond formation at the metal/semiconductor interface which can generate large strain in the crystal lattice.
As shown below in the Examples, surface-modification with Caesium and/or Rubidium results in devices with highly advantageous electrical properties.
Surface modification using alkali metals, particularly Caesium and/or Rubidium, in order to obtain heterophase contact in TMDs as described above provides a facile, non-destructive method to achieve Ohmic contact for 2D materials, while maintaining ambipolar behaviour. Indeed, the alkali metal surface functionalization, particularly surface functionalization using Caesium and/or Rubidium, can be performed in situ as will be discussed further below. Phase transition performed in this way also enables a high degree of control over the area of TMD which undergoes the phase transition.
With conventional semiconductors, ion implantation and thermal diffusion have been extensively employed to accurately modulate different carrier concentrations within them. However, in 2D materials, these doping techniques may destroy the crystal lattice or induce substantial defects into the materials due to their atomically thin nature, thus deteriorating their intrinsic properties. In contrast, surface modification is particularly effective in 2-D materials due to their large surface-body ratio.
Devices
In an embodiment, the material according to the above described embodiments is employed in electronic device. In an embodiment, the material according to Figure 1 is employed in a Field effect transistor (FET).
A schematic of a n-type FET device according to this embodiment is shown in Figure 4.
In this embodiment, the transistor comprises a monolayer of TMD 101 arranged on a substrate 401. In the embodiment of Figure 4 the substrate is a p-type Silicon wafer with SiC>2 layer. The skilled person will appreciate that other suitable substrates with insulating properties may be employed according to embodiments.
Source and drain electrodes 40S are provided on the substrate at either end of the TMD layer 101. The reason for this arrangement will become apparent from the discussion below. In the embodiment of Figure 4, the electrodes 40S comprise
Palladium (Pd). However, the person skilled in the art will appreciate that other suitable metallic materials may be employed according to embodiments.
In this embodiment, a layer of photoresist material 405 is arranged on a portion the surface of the TMD layer 101. In the embodiment of Figure 4, a photoresist such as PMMA is employed due to its photoresist properties which are advantageously employed during the manufacturing process (see below). In other embodiment, the top layer of 405 may be any insulating material capable of encapsulating the TMD layer 101 to avoid modification with one or more alkali metals including Cs and/or Rb modification. In embodiments, the photoresist or other insulating layer 405 may be omitted partially or completely.
In an embodiment, the ends 105 of the TMD layer adjacent to the source and drain electrodes 403 are not covered by the dielectric 405, i.e. they are exposed. In an embodiment, a back-gate electrode (not shown) is arranged on the Silicon substrate.
An alkali metal layer 103 is present on the portion of the surface at either end of the TMD layer 101 which is not covered by the photoresist 405. The TMD layer 101 is therefore surface modified at each end 105 but is unmodified in the centre. In an embodiment, the alkali metal layer comprises Caesium and/or Rubidium.
In an embodiment, the TMD may be selected from MoS2, WS2, MoSe2 and WSe2, MoTe2, alkali metal-doped MoTe2, alkali metal-doped MoSe2, alkali metal-doped M0S2, alkali metal-doped WSe2, and alkali metal-doped WS2.
In particular, the TMD may be selected from WSe2 and MoTe2. More particularly, the TMD may be WSe2.
In an embodiment, the width of each of the portions of the TMD layer on which alkali metal is present is in the range 0.2-5 pm. In an embodiment, they have a width in the range 0.2-0.3 pm. As explained above, beyond a certain thickness of alkali metal, the TMD layer may be metallic at each end 105 but behave as a semiconductor towards the centre of the layer 107, in the region 107 positioned under the photoresist 405. In the embodiment of Figure 4, the TMD is employed as a n-type unipolar semiconductor. In an
embodiment, the TMD has a IT or IT' phase at each end 105 adjacent to the source and drain electrodes 403 and a 2H phase in the portion 107 beneath the gate electrode which is not surface modified with alkali metal. The TMD is therefore comprises a hetero-phase contact 111 and the device 4 is therefore a hetero-phase transistor.
In an embodiment, the thickness of the alkali metal lies in the range 0.2nm to 5nm. In an embodiment, it lies in the range 0.4nm-2nm as this ensures good ohmic contact between the source and drain electrodes and the TMD, as will be shown in the Examples discussed below. In an embodiment, the thickness of the alkali metal is approximately l.Onm.
In an embodiment, the alkali metal comprises Caesium and/or Rubidium and the thickness of the Caesium and/or Rubidium lies in the range 0.2nm to 5nm. In an embodiment, it lies in the range 0.4nm-2nm. In an embodiment, the thickness of the Caesium and/or Rubidium is approximately l.Onm. In an embodiment, the thickness of the alkali metal is chosen according to the desired properties of the device.
In an embodiment, the thickness of the alkali metal is chosen such that there is substantially ohmic contact between the electrodes and the TMD layer, i.e. the current between the source and drain electrodes 403 has a substantially linear dependence on voltage.
In an embodiment, the alkali metal comprises Caesium and/or Rubidium and the thickness of the alkali metal is such that the current on/off ratio of the device 4 at room temperature (298K) is at least 106.
The current on/off ratio of the device is defined by the ratio of the on state current and off state current, i.e. it is the ratio of the current maximum and the current minimum in the transfer characteristic curve.
In an embodiment, the alkali metal comprises Caesium and/or Rubidium and the thickness of the alkali metal is such that the field-effect electron mobility in the device at room temperature (298K) is at least 30 cm2V _1s _1. The field effect electron mobility m of the device is derived from the linear regime of a transfer plot of current between source and drain electrodes (lSd) against potential difference across the source and drain electrodes (VSd) using the equation:
Figure imgf000035_0001
where L and W denote the length and width of the conduction channel between source and drain electrodes 403, respectively, denotes the capacitance per unit area of the dielectric (i.e. Si02., in the present embodiment) and dlSd/dVSd represents the slope of the linear region in the transfer plot.
In the arrangement of Figure 4, the electrodes 403 interface with the portions 105 of the TMD 101 which are surface modified, i.e. they are in direct electrical contact with these portions. However, the majority of the channel remains unmodified.
This arrangement therefore provides a field effect transistor based on the semi- conductor behaviour of the TMD, while simultaneously ensuring that the source and drain electrodes are in direct electrical contact with metallic portions of the TMD, thereby ensuring Ohmic contact between the with low contact resistance and avoiding a Schottky barrier at the contact between the electrodes and the semiconducting material. Thus, the alkali metal functionalization described above according to embodiments, particularly functionalization using Caesium and/or Rubidium, provides a simple method of achieving a high-performance transistor with high mobility, high current on/off ratio, low subthreshold swing. The device of Figure 4 therefore is a high-quality device which has a fast on/off speed and is cost-efficient.
Figure 5 shows a sandwich framework FET according to an embodiment of the invention.
As in the embodiment of Figure 4, the transistor 5 comprises a mono-layer of TMD 101 with source and drain electrodes 403 provided on the substrate 401 at either end of the TMD layer 101 and a layer of photoresist material 405 arranged on a portion the surface of the TMD layer 101. In the embodiment of Figure 5, the photoresist 405 is PMMA, however, the person skilled in the art will appreciate that other materials could be employed according to embodiments. In embodiments, the photoresist or other insulating layer 405 may be omitted partially or completely.
The TMD and source and drain electrodes are arranged on a dielectric layer 501. In the embodiment of Figure 5, the dielectric layer comprises a sheet of hexagonal boron nitride (h-BN). However, the person skilled in the art will appreciate that other dielectric layers may be employed according to embodiments. In an embodiment, the thickness of the dielectric layer 501 (in this embodiment, h-BN) may particularly be in the range 10-20nm. Thinner dielectric layers may induce undesirable quantum tunnelling into the device.
The dielectric layer is arranged on a bottom gate electrode layer 503. In the embodiment of Figure 5, the bottom gate electrode comprises a layer of Graphene. The skilled person will appreciate that other suitable materials may be employed according to embodiments. In an embodiment, the thickness of the bottom gate electrode layer may particularly be less than lOnm.
The sandwich arrangement described above is arranged on a silicon-based substrate 401 as described above in relation to the embodiment of Figure 4.
As in the embodiment of Figure 4 a layer of alkali metal is present on the portions 105 of the surface of the TMD at either end of the TMD layer 101 which are not covered by the photoresist 405. The TMD layer 101 is therefore surface modified at each end 105 but is unmodified in its central portion 107. In an embodiment, the width of each of the portions 105 of the TMD layer on which alkali metal is present (i.e. the distance from the electrodes 403 from which these portions extend) is in the range 0.2-5 pm. In an embodiment, they have a width in the range 0.2-0.3 pm.
In an embodiment, the alkali metal layer employed in the embodiment of Figure 5 comprises Caesium and/or Rubidium.
In the embodiment of Figure 5, the TMD may be selected from MoS2, WS2, MoSe2 and WSe2, MoTe2, alkali metal-doped MoTe2, alkali metal-doped MoSe2, alkali metal-doped MOS2, alkali metal-doped WSe2, and alkali metal-doped WS2.
In particular, the TMD may be selected from WSe2 and MoTe2. More particularly, the TMD may be WSe2.
As explained above, beyond a certain thickness of alkali metal, the TMD layer may be metallic at each end 105 but behave as a semiconductor towards the centre of the layer 107, in the region 107 positioned under the photoresist 405. In the embodiment of Figure 5, the TMD is employed as a n-type unipolar semiconductor. In an embodiment, the TMD has a IT or IT' phase at each end 105 adjacent to the source and drain electrodes 403 and a 2H phase in the portion 107 beneath the photoresist 405 which is not surface modified with alkali metal. The TMD is therefore comprises a hetero-phase contact 111 and the device 5 is therefore a hetero-phase transistor.
In an embodiment, the thickness of the alkali metal lies in the range 0.2nm to 5nm. In an embodiment, the thickness of the alkali metal lies in the range 0.4nm to 2nm. In an embodiment, the thickness of the alkali metal is approximately l.Onm.
In an embodiment, the thickness of the alkali metal is chosen according to the desired properties of the device.
In an embodiment, the alkali metal comprises Caesium and/or Rubidium and the thickness of the alkali metal is such that there is ohmic contact between the electrodes and the TMD layer.
In an embodiment, the alkali metal comprises Caesium and/or Rubidium and the thickness of the alkali metal is such that the current on/off ratio at room temperature (298K) of the device 5 is at least 107, in particular in the range from 107 to 109. The current on/off ratio of the device is defined by the ratio of the on state current and off state current, i.e. it is the ratio of the current maximum and the current minimum in the transfer characteristic curve.
In an embodiment, the alkali metal comprises Caesium and/or Rubidium and the thickness of the alkali metal is such that the field effect electron mobility in the surface modified potions of the TMD is at least 70 cm2V _1s _1.
The field effect electron mobility m of the device is derived from the linear regime of a transfer plot of current between source and drain electrodes (lSd) against potential difference across the source and drain electrodes (VSd) using the equation:
Figure imgf000040_0001
where L and W denote the length and width of the conduction channel between source and drain electrodes 403, respectively, Q denotes the capacitance per unit area of the dielectric 501 (i.e. BN in the embodiment of Figure 5) and dlSd/dVSd represents the slope of the linear region in the transfer plot.
In an embodiment, the alkali metal comprises Caesium and/or Rubidium and the thickness of the alkali metal is chosen such that subthreshold swing is less than 85 mV dec-1, particularly in the range 60 to 85 mV dec-1. The subthreshold swing of the device is determined from d \/g/d ( log/Sd), where Vg is the gate voltage and lSd is the current between source and drain electrodes.
Figure 6 shows a transistor-based logic inverter according to an embodiment. The device comprises a back-gate electrode 503 providing the input signal (Vm) and a dielectric layer 501 arranged on a substrate 401 as described in association with the device of Figure 4.
The device further comprises three parallel electrodes 605, 607, 609 arranged on the dielectric layer 501, serving as the power supply (VDD; 605), output signal (VOUT; 607), and ground (GND; 609), respectively, between which a layer of TMD 101 forms two channels 601 and 603 in series.
A Photoresist 405 is arranged to completely cover the TMD of one channel, 601 such that no surface modification of the TMD is present in this channel therefore enabling this channel to retain the p-type dominated ambipolar behaviour of the TMD.
In contrast, the other channel 603 is only partially covered by the PMMA photoresist 405 with alkali-metal surface modification at each end, adjacent to the corresponding electrodes 605. Thus, this channel behaves as an n-type transistor as described above in relation to Figures 4 and 5.
In embodiments, the photoresist layers 405 may be completely or partially omitted from either or both of the channels.
Thus, the embodiment of Figure 6 corresponds to a TMD inverter with two channels in series. Through spatially controlling the exposed regions near the metal electrodes of one TMD channel, unipolar hetero-phase n-type transistor can be obtained. In contrast, another channel is fully covered by the PMMA photoresist, where the p-type dominated ambipolar transport behaviour is retained. In the embodiment of Figure 6, multilayer h-BN and graphene are used as the dielectric layer and bottom gate electrode, respectively, however the skilled person will appreciate that other suitable materials could be employed according to embodiments. The graphene provides the input signal (VIN), and the three parallel electrodes on the TMD flake serve as the power supply (VDD), output signal (VOUT), and ground (GND), respectively.
In an embodiment, the thickness of the alkali metal layer is chosen according to the desired properties of the n-type channel. In an embodiment, the thickness of the alkali metal is in the range 0.2nm to 5nm, particularly 0.4nm to 2nm. In an embodiment, the thickness of the alkali metal is approximately l.Onm.
In an embodiment, the alkali metal comprises Caesium and/or Rubidium and the thickness of the alkali metal may be such that the gain (-d\/ouT/d\/iN) achievable by the inverter 6 is greater than 100 when VDD 2.5 V.
In an embodiment, the alkali metal comprises Caesium and/or Rubidium and the thickness of the alkali metal may be such that that invertor can achieve a gain greater than 5 for a static power consumption (defined as P = VDD><I DD) of less than 10 pW when VDD 0.5 V.
As shown below, experimental results have shown that inverters according to this embodiment have high voltage gain, thereby enabling fast logic state inversion, high accuracy and low power consumption.
Although the integration of materials according to the embodiment of Figure 1 have been described in relation to three devices 4, 5 and 6 according to embodiments, the person skilled in the art will understand that these devices are merely intended to be representational of the potential application of materials according to embodiments. Indeed, materials according to embodiments described above are extremely flexible and compatible with various device structures. They can be applied to almost all electronic and optoelectronic devices to improve charge injection/collection efficiency. The thickness of the alkali metal layer may be varied in order to fine-tune the electrical properties of the material according to its intended implementation.
Figure 7 shows a method of producing the material of Figure 1 according to an embodiment. It is also suitable for producing the relevant layers in the devices in Figures 4, 5 and 6.
In step S701 the TMD 101 is provided. The layer may be a monolayer, a bilayer, or comprise three or more layers according requirements of the final material. Bulk TMD crystals are commercially available, for example from HQ-Graphene. Monolayer and bilayer TMD can be produced from bulk TMD via, for example, mechanical exfoliation using Scotch tape.
In an embodiment, the TMD may be transferred to a suitable substrate such as Silicon dioxide prior to performing step S70S. In an embodiment, electrodes may be patterned onto the TMD using electron beam lithography prior to performing step S703. Thus, steps S703 to S707 may be performed in situ in an electronic device, such as those described above in relation to Figures 4, 5 and 6.
If electrode patterning is performed, after patterning the source and drain electrodes on the TMD, the electrodes may be thermally evaporated onto the substrate, for example by thermally evaporating Pd and/or Au. Excess metal may then be removed from the sample, for example by soaking in acetone according to procedures well known in the art. The method then proceeds to step S703.
In step S703 the surface 109 of the TMD layer is coated with a barrier layer 405 of photoresist such as PMMA. In an embodiment, the barrier layer is applied to the TMD layer using spin-coating.
In step S705, electron beam lithography (EBL) is employed to remove the photoresist on the portions 105 of the TMD layer to be surface modified. In the embodiment of Figure S705, these are the portions at the edge of the layer.
In step S707 a layer of one or more alkali metals 103 is evaporated directly onto the
TMD layer. In an embodiment, this is done under vacuum from one or more alkali metal getters. Suitable getters are commercially available, for example from SAES. In an embodiment, the one or more alkali metals comprise Caesium and/or Rubidium and a layer of Caesium and/or Rubidium is evaporated onto the TMD layer from, for example, a Caesium and/or Rubidium getter.
In an embodiment, the alkali metal getter is heated in a high-vacuum chamber with the TMD in order to achieve evaporation of the alkali metal onto the exposed surfaces of the TMD. Evaporation of the alkali metal from the getter may be achieved, for example by supplying a DC current to a feedthrough into the vacuum chamber.
In an embodiment, the vacuum chamber should be under a high vacuum condition of less than 107 mbar. Such pressures can be achieved by pumping a suitable chamber with a turbopump. Turbopumps suitable for achieving a high vacuum are commercially available, for example from Pfeiffer Vacuum GmbH. Components for a chamber suitable for supporting such a vacuum are also commercially available, for example, from UHV Design.
Due to the presence of the photoresist 405 acting as a barrier layer, film growth of the alkali metal is restricted to the exposed portions 105 and 105 of the TMD layer. The thickness of the alkali metal can be monitored by monitoring the weight of the material during evaporation, for example using a quartz crystal microbalance (QCM), thereby enabling it to be controlled according to the desired properties of the material or device, as appropriate.
Quartz crystal microbalances (and corresponding feedthroughs) suitable for use in accordance with embodiments are commercially available, for example from
Testbourne Ltd.
In an embodiment, the vacuum chamber is configured such that the QCM is positioned so as to protect the sample from alkali metal deposition while the evaporation rate from the alkali metal getter is brought to required levels. Once it achieves the desired rate, the QCM is moved out of the way in order to enable alkali metal deposition. Once the desired evaporation onto the sample is complete, the QCM is moved back into position to protect the sample from further deposition.
A suitable in situ vacuum characterization system for use in accordance with embodiments is given in Lei, B., et al. (2017). Nano Research, 10(4), 1282-1291. The photoresist layer may or may not be removed following the application, according to desired use.
Thus, the method of Figure 7 provides a method of producing the materials and devices according to embodiments which may be performed in situ and easily integrated with conventional CMOS processes, thereby enabling straightforward integration into the fabrication process. This method provides an effective, damage- free and non-volatile procedure for realizing phase transitions in TMDs such as WSe2.
Examples
Selected advantageous physical properties of the above described embodiments will now be described in accordance with the following non-limiting examples.
Fabrication of Pristine 2D WSe2 transistor
Scotch tape was used to mechanically exfoliate WSe2 flakes from bulk WSe2 crystals (commercially obtained from HQ-graphene), and then quickly transferred onto a degenerately p-type doped silicon substrate with S00 nm SiC>2. Monolayer and bilayer WSe2 were found by utilizing a high-resolution optical microscope (Nikon Eclipse LV100D), and further confirmed by AFM and Raman measurements.
Polymethylmethacrylate (PMMA) photoresist (commercially obtained from
MicroChem) was subsequently spin coated on the silicon substrate for the conventional e-beam lithography (EBL) process. After patterning the source and drain electrodes on WSe2, 5 nm Pd and 60 nm Au were thermally evaporated onto the substrate. The sample was then soaked in acetone for about 1 hour to lift off excess metal.
Figures 8a-c show results for the bilayer WSe2 device, where the WSe2 flakes were mechanically exfoliated onto a degenerately p-type doped silicon wafer with a 300 nm SiC>2 layer. Standard lithography was then carried out to define the WSe2 channel followed by the metal deposition of Pd/Au. Fig. 8a shows the line profile derived from the Atomic Force Microscope (AFM) image of the device. It reveals that the thickness of the WSe2 flake is around ~1.7 nm, indicating its bilayer nature. Raman and photoluminescence (PL) measurements (Figures 8b and 8c, respectively) were employed for further verification. Three Raman characteristic peaks located at 250 cm 1 (E12g), 257.5 cm 1 (Aig) and 309 cm 1 (B12g), and the PL spectrum 801 exhibits the direct bandgap emission peak 803 at ~1.64 eV and the indirect bandgap emission peak 805 at ~1.57 eV, further confirming the bilayer nature of the WSe2 flake.
Surface modification with Cs In order to investigate the Cs modification induced phase transition in bilayer WSe2 via in situ electrical measurement, the pristine WSe2 device was wire bonded onto a lead chip carrier and loaded into a home-made high vacuum system (~10 7 mbar) with in situ film growth and cryogenic electrical measurements capabilities. The vacuum system was fabricated in accordance with the design given in Lei, B., et al. (2017), Nano
Research, 10(4), 1282-1291.
An Agilent 2912A precision source/measure unit (SMU) was utilized to perform the related electrical measurements. Caesium was evaporated in situ from a SAES Getter directly to the devices and a quartz crystal microbalance (QCM) (commercially obtained from Testbourne Ltd) was employed to calibrate the nominal thickness. The temperature dependent experiments described below were conducted on a cryogenic stage with liquid nitrogen for sample cooling.
The sample was loaded onto the sample stage through a flexible fast entry door. After several hours' pumping, the sample was pulled back to a particular position for in situ deposition, where a thermal effusion cell was equipped to evaporate dopant. The quartz crystal microbalance (QCM) was placed in front of the sample stage to precisely monitor the deposition rate. Once the Cs evaporate rate was confirmed, the QCM was shifted upwards to allow Cs to deposit onto the sample. After the evaporation, the QCM was shifted downward to block Cs. The Cs was evaporated via a DC current (3.8
A) provided through a feedthrough.
Figure 9a shows a schematic representation of the bilayer WSe2 923 device in a FET structure with Pd/Au (5nm/60 nm) as the metal contacts 921 and 300 nm S1O2 layer as the dielectric.
Figure 9b and Figure 9c show the transport characteristics (lSd-Vg) of the pristine bilayer WSe2 FET in high vacuum condition (10 7 mbar). The results clearly reveal a hole- dominated ambipolar transport behaviour, where gate voltage sweeps from -80 V to
50 V under a fixed bias (VSd = 1 V).
Figure 9d shows Transfer characteristic evolution of the WSe2 FET as a function of Cs thickness following in situ deposition of Cs on the device as described above. The thicknesses shown are Onm (901), O.Olnm (903), 0.07nm (905), 0.19nm (907), 0.4nm (909) and 1.0 nm (911). Two distinct stages can be observed, including i) a significant n-type doping stage with strongly enhanced on-current in the electron transport regime under the low Cs doping level (Cs nominal thickness < 0.2 nm); and ii) the WSe2 device exhibits a nearly gate independent transport behaviour when the Cs nominal thickness is above 0.4 nm, indicating a semiconductor to metal phase transition. Figure 9e shows the electrical conductance (G) versus Cs thickness at Vg = 0V. The electrical conductance (G = lSd/VSd) under Vg = 0 V is remarkably enhanced by nearly 7 orders of magnitude, from 2.1x10 11 S to l.lxlO 4 S after 1.0 nm Cs decoration.
Figure 9f shows output curves (lSd-VSd) for the pristine (915) and 1.0 nm (913) Cs- modified WSe2 FET at different gate voltage, Vg, from 0 to 50 V. As shown in the output curves of the WSe2 device before and after 1.0 nm Cs modification, the pristine WSe2 device exhibits a Schottky contact behaviour, while ohmic contact feature is identified after 1.0 nm Cs decoration. The large enhancement of lSd reveals the reduction of contact and channel resistances, originating from the semiconductor to metal phase transition.
The semiconductor to metal phase transition in the bilayer WSe2 device was further characterised by temperature-dependent transport measurements. The temperature dependent experiments were conducted on a cryogenic stage with liquid nitrogen for sample cooling and the results are shown in Figures 9g and 9h in which the evolution of the electrical conductance for both pristine (917) and Cs-modified (919) bilayer WSe2 device as a function of temperature with the gate voltages of (Figure 9g) Vg = -80
V and (Figure 9h) 50 V. As can be seen from Figures 9g and 9h, the semiconducting and metallic phased bilayer WSe2 devices present opposite evolution trends as a function of temperature. For the pristine semiconducting WSe2 device, the electrical conductance gradually rises with the increase of temperature, originating from the dramatical enhancement of thermally activated carriers. In contrast, increasing temperature in 1.0 nm Cs-modified metallic WSe2 device leads to the decrease of the electrical conductance. High temperature enhances the electron scattering in the metallic WSe2, resulting in the reduction of electrical conductance.
Figure 9i shows the electrical conductance evolution of the bilayer WSe2 device after 1.0 nm Cs functionalization with respect to temperature at different Vg from -80 V to 50 V. The conductance progressively decreases as the temperature increases under all gate voltages, clearly revealing the metallic feature of the Cs-modified WSe2 flake and further corroborating the semiconductor to metal phase transition induced by Cs surface functionalization.
To understand the semiconductor to metal phase transition mechanism for Cs- modified WSe2, in situ XPS/UPS experiments were further employed. In situ UPS and XPS measurements on Cs surface-modified bulk WSe2 (obtained from HQ-graphene) were carried out in an ultrahigh vacuum chamber (base pressure ~ 10 10 mbar). He I
(21.2 eV) was utilized as the excitation source and a sample bias voltage of 5 V was applied for UPS characterization. Al Ka (148.7 eV) served as the excitation source for XPS measurements. The nominal thickness of in situ deposited Cs layers was estimated by monitoring the attenuation of WSe2 core level peaks and further calibrated by QCM. The results are shown in Figure 10 in which Figure 10 (a) shows UPS spectra evolution at low kinetic energy region, Figure 10(b) shows XPS core level spectra of W 4f as a function of Cs thickness on WSe2; Figure 10(c) shows XPS core level spectra of Se 3d as a function of Cs thickness on WSe2 and Figure 10(d) shows UPS valence band spectra near the Fermi level region. Pristine WSe2 is denoted by 1001, O.Olnm Cs by 1003, O.lOnm Cs by 1005, 0.20nm Cs by 1007, 0.40nm Cs by 1009, and l.OOnm Cs by 1011 in all figures. Here f denotes the work function and DE denotes the energy difference.
The work function (WF) of the pristine WSe2 is measured to be ~ 4.02 eV, which sharply dropped to ~2.2 eV after 1.0 nm Cs decoration. The decrease of WF implies the significant electron transfer from Cs to WSe2 at the Cs/WSe2 interface, resulting from the ultralow WF of Cs (~2.14 eV).
Figures 10(b) and 10(c) show the evolution of W 4f and Se 3d core level binding energy as a function of Cs thickness, respectively. As increasing the Cs deposition thickness to 0.2 nm, the electron doping effect of Cs on WSe2 makes the Fermi level of WSe2 move towards its conduction band and hence the binding energy of W 4f and Se 3d slightly increases by 0.1 eV and 0.15 eV, respectively. Intriguingly, when the Cs thickness increases from 0.2 nm to 1.0 nm, the W 4f and Se 3d core levels move towards the lower binding energy by ~0.3 eV and ~0.35 eV, respectively. This is consistent with previous reports of K-functionalization and hence electron-doping induced
semiconductor to metal (2H to IT') phase transition in bilayer WSe2. Further Cs deposition leads to the accumulated negative charge on the metallic WSe2 surface and hence the core level peaks move towards the lower binding energy.
The valence band spectra shown in Figure 10(d) can further validate the metallization of the heavily doped WSe2. At low surface modification levels (Cs thickness < 0.4 nm), a downward band bending of the valence band is observed due to the electron doping. When the Cs thickness is above 0.4 nm, a sharp peak emerges around the Fermi level, clearly revealing the metal-like features, further confirming the semiconductor to metal phase transition.
Figure 11a shows the Photoluminescence (PL) spectra for the bilayer WSe2 flake before
(1103) and after 0.1 nm Cs modification (1101). Figure lib shows the Raman spectra of the pristine, 0.1 nm and 1.0 nm Cs-modified WSe2. Among the three polymorphs in WSe2, both IT and IT' are metallic. Previous reports suggest that the IT phase of group VI TMDs is unstable and spontaneously transforms to IT' phase with energy relaxation. Therefore, without wishing to be bound by theory, it is proposed that the metallic phase of the WSe2 after Cs doping is IT'. In situ Raman and PL were carried out to reveal the phase transition of Cs-modified WSe2 and the results of Figure 11a and lib show in situ PL and Raman spectra, respectively, of the bilayer WSe2 before and after Cs deposition. Upon 0.1 nm Cs deposition, the PL peak for bilayer WSe2 is immediately quenched due to the significant charge transfer. Pristine bilayer WSe2 shows three characteristic peaks in the Raman spectrum located at 250 cm 1 (E12g), 257.5 cm 1 (Aig) and 309 cm 1 (B12g) respectively. After 0.1 nm Cs coverage, the intensity of these peaks is largely reduced. Further increasing the Cs thickness to 1.0 nm leads to the phase transition of the bilayer WSe2 from the semiconducting 2H phase to IT' metallic phase. The B1 2g peak totally vanishes, and five new peaks emerge in the low wavenumber regime, at around ~93, 114, 227, 242 and 260 cm . These new peaks correspond to the characteristic peaks of the WSe2 in IT' phase. Therefore, without wishing to be bound by theory, the phase transition of Cs-modified WSe2 observed here can be assigned to a 2H to IT' phase transition.
Hetero-phase device fabrication
For heterophase device fabrication according to the embodiment of Figure 4, the pristine WSe2 device was first fabricated in accordance with the method described above. In order to realize the partially surface-modified device, PMMA photoresist was spin-coated again and a second EBL process was performed to expose desired area around the contact after the lift off of the excess metal. The device was then loaded into a vacuum system as previously described for Caesium evaporation for electrical characterization.
Fig. 12a exhibits the evolution of the transfer characteristics as a function of Cs thickness, with thicknesses of Onm (1301), 0.05nm (1303), 0.20nm (1305), 0.50nm (1307) and l.OOnm (1309). As discussed before, the WSe2 flake is n-type doped at low Cs deposition level. Further increasing Cs thickness to a high level induces the phase transition in the exposed region, leading to the IT' contact. The saturation current with IT' phase contact is approximately 2 orders of magnitude higher than that of the pristine device with Pd contact, leading to a giant gate modulation effect as well as a high current on/off ratio of ~107.
The field-effect electron mobility is also dramatically improved from 0.6 to
37.7 cm2V 1s 1 as shown in Figure 12b, which shows the evolution of the electron mobility versus Cs thickness. This indicates the superior transport property of the device with IT' contact.
Figures 12c and Figure 12d illustrate the output curves of the device under gate voltages 0V (1311), 20V (1313), 40V (1315) and 50V (1317) before (Figure 12d) and after (Figure 12c) 1.0 nm Cs functionalization. The pristine transistor exhibits a clear
Schottky contact behaviour, whereas an ideal ohmic contact can be observed after Cs functionalization, as reflected by the symmetric and linear feature of the output curves.
Thus, In situ Cs surface modification has been demonstrated as an effective approach to induce the semiconducting to metallic phase transition in 2H WSe2, which offers the opportunity to realize high performance 2H-1T' hetero-phase WSe2 transistor via spatially controlling the phase transition region.
The Schottky barrier height of the hetero-phase transistor was further investigated, and the results are shown in Figure ISa as a function of gate voltage Vg. According to Figure ISa, the SB in the hetero-phase transistor is determined to be as low as ~9.4 meV for the electron-transport. Such negligible SB can significantly enhance the electron injection into the semiconductor, resulting in true Ohmic contact behaviour under high electrostatic doping.
To further quantify the contact quality of the ideal n-type hetero-phase WSe2 transistor, the width normalized contact resistance (Rc) was extracted via the transfer length method (TLM). A series of WSe2 (5-layer) transistors with different channel lengths were employed for the measurement. To ensure accuracy, it was assumed that the channel segments covered by the metal contact have no contribution to the overall channel length. Moreover, since one of the Schottky contacts can easily become forward-biased when applying high bias voltage, a very small bias (~10 mV) was employed in order to avoid an underestimation of the Rc. Figure 13b shows the width-normalized total resistance (Rtot) as a function of the channel length at Vg = 5 V. The Rtot is linearly fitted, where the y intercept yields the total contact resistance (2RC) and the slope represents the sheet resistance (RSh) of the channel. A low contact resistance of ~4.3 kQ pm is obtained at Vg = 5 V, which can be attributed to the combined effects of the SB height lowing and the SB width narrowing.
To fabricate a sandwich framework device, according to the embodiment of Figure 5, few-layer graphene (commercially obtained from HQ-Graphene) was firstly exfoliated on a SiCh/Si substrate via scotch tape. Then 15 nm-thick hexagonal boron nitride (n- BN) (commercially obtained from ACS Material, LLC) and WSe2 (commercially obtained from HQ-graphene) were subsequently exfoliated on a viscoelastic stamp using polydimethylsiloxane (PDMS) (commercially obtained from the Merck Group) and transferred onto the desired graphene flake. The procedures described above were employed to obtain a contact exposure channel to achieve the 2H-1T' hetero-phase FET. The device was then loaded into a high vacuum chamber for further
measurements. Figure 14a shows the transfer characteristic evolution of the device as a function of Cs thickness. Results for Cs thicknesses of O.Onm (1401), O.Olnm (1403), 0.08nm (1405),
0.20nm (1407) and l.OOnm (1409) are shown.
Low-level Cs deposition induces an electron-doping effect in the uncovered WSe2. Further increasing the Cs thickness leads to the phase transition of the uncovered WSe2, and hence the realization of 2H-GG contact. It is worth noting that the on current of the 2H-GG hetero-phase device is approximately 3 orders of magnitude higher than that of the pristine device with Pd contact, leading to an ultrahigh current on/off ratio ~108. In addition, the subthreshold swing (SS) defined as dVg/d(loglSd) is optimized to 75 mV dec-1, which is close to the theoretical limit of 60 mV dec-1. The field-effect mobility can be extracted from the linear regime of the transfer curve by using the equation:
Figure imgf000060_0001
where L and W denote the length and width of the conduction channel, respectively, Q denotes the capacitance per unit area of the dielectric and dlSd/dVSd represents the slope of the linear region in the transfer plot. Figure 14b shows the corresponding electron mobility versus Cs thickness. The electron mobility is significantly enhanced from 1.33 cm2V _1s 1 to 70 cm2V _1s 1 by nearly
50 times.
Figures 14c and 14d show output curves for the device before (Figure 14c) and after 1.0 nm (Figure 14d) Cs contact doping at different gate voltages 0V (1415), IV (1417), 2V (1419), 3V (1421), 4V (1423) and 5V (1425). The output curves of the pristine WSe device are nonlinear even at a high electrostatically doping level (Vg ~ 5V), illustrating a clear Schottky contact behaviour. After 1.0 nm Cs modification, the current is largely improved by over 2 orders of magnitude at each gate voltage. Moreover, the output curves are almost linear especially at the low VSd regime, suggesting a nearly-ideal ohmic contact.
A second sandwich framework device according to the embodiment of Figure 5, was fabricated in accordance with the same procedure described above. Figure 14e shows the transfer characteristic evolution as a function of Cs thickness for this second device. Results for Cs thicknesses of O.Onm (i.e. pristine WSe2; 1413) and l.OOnm
(1411) are shown.
The current on/off ratio of the Cs doped device was found to be even higher at ~109. In addition, the subthreshold swing (SS) defined was measured to be 61 mV dec-1. A device according to the embodiment of Figure 6 was fabricated as described above with regard to the FET sandwich device but modified to obtain a contact exposure channel and a full PMMA covered channel. As before, the device was loaded into a high vacuum chamber for further measurements.
Figure 15a shows transfer characteristics for N-FET 1501 and P-FET 1503
demonstrating that unipolar hetero-phase n-type transistor can be obtained through spatially controlling the exposed regions near the metal electrodes of one WSe2 channel, while p-type dominated ambipolar transport behaviour is retained in the other channel which is fully covered by the PMMA photoresist.
Figure 15b shows the output characteristics of the homogeneous WSe2 inverter as a function of V,N at VDD = 1 V (1505), 2 V (1507), and 2.5 V (1509) respectively. By sweeping the input voltage from -1 V to 2 V, the inverter experiences a 'high state' (high VOUT), 'steep slope' (sharp decrease of VOUT), and a 'low state' (low VOUT) sequentially. One key parameter to evaluate the performance of the inverter is the voltage gain defined by the slope of output characteristics (gain = -dVoui/dViN). This is further shown in Figure 16 (a) which shows the output characteristics as a function of VIM at VDD = 0.5 V (1601), 1.0 V (1603), 1.5 V (1605), 2.0V (1607) and 2.5V (1609). Figure 15c shows the extracted gain as a function of VIN at three different VDD
(reference numerals as above). At small VDD of 1 V, the gain is around 13. By increasing the VDD to 2 V and 2.5 V, the gain can reach up to 49 and 106, respectively. It is noted that these gains are the highest among all 2D-material-based homo-inverters. Without wishing to be bound by theory, it is proposed that such high gain is mainly attributed to the low SS (~75 mV dec-1) and ultrahigh current on/off ratio (~108) of the Cs- modified WSe2 transistor, which ensure the fast switching between the 'high state' and the 'low state' of the inverter.
Figure 15d shows the evolution of the power consumption of the device versus \/DDfrom 0.5 V to 2.5 V. The power is around 280 nW at VDD = 2.5 V, which progressively decreases to an ultralow value of ~5 pW at VDD = 0.5 V. It is worth noting that the gain at VDD = 0.5 V can be maintained at a proper level of around 8 which is highly competitive among all 2D-material-based logic inverters for such an ultralow power consumption. This is shown in Figure 16(b) which shows the output curve (1611) and corresponding voltage gain (1613) as a function of VIN at VDD = 0.5 V.
The results above show the realisation of a semiconducting-to-metallic (2H to IT') phase transition in WSe2 via in situ Cs surface functionalization. The phase transition is firstly revealed by the in situ electrical characterization of the WSe2 FET. The Cs- functionalized WSe2 transistor exhibits gate-independent transport behaviour with nearly 7 orders of magnitude enhancement in electrical conductance. As revealed by the in-situ UPS/XPS and Raman measurements, the 2H to IT' phase transition originates from the giant electron doping from Cs to WSe2. By implementing the IT' phase WSe2 so formed as the contact electrodes, a 2H-1T' hetero-phase WSe2 transistor is obtained with remarkably enhanced field-effect electron mobility, increased by nearly 50 times, reaching up to ~70 cm2V _1s _1. Moreover, the device demonstrates an ultrahigh current on/off ratio ~108and low SS ~75 mV dec-1, enabling the realization of high performance WSe2 logic inverter with ultralow power consumption of ~5 pW and a high voltage gain of ~106, higher than all the 2D-material- based homo-inverters.
Although the above results were obtained under vacuum, the skilled person will appreciate that any environment that excludes oxygen and water could equivalently have been employed, such as a substantially 100% N2, or otherwise inert environment under normal atmospheric conditions.
Thus, alkali metal functionalization induced phase transition, particularly Cs metal functionalization induce phase transition in TMDs provides a simple method to achieve high performance TMD hetero-phase transistor and logic inverter. In particular, in situ alkali-metal surface modification, particularly in situ Cs surface modification, has been demonstrated as an effective approach to induce the semiconducting to metallic phase transition in 2H TMDs, which offers the opportunity to realize a high performance 2H-1T' hetero-phase TMD transistor via spatially controlling the phase transition region.
In the foregoing detailed description, embodiments of the present disclosure in relation to a transition metal dichalcogenide and devices thereof are described with reference to the provided figures. The description of the various embodiments herein is not intended to call out or be limited only to specific or particular representations of the present disclosure, but merely to illustrate non-limiting examples of the present disclosure. The present disclosure serves to address at least one of the mentioned problems and issues associated with the prior art. Although only some embodiments of the present disclosure are disclosed herein, it will be apparent to a person having ordinary skill in the art in view of this disclosure that a variety of changes and/or modifications can be made to the disclosed embodiments without departing from the scope of the present disclosure. Therefore, the scope of the disclosure as well as the scope of the following claims is not limited to embodiments described herein.
Further embodiments are given in the following statements:
1. A transition metal dichalcogenide (TMD) including a first portion, wherein the first portion is surface modified with a Group 1 alkali metal.
2. The TMD of 1, wherein the Group 1 alkali metal forms a layer on a side of the first portion.
3. The TMD of 1 or 2, wherein the Group 1 alkali metal is selected from lithium, sodium, potassium, rubidium, caesium or francium.
4. The TMD of any of 1 to 3, further including a second portion, wherein the first portion has a different phase structure to the second portion.
5. The TMD of any of 1 to 4, wherein the first portion has a metallic octahedral (IT') phase structure. 6. The TMD of any of 1 to 5, wherein a thickness of the Group 1 alkali metal in the first portion is from about 0.2 nm to about 10 nm.
7. The TMD of any of 1 to 6, the TMD is selected from M0S2, WS2, MoSe2 and WSe2,
MoTe2, alkali metal-doped MoTe2, alkali metal-doped MoSe2, alkali metal-doped M0S2, alkali metal-doped WTe2, alkali metal-doped WSe2, or alkali metal-doped WS2. 8. An electronic device, including: a layer of a transition metal dichalcogenide (TMD) including a first portion, wherein the first portion is surface modified with a Group 1 alkali metal; and a pair of electrodes connected to the layer of the TMD. 9. The electronic device of 8, having an electrical conductance of at least 4 times to that of a control.
10. The electronic device of 8 or 9, having a contact resistance of about 1 kQ pm to about 10 kQ pm.
11. The electronic device of any of 8 to 10, having an electron mobility of at least about 70 cm2V _1s _1.
12. The electronic device of any of 8 to 11, having a current on/off ratio of at least about 80.
13. The electronic device of any of 8 to 12, having a subthreshold swing (SS) of at least about 60 mV dec 1.
14. The electronic device of any of 8 to 13, having a voltage gain of about 100.
15. The electronic device of any of 8 to 14, having a power consumption of less than about 10 pW.
16. The electronic device of any of 8 to 15, the electronic device is a logic inverter or a field effect transistor.
17. An electronic circuit comprising the electronic device of any of 8 to 16.
18. An electronic system comprising the electronic circuit of 17.

Claims

1. A material comprising: a transition metal dichalcogenide (TMD) comprising a surface, a least a portion of the surface being surface-modified with one or more Group 1 metals, wherein the one or more Group 1 metals comprise Cs and/or Rb.
2. The material of claim 1, wherein the transition metal dichalcogenide comprises one or more of M0S2, WS2, MoSe2, WSe2, MoTe2, alkali metal-doped MoTe2, alkali metal-doped MoSe2, alkali metal-doped M0S2, alkali metal-doped WSe2, and alkali metal-doped WS2.
3. The material of claim 2, wherein the transition metal dichalcogenide comprises one or more of WSe2 and/or MoTe2.
4. The material of claim 3, wherein the transition metal dichalcogenide comprises
WSe2.
5. The material any one of the preceding claims, the one or more Group 1 metals forming a layer on the surface.
6. The material of any one of the preceding claims, the one or more Group 1 metals forming a layer on the surface of at least first and second portions of the transition metal dichalcogenide.
7. The material of claim 6, wherein the transition metal dichalcogenide further comprises a third portion which is not surface modified with one or more
Group 1 metals.
8. The material of claim 7, wherein the first and second portions are in a different phase than the third portion.
9. The material of either of claims 7 or 8, wherein the layer of one or more Group 1 metals has a thickness of greater than or equal to 0.2nm.
10. The material of claim 9, wherein the layer of one or more Group 1 metals has a thickness of between 0.4nm and 2.0nm.
11. The material of any one of the preceding claims, wherein at least a portion of the transition metal dichalcogenide has a thickness of between 1 and 5 layers.
12. The material of claim 11, wherein at least a portion of the transition metal dichalcogenide is a mono-layer or a bi-layer. IB. An electronic device comprising the material of any one of claims 7 to 12; and first and second electrodes,
wherein the first and second electrodes are in direct electrical contact with the first and second portions of the transition metal dichalcogenide, respectively.
14. The electronic device of claim 13, wherein the device exhibits substantially Ohmic contact behaviour with respect to the first and second electrodes.
15. The electronic device of either claim 13 or 14 having a Schottky barrier height of less than or equal to lOmeV.
16. The electronic device of any one of claims 13 to 15, wherein the electronic device is a field-effect transistor.
17. The electronic device of any one of claims 13 to 15, wherein the electronic device is a logic inverter.
18. A method of producing the material of any one of claims 1 to 12, the method comprising: providing a transition metal dichalcogenide; and evaporating one or more Group 1 metals onto at least a portion of a surface of the transition metal dichalcogenide, wherein the one or more group 1 metals comprises Cs and/or Rb.
19. A method of producing the electronic device of any one of claims 13 to 17, the method comprising: providing a layer of transition metal dichalcogenide and first and second electrodes on the surface of a substrate, such that the first and second electrodes are in electrical contact with the layer of transition metal dichalcogenide; evaporating one or more Group 1 metals onto a surface of first and second portions of the layer of transition metal dichalcogenide such that the one or more Group 1 metals has a thickness of at least 0.2nm, wherein the first and second portions of the layer of transition metal dichalcogenide are adjacent to the first and second electrodes respectively, and wherein the one or more
Group 1 metals comprise Cs and/or Rb.
20. The method of claim 19, wherein evaporating a Group 1 metal onto a surface of first and second portions of the layer of transition metal dichalcogenide comprises forming a barrier layer on portions of the surface of all but the first and second portions of the transition metal dichalcogenide prior to evaporating the one or more Group 1 metals.
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