CN114072926A - Transition metal dichalcogenides and their use - Google Patents
Transition metal dichalcogenides and their use Download PDFInfo
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- 229910052723 transition metal Inorganic materials 0.000 title claims abstract description 56
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- 239000003513 alkali Substances 0.000 claims description 8
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
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- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
- H01L21/441—Deposition of conductive or insulating materials for electrodes
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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Abstract
A material (1) comprising: a transition metal dichalcogenide (107), said transition metal dichalcogenide (107) comprising a surface (109), at least a portion of said surface being surface modified with one or more group 1 metals (103), wherein said one or more group 1 metals comprise cesium and/or rubidium.
Description
Cross Reference to Related Applications
The present disclosure claims the benefit of singapore patent application No. 10201906808T, which is incorporated herein by reference in its entirety.
Technical Field
The present invention relates to transition metal dichalcogenides, and in particular to the use of transition metal dichalcogenides in electronic devices.
Background
Two-dimensional (2D) Transition Metal Dichalcogenide (TMD) has been established as a promising building block for next generation nanoelectronic devices, showing great potential to extend the scale limitations of silicon-based Complementary Metal Oxide Semiconductor (CMOS) Field Effect Transistors (FETs).
Tungsten diselenide (WSe), one of the most studied TMD materials2) There are three major polymorphs, including a semiconducting triangular prism (2H phase), a metal octahedron (1T phase) and a distorted octahedron (1T' phase). 2H semiconductor WSe2A great advantage is shown in complementary logic devices due to their bipolar transmission properties with high current on/off ratios. However, similar to other TMDs, based on 2H WSe2Is usually in the metal contact/WSe2High Schottky barrier height (Schottky barrier height) and high contact resistance at the interface, which reduces WSe2The performance of the FET, including conductivity and carrier mobility.
In order to reduce the WSe-based2Various methods such as metal contact engineering, ionic liquid gate, photodoping, and surface charge transfer doping are currently being explored for the contact resistance of FETs.
Several methods have also been employed to induce the 2H to 1T/1T' phase transition in TMD, such as alkali metal intercalation, strain engineering, ionic liquid grids, and laser irradiation. However, alkali metal intercalation requires soaking TMD in chemical liquids, such as n-butyl lithium (n-BuLi) or t-butyl lithium (t-BuLi), which is complicated and time consuming. Strain engineering and ionic liquid grids require harsh conditions to be successful. High energy laser irradiation can cause undesirable and irreversible damage to the sample.
There is a continuing need to improve the performance of electronic devices based on TMD materials.
Disclosure of Invention
In a first aspect, there is provided a material comprising: a Transition Metal Dichalcogenide (TMD) comprising a surface, at least a portion of the surface being surface modified with one or more group 1 metals, wherein the one or more group 1 metals comprise Cs and/or Rb.
The Transition Metal Dichalcogenide (TMD) has the general formula MX2Wherein M is a transition metal atom and X is a chalcogen atom.
The transition metal dichalcogenide may include one or more of the following: MoS2、WS2、MoSe2And WSe2、MoTe2Alkali metal doped MoTe2Alkali metal doped MoSe2Alkali metal doped MoS2Alkali metal doped WSe2And alkali metal-doped WS2. The transition metal dichalcogenide may include WSe2And/or MoTe2One or more of (a). The transition metal dichalcogenide may include WSe 2.
The TMD may comprise one or more impurities.
The transition metal dichalcogenide may be substantially two-dimensional (2-D). A portion of the transition metal dichalcogenide may be substantially two-dimensional. A portion or all of the transition metal dichalcogenide may have a thickness of 1 layer to 5 layers. A portion or all of the transition metal dichalcogenide may comprise a monolayer or bilayer.
"surface modified" or "surface modification" refers to altering the surface of a material by introducing a physical, chemical, or biological property that is different from the physical, chemical, or biological property originally found on the surface of the material. For example, if a surface is functionalized by adding new functions, features, capabilities, or properties to the material, the surface is modified. The modification changes the surface chemistry of the material. In this respect, the modification or functionalization is only present on the surface and does not penetrate into the material. In contrast, "doping" refers to the intentional introduction of impurities into an intrinsic semiconductor to adjust its electrical, optical, and structural properties. In this regard, impurities are present within the semiconductor.
Part of the TMD surface may be surface modified and part may not be surface modified. All surfaces may be surface modified. Portions of the surface may be surface modified. The surface may be modified with a mixture of two or more alkali metals. The surface may be modified with cesium and/or rubidium only. A portion of the TMD may be surface modified with cesium and/or rubidium, while another portion may be surface modified with another alkali metal. The one or more alkali metals may comprise one or more impurities.
The one or more alkali metals may include cesium and one or more elements selected from lithium, sodium, potassium, and rubidium.
The one or more alkali metals may include rubidium and one or more elements selected from lithium, sodium, potassium, and cesium.
The alkali metal may be in direct contact with the surface of the TMD. There may be a direct interface between the alkali metal and the TMD.
One or more group 1 metals may form a layer on the surface of TMD. The layer of the group 1 metal can have a thickness greater than or equal to 0.2 nm. The layer may have a thickness of less than or equal to 5.0 nm. The layer of the group 1 metal may have a thickness of 0.4nm to 2.0 nm.
For the avoidance of doubt, it is expressly contemplated that where a plurality of numerical ranges relating to the same feature are referred to herein, the endpoints of each range are intended to be combined in any order to provide other contemplated (and implicitly disclosed) ranges. Accordingly, with respect to the above-described relevant numerical ranges, there are disclosed:
0.0nm to 0.01nm, 0.0nm to 0.05nm, 0.0nm to 0.07nm, 0.0nm to 0.08nm, 0.0nm to 0.1nm, 0.0nm to 0.19nm, 0.0nm to 0.20nm, 0.0nm to 0.4nm, 0.0nm to 0.5nm, 0.0nm to 0.6nm, 0.0nm to 1.0nm, 0.0nm to 2.0nm, 0.0nm to 5.0 nm;
0.01nm to 0.05nm, 0.01nm to 0.07nm, 0.01nm to 0.08nm, 0.01nm to 0.1nm, 0.01nm to 0.19nm, 0.01nm to 0.20nm, 0.01nm to 0.4nm, 0.01nm to 0.5nm, 0.01nm to 0.6nm, 0.01nm to 1.0nm, 0.01nm to 2.0nm, 0.01nm to 5.0 nm;
0.05nm to 0.07nm, 0.05nm to 0.08nm, 0.05nm to 0.1nm, 0.05nm to 0.19nm, 0.05nm to 0.20nm, 0.05nm to 0.4nm, 0.05nm to 0.5nm, 0.05nm to 0.6nm, 0.05nm to 1.0nm, 0.05nm to 2.0nm, 0.05nm to 5.0 nm;
0.07nm to 0.08nm, 0.07nm to 0.1nm, 0.07nm to 0.19nm, 0.07nm to 0.20nm, 0.07nm to 0.4nm, 0.07nm to 0.5nm, 0.07nm to 0.6nm, 0.07nm to 1.0nm, 0.07nm to 2.0nm, 0.07nm to 5.0 nm;
0.08 to 0.1nm, 0.08 to 0.19nm, 0.08 to 0.20nm, 0.08 to 0.4nm, 0.08 to 0.5nm, 0.08 to 0.6nm, 0.08 to 1.0nm, 0.08 to 2.0nm, 0.08 to 5.0 nm;
0.10nm to 0.19nm, 0.10nm to 0.20nm, 0.10nm to 0.4nm, 0.10nm to 0.5nm, 0.10nm to 0.6nm, 0.10nm to 1.0nm, 0.10nm to 2.0nm, 0.10nm to 5.0 nm;
0.19nm to 0.20nm, 0.19nm to 0.4nm, 0.19nm to 0.5nm, 0.19nm to 0.6nm, 0.19nm to 1.0nm, 0.19nm to 2.0nm, 0.19nm to 5.0 nm;
0.2nm to 0.4nm, 0.2nm to 0.5nm, 0.2nm to 0.6nm, 0.2nm to 1.0nm, 0.2nm to 2.0nm, 0.2nm to 5.0 nm;
0.4nm to 0.5nm, 0.4nm to 0.6nm, 0.4nm to 1.0nm, 0.4nm to 2.0nm, 0.4nm to 5.0 nm;
0.5nm to 0.6nm, 0.5nm to 1.0nm, 0.5nm to 2.0nm, 0.5nm to 5.0 nm;
0.6nm to 1.0nm, 0.6nm to 2.0nm, 0.6nm to 5.0 nm;
1.0nm to 2.0nm, 1.0nm to 5.0 nm; and
2.0nm to 5.0 nm.
The one or more surface modified portions of a TMD may be in a different phase than the one or more non-surface modified portions of the TMD. The one or more surface-modified moieties may be in the 1T or 1T' phase, while the one or more non-surface-modified moieties may be in the 2H phase.
As known in the art, "2H" refers to a hexagonal phase structure and "1T" refers to a metal monoclinic or octahedral phase structure.
In one aspect, there is provided an electronic device comprising: a Transition Metal Dichalcogenide (TMD) comprising first and second portions that are surface modified with one or more group 1 metals and a third portion that is not surface modified with one or more group 1 metals; and first and second electrodes, wherein the first and second electrodes are in direct electrical contact with the first and second portions of the transition metal dichalcogenide, respectively, wherein the one or more group 1 metals comprise cesium and/or rubidium.
The transition metal dichalcogenide may include one or more of the following: MoS2、WS2、MoSe2And WSe2、MoTe2Alkali metal doped MoTe2Alkali metal doped MoSe2Alkali metal doped MoS2Alkali metal doped WSe2And alkali metal-doped WS2. The transition metal dichalcogenide may include WSe2And/or MoTe2One or more of (a). The transition metal dichalcogenide may include WSe 2.
The one or more alkali metals may include cesium, and the transition metal dichalcogenide may include WSe2。
The TMD may comprise one or more impurities.
The transition metal dichalcogenide may be substantially two-dimensional (2-D). A portion of the transition metal dichalcogenide may be substantially two-dimensional. A portion or all of the transition metal dichalcogenide may have a thickness of 1 layer to 5 layers. A portion or all of the transition metal dichalcogenide may comprise a monolayer or bilayer.
The surface may be modified with a mixture of two or more alkali metals. The surface may be modified with cesium and/or rubidium only. A portion of the TMD may be surface modified with cesium and/or rubidium, while another portion may be surface modified with another alkali metal. The one or more alkali metals may comprise one or more impurities.
One or more group 1 metals may form a layer on the surface of TMD. The layer of the group 1 metal can have a thickness greater than or equal to 0.2 nm. The layer may have a thickness of less than or equal to 5.0 nm. The layer of the group 1 metal may have a thickness of 0.4nm to 2.0 nm.
The thickness of the one or more alkali metals may fall within one of the following ranges: 0.0nm to 0.01nm, 0.0nm to 0.05nm, 0.0nm to 0.07nm, 0.0nm to 0.08nm, 0.0nm to 0.1nm, 0.0nm to 0.19nm, 0.0nm to 0.20nm, 0.0nm to 0.4nm, 0.0nm to 0.5nm, 0.0nm to 0.6nm, 0.0nm to 1.0nm, 0.0nm to 2.0nm, 0.0nm to 5.0 nm; 0.01nm to 0.05nm, 0.01nm to 0.07nm, 0.01nm to 0.08nm, 0.01nm to 0.1nm, 0.01nm to 0.19nm, 0.01nm to 0.20nm, 0.01nm to 0.4nm, 0.01nm to 0.5nm, 0.01nm to 0.6nm, 0.01nm to 1.0nm, 0.01nm to 2.0nm, 0.01nm to 5.0 nm; 0.05nm to 0.07nm, 0.05nm to 0.08nm, 0.05nm to 0.1nm, 0.05nm to 0.19nm, 0.05nm to 0.20nm, 0.05nm to 0.4nm, 0.05nm to 0.5nm, 0.05nm to 0.6nm, 0.05nm to 1.0nm, 0.05nm to 2.0nm, 0.05nm to 5.0 nm;
0.07nm to 0.08nm, 0.07nm to 0.1nm, 0.07nm to 0.19nm, 0.07nm to 0.20nm, 0.07nm to 0.4nm, 0.07nm to 0.5nm, 0.07nm to 0.6nm, 0.07nm to 1.0nm, 0.07nm to 2.0nm, 0.07nm to 5.0 nm; 0.08 to 0.1nm, 0.08 to 0.19nm, 0.08 to 0.20nm, 0.08 to 0.4nm, 0.08 to 0.5nm, 0.08 to 0.6nm, 0.08 to 1.0nm, 0.08 to 2.0nm, 0.08 to 5.0 nm; 0.10nm to 0.19nm, 0.10nm to 0.20nm, 0.10nm to 0.4nm, 0.10nm to 0.5nm, 0.10nm to 0.6nm, 0.10nm to 1.0nm, 0.10nm to 2.0nm, 0.10nm to 5.0 nm;
0.19nm to 0.20nm, 0.19nm to 0.4nm, 0.19nm to 0.5nm, 0.19nm to 0.6nm, 0.19nm to 1.0nm, 0.19nm to 2.0nm, 0.19nm to 5.0 nm; 0.2nm to 0.4nm, 0.2nm to 0.5nm, 0.2nm to 0.6nm, 0.2nm to 1.0nm, 0.2nm to 2.0nm, 0.2nm to 5.0 nm; 0.4nm to 0.5nm, 0.4nm to 0.6nm, 0.4nm to 1.0nm, 0.4nm to 2.0nm, 0.4nm to 5.0 nm; 0.5nm to 0.6nm, 0.5nm to 1.0nm, 0.5nm to 2.0nm, 0.5nm to 5.0 nm; 0.6nm to 1.0nm, 0.6nm to 2.0nm, 0.6nm to 5.0 nm; 1.0nm to 2.0nm, 1.0nm to 5.0 nm; and 2.0nm to 5.0 nm.
The one or more surface modified portions of a TMD may be in a different phase than the one or more non-surface modified portions of the TMD. The one or more surface-modified moieties may be in the 1T or 1T' phase, while the one or more non-surface-modified moieties may be in the 2H phase.
The device may exhibit substantially ohmic contact characteristics with respect to the first and second electrodes. In this context, the ohmic contact characteristic means that the current between the two electrodes of the device has a substantially linear dependence on the voltage.
The device may have a schottky barrier height of less than or equal to 10 meV. The device may have a schottky barrier height of less than or equal to 9.4 meV. The device may have a schottky barrier height of 9meV to 10meV or 9.4meV to 10 meV.
The field effect electron mobility of the device at room temperature (298K) may be 35cm2V1s-1Or larger, in particular 37.7cm2V1s-1Or larger, more particularly 70cm2V1s-1Or larger. The device may have a field effect electron mobility at room temperature (298K) that falls within one of the following ranges: 35cm2V1s-1To 37.7cm2V1s-1、35cm2V1s-1To 70cm2V-1s-1、35cm2V1s-1To 75cm2V-1s-1；37.5cm2V1s-1To 70cm2V-1s-1、37.5cm2V1s-1To 75cm2V-1s-1；70cm2V1s-1To 75cm2V-1s-1。
The device may have a 10 at room temperature (298K)6Or greater, especially 107Or greater, further especially 108Or a greater current on/off ratio. The device may have a thickness of about 109Current on/off ratio of (d). The current on/off ratio of the device at room temperature may fall within one of the following ranges: 106To 107、106To 108、106To 109；107To 108、107To 109(ii) a And 108To 109。
The device may have 85mV dec at room temperature (298K)-1Or less, in particular 75mV dec-1Or less, further especially at 60mV dec-1To 75mV dec-1A subthreshold swing within a range of (a). The device may have 61mV dec-1Sub-threshold swing of (d). The device may have a subthreshold swing that falls within one of the following ranges: 60mV dec-1To 61mV dec-1、60mV dec-1To 75mV dec-1、60mV dec-1To 85mV dec-1；61mV dec-1To 75mV dec-1、61mV dec-1To 85mV dec-1(ii) a And 75mV dec-1To 85mV dec-1。
The electronic device may be a field effect transistor.
The electronic device may be a logic inverter. The gain of the inverter can be greater than 100. In the case where the power consumption is less than 10pW, the gain of the inverter may be able to be greater than 5.
The material and/or device may be maintained under substantially vacuum conditions. The device may be operated under substantially vacuum conditions. The device may also include a vacuum chamber configured to accommodate the surface modified TMD under substantially vacuum conditions. Substantially vacuum conditions mean 10-7A pressure of mbar or less.
The materials and/or devices may be kept under a nitrogen atmosphere. The material and/or device may be encapsulated with a nitrogen atmosphere. The nitrogen atmosphere may be a substantially 100% nitrogen environment.
The material and/or device may include a package configured or arranged to prevent oxygen and water from contacting the surface modified TMD. The package may be configured to retain the surface modified TMD under vacuum. The packaging can be configured to maintain the surface modified TMD under nitrogen (N)2) Or other inert atmosphere.
In one aspect, there is provided a method of producing a material comprising: a Transition Metal Dichalcogenide (TMD) comprising a surface, at least a portion of the surface being surface modified with one or more group 1 metals, wherein the one or more group 1 metals comprise Cs and/or Rb, the method comprising: providing a transition metal dichalcogenide; and evaporating one or more group 1 metals onto at least a portion of the surface of the transition metal dichalcogenide, wherein the one or more group 1 metals include Cs and/or Rb.
In one aspect, there is provided a method of producing an electronic device comprising: a Transition Metal Dichalcogenide (TMD) comprising first and second portions that are surface modified with one or more group 1 metals and a third portion that is not surface modified with one or more group 1 metals; and first and second electrodes, wherein the first and second electrodes are in direct electrical contact with first and second portions of a transition metal dichalcogenide, respectively, wherein the one or more group 1 metals comprise cesium and/or rubidium, the method comprising: providing a transition metal dichalcogenide layer and first and second electrodes on a surface of a substrate such that the first and second electrodes are in electrical contact with the transition metal dichalcogenide layer; evaporating one or more group 1 metals onto surfaces of the first and second portions of the transition metal dichalcogenide layer such that the thickness of the one or more group 1 metals is at least 0.2nm, wherein the first and second portions of the transition metal dichalcogenide layer are adjacent to the first and second electrodes, respectively, and wherein the one or more group 1 metals comprise Cs and/or Rb.
Drawings
Embodiments are described below with reference to the drawings, in which:
FIG. 1 illustrates a material according to one embodiment;
FIG. 2 illustrates a material according to one embodiment;
FIG. 3a and FIG. 3b show WSe, respectively22H phase and 1T' phase;
FIG. 4 illustrates a device according to an embodiment;
FIG. 5 illustrates a device according to an embodiment;
FIG. 6 shows a device according to an embodiment;
FIG. 7 illustrates a method of producing a material according to one embodiment;
FIG. 8a shows a slave dual layer WSe2Line profile from Atomic Force Microscope (AFM) images of the devices;
FIG. 8b shows a dual layer WSe2Raman measurement of the device;
FIG. 8c shows a dual layer WSe2Photoluminescence (PL) measurements of the devices;
FIG. 9a shows a bilayer WSe with surface modification2A schematic diagram of a device;
FIGS. 9b and 9c show the original dual layer WSe2Transfer characteristic (I) of FETsd-Vg)；
FIG. 9d shows WSe as a function of Cs thickness2The propagation characteristics of the FET evolve;
FIG. 9e shows WSe2The conductivity (G) of the FET at Vg ═ 0V versus Cs thickness;
FIG. 9f shows the pristine and 1.0nm Cs modified WSe2Output curve (I) of FETsd-Vsd)；
FIGS. 9g and 9h show Cs-modified WSe2A temperature dependent transmission measurement of the FET;
FIG. 9i shows the dual layer WSe after 1.0nm Cs functionalization versus temperature at different Vg2The evolution of the conductivity of the device;
FIGS. 10(a) to 10(d) show a double-layer WSe2In-situ XPS and UPS results of the device;
FIG. 11a shows a bilayer WSe before and after 0.1nm Cs modification2Photoluminescence (PL) spectrum of the flake;
FIG. 11b shows bilayer WSe before and after 0.1nm Cs modification2Raman measurement of the thin slice;
figure 12a shows the evolution of the transfer characteristic of a device according to an embodiment as a function of the Cs thickness;
FIG. 12b shows the evolution of the field effect electron mobility of the device;
fig. 12c and 12d show the output curves of the device before and after Cs modification at a range of gate voltages, respectively;
fig. 13a shows schottky barrier heights of a multiphase transistor according to an embodiment;
FIG. 13b shows a view at VgWidth-normalized total resistance (R) of a multiphase transistor as a function of channel length at 5Vtot)；
Fig. 14a shows the device transfer characteristic evolution as a function of Cs thickness for a sandwich structure device according to an embodiment;
FIG. 14b shows the corresponding electron mobility versus Cs thickness;
FIGS. 14c and 14d show the output curves of the device before and after 1.0nm Cs contact doping at different gate voltages in the range of 1V to 5V, respectively;
fig. 14e shows the device transfer characteristic evolution as a function of Cs thickness for another sandwich structure device according to an embodiment;
FIG. 15a illustrates a transfer characteristic of a logic inverter according to one embodiment;
FIG. 15b shows the output characteristics of the inverter;
FIG. 15c shows the inverter at three different VDDLower following VINA varying extraction gain;
FIG. 15d shows the evolution of the power consumption of the inverter with VDDThe relationship of (1);
FIG. 16(a) shows an in-phase WSe according to one embodiment2An output characteristic of the inverter; and
FIG. 16(b) shows the following V of the inverterINA varying output curve and corresponding voltage gain.
Detailed Description
For the sake of brevity and clarity, the description of the methods of practice of the present disclosure refers to transition metal dichalcogenides and uses thereof, in accordance with the accompanying drawings. While various aspects of the present disclosure will be described in conjunction with the embodiments provided herein, it will be understood that they are not intended to limit the present disclosure to these embodiments. On the contrary, the present disclosure is intended to cover alternatives, modifications and equivalents of the embodiments described herein, which are included within the scope of the present disclosure as defined by the appended claims. Furthermore, in the following detailed description, specific details are set forth in order to provide a thorough understanding of the present disclosure. However, one of ordinary skill in the art, i.e., the skilled artisan will recognize that the present disclosure can be practiced without, and/or with multiple details from, the combination of particular embodiments of the various aspects. In many instances, well known systems, methods, procedures, and components have not been described in detail so as not to unnecessarily obscure implementations of aspects of the present disclosure.
In embodiments of the disclosure, a description of a given element or a consideration or use of a particular element number in a particular figure or its reference in corresponding descriptive material may encompass the same, equivalent, or similar element or element number specified in another figure or the descriptive material associated therewith.
References to "one embodiment/example," "another embodiment/example," "some embodiments/examples," "some other embodiments/examples," etc., indicate that the embodiment/example so described may include a particular feature, structure, characteristic, property, element, or limitation, but not every embodiment/example necessarily includes the particular feature, structure, characteristic, property, element, or limitation. Moreover, repeated use of the phrases "in one embodiment" or "in another embodiment" does not necessarily refer to the same embodiment/embodiment.
The terms "comprising", "including", "having" and the like do not exclude the presence of other features/elements/steps than those listed in a particular embodiment, nor do they require the presence of other features. The recitation of certain features/elements/steps in mutually different embodiments does not imply that a combination of these features/elements/steps cannot be used in an embodiment.
The terms "a" and "an," as used herein, are defined as one or more than one. The use of "/" in the figures or related text should be understood as "and/or" unless otherwise indicated. Recitation of specific values or ranges of values herein is understood to include or describe the approximate value or range of values.
Fig. 1 shows a schematic view of a material 1 according to an embodiment. In the embodiment of fig. 1, the material comprises a Transmissive Metal Dichalcogenide (TMD) layer 101.
On the surface 109 of the TMD 101, a layer 103 of one or more alkali metals is provided, i.e. the surface of the TMD is surface modified with one or more alkali metals. In the embodiment of fig. 1, an alkali metal is disposed on the surface of two portions 105 of the TMD 101. In the embodiment of fig. 1, the portions 107 of the TMD located between the regions 105 are not surface modified by the alkali metal 103. In other embodiments, all portions of a TMD may be surface modified, or only one portion or a greater number of portions of a TMD may be surface modified.
The thickness of the TMD is not particularly limited. In embodiments, the TMD may be provided as a single layer, a double layer, or a multilayer, for example, having a thickness of 3 to 5 layers. However, TMDs in single, dual, or other substantially two-dimensional forms may be advantageous for use in electronic devices, thereby enabling the provision of thin-profile devices.
The thickness of the TMD layer can be roughly determined by using a high-resolution optical microscope (e.g., Nikon Eclipse LV100D) and further confirmed by Atomic Force Microscope (AFM).
In one embodiment, the alkali metal layer comprises cesium and/or rubidium.
In one embodiment, the alkali metal layer comprises a mixture of more than one alkali metal.
The alkali metal layer may comprise cesium and one or more elements selected from lithium, sodium, potassium, and rubidium.
The alkali metal layer may comprise rubidium and one or more elements selected from the group consisting of lithium, sodium, potassium, and cesium.
In one embodiment, the alkali metal layer has a thickness in the range of 0.2nm to 5 nm. In one embodiment, the thickness of the alkali metal may be in the range of 0.4nm to 2 nm. In one embodiment, the thickness of cesium and/or rubidium is in the range of 0.2nm to 5 nm. In one embodiment, the thickness of cesium and/or rubidium may be in the range of 0.4nm to 2 nm. Thicknesses within this range may impart favorable electrical properties to the surface modified portion 105 of the TMD. These properties will be discussed further below.
The thickness of the alkali metal layer can be determined by weight, for example using a quartz crystal microbalance.
X-ray photoelectron spectroscopy (XPS) can also be used to determine the thickness of alkali metals. One such scheme suitable for determining alkali metal thickness is given in the following references: seah, M.P., & Dench, W.A. (1979), Quantitative electron spectroscopy of surfaces A standard data base for electron atomic free hands in sources, 1(1), 2-11.
In one embodiment, the TMD may be selected from MoS2、WS2、MoSe2And WSe2、MoTe2Alkali metal doped MoTe2Alkali metal doped MoSe2Alkali metal doped MoS2Alkali metal doped WSe2And alkali metal-doped WS2。
In particular, TMD may be selected from WSe2And MoTe2. More particularly, TMD may be WSe2。
In one embodiment, the alkali metal may include cesium and/or rubidium, and the TMD may be selected from MoS2、WS2、MoSe2And WSe2、MoTe2Alkali metal doped MoTe2Alkali metal doped MoSe2Alkali metal doped MoS2Alkali metal doped WSe2And alkali metal-doped WS2. In particular, the alkali metal may comprise cesium and/or rubidium, and the TMD may be selected from WSe2And MoTe2. More particularly, the alkali metal may include cesium and/or rubidium, and the TMD may include tungsten diselenide (WSe)2)。
The material according to this embodiment, which is WSe modified with Cs, is shown in fig. 22Schematic representation of a surface. In the embodiment of FIG. 2, WSe2Arranged as a single layer. However, in other embodiments, WSe2May be provided as a bi-layer or multi-layer (e.g., 3-5 layers) material.
In one embodiment, the portion 107 of the TMD 101 that is not surface modified (if present) may have a 2H crystal structure. In one embodiment, surface modification of one or more portions 105 of the TMD 101 may result in those portions having a different phase than the portions 107 that are not surface modified. In one embodiment, one or more portions 105 may have a 1T or 1T 'crystal structure, particularly a 1T' crystal structure. FIGS. 3a and 3b are schematic views of a drawingShow WSe2The 2H and 1T' crystal structures of (1), wherein a tungsten atom is represented by 301 and a selenium atom is represented by 303.
An atomically clear interface between the 2H and 1T/1T' phases in the material according to embodiments may be directly observed using a High-resolution transmission electron microscope (HRTEM). Suitable protocols for this characterization are given, for example, in kappa, r., et al. nat. mater.13.12(2014): 1128.
The crystal structure of TMD in the surface-modified portion may depend on the thickness of the alkali metal layer 103 present on the surface. In an embodiment, the thickness of the alkali metal 103 may be selected such that the surface modified portion 105 of the TMD has a crystal structure of substantially 1T or 1T'. Generally, TMD will exhibit 1T or 1T' properties with greater thicknesses of alkali metals, as shown by the experimental results discussed below.
In one embodiment, the portion 107 of the TMD 101 that is not surface modified may be a semiconductor. In an embodiment, surface modification of one or more portions 105 may cause those portions to exhibit different electrical properties than the non-surface modified portions 107 of the TMD. In one embodiment, one or more portions 105 may exhibit metallic properties. In one embodiment, one or more portions 105 may exhibit n-type doping characteristics.
The electrical properties of the surface-modified and unmodified portions can be determined by examining the electrical transport properties of the material according to methods well known in the art.
In one embodiment, the electrical properties of the surface modified portions of the TMDs may depend on the thickness of the alkali metal layer 103 on their respective surfaces. In one embodiment, the thickness of the alkali metal layer may be selected such that the surface modified portion 105 of the TMD exhibits metallic or substantially metallic properties. Generally, the surface modified portion of TMD will exhibit metallic behavior with greater thicknesses of alkali metals.
In other embodiments, the thickness of the alkali metal can be selected to obtain other electrical properties, such as n-type doping properties, relative to TMD that is not surface modified.
In one embodiment, the alkali metal has a thickness in the range of 0.2nm to 5 nm. In one embodiment, the thickness of the alkali metal may be in the range of 0.4nm to 2 nm. In this embodiment, TMD may exhibit a metal characteristic and an ohmic contact characteristic.
In one embodiment, the thickness of the alkali metal layer may be less than 0.4 nm. In one embodiment, the alkali metal layer may have a thickness of 0.2nm to 0.4 nm. In this embodiment, the TMD may be represented as a surface modified portion 105 of the TMD having an n-type doping characteristic relative to an un-surface modified portion 107.
In one embodiment, the thickness of cesium and/or rubidium is in the range of 0.2nm to 5 nm. In one embodiment, the thickness of cesium and/or rubidium may be in the range of 0.4nm to 2 nm. In this embodiment, TMD may exhibit a metal characteristic and an ohmic contact characteristic.
In one embodiment, the thickness of cesium and/or rubidium may be less than 0.4 nm. In one embodiment, cesium and/or rubidium may be from 0.2nm to 0.4nm thick. In this embodiment, the TMD may be represented as a surface modified portion 105 of the TMD having an n-type doping characteristic relative to an un-surface modified portion 107.
According to the above embodiments, the material of fig. 1 may include a multiphase contact within the TMD layer at the interface 111 between the surface modified portion and the unmodified portion. In an embodiment, the multiphase contact is between the 2H phase in the non-surface modified portion and the 1T' phase in the surface modified portion.
Thus, the materials according to these embodiments described above may enable the utilization of the semiconducting and metallic properties of the two phases of TMD within the same material, i.e. the advantageous bipolar transmission properties of the 2H phase and the advantageous ohmic electrical contact through the surface doped metallic 1T' portion.
In particular, by employing TMD of 1T/1T 'phase of metal as a buffer contact layer, the material according to the above embodiment can be advantageously disposed in an electronic device such as a transistor, thereby realizing a 2H-1T/1T' multiphase transistor having low contact resistance and ohmic characteristics.
Compared to metal contacts in existing 2D TMD transistors, 2H-1T/1T' poly phase contacts in the material according to the above embodiments may: i) avoiding lattice mismatch between the metal electrode and the channel material, which significantly improves the carrier injection efficiency; ii) eliminating Fermi level pinning effects (Fermi level pinning effects) from surface states; iii) and the formation of atomically sharp interfaces to avoid the formation of chemical bonds at the metal/semiconductor interface (which can create large strains in the crystal lattice).
As shown in the examples below, surface modification with cesium and/or rubidium produces devices with very favorable electrical properties.
The use of alkali metals, in particular cesium and/or rubidium for surface modification to achieve heterogeneous contact in TMD as described above, provides a simple, non-destructive method to achieve ohmic contact of 2D materials while maintaining bipolar properties. In fact, alkali metal surface functionalization, particularly with cesium and/or rubidium, may be performed in situ, as will be discussed further below. The phase transition performed in this manner also enables a high degree of control over the TMD region undergoing the phase transition.
For conventional semiconductors, ion implantation and thermal diffusion have been widely used to precisely adjust different carrier concentrations therein. However, in 2D materials, these doping techniques may damage the crystal lattice or introduce a large number of defects in the material due to their thin nature at the atomic level, thereby compromising their intrinsic properties. In contrast, surface modification is particularly effective in 2-D materials due to its large surface-to-bulk ratio.
Device with a metal layer
In one embodiment, the material according to the above embodiments is used in an electronic device. In one embodiment, the material according to fig. 1 is used for a Field Effect Transistor (FET).
A schematic diagram of an n-type FET device according to this embodiment is shown in fig. 4.
In this embodiment, the transistor includes a single layer TMD 101 disposed on a substrate 401. In the embodiment of FIG. 4, the substrate is of SiO2A p-type silicon wafer of layers. Those skilled in the art will appreciate that an appliance may be employed depending on the embodimentOther suitable substrates having insulating properties.
Source and drain electrodes 403 are disposed on both ends of the TMD layer 101 on the substrate. The reasons for this arrangement will become apparent from the discussion below. In the embodiment of fig. 4, the electrode 403 includes palladium (Pd). However, those skilled in the art will appreciate that other suitable metallic materials may be employed depending on the implementation.
In this embodiment, a photoresist material layer 405 is provided on a portion of the surface of the TMD layer 101. In the embodiment of fig. 4, a photoresist such as PMMA is used because of its photoresist properties that are advantageously used in the manufacturing process (see below). In other embodiments, the top layer of 405 may be any insulating material capable of encapsulating the TMD layer 101 to avoid modification of one or more alkali metals (including Cs and/or Rb modification). In an embodiment, the photoresist or other insulating layer 405 may be partially or completely omitted.
In one embodiment, the ends 105 of the TMD layer adjacent to the source and drain electrodes 403 are not covered by the dielectric 405, i.e. they are exposed.
In one embodiment, a back gate electrode (not shown) is disposed on the silicon substrate.
The alkali metal layer 103 exists on a part of the surfaces of both ends of the TMD layer 101 not covered with the photoresist 405. Thus, the TMD layer 101 is surface modified at each end 105 but not modified in the middle. In one embodiment, the alkali metal layer comprises cesium and/or rubidium.
In one embodiment, the TMD may be selected from MoS2、WS2、MoSe2And WSe2、MoTe2Alkali metal doped MoTe2Alkali metal doped MoSe2Alkali metal doped MoS2Alkali metal doped WSe2And alkali metal-doped WS2。
In particular, TMD may be selected from WSe2And MoTe2. More particularly, TMD may be WSe2。
In one embodiment, each portion of the TMD layer on which the alkali metal is present has a width in a range of 0.2 μm to 5 μm. In one embodiment, they have a width in the range of 0.2 μm to 0.3 μm.
As described above, beyond a certain alkali metal thickness, the TMD layer may be metallic at each end 105, but in the region 107 underlying the photoresist 405, towards the middle of the layer 107, it behaves as a semiconductor. In the embodiment of fig. 4, TMD is used as an n-type unipolar semiconductor. In one embodiment, the TMD has a 1T phase or a 1T' phase at each end 105 adjacent to the source and drain electrodes 403 and a 2H phase in a portion 107 not surface-modified with an alkali metal under the gate electrode. Thus, TMD includes poly-phase contacts 111 and device 4 is thus a poly-phase transistor.
In one embodiment, the alkali metal has a thickness in the range of 0.2nm to 5 nm. In one embodiment, the thickness of the alkali metal is in the range of 0.4nm to 2nm, as this ensures good ohmic contact between the source and drain electrodes and the TMD, as shown in the examples discussed below. In one embodiment, the thickness of the alkali metal is about 1.0 nm.
In one embodiment, the alkali metal comprises cesium and/or rubidium, and the thickness of cesium and/or rubidium is in the range of 0.2nm to 5 nm. In one embodiment, the thickness of cesium and/or rubidium is in the range of 0.4nm to 2 nm. In one embodiment, the thickness of cesium and/or rubidium is about 1.0 nm.
In one embodiment, the thickness of the alkali metal is selected according to the desired device properties.
In one embodiment, the thickness of the alkali metal is selected such that there is a substantially ohmic contact between the electrode and the TMD layer, i.e. the current between the source and drain electrodes 403 has a substantially linear voltage dependence.
In one embodiment, the alkali metal comprises cesium and/or rubidium, and the thickness of the alkali metal is such that the device 4 has a current on/off ratio of at least 10 at room temperature (298K)6。
The current on/off ratio of a device is defined as the ratio of the on-state current to the off-state current, i.e., the ratio of the maximum current to the minimum current in the transfer characteristic curve.
In one embodiment, the alkali metal comprises cesium and/or rubidium, and the thickness of the alkali metal is such that the field effect electron mobility in the device at room temperature (298K) is at least 30cm2V-1s-1。
The field effect electron mobility, μ, of the device is the current (I) from the source to the drain using the following equationsd) And the potential difference (V) between the source and drainsd) The linear relationship of (a) yields:
where L and W denote the length and width, respectively, of the conduction channel between the source and drain electrodes 403, CiRepresents a dielectric substance (i.e. SiO)2In the present embodiment), and dIsd/dVsdRepresenting the slope of the linear region in the transmission curve.
In the arrangement of fig. 4, the electrodes 403 interface with the surface modified portions 105 of the TMD 101, i.e. they are in direct electrical contact with these portions. However, a large portion of the channels remain unmodified.
This arrangement thus provides a field effect transistor based on the TMD semiconductor properties while ensuring that the source and drain electrodes are in direct electrical contact with the metallic parts of the TMD, thereby ensuring an ohmic contact between them with a low contact resistance, avoiding the occurrence of a schottky barrier at the contact between the electrodes and the semiconductor material.
Thus, the above-described alkali metal functionalization, particularly functionalization with cesium and/or rubidium according to embodiments, provides a simple method to achieve high performance transistors with high mobility, high current on/off ratio, low sub-threshold swing. Thus, the device of fig. 4 is a high quality device with fast on/off speed and cost-effective.
Fig. 5 shows a sandwich FET according to an embodiment of the invention.
As in the embodiment of fig. 4, the transistor 5 includes a single layer TMD 101, source and drain electrodes 403 are provided at both ends of the TMD layer 101 on a substrate 401, and a photoresist material layer 405 is disposed on a portion of a surface of the TMD layer 101. In the embodiment of fig. 5, the photoresist 405 is PMMA, however, one skilled in the art will appreciate that other materials may be employed depending on the embodiment. In an embodiment, the photoresist or other insulating layer 405 may be partially or completely omitted.
TMD and source and drain electrodes are disposed on the dielectric layer 501. In the embodiment of fig. 5, the dielectric layer comprises a hexagonal boron nitride (h-BN) sheet. However, one skilled in the art will appreciate that other dielectric layers may be employed depending on the implementation.
In one embodiment, the thickness of the dielectric layer 501 (in this embodiment, h-BN) may be particularly in the range of 10nm to 20 nm. A thinner dielectric layer may result in undesirable quantum tunneling into the device.
A dielectric layer is disposed on the bottom gate electrode layer 503. In the embodiment of fig. 5, the bottom gate electrode comprises a layer of graphene. Those skilled in the art will appreciate that other suitable materials may be used depending on the implementation. In one embodiment, the thickness of the bottom gate electrode layer may in particular be less than 10 nm.
As described above with respect to the embodiment of fig. 4, the above-described sandwich arrangement is arranged on a silicon-based substrate 401.
As in the embodiment of fig. 4, an alkali metal layer is present on the portion 105 of the surface of the TMD at both ends of the TMD layer 101 not covered by the photoresist 405. Thus, the TMD layer 101 is surface modified at each end portion 105, but is not modified at its middle portion 107.
In one embodiment, the width of each portion 105 of the TMD layer on which the alkali metal is present (i.e., the distance that these portions extend from the electrode 403) is in the range of 0.2 μm to 5 μm. In one embodiment, they have a width in the range of 0.2 μm to 0.3 μm.
In one embodiment, the alkali metal layer used in the embodiment of fig. 5 comprises cesium and/or rubidium.
In the embodiment of FIG. 5, TMD may be selected from MoS2、WS2、MoSe2And WSe2、MoTe2Alkali metal doped MoTe2Alkali metal doped MoSe2Alkali metal doped MoS2Alkali metal doped WSe2And alkali metal-doped WS2。
In particular, TMD may be selected from WSe2And MoTe2. More particularly, TMD may be WSe2。
As described above, beyond a certain alkali metal thickness, the TMD layer may be metallic at each end 105, but in the region 107 underlying the photoresist 405, towards the middle of the layer 107, it behaves as a semiconductor. In the embodiment of fig. 5, TMD is used as an n-type unipolar semiconductor. In one embodiment, the TMD has a 1T phase or a 1T' phase at each end 105 adjacent to the source and drain electrodes 403 and a 2H phase in a portion 107 not surface-modified with an alkali metal under the photoresist 405. Thus, TMD includes poly-phase contacts 111 and device 5 is thus a poly-phase transistor.
In one embodiment, the alkali metal has a thickness in the range of 0.2nm to 5 nm. In one embodiment, the alkali metal has a thickness in the range of 0.4nm to 2 nm. In one embodiment, the thickness of the alkali metal is about 1.0 nm.
In one embodiment, the thickness of the alkali metal is selected according to the desired device properties.
In one embodiment, the alkali metal comprises cesium and/or rubidium, and the thickness of the alkali metal is such that there is ohmic contact between the electrode and the TMD layer.
In one embodiment, the alkali metal comprises cesium and/or rubidium, and the thickness of the alkali metal is such that the device 5 has a current on/off ratio of at least 10 at room temperature (298K)7In particular at 107To 109Within the range of (1).
The current on/off ratio of a device is defined as the ratio of the on-state current to the off-state current, i.e., the ratio of the maximum current to the minimum current in the transfer characteristic curve.
In one embodiment, the alkali metal comprises cesium and +Or rubidium, and the alkali metal has a thickness such that the field effect electron mobility of the surface modified portion of TMD is at least 70cm2V-1s-1。
The field effect electron mobility, μ, of the device is from the current between the source and drain using the following equation (I)sd) The potential difference (V) between the transfer curve and the source and drainsd) The linear relationship of (a) yields:
where L and W represent the length and width, respectively, of the conduction channel between the source and drain 403 electrodes, CiRepresents the capacitance per unit area of the dielectric 501 (i.e., BN in the embodiment of fig. 5), and dIsd/dVsdRepresenting the slope of the linear region in the transmission curve.
In one embodiment, the alkali metal comprises cesium and/or rubidium, and the thickness of the alkali metal is selected such that the subthreshold swing is less than 85mV dec-1In particular at 60mV dec-1To 85mV dec-1Within the range of (1).
Sub-threshold swing of device from dVg/d(logIsd) Is determined in which VgIs the gate voltage, IsdIs the current between the source and drain electrodes.
FIG. 6 illustrates a transistor-based logic inverter, according to one embodiment. The device comprises a supply of an input signal (V)IN) And a dielectric layer 501 disposed on the substrate 401, as described in connection with the device of fig. 4.
The device further comprises three parallel electrodes 605, 607, 609 arranged on the dielectric layer 501, which serve as power supply (VDD; 605), output signal (VOUT; 607) and ground (GND; 609), respectively, with the TMD layer 101 between them forming two channels 601 and 603 in series.
The photoresist 405 is arranged to completely cover the TMD of one channel 601 such that there is no surface modification of the TMD in that channel, thus enabling that channel to maintain the p-type dominated dipole properties of the TMD.
In contrast, the other channel 603 is only partially covered by the PMMA photoresist 405 with an alkali metal surface modification at each end adjacent to the respective electrode 605. Thus, the channel behaves as an n-type transistor as described above with respect to fig. 4 and 5.
In an embodiment, the photoresist layer 405 may be omitted, either completely or partially, from one or both channels.
Thus, the embodiment of FIG. 6 corresponds to a TMD inverter with two series channels. By spatially controlling the exposed area near the metal electrode of one TMD channel, a unipolar multiphase n-type transistor can be obtained. In contrast, the other channel is completely covered by the PMMA photoresist, wherein the p-type dominant bipolar transport properties are retained. In the embodiment of fig. 6, multiple layers of h-BN and graphene are used as the dielectric layer and bottom gate electrode, respectively, however the skilled person will appreciate that other suitable materials may be employed depending on the embodiment. Graphene provides an input signal (V)IN) Three parallel electrodes on a TMD foil are used as power supplies (V)DD) And an output signal (V)OUT) And Ground (GND).
In one embodiment, the thickness of the alkali metal layer is selected according to the desired properties of the n-type channel.
In one embodiment, the thickness of the alkali metal is in the range of 0.2nm to 5nm, in particular 0.4nm to 2 nm. In one embodiment, the thickness of the alkali metal is about 1.0 nm.
In one embodiment, the alkali metal comprises cesium and/or rubidium, and the thickness of the alkali metal may be such that when V is greater than VDDThe gain (-dV) achievable by inverter 6 at 2.5VOUT/dVIN) Greater than 100.
In one embodiment, the alkali metal comprises cesium and/or rubidium, and the thickness of the alkali metal may be such that when V is greater than VDDFor static power consumption less than 10pW (defined as P ═ V) at 0.5VDD×IDD) The inverter can obtain a gain greater than 5.
As shown below, experimental results show that the inverter according to the present embodiment has a high voltage gain, thereby enabling rapid logic state inversion, high accuracy, and low power consumption.
Although the integration of the material according to the embodiment of fig. 1 has been described with respect to three devices 4, 5 and 6 according to the embodiment, the skilled person will understand that these devices are only intended to represent potential applications of the material according to the embodiment. In fact, the materials according to the above embodiments are very flexible and compatible with various device structures. They are applicable to almost all electronic and optoelectronic devices to improve charge injection/collection efficiency. The thickness of the alkali metal layer may be varied to fine tune the electrical properties of the material according to its intended implementation.
Fig. 7 illustrates a method of producing the material of fig. 1, according to one embodiment. It is also applicable to the generation of the relevant layers in the devices in fig. 4, 5 and 6.
In step S701, the TMD 101 is provided. The layer may be a single layer, a double layer or comprise three or more layers, depending on the requirements of the final material. Bulk TMD crystals are commercially available, for example, from HQ-Graphene. Single and dual layer TMDs can be generated from a bulk TMD by mechanical peeling, for example, using transparent adhesive tape.
In one embodiment, the TMD may be transferred to a suitable substrate, such as silicon dioxide, before performing step S703. In one embodiment, the electrode may be patterned onto the TMD using e-beam lithography before performing step S703. Thus, steps S703 to S707 may be performed in situ in an electronic device, such as those described above with respect to fig. 4, 5, and 6.
If electrode patterning is performed, the electrodes can be thermally evaporated onto the substrate, for example by thermally evaporating Pd and/or Au, after patterning the source and drain electrodes on TMD. Excess metal may then be removed from the sample according to procedures well known in the art, for example by soaking in acetone. The method then proceeds to step S703.
In step S703, the surface 109 of the TMD layer is coated with a barrier layer 405 of photoresist such as PMMA. In one embodiment, the barrier layer is applied to the TMD layer using spin coating.
In step S705, the photoresist on the portion 105 of the TMD layer to be surface-modified is removed using Electron Beam Lithography (EBL). In the embodiment of fig. S705, these are portions at the edges of the layers.
In step S707, a layer 103 of one or more alkali metals is evaporated directly onto the TMD layer. In one embodiment, this is accomplished under vacuum by one or more alkali metal getters. Suitable getters are commercially available, for example from SAES. In one embodiment, the one or more alkali metals comprise cesium and/or rubidium, and the layer of cesium and/or rubidium is evaporated onto the TMD layer by, for example, a cesium and/or rubidium getter.
In one embodiment, an alkali metal getter is heated in a high vacuum chamber with a TMD to effect evaporation of the alkali metal onto exposed surfaces of the TMD. The evaporation of the alkali metal from the getter can be achieved, for example, by supplying a DC current to the feed-throughs in the vacuum chamber.
In one embodiment, the vacuum chamber should be at less than 10 deg.f-7Under high vacuum conditions of mbar. Such pressure can be achieved by pumping a suitable chamber with a turbo pump. Turbo pumps suitable for achieving high Vacuum are commercially available, for example from Pfeiffer Vacuum GmbH. Chamber components suitable for supporting such a vacuum are also commercially available, for example, from UHV Design.
Due to the presence of the photoresist 405 as a barrier layer, the film growth of the alkali metal is limited to the exposed portions 105 and 105 of the TMD layer.
The thickness of the alkali metal can be monitored by monitoring the weight of the material during evaporation, for example using a Quartz Crystal Microbalance (QCM), so that it can be controlled as appropriate according to the desired material or device properties.
Quartz crystal microbalances (and corresponding feed-throughs) suitable for use according to embodiments are commercially available, for example from Testbourne Ltd.
In one embodiment, the vacuum chamber is configured such that the QCM is positioned to protect the sample from alkali metal deposition while allowing the evaporation rate from the alkali metal getter to reach a desired level. Once the desired ratio is reached, the QCM is removed to enable deposition of the alkali metal. Once the desired evaporation on the sample is complete, the QCM is moved back into place to prevent further deposition of the sample.
A suitable in situ vacuum characterization system for use according to embodiments is given in Lei, b., et al (2017). Nano Research,10(4), 1282-.
Depending on the desired use, the photoresist layer may or may not be removed after application.
Thus, the method of fig. 7 provides a method of producing materials and devices according to embodiments that can be performed in situ and easily integrated with conventional CMOS processes, thereby making direct integration into the fabrication process possible. The method provides an efficient, non-invasive and non-volatile process for implementing, for example, WSe2Phase transition of TMD of (1).
Examples
Selected advantageous physical properties of the above-described embodiments will now be described in accordance with the following non-limiting examples.
Raw 2D WSe2Fabrication of transistors
Bulk WSe Using Scotch tape2Mechanical exfoliation of crystals (commercially available from HQ-graphene) WSe2Flakes, then rapidly transferred to a substrate having 300nm SiO2On a degenerate p-type doped silicon substrate. Single and double layer WSes were discovered by using high resolution optical microscopy (Nikon Eclipse LV100D)2And further verified by AFM and raman measurements. A Polymethylmethacrylate (PMMA) photoresist (commercially available from MicroChem) was then spin coated on the silicon substrate to perform a conventional Electron Beam Lithography (EBL) process. In patterning the source and drain electrodes to WSe2After this, 5nm Pd and 60nm Au were thermally evaporated onto the substrate. The sample was then soaked in acetone for about 1 hour to remove excess metal.
FIGS. 8 a-8 c illustrate a dual layer WSe2Results of devices in which WSe2The flakes were mechanically exfoliated to have a SiO of 300nm2A degenerate p-type doped silicon wafer of layers. Standard photolithography is then performed to define the WSe2Channel, then metal deposition of Pd/Au. Fig. 8a shows a line profile derived from an Atomic Force Microscope (AFM) image of a device. It discloses WSe2The thickness of the flake was about 1.7nm, indicating its bilayer nature. Further validation was performed using raman and Photoluminescence (PL) measurements (fig. 8b and 8c, respectively). Three Raman characteristic peaks are positioned at 250cm-1(E1 2g)、257.5cm-1(A1g) And 309cm-1(B1 2g) PL Spectrum 801 shows a direct band gap emission peak 803 at 1.64eV and an indirect band gap emission peak 805 at 1.57eV, further confirming WSe2The two-layer nature of the sheet.
Surface modification with Cs
To study bilayer WSe by in situ electrical measurements2Phase change caused by modification of middle Cs, and original WSe2The device was wire bonded to a wire chip carrier and loaded into a self-made high vacuum system (-10) with in-situ film growth and low temperature electrical measurement capability-7mbar). The vacuum system was manufactured according to the design given by Lei, b., et al. (2017), Nano Research,10(4), 1282-.
Agilent 2912A precision Source/measurement unit (SMU) was used to perform the relevant electrical measurements. Cesium was evaporated in situ to the device directly from SAES getter and the nominal thickness was calibrated using a Quartz Crystal Microbalance (QCM) (commercially available from testbore Ltd). The temperature-related experiments described below were performed on a cryobench, with liquid nitrogen used for sample cooling.
The samples were loaded onto the sample stage through a flexible quick access door. After several hours of pumping, the sample was pulled back to a specific location for in situ deposition where a thermal diffusion cell was equipped to evaporate the dopant. A Quartz Crystal Microbalance (QCM) was placed in front of the sample stage to accurately monitor the deposition rate. Once Cs evaporation rate was confirmed, the QCM was moved upward to allow Cs to deposit onto the sample. After evaporation, the QCM is moved down to block Cs. Cs was evaporated with a DC current (3.8A) supplied through the feedthrough.
FIG. 9a showsDouble-layer WSe in FET structure 2923 device in which Pd/Au (5nm/60nm) is used as the metal contact 921, and 300nm SiO2The layer serves as a dielectric.
FIGS. 9b and 9c show the original dual layer WSe2FET in high vacuum condition (10)-7Transmission characteristic at mbar) (I)sd-Vg). The results clearly reveal hole dominated bipolar transport characteristics with a fixed bias (V)sd1V) from-80V to 50V.
FIG. 9d shows WSe after in situ deposition of Cs on the device as described above2The transfer characteristics of the FET evolve with the Cs thickness. Thicknesses shown are 0nm (901), 0.01nm (903), 0.07nm (905), 0.19nm (907), 0.4nm (909), and 1.0nm (911). Two distinct phases can be observed, including: i) a significant n-type doping stage with strongly enhanced on-current in the electron transport mechanism at low Cs doping levels (Cs nominal thickness < 0.2 nm); ii) WSe when the Cs nominal thickness is above 0.4nm2The device exhibits a transfer characteristic that is nearly independent of the gate, which indicates a semiconductor to metal phase transition.
Fig. 9e shows the conductivity (G) versus Cs thickness at Vg ═ 0V. Conductivity at Vg of 0V (G ═ I)sd/Vsd) The improvement is remarkably improved by nearly 7 orders of magnitude from 2.1 multiplied by 10-111.1X 10 modified by S to 1.0nm Cs-4S。
FIG. 9f shows the pristine (915) and 1.0nm (913) Cs modified WSe2FET different gate voltages V from 0V to 50VgLower output curve (I)sd/Vsd). E.g. WSe before and after 1.0nm Cs modification2The output curve of the device shows the original WSe2The device exhibited schottky contact characteristics, while ohmic contact characteristics were determined after 1.0nm Cs modification. I issdThe large enhancements reveal a reduction in contact resistance and channel resistance resulting from the semiconductor to metal phase transition.
Dual layer WSe2The semiconductor to metal phase change in the device is further characterized by temperature dependent transport measurements. Temperature-related experiments were performed on a cryobench using liquid nitrogen for sample cooling, and the results were shownShown in FIGS. 9g and 9h, the dual layer WSe with original (917) and Cs modified (919)2The conductivity evolution of the device varies with temperature with a gate voltage Vg of-80V (fig. 9g) and 50V (fig. 9 h).
As can be seen from FIGS. 9g and 9h, the double layer WSe of the semiconductor phase and the metal phase2The device shows an opposite trend of evolution with temperature change. For the original semiconductor WSe2The device, conductivity, gradually increases with increasing temperature, which results from a significant enhancement of thermally activated carriers. In contrast, Cs modified metallic WSe at 1.0nm2In devices, increasing temperature leads to a decrease in conductivity. High temperatures enhance metallic WSe2Resulting in a decrease in conductivity.
FIG. 9i shows the dual layer WSe after 1.0nm Cs functionalization at different Vg from-80V to 50V2The conductivity of the device evolves with respect to temperature. At all gate voltages, the conductivity gradually decreased with increasing temperature, clearly revealing the Cs-modified WSe2The metallic nature of the flakes and further confirms the semiconductor to metal phase transition caused by the Cs surface functionalization.
To understand the Cs modified WSe2The semiconductor to metal phase transition mechanism of (1) further adopts an in-situ XPS/UPS experiment. In an ultrahigh vacuum chamber (base pressure-10)-10Bulk WSe for Cs surface modification in mbar)2In situ UPS and XPS measurements were performed (obtained from HQ-graphene). He I (21.2eV) was used as excitation source and a sample bias voltage of 5V was applied for UPS characterization. Al K α (148.7eV) was used as an excitation source for XPS measurements. Nominal thickness of the in-situ deposited Cs layer was determined by monitoring WSe2The decay of the core energy level peak is estimated and further calibrated by the QCM. The results are shown in FIG. 10, where FIG. 10(a) shows the evolution of the UPS spectra in the low kinetic energy region and FIG. 10(b) shows the evolution with WSe2XPS core power spectrum of W4 f with Cs thickness variation; FIG. 10(c) shows the following WSe2XPS core energy spectrum of Se 3d with varying Cs thickness, and fig. 10(d) shows UPS valence band spectrum around the fermi level region. In all figures, the original WSe 21001 for 0.01 nm Cs 1003 and 10 for 0.10 nm Cs 1005, 1007 for 0.20nm Cs, 1009 for 0.40nm Cs and 1011 for 1.00nm Cs. Here, the
Represents work function, and Δ E represents energy difference.
Original WSe2Measured at about 4.02eV, and dropped sharply to about 2.2eV after 1.0nm Cs modification. Reduction of WF means Cs/WSe2From Cs to WSe at the interface2Due to the ultra-low WF of Cs (about 2.14 eV).
Fig. 10(b) and 10(c) show the evolution of the binding energy of the W4 f and Se 3d core levels as a function of the Cs thickness, respectively. Cs vs. WSe as the deposition thickness of Cs increases to 0.2nm2Electron doping effects of (2) make WSe2The fermi level of (a) is shifted towards its conduction band, so the binding energy of W4 f and Se 3d increases slightly by 0.1eV and 0.15eV, respectively. Interestingly, as the Cs thickness increased from 0.2nm to 1.0nm, the W4 f and Se 3d core levels shifted to lower binding energies by about 0.3eV and about 0.35eV, respectively. This is consistent with previous reports on K functionalization, so electron doping induces a bilayer WSe2Phase transition of the mesosemiconductor to the metal (2H to 1T'). Further Cs deposition leads to metallic WSe2Negative charges accumulate on the surface, and thus the core energy level peak moves toward lower binding energies.
The valence band spectrum shown in FIG. 10(d) can further verify heavily doped WSe2Metallization of (2). At low surface modification levels (Cs thickness < 0.4nm), band-down bending of the valence band is observed due to electron doping. When the Cs thickness is greater than 0.4nm, a spike appears near the fermi level, clearly showing a metalloid character, which further confirms the semiconductor to metal phase transition.
FIG. 11a shows a bilayer WSe before (1103) and after (1101) modification with 0.1nm Cs2Photoluminescence (PL) spectrum of the flakes. FIG. 11b shows pristine, 0.1nm and 1.0nm Cs modified WSe2The raman spectrum of (a). In WSe2In the three polymorphs of (a), 1T and 1T' are both metallic. Previous reports indicate that the 1T phase of group VI TMD is unstable and spontaneously converts with energy relaxationIs 1T' phase. Thus, without wishing to be bound by theory, it is proposed that WSe is Cs doped2The metal phase of (1T'). In situ Raman and PL Generation to reveal Cs modified WSe211a and 11b show the double layer WSe before and after Cs deposition, respectively2In situ PL spectra and raman spectra. Bilayer WSe after 0.1nm Cs deposition2The PL peak of (a) is immediately quenched due to significant charge transfer. Original dual-layer WSe2Three characteristic peaks are shown in the Raman spectrum and are respectively positioned at 250cm-1(E1 2g)、257.5cm-1(A1g) And 309cm-1(B1 2g). The intensity of these peaks was greatly reduced after 0.1nm Cs coverage. Further increasing the Cs thickness to 1.0nm results in a bilayer WSe2Phase transition from the semiconductor 2H phase to the 1T' metal phase. B is1 2gThe peak disappeared completely, and 5 new peaks appeared in the low wavenumber region at about 93cm-1、114cm-1、227cm-1、242cm-1And 260cm-1Left and right. These new peaks correspond to WSe in the 1T' phase2Characteristic peak of (2). Thus, without wishing to be bound by theory, the Cs-modified WSe observed here2The phase transition of (2H) to (1T') can be classified.
Multi-phase device fabrication
For multiphase device fabrication according to the embodiment of FIG. 4, the original WSe is first fabricated according to the method described above2A device. To achieve a partially surface modified device, the PMMA photoresist is spun again and a second EBL process is performed to expose the desired area around the contact after the excess metal is stripped. The device was then loaded into a vacuum system as previously described for cesium evaporation for electrical characterization.
Fig. 12a shows the evolution of the transmission characteristics as a function of the Cs thickness, 0nm (1301), 0.05nm (1303), 0.20nm (1305), 0.50nm (1307) and 1.00nm (1309). As previously described, WSe2The sheet is n-type doped at low Cs deposition levels. Further increasing the Cs thickness to a high level causes a phase change in the exposed region, resulting in a 1T' contact. The saturation current with the 1T' contact is about 2 orders of magnitude higher than the original device with the Pd contact, resulting in a giantLarge gate modulation effect and about 107High current on/off ratio.
Field effect electron mobility is also from 0.6cm2V-1s-1Remarkably improved to 37.7cm2V-1s-1As shown in fig. 12b, this figure shows the evolution of electron mobility with Cs thickness. This indicates that devices with 1T' contacts have superior transmission performance.
Fig. 12c and 12d show the output curves of the device before (fig. 12d) and after (fig. 12c) 1.0nm Cs functionalization at gate voltages 0V (1311), 20V (1313), 40V (1315) and 50V (1317). The original transistor exhibited a sharp schottky contact characteristic, whereas the ideal ohmic contact was observed after Cs functionalization, as reflected by the symmetrical and linear nature of the output curve.
Thus, in situ Cs surface modification has been demonstrated as a 2H WSe2An efficient method for inducing semiconductor-to-metal phase transformation, which is to realize high-performance 2H-1T' multiphase WSe by spatially controlling the phase transformation region2Transistors provide opportunities.
The following gate voltage V of the multiphase transistor was further investigatedgThe result of the changed schottky barrier height is shown in fig. 13 a. According to fig. 13a, SB in a multiphase transistor is determined to be as low as about 9.4meV for electron transport. This negligible SB can significantly enhance the injection of electrons into the semiconductor, resulting in a true ohmic contact characteristic at high electrostatic doping.
To further quantify the ideal n-type multiphase WSe2Contact quality of transistor, width-normalized contact resistance (R) extracted by Transfer Length Method (TLM)c). A series of WSes with different channel lengths2The (5-layer) transistor was used for the measurement. To ensure accuracy, it is assumed that the channel segments covered by the metal contacts have no effect on the overall channel length. In addition, since one of the Schottky contacts easily becomes forward biased when a high bias voltage is applied, a very small bias (about 10mV) is used to avoid underestimating Rc. FIG. 13b shows a view at VgWidth varying with channel length at 5VNormalized total resistance (R)tot)。RtotIs a linear fit, where the y-intercept yields the total contact resistance (2R)c) The slope represents the sheet resistance (R) of the channelsh). At VgA low contact resistance of about 4.3k Ω μm is obtained at 5V, which can be attributed to the combined effect of reduced SB height and narrowed SB width.
To fabricate a sandwich structure device according to the embodiment of fig. 5, a few layers of Graphene (commercially available from HQ-Graphene) were first peeled off at SiO by scotch tape2On a/Si substrate. Then, hexagonal boron nitride (n-BN) (commercially available from ACS Material, LLC) 15nm thick was then followed by WSe2(commercially available from HQ-graphene) was peeled off on a viscoelastic stamp using Polydimethylsiloxane (PDMS) (commercially available from Merck Group) and transferred to the desired graphene sheet. The above procedure was used to obtain a contact exposure channel to achieve a 2H-1T' multiphase FET. The device was then loaded into a high vacuum chamber for further measurements.
Fig. 14a shows the device transfer characteristics evolution as a function of Cs thickness. Results for Cs thicknesses of 0.0nm (1401), 0.01nm (1403), 0.08nm (1405), 0.20nm (1407), and 1.00nm (1409) are shown.
Low levels of Cs deposition will occur in the uncoated WSe2Causing an electron doping effect. Further increasing the Cs thickness resulted in an uncovered WSe2Thereby achieving 2H-1T' contact. Notably, the 2H-1T' multiphase device has an on-current about 3 orders of magnitude higher than the original device with Pd contacts, resulting in an ultra-high current on/off ratio of about 108. Further, defined as dVg/d(logIsd) Is optimized to 75mV dec-1Approximately 60mV dec-1The theoretical limit of (c). The field effect mobility can be extracted from the linear region of the transfer curve by using the following equation:
wherein L and W denote the length and width of the conduction channel, respectively, CiRepresenting the dielectricCapacitance per unit area of mass, and dIsd/dVsdIndicating the slope of the linear region in the transmission plot.
Fig. 14b shows the corresponding electron mobility versus Cs thickness. Electron mobility from 1.33cm2V-1s-1Remarkably improved by about 50 times to 70cm2V-1s-1。
Fig. 14c and 14d show the output curves of the device before (fig. 14c) and after (fig. 14d) 1.0nm Cs contact doping at different gate voltages 0V (1415), 1V (1417), 2V (1419), 3V (1421), 4V (1423) and 5V (1425). Original WSe even at high electrostatic doping levels (Vg-5V)2The output curve of the device is also non-linear, illustrating the well-defined schottky contact characteristics. After 1.0nm Cs modification, the current is greatly improved by more than 2 orders of magnitude under each grid voltage. Furthermore, the output curve is almost linear, especially at low VsdIn this state, almost ideal ohmic contact is shown.
The second sandwich structured device according to the embodiment of fig. 5 is manufactured according to the same procedure as described above. Fig. 14e shows the evolution of the transfer characteristic of the second device as a function of the Cs thickness. Shows 0.0nm (i.e. the original WSe)2(ii) a 1413) And a thickness of 1.00nm (1411) Cs.
The current on/off ratio of Cs doped devices was found to be even higher, about 109. Furthermore, the defined sub-threshold swing (SS) was measured as 61mV dec-1。
The device according to the embodiment of fig. 6 was fabricated as described above with respect to the FET sandwich device, but modified to obtain a contact exposed channel and a full PMMA covered channel. The devices were loaded into a high vacuum chamber for further measurements as before.
FIG. 15a shows the transfer characteristics of N-FET 1501 and P-FET 1503, indicating that a WSe can be spatially controlled2The unipolar multiphase n-type transistor is obtained by an exposed area near the metal electrode of the channel, while the p-type dominated bipolar transmission characteristic remains in the other channel completely covered by the PMMA photoresist.
FIG. 15b shows the position at VDDWhen 1V (1505), 2V (1507) and 2.5V (1509) are followed by VINVarying in-phase WSe2The output characteristics of the inverter. By sweeping the input voltage from-1V to 2V, the inverter goes through a "high state" (high V) in sequenceOUT) "high slope" (V)OUTSharp drop) and "low" (low V)OUT). One key parameter in evaluating inverter performance is the voltage gain defined by the slope of the output characteristic (gain-dV)OUT/dVIN). This is further illustrated in FIG. 16(a), which shows the position at VDD0.5V (1601), 1.0V (1603), 1.5V (1605), 2.0V (1607), and 2.5V (1609) with VINA varying output characteristic.
FIG. 15c shows the position of the three different VDD(reference numerals are as above) is followed by VINVarying extraction gain. Small V at 1VDDThe gain is about 13. By mixing VDDIncreasing to 2V and 2.5V, the gains can reach 49 and 106 respectively. Notably, these gains are the highest of all 2D material based in-phase inverters. Without wishing to be bound by theory, we propose that such high gains are primarily due to Cs-modified WSe2Low SS (about 75mV dec) of transistor-1) And ultra high current on/off ratio (about 10)8) This ensures that the inverter switches rapidly between "high" and "low".
FIG. 15d shows V vs. from 0.5V to 2.5VDDThe evolution of the power consumption of the devices. At VDDAt 2.5V, the power is about 280nW, at VDDGradually decreases to an ultra-low value of about 5pW at 0.5V. Notably, VDDThe gain at 0.5V can be kept at a suitable level around 8, which is very competitive in all 2D material based logic inverters due to such ultra-low power consumption. This is shown in FIG. 16(b), where V is shownDDWhen it is 0.5V, it follows VINA varying output curve (1611) and a corresponding voltage gain (1613).
The above results indicate that in situ Cs surface functionalization is used in WSe2The semiconductor to metal (2H to 1T') phase transition is achieved. WSe2In-situ electrical characterization of the FET first revealed a phase change. Cs functionalizationWSe (wireless sensor network)2The transistor exhibits gate independent transfer characteristics with conductivity improvements of approximately 7 orders of magnitude. As revealed by in situ UPS/XPS and Raman measurements, the 2H to 1T' phase transition results from Cs to WSe2Giant electron doping. By carrying out the 1T' phase WSe thus formed2As a contact electrode, a significantly enhanced field effect electron mobility (nearly 50-fold increase, up to about 70 cm) was obtained2V-1s-1) 2H-1T' multiphase WSe2A transistor. In addition, the device also exhibits about 108And an ultra-high current on/off ratio of about 75mV dec-1Thereby enabling ultra-low power consumption of about 5pW and about 106High voltage gain high performance WSe2Logic inverters, which are higher than all 2D material based in-phase inverters.
Although the above results are obtained under vacuum, the skilled person will appreciate that any environment excluding oxygen and water may be equivalently used, e.g. substantially 100% N2Or other inert environment under normal atmospheric conditions.
Thus, the alkali metal functionalization induced phase transition in TMD, and in particular Cs metal functionalization induced phase transition, provides a simple way to implement high performance TMD multiphase transistors and logic inverters.
In particular, in situ alkali metal surface modification, in particular in situ Cs surface modification, has proven to be an efficient method of inducing semiconductor to metal phase transitions in 2H TMD, which provides an opportunity to achieve high performance 2H-1T' multiphase TMD transistors by spatially controlling the phase transition region.
In the foregoing detailed description, embodiments of the present disclosure related to transition metal dichalcogenides and devices thereof are described with reference to the provided figures. The description of the various embodiments herein is not intended to be exhaustive or limited to the precise or specific representation of the disclosure, but is merely illustrative of a non-limiting example of the disclosure. The present disclosure is directed to addressing at least one of the problems and issues associated with the prior art. Although only a few embodiments of the present disclosure have been disclosed herein, it will be apparent to those of ordinary skill in the art in view of this disclosure that various changes and/or modifications can be made to the disclosed embodiments without departing from the scope of the present disclosure. Accordingly, the scope of the present disclosure and the scope of the appended claims are not limited to the embodiments described herein.
Further embodiments are given in the following description:
1. a Transition Metal Dichalcogenide (TMD) comprising a first moiety, wherein the first moiety is surface modified with a group 1 alkali metal.
2. The TMD of 1, wherein the group 1 alkali metal forms a layer on one side of the first portion.
3. The TMD according to 1 or 2, wherein the group 1 alkali metal is selected from lithium, sodium, potassium, rubidium, cesium or francium.
4. The TMD of any one of claims 1 to 3, further comprising a second portion, wherein the first portion has a different phase structure than the second portion.
5. The TMD according to any one of claims 1 to 4, wherein the first part has a metal octahedral (1T') phase structure.
6. The TMD according to any one of claims 1 to 5, wherein the thickness of the group 1 alkali metal in the first part is from about 0.2nm to about 10 nm.
7. TMD according to any of claims 1 to 6, selected from MoS2、WS2、MoSe2And WSe2、MoTe2Alkali metal doped MoTe2Alkali metal doped MoSe2Alkali metal doped MoS2Alkali metal doped WTE2Alkali metal doped WSe2Or alkali metal-doped WS2。
8. An electronic device, comprising:
a Transition Metal Dichalcogenide (TMD) layer comprising a first portion, wherein the first portion is surface modified with a group 1 alkali metal; and
a pair of electrodes connected to the TMD layer.
9. The electronic device of 8, having a conductivity at least 4 times greater than a conductivity of a control.
10. The electronic device of 8 or 9, having a contact resistance of about 1k Ω μm to about 10k Ω μm.
11. The electronic device of any one of claims 8 to 10, having at least about 70cm2V-1s-1Electron mobility of (2).
12. The electronic device of any one of claims 8-11, having a current on/off ratio of at least about 80.
13. The electronic device of any one of claims 8 to 12, having a dec of at least about 60mV-1Sub-threshold swing (SS).
14. The electronic device of any one of claims 8-13, having a voltage gain of about 100.
15. The electronic device of any one of claims 8-14, having a power consumption of less than about 10 pW.
16. The electronic device according to any one of claims 8 to 15, which is a logic inverter or a field effect transistor.
17. An electronic circuit comprising the electronic device of any one of 8 to 16.
18. An electronic system comprising the electronic circuit of 17.
Claims (20)
1. A material, comprising: a Transition Metal Dichalcogenide (TMD) comprising a surface, at least a portion of the surface being surface modified with one or more group 1 metals, wherein the one or more group 1 metals comprise Cs and/or Rb.
2. The material of claim 1, wherein the transition metal dichalcogenide comprises MoS2、WS2、MoSe2、WSe2、MoTe2Alkali metal doped MoTe2Alkali metal doped MoSe2Alkali metal doped MoS2Alkali metal doped WSe2And alkali metal-doped WS2One or more of (a).
3. The material of claim 2, wherein the transition metal dichalcogenide packageScraper WSe2And/or MoTe2One or more of (a).
4. The material of claim 3, wherein the transition metal dichalcogenide comprises WSe2。
5. A material according to any preceding claim, wherein the one or more group 1 metals form a layer on the surface.
6. The material of any preceding claim, wherein the one or more group 1 metals form a layer on the surface of at least first and second portions of the transition metal dichalcogenide.
7. The material of claim 6, wherein the transition metal dichalcogenide further comprises a third portion that is not surface modified with one or more group 1 metals.
8. The material of claim 7, wherein the first and second portions are in different phases than the third portion.
9. The material of claim 7 or 8, wherein the layer of the one or more group 1 metals has a thickness greater than or equal to 0.2 nm.
10. The material of claim 9, wherein the layer of the one or more group 1 metals has a thickness of 0.4nm to 2.0 nm.
11. The material of any preceding claim, wherein at least a portion of the transition metal dichalcogenide has a thickness of 1 to 5 layers.
12. The material of claim 11, wherein at least a portion of the transition metal dichalcogenide is a monolayer or a bilayer.
13. An electronic device, comprising:
a material according to any one of claims 7 to 12; and
a first electrode and a second electrode, wherein,
wherein the first and second electrodes are in direct electrical contact with the first and second portions of the transition metal dichalcogenide, respectively.
14. The electronic device of claim 13, wherein the device exhibits substantially ohmic contact characteristics with respect to the first and second electrodes.
15. The electronic device of claim 13 or 14, having a schottky barrier height of less than or equal to 10 meV.
16. The electronic device of any one of claims 13 to 15, wherein the electronic device is a field effect transistor.
17. The electronic device of any of claims 13-15, wherein the electronic device is a logic inverter.
18. A method of producing a material according to any one of claims 1 to 12, the method comprising:
providing a transition metal dichalcogenide; and
evaporating one or more group 1 metals onto at least a portion of the surface of the transition metal dichalcogenide, wherein the one or more group 1 metals comprise Cs and/or Rb.
19. A method of producing an electronic device according to any one of claims 13 to 17, the method comprising:
providing a transition metal dichalcogenide layer and first and second electrodes on a surface of a substrate such that the first and second electrodes are in electrical contact with the transition metal dichalcogenide layer;
evaporating one or more group 1 metals onto surfaces of first and second portions of the transition metal dichalcogenide layer such that the thickness of the one or more group 1 metals is at least 0.2nm, wherein the first and second portions of the transition metal dichalcogenide layer are adjacent to the first and second electrodes, respectively, and wherein the one or more group 1 metals comprise Cs and/or Rb.
20. The method of claim 19, wherein evaporating a group 1 metal onto surfaces of the first and second portions of the transition metal dichalcogenide layer comprises: forming a barrier layer on portions of the surface of all portions of the transition metal dichalcogenide except the first and second portions prior to evaporating the one or more group 1 metals.
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