WO2021014875A1 - Dispositif à semi-conducteur - Google Patents

Dispositif à semi-conducteur Download PDF

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Publication number
WO2021014875A1
WO2021014875A1 PCT/JP2020/024940 JP2020024940W WO2021014875A1 WO 2021014875 A1 WO2021014875 A1 WO 2021014875A1 JP 2020024940 W JP2020024940 W JP 2020024940W WO 2021014875 A1 WO2021014875 A1 WO 2021014875A1
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WIPO (PCT)
Prior art keywords
bus bar
region
semiconductor
substrate
semiconductor element
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PCT/JP2020/024940
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English (en)
Japanese (ja)
Inventor
潤一 木村
惇 松本
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パナソニックＩｐマネジメント株式会社
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Publication of WO2021014875A1 publication Critical patent/WO2021014875A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate

Definitions

  • This disclosure relates to semiconductor devices.
  • the semiconductor device is used, for example, as a drive control device for industrial equipment, a drive control device for home appliances equipped with a motor, an electric vehicle, an in-vehicle control device for a hybrid vehicle, or the like.
  • the semiconductor device is equipped with a semiconductor element represented by a power semiconductor element.
  • a semiconductor element represented by a power semiconductor element.
  • the power semiconductor element include an insulated gate bipolar transistor (IGBT) and a metal-oxide field effect transistor (Metal Oxide Semiconductor Field Effect Transistor: MOSFET).
  • Patent Document 1 discloses a power semiconductor device including a MOSFET.
  • the semiconductor device includes a substrate having a first region and a second region on the upper surface, a first input terminal provided in the first region of the substrate, and a current input terminal and a current.
  • a first circuit including a first semiconductor element having a first output terminal, and a second circuit provided in the second region of the substrate and having a second input terminal for inputting a current and a second output terminal for outputting a current.
  • the first output terminal has a second circuit including a semiconductor element, a first connection terminal that can be connected to the outside, and a flat plate-shaped portion provided above the substrate so as to face the upper surface of the substrate.
  • first bus bar for connecting the second input terminal and a flat plate-shaped portion provided above the substrate so as to face the upper surface of the substrate, and connects the second output terminal to the first connection. It is provided with a second bus bar for connecting to a terminal.
  • the distance between the substrate and the flat plate-shaped portion of the first bus bar is longer than the thickness of the first semiconductor element provided in the first region, and the flat plate-shaped portion of the substrate and the second bus bar.
  • the distance between the substrates is longer than the distance between the flat plate-shaped portion of the first bus bar, and the flat plate-shaped portion of the second bus bar is from above the first region to above the second region.
  • the flat plate-shaped portion of the first bus bar and the flat plate-shaped portion of the second bus bar overlap at least a part thereof.
  • FIG. 1 is a perspective view showing a schematic configuration of a semiconductor device according to an embodiment.
  • FIG. 2 is a plan view of the semiconductor device according to the embodiment.
  • FIG. 3 is a cross-sectional view showing a cut surface taken along the line III-III in FIG.
  • FIG. 4 is a cross-sectional view showing a cut surface taken along line IV-IV in FIG.
  • FIG. 5 is a plan view of the semiconductor device according to the embodiment in a state where the first bus bar and the second bus bar are not arranged.
  • FIG. 6 is a plan view of the semiconductor device according to the embodiment in a state where the second bus bar is not arranged.
  • FIG. 7 is an enlarged cross-sectional view of the semiconductor device according to the embodiment.
  • FIG. 8 is a circuit diagram of the semiconductor device according to the embodiment.
  • the inductance of the main circuit is reduced by arranging the positive electrode side internal electrode and the negative electrode side internal electrode close to each other at the center of the power semiconductor device.
  • the effect of reducing the inductance is not sufficient, and further improvement in the reliability of the semiconductor device is required.
  • the terms “upper” and “lower” do not refer to the upward direction (vertically upward) and the downward direction (vertically downward) in absolute spatial recognition, but are based on the stacking order in the laminated structure. It is used as a term defined by the relative positional relationship with. Specifically, the vertical direction of the substrate of the semiconductor device on the surface side on which the semiconductor element or the like is mounted is set as the upward direction.
  • the terms “upper”, “lower”, “upper surface” and “lower surface” are used only to specify the mutual arrangement between the members, and are intended to limit the posture when the semiconductor device is used. Absent.
  • the terms “upper” and “lower” are used not only when the two components are spaced apart from each other and another component exists between the two components, but also when the two components It also applies when the two components are placed in close contact with each other and touch each other. Further, in the present specification, the “height” is an upward height from the substrate.
  • FIG. 1 is a perspective view showing a schematic configuration of a semiconductor device 1 according to the present embodiment.
  • FIG. 2 is a plan view of the semiconductor device 1.
  • the semiconductor device 1 is, for example, a semiconductor device 1 arranged in an outer frame 3 provided on the heat radiating plate 2.
  • the semiconductor device 1 is a first connection terminal 41 for connecting the substrate 10, the first circuit composed of the first semiconductor element 20, the second circuit composed of the second semiconductor element 30, and the outside.
  • a second bus bar 42 and a third connection terminal 43, and a first bus bar 50, a second bus bar 60, a third bus bar 70, and a fourth bus bar 80 for connecting circuits are provided.
  • the semiconductor device 1 includes insulating layers 91 and 92, which are not shown in FIGS. 1 and 2.
  • the first bus bar 50, the second bus bar 60, the third bus bar 70, and the fourth bus bar 80 may be collectively referred to as a “bus bar”.
  • the bus bar is a conductor having a large flat plate shape for passing a large current.
  • a metal having high electrical conductivity such as copper, silver, gold or aluminum is used.
  • the metal used in the busbar may be an alloy containing at least one of copper, silver, gold and aluminum.
  • the thickness of the bus bar is, for example, 0.4 mm or more and 3.0 mm or less. The thickness of the busbar may be different within the busbar.
  • the first bus bar 50, the second bus bar 60, the third bus bar 70, and the fourth bus bar 80 may have the same thickness, or may have different thicknesses.
  • the semiconductor device 1 has a half-bridge type circuit configuration, and is, for example, a semiconductor device that constitutes one phase of a three-phase inverter device.
  • the first connection terminal 41 is an external connection terminal on the negative electrode side
  • the second connection terminal 42 is an external connection terminal on the positive electrode side
  • the third connection terminal 43 is an external connection terminal on the output side.
  • the first circuit and the second circuit are switch circuits that control the flow of current by switching on and off.
  • the heat radiating plate 2 is a heat sink made of a metal having high thermal conductivity such as copper or aluminum. Further, the metal forming the heat radiating plate 2 may be an alloy containing at least one of copper and aluminum.
  • the outer frame 3 is made of, for example, a resin or the like, and is a rectangular annular structure in a plan view with respect to the substrate 10 for holding connection terminals and the like. Further, the inside of the outer frame 3 may be sealed with a sealing resin or the like.
  • the first connection terminal 41, the second connection terminal 42, and the third connection terminal 43 are made of, for example, copper or the like.
  • FIG. 3 is a cross-sectional view showing a cut surface taken along the line III-III in FIG.
  • FIG. 4 is a cross-sectional view showing a cut surface taken along line IV-IV in FIG.
  • FIG. 5 is a plan view of the semiconductor device 1 for explaining a state in which the first bus bar 50 and the second bus bar 60 are not arranged in the semiconductor device 1.
  • FIG. 6 is a plan view of the semiconductor device 1 for explaining a state in which the second bus bar 60 is not arranged in the semiconductor device 1.
  • the illustration of the wiring pattern of the substrate 10 is omitted.
  • FIGS. 2 to 6 the insulating layers 91 and 92 are not shown.
  • the first semiconductor element 20, the second semiconductor element 30, the first bus bar 50, the second bus bar 60, the third bus bar 70 and the fourth The bus bar 80 is arranged above the substrate 10.
  • the substrate 10 and the first semiconductor element 20, the second semiconductor element 30, the third bus bar 70, and the fourth bus bar 80 mounted directly on the substrate 10 will be described.
  • the substrate 10 is arranged on the heat radiating plate 2, and is formed in contact with the insulator layer 10a, the upper metal layers 10b and 10c formed in contact with the upper surface of the insulator layer 10a, and the lower surface of the insulator layer 10a. It has a lower surface metal layer 10d. Further, a wiring pattern is formed on the insulator layer 10a.
  • the upper surface metal layer 10b and the upper surface metal layer 10c are formed separately and are electrically insulated.
  • the substrate 10 is, for example, a ceramic substrate or a resin substrate.
  • the insulator layer 10a is formed of, for example, ceramics such as alumina, silicon nitride or aluminum nitride, or a resin such as an epoxy resin. Among these, from the viewpoint of enhancing the heat dissipation of the semiconductor device 1, the insulator layer 10a may be formed of, for example, ceramics having high thermal conductivity.
  • the upper surface metal layers 10b and 10c and the lower surface metal layer 10d are formed of a metal foil or a thin metal plate having high electrical conductivity.
  • the metal of the metal foil or the thin metal plate include copper, silver, gold, and aluminum.
  • the metal of the metal foil or the metal sheet may be an alloy containing at least one of copper, silver, gold and aluminum.
  • the upper surface metal layer 10c is connected to the third connection terminal 43 by soldering or the like.
  • the lower metal layer 10d is connected to the heat radiating plate 2 by soldering or the like.
  • the lower metal layer 10d may be connected to the heat radiating plate 2 by joining, brazing, diffusion bonding, or the like with a sintered metal.
  • the heat of the semiconductor device 1 is conducted to the heat radiating plate 2 and radiated through the lower metal layer 10d.
  • the substrate 10 has a first region 11 and a second region 12.
  • the first region 11 is divided into a third region 13 and a fourth region 14 in a plan view by the third bus bar 70.
  • the second region 12 is divided into a fifth region 15 and a sixth region 16 in a plan view by the fourth bus bar 80.
  • the upper surface metal layer 10b is arranged in the first region 11, and the upper surface metal layer 10c is arranged in the second region 12.
  • the first semiconductor element 20 is mounted in the first region 11 on the substrate 10 to form the first circuit.
  • the first circuit is composed of six first semiconductor elements 20.
  • three first semiconductor elements 20 are mounted in the third region 13 and the fourth region 14, respectively, along the direction in which the third bus bar 70 extends.
  • the three first semiconductor elements 20 mounted in the third region 13 and the fourth region 14, respectively, are arranged so as to face each other with the third bus bar 70 as the target axis.
  • the number of the first semiconductor elements 20 mounted in the third region 13 and the fourth region 14, respectively is not limited to three, and may be one or more and two or less, and four or more. May be good.
  • the same number of first semiconductor elements 20 are arranged in the third region 13 and the fourth region 14 so as to face each other with the third bus bar 70 as the target axis.
  • the first semiconductor element 20 has a first input terminal 21 for inputting a current and a first output terminal 22 for outputting a current (see FIG. 4).
  • the first input terminal 21 is formed on the lower surface of the first semiconductor element 20, and is connected to the upper surface metal layer 10b in the first region 11 by soldering or the like.
  • the first output terminal 22 is formed on the upper surface of the first semiconductor element 20 and is connected to the first bus bar 50 described later. Further, the six first semiconductor elements 20 are all connected so as to be electrically parallel in order to increase the current.
  • the second semiconductor element 30 is mounted in the second region 12 on the substrate 10 to form a second circuit.
  • the second circuit is composed of six second semiconductor elements 30.
  • three second semiconductor elements 30 are mounted in the fifth region 15 and the sixth region 16 along the direction in which the fourth bus bar 80 extends.
  • the three second semiconductor elements 30 mounted in the fifth region 15 and the sixth region 16 are arranged so as to face each other with the fourth bus bar 80 as the target axis.
  • the number of the second semiconductor elements 30 mounted in the fifth region 15 and the sixth region 16 is not limited to three, and may be one or more and two or less, and four or more. May be good.
  • the same number of second semiconductor elements 30 are arranged in the fifth region 15 and the sixth region 16 so as to face each other with the fourth bus bar 80 as the target axis.
  • the second semiconductor element 30 has a second input terminal 31 for inputting a current and a second output terminal 32 for outputting a current (see FIG. 4).
  • the second input terminal 31 is formed on the lower surface of the second semiconductor element 30, and is connected to the upper surface metal layer 10c in the second region 12 by soldering or the like. As a result, the second input terminal 31 is connected to the third connection terminal 43 via the upper surface metal layer 10c.
  • the second output terminal 32 is formed on the upper surface of the second semiconductor element 30, and is connected to the second bus bar 60, which will be described later. Further, the six second semiconductor elements 30 are all connected so as to be electrically parallel in order to increase the current.
  • the first semiconductor element 20 and the second semiconductor element 30 are composed of, for example, a silicon semiconductor, a gallium nitride semiconductor, a silicon carbide semiconductor, or the like.
  • the first semiconductor element 20 and the second semiconductor element 30 may be made of a gallium nitride semiconductor or a silicon carbide semiconductor from the viewpoint that the switching frequency can be made higher.
  • the first semiconductor element 20 and the second semiconductor element 30 are transistors such as MOSFETs and IGBTs. Such a semiconductor element is used, for example, in a semiconductor device capable of passing a large current.
  • MOSFETs MOSFETs
  • the first semiconductor element 20 and the second semiconductor element 30 When the first semiconductor element 20 and the second semiconductor element 30 are MOSFETs, the first semiconductor element 20 and the second semiconductor element 30 have a drain electrode, a source electrode, and a gate electrode (not shown). When the first semiconductor element 20 and the second semiconductor element 30 are n-type MOSFETs, the first input terminal 21 and the second input terminal 31 are drain electrodes, and the first output terminal 22 and the second output terminal 32 are It is a source electrode.
  • the first semiconductor element 20 and the second semiconductor element 30 may be p-type MOSFETs.
  • the number of the first semiconductor element 20 and the number of the second semiconductor element 30 are 6 respectively, but the number is not limited to this.
  • the number of the first semiconductor element 20 and the number of the second semiconductor element 30 may be one or more, respectively, and may be any number according to the amount of current to be passed and the characteristics of the semiconductor element.
  • the third bus bar 70 is mounted in the first region 11 on the substrate 10.
  • the shape of the third bus bar 70 is a flat plate shape, for example, a rectangular flat plate shape.
  • the third bus bar 70 is used to connect the second connection terminal 42 and the first input terminal 21.
  • One end of the upper surface of the third bus bar 70 is connected to the second connection terminal 42 by soldering or the like.
  • the lower surface of the third bus bar 70 is connected to the upper metal layer 10b by soldering or the like. Therefore, the third bus bar 70 is connected to the first input terminal 21 via the upper surface metal layer 10b.
  • the first input terminal 21 is connected to the second connection terminal 42 via the third bus bar 70 and the upper surface metal layer 10b.
  • the third bus bar 70 does not have to be directly connected to the second connection terminal 42, and may be connected to the second connection terminal 42 via the upper metal layer 10b, for example.
  • the thickness of the third bus bar 70 is thicker than the thickness of the upper surface metal layer 10b. Therefore, the current resistance of the third bus bar 70 tends to be smaller than that of the upper surface metal layer 10b. Further, the material of the third bus bar 70 may be a material having higher conductivity than the material of the upper surface metal layer 10b.
  • the fourth bus bar 80 is mounted in the second region 12 on the substrate 10.
  • the shape of the fourth bus bar 80 is a flat plate shape, for example, a rectangular flat plate shape.
  • the fourth bus bar 80 is used to connect the first bus bar 50 to the second input terminal 31 and the third connection terminal 43.
  • the fourth bus bar 80 is also used to connect the second input terminal 31 and the third connection terminal 43.
  • the lower surface of the fourth bus bar 80 is connected to the upper metal layer 10c by soldering or the like. Therefore, the fourth bus bar 80 is connected to the second input terminal 31 and the third connection terminal 43 via the upper surface metal layer 10c. Further, the fourth bus bar 80 is connected to the first bus bar 50 via the upper metal layer 10c.
  • the fourth bus bar 80 and the third connection terminal 43 and / or the first bus bar 50 may be directly connected by soldering or the like without passing through the upper surface metal layer 10c.
  • the thickness of the fourth bus bar 80 is thicker than the thickness of the upper surface metal layer 10c. Therefore, the electric resistance of the fourth bus bar 80 tends to be smaller than that of the upper surface metal layer 10c. Further, the material of the fourth bus bar 80 may be a material having higher conductivity than the material of the upper surface metal layer 10c.
  • the flat plate-shaped portion 53 of the first bus bar 50 is located above the first semiconductor element 20 provided on the substrate 10.
  • the distance from the substrate 10 to the flat plate-shaped portion 53 of the first bus bar 50 in the Z direction is shown by “H1” in FIGS. 3 and 4.
  • the distance from the substrate 10 to the flat plate-shaped portion 62 of the second bus bar 60 in the Z direction is shown by “H2” in FIGS. 3 and 4.
  • the first bus bar 50 extends from above the first region 11 toward above the second region 12 and has a flat plate-shaped portion 53 parallel to the substrate 10.
  • the first bus bar 50 has a region that overlaps with the third bus bar 70 in a plan view with respect to the substrate 10.
  • the first bus bar 50 is used to connect the first output terminal 22 and the second input terminal 31.
  • the first bus bar 50 is also used to connect the first output terminal 22 and the third connection terminal 43.
  • the first bus bar 50 has rising portions 51 and 52 extending from below toward the flat plate-shaped portion 53.
  • the rising portions 51 and 52 are examples of the first rising portion.
  • Three rising portions 51 are formed at both ends of the rectangular flat plate-shaped portion 53 of the first bus bar 50 in a plan view with respect to the substrate 10 in a direction perpendicular to the direction from the first region 11 to the second region 12. Has been done.
  • the rising portion 51 is a leg-shaped portion that rises from the height of the upper surface of the first semiconductor element 20 to the height of the flat plate-shaped portion 53 of the first bus bar 50.
  • the rising portion 52 is formed at an end portion of the flat plate-shaped portion 53 of the first bus bar 50 located above the second region 12 in a plan view with respect to the substrate 10.
  • the rising portion 52 is a stepped portion that rises from the upper surface of the upper surface metal layer 10c of the substrate 10 to the flat plate-shaped portion 53 of the first bus bar 50.
  • Each of the rising portions 51 is connected to the first output terminal 22 of the first semiconductor element 20 by soldering or the like.
  • the rising portion 52 is connected to the upper surface metal layer 10c of the substrate 10 by soldering or the like.
  • the first bus bar 50 is connected to the first output terminal 22 and the upper surface metal layer 10c. Therefore, the first bus bar 50 is connected to the second input terminal 31 and the third connection terminal 43 via the upper surface metal layer 10c and the fourth bus bar 80.
  • the distance H2 from the substrate 10 to the flat plate-shaped portion 62 of the second bus bar 60 is the distance from the substrate 10 to the flat plate-shaped portion 53 of the first bus bar 50 in the Z direction. Longer than H1.
  • the flat plate-shaped portion 53 of the first bus bar 50 extends from above the first region 11 toward above the second region 12.
  • the flat plate-shaped portion 53 has a flat plate shape parallel to the substrate 10.
  • the second bus bar 60 is used to connect the second output terminal 32 and the first connection terminal 41.
  • the second bus bar 60 has a region that overlaps with the first bus bar 50 in a plan view with respect to the substrate 10. That is, the first bus bar 50 and the second bus bar 60 are arranged in parallel facing each other at positions at different heights from the substrate 10.
  • the second bus bar 60 has a region that overlaps with the third bus bar 70 in a plan view with respect to the substrate 10. Further, the second bus bar 60 has a region that overlaps with the fourth bus bar 80 in a plan view with respect to the substrate 10. As shown in FIG. 2, the second bus bar 60 is arranged so as to completely cover the first bus bar 50 and the fourth bus bar 80 in a plan view with respect to the substrate 10.
  • the second bus bar 60 may not be arranged so as to completely cover the first bus bar 50 and the fourth bus bar 80, or may cover a part of the first bus bar 50 and the fourth bus bar 80.
  • the second bus bar 60 has a rising portion 61 extending from below toward the flat plate-shaped portion 62.
  • the rising portion 61 is an example of the second rising portion.
  • the rising portion 61 is formed at one end of the flat plate-shaped portion 62 of the second bus bar 60 in a plan view with respect to the substrate 10.
  • the end of the flat plate-shaped portion 62 on which the rising portion 61 is formed is located above the second region 12.
  • the rising portion 61 is a portion that rises from the upper surface of the second semiconductor element 30 to the flat plate-shaped portion 62 of the second bus bar 60.
  • the rising portion 61 is composed of a leg-shaped portion 61a, a plate portion 61b, and a connecting portion 61c.
  • Three leg-shaped portions 61a are formed at both ends of the plate portion 61b in a direction perpendicular to the direction from the second region 12 to the first region 11 in a plan view with respect to the substrate 10.
  • the leg-shaped portion 61a is a leg-shaped portion that rises from the upper surface of the second semiconductor element 30 to the plate portion 61b.
  • the plate portion 61b and the leg-shaped portion 61a are located above the second semiconductor element 30, and the plate portion 61b is a flat plate parallel to 10. It has a region that overlaps with the fourth bus bar 80 in a plan view with respect to the substrate 10.
  • the connecting portion 61c joins the end portion of the flat plate-shaped portion 62 of the second bus bar 60 on the second region 12 side and the end portion of the plate portion 61b on the first region 11 side in a plan view with respect to the substrate 10. It is formed.
  • the connecting portion 61c may be formed of a joining material such as solder, or may be formed by welding a metal material or the like. Further, the connecting portion 61c may be formed by bending a flat plate.
  • the rising portion 61 may be composed of only the leg-shaped portion 61a.
  • the flat plate-shaped portion 62 of the second bus bar 60 extends above the second semiconductor element 30, and the leg-shaped portion 61a is formed at the end of the flat plate-shaped portion 62.
  • the end of the second bus bar 60 on the first region 11 side is connected to the first connection terminal 41 by soldering or the like. Further, each of the leg-shaped portions 61a of the second bus bar 60 is connected to the second output terminal 32 of the second semiconductor element 30 by soldering or the like. As a result, the second bus bar 60 connects the first connection terminal 41 and the second output terminal 32.
  • FIG. 7 is an enlarged cross-sectional view of a part of the semiconductor device 1.
  • FIG. 7 shows a portion including a space between the first bus bar 50 and the second bus bar 60.
  • the semiconductor device 1 includes insulating layers 91 and 92 that electrically insulate the first bus bar 50 and the second bus bar 60.
  • the insulating layers 91 and 92 are, for example, insulating films coated on the surfaces of the first bus bar 50 and the second bus bar 60, respectively. That is, the surface of the first bus bar 50 is covered with the insulating layer 91 made of an insulating film, and the surface of the second bus bar 60 is covered with the insulating layer 92 made of an insulating film.
  • the insulating layers 91 and 92 do not have to cover all the surfaces of the first bus bar 50 and the second bus bar 60, respectively.
  • the first bus bar 50 and the second bus bar 60 are attached to the substrate 10. It may cover the surface of the overlapping regions in a plan view.
  • the insulating film is, for example, a film coated with an insulator such as a resin material, and is formed by electrodeposition coating, laminate coating, or the like.
  • an insulator such as a resin material
  • the resin material of the insulating film for example, a polyimide resin, an epoxy resin, a silicone resin, or the like is used.
  • the structure can be such that the first bus bar 50 and the second bus bar 60 are close to each other.
  • the insulating layers 91 and 92 are insulating films coated on the surfaces of the first bus bar 50 and the second bus bar 60, the insulating layers 91 and 92 can be made thinner, so that the first bus bar can be made thinner.
  • the structure can be such that the 50 and the second bus bar 60 are close to each other.
  • a space is provided between the insulating layer 91 and the insulating layer 92, but even if the first bus bar 50 and the second bus bar 60 are in contact with each other via the insulating layers 91 and 92. Good. Further, the insulating layers 91 and 92 may be provided with only one of them.
  • the semiconductor device 1 may include an insulating layer that insulates the first bus bar 50 and the third bus bar 70, or the second bus bar 60 and the fourth bus bar 80.
  • FIG. 8 is a circuit diagram of the semiconductor device 1 according to the present embodiment.
  • the six first semiconductor elements 20 and the six second semiconductor elements 30 connected in parallel are referred to as one first semiconductor element 20 and a second semiconductor element 30, respectively. , Is abbreviated.
  • the first semiconductor element 20 and the second semiconductor element 30 function as switching elements to turn on / off the current flow.
  • the switch by the first semiconductor element 20 is on and the switch by the second semiconductor element 30 is off will be described.
  • the current flows from the second connection terminal 42 to the third connection terminal 43 via the third bus bar 70, the first semiconductor element 20, the first bus bar 50, and the fourth bus bar 80 in this order. Therefore, when referring to FIG. 3, the third bus bar 70, the first bus bar 50, and the fourth bus bar 80 have a first direction from the first region 11 (see FIG. 2) to the second region 12 (see FIG. 2). Current flows through.
  • a current flows in the first bus bar 50 in the first direction, and a current flows in the second bus bar 60 arranged to face the first bus bar 50 in the second direction opposite to the first direction.
  • the mutual inductance of the first bus bar 50 and the second bus bar 60 acts to cancel the parasitic inductance of each of the first bus bar 50 and the second bus bar 60. Therefore, the inductance of the semiconductor device 1 as a whole is reduced.
  • the mutual inductance increases as the facing area of the first bus bar 50 and the second bus bar 60 increases. Further, the mutual inductance increases as the distance between the first bus bar 50 and the second bus bar 60 becomes closer. Therefore, the flat plate-shaped portion 53 of the first bus bar 50 and the flat plate-shaped portion 62 of the second bus bar 60 are arranged so as to face each other.
  • the mutual inductance of the first bus bar 50 and the second bus bar 60 increases by having a region where the first bus bar 50 and the second bus bar 60 overlap in a plan view with respect to the substrate 10. Therefore, the effect of reducing the inductance of the entire semiconductor device 1 is enhanced.
  • the second bus bar 60 is arranged so as to completely cover the first bus bar 50 in a plan view with respect to the substrate 10, so that the entire semiconductor device 1 is formed. The effect of reducing the inductance becomes higher.
  • a current flows through the third bus bar 70 in the first direction
  • a current flows through the second bus bar 60 which overlaps with the third bus bar 70 in a plan view with respect to the substrate 10 in the second direction opposite to the first direction.
  • the mutual inductance of the third bus bar 70 and the second bus bar 60 acts to cancel the parasitic inductance of each of the third bus bar 70 and the second bus bar 60. Therefore, the inductance of the semiconductor device 1 as a whole is further reduced.
  • the semiconductor device 1 does not have the third connection terminal 43, and the first semiconductor element 20 and the second semiconductor element 30 may be connected to other electronic components provided in the semiconductor device 1. .. Even in such a case, since the direction of the current flowing through each bus bar is the same, the inductance of the semiconductor device 1 as a whole is reduced.
  • the semiconductor device 1 of one aspect of the present disclosure includes a substrate 10 having a first region 11 and a second region 12 on the upper surface, a first input terminal 21 provided in the first region 11 of the substrate 10 and into which a current is input.
  • a first circuit including a first semiconductor element 20 having a first output terminal 22 for outputting a current, a second input terminal 31 provided in a second region 12 of a substrate 10 for receiving a current, and a second circuit for outputting a current.
  • a second circuit including a second semiconductor element 30 having two output terminals 32, a first connection terminal 41 that can be connected to the outside, and a flat plate-shaped portion 53 provided above the substrate 10 so as to face the upper surface of the substrate 10.
  • first bus bar 50 for connecting the first output terminal 22 and the second input terminal 31, and a flat plate-shaped portion 62 provided above the substrate 10 so as to face the upper surface of the substrate 10.
  • a second bus bar 60 for connecting the second output terminal 32 and the first connection terminal 41 is provided.
  • the distance H1 between the substrate 10 and the flat plate-shaped portion 53 of the first bus bar 50 is longer than the thickness of the first semiconductor element 20 provided in the first region 11, and the flat plate-shaped portion 62 of the substrate 10 and the second bus bar 60.
  • the distance H2 between the two is longer than the distance H1 between the substrate 10 and the flat plate-shaped portion 53 of the first bus bar 50, and the flat plate-shaped portion 62 of the second bus bar 60 is from above the first region 11 to the second region.
  • the flat plate-shaped portion 53 of the first bus bar 50 and the flat plate-shaped portion 62 of the second bus bar 60 are at least partially overlapped with each other in a plan view extending upward of 12.
  • the first bus bar 50 and the second bus bar 60 are arranged above the substrate 10 so that at least a part of them overlap each other in a plan view with respect to the substrate 10. Further, a current flows through the first bus bar 50 from the first region 11 toward the second region 12, and the second bus bar 60 starts from the second region 12 opposite to the direction in which the current flows through the first bus bar 50. A current flows toward the first region 11. As a result, the mutual inductance of the first bus bar 50 and the second bus bar 60 acts to cancel the parasitic inductance of each of the first bus bar 50 and the second bus bar 60. Therefore, the inductance of the semiconductor device 1 as a whole is reduced, and the generation of an unintended electromotive force is suppressed, so that the reliability of the semiconductor device 1 is improved.
  • a current flows through the first bus bar 50 across the regions where the first semiconductor element 20 and the second semiconductor element 30 are mounted. Therefore, for convenience of design, even when the first semiconductor element 20 and the second semiconductor element 30 are mounted at distant positions, the current from the first output terminal 22 of the first semiconductor element 20 is the first. It is easy to flow uniformly in the bus bar 50. Similarly, the current from the second output terminal 32 of the second semiconductor element 30 also tends to flow uniformly in the second bus bar 60. Therefore, the reliability of the semiconductor device 1 can be further improved.
  • the semiconductor device 1 of another aspect of the present disclosure is provided in the second connection terminal 42 that can be connected to the outside, the third connection terminal 43 that can be connected to the outside, and the first region 11 of the substrate 10, and the second connection terminal 42.
  • a fourth bus bar 80 connected to is provided.
  • the third bus bar 70 and the fourth bus bar which are thick conductors, are connected to the connection between the second connection terminal 42 and the first input terminal 21 and the connection between the second connection terminal 42 and the first input terminal 21. 80 and are used. Therefore, in the semiconductor device 1, the electric resistance in the current path becomes small, and wasteful power consumption is suppressed. Further, the parasitic inductance in the connection path between the second connection terminal 42 and the first input terminal 21 and the connection path between the second connection terminal 42 and the first input terminal 21 can be reduced.
  • the semiconductor device 1 includes a first circuit composed of six first semiconductor elements 20, a first region 11 including a third region 13 and a fourth region 14, in a plan view.
  • the third bus bar 70 is located between the third region 13 and the fourth region 14, three first semiconductor elements 20 are provided in the third region 13, and the three first semiconductor elements 20 are the fourth.
  • the second circuit is composed of six second semiconductor elements 30, the second region 12 includes the fifth region 15 and the sixth region 16, and the fourth bus bar 80 is in plan view. Located between the fifth region 15 and the sixth region 16, three second semiconductor elements 30 are provided in the fifth region 15, and three second semiconductor elements 30 are provided in the sixth region.
  • the semiconductor device 1 can easily flow a current having a larger capacity. Further, a plurality of first semiconductor elements 20 are mounted in the third region 13 and the fourth region 14 divided by the third bus bar 70 connected to the first input terminal of the first semiconductor element 20. Therefore, since it is easy to mount each of the plurality of first semiconductor elements 20 in a region at an equal distance from the third bus bar 70, it is difficult for a difference in electrical resistance to occur until the current reaches each of the plurality of first semiconductor elements 20. That is, the amount of current flowing through each of the plurality of first semiconductor elements 20 tends to be uniform. Further, for the same reason as that of the first semiconductor element 20, the amount of current flowing through each of the plurality of second semiconductor elements 30 tends to be uniform. Therefore, the reliability of the semiconductor device 1 is further improved.
  • the number of the first semiconductor element 20 and the second semiconductor element 30 is not limited to the above number.
  • the three first semiconductor elements 20 provided in the third region 13 are arranged along the direction (x direction) in which the third bus bar extends.
  • the three first semiconductor elements 20 provided in the fourth region 14 are arranged along the direction (x direction) in which the third bus bar 70 extends, and the three second semiconductor elements 20 provided in the fifth region 15 are arranged.
  • the semiconductor elements 30 are arranged along the direction in which the fourth bus bar 80 extends (x direction), and the three second semiconductor elements 30 provided in the sixth region 16 extend in the direction in which the fourth bus bar 80 extends (x direction). ) Are lined up.
  • the plurality of first semiconductor elements 20 are mounted in the third region 13 or the fourth region 14, and the plurality of second semiconductor elements 30 are mounted in the fifth region 15 or the sixth region 16, so that the semiconductor device 1 Makes it easier to carry a larger amount of current.
  • the plurality of first semiconductor elements 20 are mounted along the direction in which the third bus bar 70 having a small electric resistance extends, the distances from each of the plurality of first semiconductor elements 20 to the third bus bar 70 become uniform. .. Therefore, it is difficult for a difference in electrical resistance to occur until the current reaches each of the plurality of first semiconductor elements 20, and the amount of current flowing through each of the plurality of first semiconductor elements 20 tends to be uniform. Further, for the same reason as that of the first semiconductor element 20, the amount of current flowing through each of the plurality of second semiconductor elements 30 tends to be uniform. Therefore, the reliability of the semiconductor device 1 can be further improved.
  • the second bus bar 60 has a second rising portion 61 extending from below toward the flat plate-shaped portion 62 of the second bus bar 60.
  • the semiconductor device 1 of another aspect of the present disclosure includes insulating layers 91 and 92 that electrically insulate the first bus bar 50 and the second bus bar 60.
  • the semiconductor device 1 can be miniaturized.
  • the first semiconductor element 20 and the second semiconductor element 30 are composed of a gallium nitride semiconductor or a silicon carbide semiconductor.
  • a gallium nitride semiconductor or a silicon carbide semiconductor is a semiconductor material suitable for increasing the switching frequency. Therefore, when the semiconductor device 1 is used for switching at a higher frequency, the effect of improving the reliability of the semiconductor device 1 by reducing the inductance becomes greater.
  • the semiconductor device 1 includes the third bus bar 70 and the fourth bus bar 80, but the semiconductor device 1 does not have to include the third bus bar 70 and the fourth bus bar 80.
  • the second connection terminal 42 and the first input terminal 21 are connected to each other via the upper metal layer 10b of the substrate 10, and the first bus bar 50, the second input terminal 31, and the third connection terminal 43 are connected to the substrate 10. It may be connected via the upper surface metal layer 10c of the above. Further, the thickness of the upper surface metal layer 10b and the upper surface metal layer 10c may be set to the same thickness as the bus bar to facilitate the flow of current through the semiconductor device 1.
  • the first semiconductor element 20 and the second semiconductor element 30 each have a first input terminal 21 or a second input terminal 31 (hereinafter referred to as an input terminal) formed on the lower surface thereof, and the upper surface thereof is formed.
  • the first output terminal 22 or the second output terminal 32 (hereinafter, the output terminal) is formed in the above, but the present invention is not limited to this.
  • the first semiconductor element 20 or the second semiconductor element 30 may have an input terminal formed on the upper surface and an output terminal formed on the lower surface, or an input terminal and an output terminal may be formed on the upper surface, or the lower surface. An input terminal and an output terminal may be formed on the surface.
  • the first bus bar 50 has rising portions 51 and 52
  • the second bus bar 60 has rising portions 61
  • the first bus bar 50 and the second bus bar 60 are flat plates without steps, and may be connected to other components via a bonding wire or the like. Further, the flat plate-shaped portion of the first bus bar 50 or the second bus bar 60 may be directly connected to the first semiconductor element 20 or the second semiconductor element 30 in contact with each other. Further, by making a difference in the heights of the mounting positions of the first semiconductor element 20 and the second semiconductor element 30, a structure in which the bus bars are laminated may be formed.
  • the semiconductor device 1 has a half-bridge type circuit configuration, and the first semiconductor element 20 and the second semiconductor element 30 are transistors, but the present invention is not limited to this.
  • the first semiconductor element 20 and the second semiconductor element 30 may be any semiconductor element having an input terminal and an output terminal, for example, a diode or the like, and even if the semiconductor device 1 is a semiconductor device used for rectification. Good.
  • each bus bar and the first connection terminal 41, the second connection terminal 42, and the third connection terminal 43 are formed separately, but the present invention is not limited to this.
  • the third bus bar 70 and the second connection terminal 42, the fourth bus bar 80 and the third connection terminal 43, or the second bus bar 60 and the first connection terminal 41 may be integrally formed.
  • the first bus bar 50 and the fourth bus bar 80 may be integrally formed.
  • the semiconductor device according to the present disclosure can be used as a semiconductor device for various purposes such as a drive control device for industrial equipment, a drive control device for home appliances equipped with a motor, an electric vehicle, or an in-vehicle control device for a hybrid vehicle. ..

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Inverter Devices (AREA)

Abstract

L'invention concerne un dispositif à semi-conducteur comprenant : un substrat ; un premier circuit disposé dans une première région du substrat et comprenant un premier élément semi-conducteur ayant une première borne d'entrée pour entrer un courant et une première borne de sortie pour délivrer un courant ; un second circuit disposé dans une seconde région du substrat et comprenant un second élément semi-conducteur ayant une seconde borne d'entrée pour entrer un courant et une seconde borne de sortie pour délivrer un courant ; une première borne de connexion pour une connexion externe ; une première barre omnibus qui comprend une partie en forme de plaque disposée sur le substrat de façon à s'opposer à une surface supérieure du substrat, et qui relie la première borne de sortie et la seconde borne d'entrée ; et une seconde barre omnibus qui comprend une partie en forme de plaque disposée sur le substrat de façon à s'opposer à la surface supérieure du substrat, et qui relie la seconde borne de sortie et la première borne de connexion.
PCT/JP2020/024940 2019-07-24 2020-06-25 Dispositif à semi-conducteur WO2021014875A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019-136127 2019-07-24
JP2019136127A JP2022130754A (ja) 2019-07-24 2019-07-24 半導体装置

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WO2021014875A1 true WO2021014875A1 (fr) 2021-01-28

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JP (1) JP2022130754A (fr)
WO (1) WO2021014875A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004214452A (ja) * 2003-01-06 2004-07-29 Fuji Electric Device Technology Co Ltd 電力用半導体モジュールおよび外部電極との結線方法
JP2015035627A (ja) * 2009-05-14 2015-02-19 ローム株式会社 半導体装置
JP2016103887A (ja) * 2014-11-27 2016-06-02 日立オートモティブシステムズ株式会社 パワー半導体モジュール
JP2019067950A (ja) * 2017-10-02 2019-04-25 トヨタ自動車株式会社 半導体装置の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004214452A (ja) * 2003-01-06 2004-07-29 Fuji Electric Device Technology Co Ltd 電力用半導体モジュールおよび外部電極との結線方法
JP2015035627A (ja) * 2009-05-14 2015-02-19 ローム株式会社 半導体装置
JP2016103887A (ja) * 2014-11-27 2016-06-02 日立オートモティブシステムズ株式会社 パワー半導体モジュール
JP2019067950A (ja) * 2017-10-02 2019-04-25 トヨタ自動車株式会社 半導体装置の製造方法

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