WO2021014875A1 - Dispositif à semi-conducteur - Google Patents

Dispositif à semi-conducteur Download PDF

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Publication number
WO2021014875A1
WO2021014875A1 PCT/JP2020/024940 JP2020024940W WO2021014875A1 WO 2021014875 A1 WO2021014875 A1 WO 2021014875A1 JP 2020024940 W JP2020024940 W JP 2020024940W WO 2021014875 A1 WO2021014875 A1 WO 2021014875A1
Authority
WO
WIPO (PCT)
Prior art keywords
bus bar
region
semiconductor
substrate
semiconductor element
Prior art date
Application number
PCT/JP2020/024940
Other languages
English (en)
Japanese (ja)
Inventor
潤一 木村
惇 松本
Original Assignee
パナソニックＩｐマネジメント株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パナソニックＩｐマネジメント株式会社 filed Critical パナソニックＩｐマネジメント株式会社
Publication of WO2021014875A1 publication Critical patent/WO2021014875A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Inverter Devices (AREA)

Abstract

L'invention concerne un dispositif à semi-conducteur comprenant : un substrat ; un premier circuit disposé dans une première région du substrat et comprenant un premier élément semi-conducteur ayant une première borne d'entrée pour entrer un courant et une première borne de sortie pour délivrer un courant ; un second circuit disposé dans une seconde région du substrat et comprenant un second élément semi-conducteur ayant une seconde borne d'entrée pour entrer un courant et une seconde borne de sortie pour délivrer un courant ; une première borne de connexion pour une connexion externe ; une première barre omnibus qui comprend une partie en forme de plaque disposée sur le substrat de façon à s'opposer à une surface supérieure du substrat, et qui relie la première borne de sortie et la seconde borne d'entrée ; et une seconde barre omnibus qui comprend une partie en forme de plaque disposée sur le substrat de façon à s'opposer à la surface supérieure du substrat, et qui relie la seconde borne de sortie et la première borne de connexion.
PCT/JP2020/024940 2019-07-24 2020-06-25 Dispositif à semi-conducteur WO2021014875A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019136127A JP2022130754A (ja) 2019-07-24 2019-07-24 半導体装置
JP2019-136127 2019-07-24

Publications (1)

Publication Number Publication Date
WO2021014875A1 true WO2021014875A1 (fr) 2021-01-28

Family

ID=74193440

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2020/024940 WO2021014875A1 (fr) 2019-07-24 2020-06-25 Dispositif à semi-conducteur

Country Status (2)

Country Link
JP (1) JP2022130754A (fr)
WO (1) WO2021014875A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004214452A (ja) * 2003-01-06 2004-07-29 Fuji Electric Device Technology Co Ltd 電力用半導体モジュールおよび外部電極との結線方法
JP2015035627A (ja) * 2009-05-14 2015-02-19 ローム株式会社 半導体装置
JP2016103887A (ja) * 2014-11-27 2016-06-02 日立オートモティブシステムズ株式会社 パワー半導体モジュール
JP2019067950A (ja) * 2017-10-02 2019-04-25 トヨタ自動車株式会社 半導体装置の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004214452A (ja) * 2003-01-06 2004-07-29 Fuji Electric Device Technology Co Ltd 電力用半導体モジュールおよび外部電極との結線方法
JP2015035627A (ja) * 2009-05-14 2015-02-19 ローム株式会社 半導体装置
JP2016103887A (ja) * 2014-11-27 2016-06-02 日立オートモティブシステムズ株式会社 パワー半導体モジュール
JP2019067950A (ja) * 2017-10-02 2019-04-25 トヨタ自動車株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
JP2022130754A (ja) 2022-09-07

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