WO2021012179A1 - 存储系统中实现存储业务连续性的方法、前端接口卡和存储系统 - Google Patents

存储系统中实现存储业务连续性的方法、前端接口卡和存储系统 Download PDF

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Publication number
WO2021012179A1
WO2021012179A1 PCT/CN2019/097260 CN2019097260W WO2021012179A1 WO 2021012179 A1 WO2021012179 A1 WO 2021012179A1 CN 2019097260 W CN2019097260 W CN 2019097260W WO 2021012179 A1 WO2021012179 A1 WO 2021012179A1
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WIPO (PCT)
Prior art keywords
storage controller
host
storage
interface card
end interface
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PCT/CN2019/097260
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English (en)
French (fr)
Inventor
徐启明
陈灿
杨松
周丽南
晏大洪
杨俊涛
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN201980098752.7A priority Critical patent/CN114174999A/zh
Priority to EP19938398.5A priority patent/EP3995965A4/en
Priority to PCT/CN2019/097260 priority patent/WO2021012179A1/zh
Publication of WO2021012179A1 publication Critical patent/WO2021012179A1/zh
Priority to US17/580,940 priority patent/US11860719B2/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0766—Error or fault reporting or storing
    • G06F11/0784—Routing of error reports, e.g. with a specific transmission path or data flow
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2002—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant
    • G06F11/2005—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant using redundant communication controllers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0727—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a storage system, e.g. in a DASD or network based storage system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2053—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where persistent mass storage functionality or persistent mass storage control functionality is redundant
    • G06F11/2089—Redundant storage control functionality
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Definitions

  • the present invention relates to the field of information technology, and more specifically, to a method for realizing storage business continuity in a storage system.
  • the storage system includes storage controller A and storage controller B.
  • Storage controller A includes two front-end ports, namely port CA1 and port CA2; storage controller B includes two front-end ports, port CB1 and port CB2, respectively.
  • Port CA1 is connected to port A2 of switch A, port CA2 is connected to port B2 of switch B; port CB1 is connected to port A3 of switch A, and port CB2 is connected to port B3 of switch B.
  • Switch A is connected to the host bus adapter (Host Bus Adapter, HBA) H1 through port A1, and switch B is connected to HBA H2 of the host through port B1.
  • HBA host bus adapter
  • Storage controller A changes to an abnormal state, for example, storage controller A fails or storage controller A is not available due to upgrade, or storage controller does not respond due to software reasons. Since the storage controller A becomes an abnormal state, the storage controller B needs to take over the storage controller A to process the access request from the host. In the prior art, the storage controller A fails, and the link between the port CA1 and the host H1 is disconnected. Switch A detects that port CA1 is disconnected and notifies H1 of the host of the link disconnection event. After receiving the notification, the host H1 suspends issuing an access request to the storage controller A, and starts timing.
  • the storage system When the storage system detects that storage controller A is in an abnormal state, it uses the world wide port name (WWPN) of port CA1 to register with switch A on port CB1 of storage controller B. After the switch receives the registration, it considers it CA1 returns to the normal state and notifies H1 of the host that the link is restored. After receiving the notification, the host's H1 continues to send access requests.
  • WWPN world wide port name
  • the host access request will be interrupted in the storage system during the process of switching the storage controller, which affects business continuity.
  • the present invention provides a method for realizing storage business continuity in a storage system, which can ensure that when a storage controller in the storage system changes from a normal state to an abnormal state, no host access request occurs during the storage system system switching storage controller. Interruption, thereby improving business continuity.
  • a method for realizing storage business continuity in a storage system includes a front-end interface card and a plurality of storage controllers.
  • the front-end interface card communicates with the plurality of storage controllers.
  • the front-end interface card communicates with the host; in the method, the front-end interface card detects the state of the first storage controller; wherein, the first storage controller is one of the plurality of storage controllers for processing the The storage controller of the host's access request; when the state of the first storage controller is an abnormal state, the front-end interface card allows the host to select a second storage controller from the plurality of storage controllers to process The access request of the host; the second storage controller is that the plurality of storage controllers are storage controllers different from the first storage controller.
  • the multiple storage controllers share a front-end interface card.
  • the host When a storage controller changes from a normal state to an abnormal state, the host does not perceive the storage control of the storage system when the storage system switches the storage controller. The host does not need to stop sending access requests to the storage system, thereby improving business continuity.
  • the embodiment of the present invention also avoids the problem of failure to switch the storage controller due to the inability to establish a link with the storage controller due to host software compatibility.
  • the front-end interface card when the state of the first storage controller is an abnormal state, the front-end interface card sends an access request error message to the host; the access request error message is used to report the Error status of the access request; the front-end interface card receives the access request resent by the host in response to the access request error information.
  • the front-end interface card obtains the processing result of the access request of the host from the second storage controller, and selects the unfinished first storage controller from the processing result of the access request of the host The result of the processed access request of the host.
  • the front-end interface card processes the host's access request based on the first storage controller that handles the abnormal state, and the second storage controller after the switch continues to process the unprocessed access requests of the first storage controller to ensure Continuity of business.
  • the front-end interface card transfers the storage controller that processes the service request of the host to the second storage controller.
  • the controller is switched to the first storage controller.
  • the front-end interface card is connected to the host through Ethernet.
  • the front-end interface card and the host are connected through a fiber channel.
  • the front-end interface card and the multiple storage controllers are connected via a peripheral component rapid interconnection bus.
  • the front-end interface card selects a second storage controller from the plurality of storage controllers for the host to process the access request of the host, which specifically includes: the front-end interface card according to The performance of the plurality of storage controllers selects the second storage controller.
  • the first storage controller mirrors the data in the cache of the first storage controller to at least one of the plurality of storage controllers except the first storage controller.
  • the second storage controller is one of the at least one storage controller. This solution can ensure that the second storage controller can quickly take over the work of the first storage controller.
  • the front-end interface card sends the access request sent by the host to the first storage controller to one of the plurality of storage controllers other than the first storage controller. At least one storage controller, and the second storage controller is one of the at least one storage controller. This solution can ensure that the second storage controller can quickly take over the work of the first storage controller.
  • a front-end interface card in a storage system includes the front-end interface card and a plurality of storage controllers, the front-end interface card includes a first interface and a second interface; the first The interface is used to communicate with the host, the second interface is used to communicate with the multiple storage controllers; the front-end interface card also includes the first aspect or any one of the possible implementations of the first aspect Method of the module.
  • a front-end interface card in a storage system includes the front-end interface card and a plurality of storage controllers, the front-end interface card includes a first interface and a second interface; the first The interface is used to communicate with the host, the second interface is used to communicate with the multiple storage controllers; the front-end interface card further includes a processor, the processor is used to communicate with the first interface and the second For interface communication, the processor is further configured to execute the first aspect or the method in any possible implementation manner of the first aspect.
  • a chip in a fourth aspect, includes a first interface and a second interface; the first interface is used to communicate with a host, and the second interface is used to communicate with multiple storage controllers of a storage system
  • the chip also includes a processor, the processor is used to communicate with the first interface and the second interface, the processor is also used to execute the first aspect or any possible implementation of the first aspect Method in.
  • a storage system in a fifth aspect, includes a front-end interface card and a plurality of storage controllers.
  • the front-end interface card is used to communicate with the plurality of storage controllers and a host;
  • the front-end interface card is also used to execute the first aspect or the method in any possible implementation of the first aspect.
  • a computer-readable storage medium stores instructions, and when a processor runs the instructions, they are used to execute the first aspect or any possible implementation of the first aspect The method in the way.
  • a computer program product containing instructions is provided.
  • the processor runs the instructions in the computer program product, the processor is used to execute the first aspect or the method in any possible implementation manner of the first aspect.
  • Figure 1 is a schematic diagram of the prior art storage system and host architecture
  • FIG. 2 is a schematic diagram of the architecture of a storage system and a host according to an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of a storage controller according to an embodiment of the present invention.
  • Figure 4 is a schematic structural diagram of a front-end interface card according to an embodiment of the present invention.
  • Figure 5 is a schematic diagram of the communication between the host and the storage system
  • FIG. 6 is a schematic flowchart of implementing storage service continuity according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a process of processing an access request sent by a host during a storage controller switching process according to an embodiment of the present invention
  • Figure 8 is a schematic structural diagram of a front-end interface card provided by an embodiment of the present invention.
  • the storage system in the embodiment of the present invention may be a storage array (such as of series, Series etc.).
  • the storage system includes front-end interface cards, storage controller A, storage controller B, and hard disk enclosures.
  • the front-end interface card is respectively connected to the interface CA1 of the storage controller A and the interface CB1 of the storage controller B.
  • PCIE Peripheral Component Interconnect Express
  • the storage controller A The interface CA1, the interface CB1 of the storage controller B, and the interfaces between the front-end interface card and the storage controller A and the storage controller B are PCIe interfaces.
  • the storage controller A and the storage controller B are respectively connected to a hard disk enclosure.
  • the hard disk enclosure contains multiple hard disks.
  • the hard disks include solid state disks (Solid State Disk, SSD) and/or mechanical hard disks.
  • the connection between storage controller A and storage controller B and the hard disk enclosures can use PCIe bus connection, or use Fibre Channel (FC) or Ethernet connection or unlimited bandwidth (Infiniband, IB) connection, or use string Line Small Computer Protocol (Serial Attached SCSI, SAS) cable connection.
  • the Ethernet connection can be the use of remote direct memory access (RDMA over Converged Ethernet, RoCE) based on converged Ethernet.
  • the storage controller A and the storage controller B can use the SAS protocol, the non-volatile memory standard (Non-volatile Memory Express, NVMe) protocol, or the private protocol based on the above connection mode.
  • NVMe non-volatile Memory Express
  • the front-end interface card can be connected to the HBA of the host through switch A and switch B, and the front-end interface card can also be directly connected to the HBA of the host.
  • the communication interface between the front-end interface card and the host can be an FC interface or an Ethernet interface, or an IB interface.
  • the front-end interface card is a shared interface card, that is, multiple storage controllers are connected to the front-end interface card and communicate with the host through the front-end interface card.
  • FIG. 3 The structure of the storage controller in the embodiment of the present invention is shown in FIG. 3, which includes a central processing unit (CPU) 301, a memory 302, and an interface 303.
  • the memory 202 can be used to cache data and access instructions of the storage controller .
  • the memory 202 is also used to store the driver of the front-end interface card.
  • the interface 303 is used to communicate with the front-end interface card, and the interface 303 may be a port supporting the PCIe protocol.
  • the storage controller also includes an interface for communicating with the hard disk enclosure, which can be a PCIe interface, FC interface, Ethernet interface, or IB interface.
  • the structure of the front-end interface card is shown in FIG. 4, which includes a processor 401, a first interface 402, and a second interface 403.
  • the first interface 402 may be an FC interface, an Ethernet interface or an IB interface, and the first interface 402 is used to communicate with the HBA of the host.
  • the second interface 402 may be a PCIe interface for communicating with the storage controller A and the storage controller B.
  • the processor 401 may be a Field Programmable Gate Array (FPGA), or an application-specific integrated circuit (ASIC), or a Central Processing Unit (CPU), or other hardware Or, FPGA or other hardware and CPU together as a processor.
  • the processor 401 is used to implement various functions of the front-end interface card in the embodiment of the present invention.
  • first interface 402 and second interface 403 there may be one or more first interface 402 and second interface 403 respectively.
  • one first interface 402 communicates with one HBA.
  • multiple HBAs or switches may also multiplex one first interface 402, that is, multiple HBAs communicate with one first interface 402.
  • the embodiment of the present invention does not limit this.
  • the driver of the front-end interface card in the embodiment of the present invention runs in the storage controller shown in FIG. 3.
  • the front-end interface card in the embodiment of the present invention serves as the network interface card of the storage controller to communicate with the host.
  • the second interface 403 can directly communicate with the storage controller and connect to the switching device.
  • the second interface 403 is a PCIe interface, and the second interface 403 communicates with the storage controller without using a PCIe switching device.
  • the front-end interface card does not require a dynamic random access memory and does not need to cache access request-level data, that is, there is no need to cache the data carried by the write request or the data requested by the read request.
  • the embodiment of the present invention as shown in FIG. 5, to realize the communication between the host and the storage system, includes the following steps:
  • Step 501 The front-end interface card establishes a physical link with the HBA of the host.
  • the establishment of a physical link between the front-end interface card and the HBA of the host includes operations such as rate coordination and link initialization.
  • Step 502 The HBA of the host sends a connection establishment request to the front-end interface card.
  • the HBA of the host After the HBA of the host establishes a physical link with the front-end interface card, the HBA of the host sends a connection establishment request to the front-end interface card, and the request is used to communicate with the storage system.
  • Step 503 The front-end interface card selects a storage controller from multiple storage controllers as the main storage controller for the host.
  • the front-end interface card selects a storage controller from multiple storage controllers as the main storage controller, which is used to manage the connection established between the storage system and the host, and synchronize the connection to other storage controllers of the storage system.
  • the storage controller A is selected as the main storage controller.
  • the storage controller of the storage system establishes a connection with the host HBA, that is, establishes a session. In this case, the storage controller directly talks to the host HBA.
  • the front-end interface card establishes a connection with the host HBA, that is, a session is established.
  • the front-end interface card establishes a virtual connection with each storage controller, that is, the front-end interface card establishes a connection with the host HBA on behalf of the storage controller.
  • the front-end interface card receives the session notification sent by the host's HBA, and the front-end interface card notifies the storage controller in the storage system that the storage system has established a connection with the host, that is, the front-end interface card establishes a connection with the host on behalf of the storage system.
  • the front-end interface card receives the access request sent by the host, determines the storage controller that processes the access request according to the address information carried in the access request, and sends the access request to the corresponding storage controller for processing.
  • the embodiment is the storage controller A.
  • the access request can be a read request, a write request, or a management request.
  • the management request in the embodiment of the present invention is used by the host to send a management command to the storage system.
  • the front-end interface card distributes the access request to the storage system at the granularity of the access request.
  • the front-end interface card distributing access requests to the storage system at the granularity of the access request means that the front-end interface card selects the corresponding storage controller for the access request sent by the host.
  • the storage controller that processes the access request can be determined according to the address request carried in the access request.
  • the corresponding storage controller that processes the access request is also called the home storage controller, so that the front-end interface card can directly send the access request to the corresponding storage controller, without the need to forward the access request between storage controllers, thereby increasing the access request
  • the processing efficiency is reduced, and the processing delay of access request is reduced.
  • the front-end interface card stores the correspondence between the address information of the access request and the storage controller.
  • the front-end interface card can send the access request issued by the host to different storage controllers for parallel processing, thereby improving the processing efficiency of the access request and reducing the processing delay of the access request.
  • the front-end interface card distributes access requests to the storage system at the granularity of links.
  • the front-end interface card distributes access requests to the storage system at the granularity of links. This means that the front-end interface card processes all the access requests of the same link from the host by the same storage controller. That is, every time a link is established, the front-end interface card designates a storage controller to handle all access requests from the link.
  • the front-end interface card performs the following operations:
  • Step 601 The front-end interface card detects the state of the storage controller.
  • the front-end interface card detects whether the storage controller is in a normal state. During the operation of the storage controller, due to various reasons, it changes from a normal state to an abnormal state. For example, the storage controller becomes offline due to a failure, power failure, upgrade, etc., or there is no response due to the storage controller software.
  • Step 602 The front-end interface card detects that the state of the storage controller is an abnormal state, and the front-end interface card selects a new storage controller from multiple storage controllers for the host.
  • the front-end interface card selects a new storage controller from a plurality of storage controllers for the host to process the access request of the host.
  • multiple storage controllers share a front-end interface card.
  • the host When a storage controller changes from a normal state to an abnormal state, the host does not perceive the storage controller of the storage system when the storage system switches the storage controller. Switch. Therefore, the host does not need to stop sending access requests to the storage system, thereby improving business continuity.
  • the embodiment of the present invention also avoids the problem of failure to switch the storage controller due to the inability to establish a link with the storage controller due to host software compatibility.
  • the front-end interface card maintains a storage controller state table for recording the state of the storage controller in the storage system. Further, the front-end interface card can also maintain a storage controller switching table, which is used to record the backup storage controller of the current storage controller if the current storage controller becomes abnormal.
  • the backup storage controller can replace the storage controller of the current storage controller.
  • the front-end interface card may determine the backup storage controller for the current storage controller according to the performance and load of each storage controller, or set the backup storage controller and record the backup relationship in the storage controller switching table.
  • the front-end interface card can select a new storage controller, that is, a backup storage controller, according to the storage controller switching table.
  • the embodiment of the present invention provides multiple implementation manners for processing the access request sent by the host during the switching process of the storage controller.
  • the embodiment of the present invention describes various implementation manners with reference to FIG. 2.
  • One of the implementation methods, as shown in Figure 7, includes:
  • Step 701 The host sends an access request.
  • the access request can be a read request, a write request, or a management request.
  • the embodiment of the present invention takes a read request as an example for description.
  • Step 702 The host starts a timer to determine whether to wait for a timeout.
  • the host starts a timer to determine whether the storage system returns a response within a predetermined time.
  • Step 703 The front-end interface card records the access request information.
  • the access request information includes one or more of the type of the access request, the source address for sending the access request, and the destination address of the access request.
  • Step 704 The front-end interface card sends the access request to the storage controller A.
  • Step 705 The storage controller A reads the data from the cache or the hard disk, and sends the description information of the data to the front-end interface card.
  • the cache may be located in the memory 302 shown in FIG. 3.
  • the hard disk refers to the hard disk shown in Figure 2.
  • the description information of the data includes the address of the data in the cache and the data length.
  • Step 706 The front-end interface card acquires the data by direct memory access (DMA) according to the description information of the data and sends the data to the host.
  • DMA direct memory access
  • Step 707 The front-end interface card detects that the storage controller A has changed to an abnormal state, and selects the storage controller B instead of the storage controller A.
  • the front-end interface card detects that storage controller A has changed to an abnormal state, and selects storage controller B instead of storage controller A, that is, switches to storage controller B.
  • Step 708 The front-end interface card sends an access request error message to the host according to the recorded access request information.
  • the access request error message is used to report the error status of the access request.
  • the access request error message is a read request error message.
  • Step 709 In response to the access request error message, the host resends the access request.
  • Step 710 The front-end interface card receives the access request sent by the host and sends the access request to the storage controller B.
  • Step 711 The storage controller B reads data from the cache or the hard disk according to the access request, and sends the description information of the data to the front-end interface card.
  • Step 712 The front-end interface card acquires the data by DMA and sends the data to the host according to the description information of the data.
  • Step 713 The front-end interface card sends the access request normal completion response to the host.
  • the front-end interface card does not require a dynamic random access memory and does not need to cache access request-level data, that is, there is no need to cache the data carried by the write request or the data requested by the read request.
  • storage controller A receives the access request sent by the front-end interface card, but has not yet performed step 705, that is, storage controller A has not processed the access request, or has read data from the cache or hard disk, but has not yet sent The description of the data sent by the front-end interface card. At this time, the storage controller A fails.
  • the difference from step 712 is that when the front-end interface card has not finished obtaining the result of the host's access request processed by the storage controller A, the front-end interface card obtains the processing result of the host's access request from the storage controller B.
  • the result of the host's access request processed by the storage controller A that has not been acquired is selected from the processing result of the host's access request acquired by the storage controller B.
  • the front-end interface card sends the unfinished result of the host's access request processed by the storage controller A to the host.
  • the front-end interface card Because storage controller A becomes abnormal, the front-end interface card has not finished obtaining the result of the host's access request processed by storage controller A, such as reading data.
  • the front-end interface card only obtains part of the read data and sends this part to the host. Read the data. Therefore, in this implementation, combining steps 701 to 711, the front-end interface card obtains data in DMA mode according to the description information of the data, and the front-end interface card obtains data from the storage controller according to the data of the partial read request that has been sent to the host. Select the processing result of the access request of the unfinished host from the acquired processing result of the host's access, and complete the processing result of the uncompleted access request to the host.
  • the front-end interface card After the front-end interface card completes the requested data that has not been sent to the host, it sends the access request to the host and responds normally. For example, the data requested by the host is 000011110001, and the front-end interface card obtains 000011 from storage controller A and sends 000011 to the host. The front-end interface card obtains the host read request data 000011110001 from the storage controller B. Since the front-end interface card has sent 000011 to the host, the front-end interface card only needs the host read request data 000011110001 from the storage controller B to select 110001. The host sends 110001.
  • the front-end interface card detects the state of the storage controller, and when it is detected that the storage controller A returns from the abnormal state to the normal state, the storage controller B can be switched to the storage controller A.
  • FIG. 8 Another embodiment of the present invention provides a front-end interface card of a storage system, as shown in FIG. 8, including a first interface 801, a second interface 802, a detection unit 803, and a selection unit 804.
  • the first interface 801 is used to communicate with the host
  • the second interface 802 is used to communicate with multiple storage controllers of the storage system
  • the detection unit 803 is used to detect the state of the first storage controller
  • the first storage controller It is the storage controller used to process the access request of the host among the multiple storage controllers
  • the selecting unit 804 is used to select the second storage controller from the multiple storage controllers for the host when the state of the first storage controller is abnormal.
  • the storage controller processes the access request of the host; the second storage controller is a plurality of storage controllers different from the first storage controller.
  • the selection unit 804 is configured to select the second storage controller according to the performance of the multiple storage controllers.
  • the front-end interface card further includes a sending unit and a receiving unit, wherein the sending unit is used to send access request error information to the host when the state of the first storage controller is abnormal; the access request error message is used to report the access request The receiving unit is used to receive the access request resent by the host in response to the access request error information.
  • the front-end interface card shown in FIG. 8 it further includes an obtaining unit, which is used to, when the state of the first storage controller is an abnormal state and the front-end interface card has not completed obtaining the result of the host's access request processed by the first storage controller,
  • the processing result of the host's access request is obtained from the second storage controller;
  • the selection unit 804 is further configured to select the unfinished result of the host's access request processed by the first storage controller from the processing result of the host's access request.
  • a switching unit which is used to switch the storage controller that processes the service request of the host from the second storage controller when the state of the first storage controller changes from the abnormal state to the normal state. Switch to the first storage controller
  • the first interface 801 is an Ethernet interface or an FC interface.
  • the second interface 802 is a PCIe interface.
  • the specific implementation can refer to the implementation of the front-end interface card described in the embodiment of the present invention, which is not repeated here.
  • the present invention provides a chip, which includes a first interface and a second interface; the first interface is used to communicate with a host, and the second interface is used to communicate with multiple storage controllers of a storage system; the chip also includes a processor,
  • the processor is used to implement various implementations of the front-end interface card in the embodiment of the present invention.
  • the processor can be a Field Programmable Gate Array (FPGA), or an application-specific integrated circuit (ASIC), or a central processing unit (Central Processing Unit, CPU), or other hardware, or, FPGA or other hardware functions as a processor together with the CPU.
  • FPGA Field Programmable Gate Array
  • ASIC application-specific integrated circuit
  • CPU central processing unit
  • FPGA central processing unit
  • one of the implementations, the first interface, the second interface, and the processor may be presented in the form of an intellectual property core (intellectual property core), corresponding to different intellectual property cores.
  • the present invention provides a computer-readable storage medium in which instructions are stored. When the instructions are executed by a processor, they are used to perform various functions of the front-end interface card in the embodiments of the present invention.
  • the present invention provides a computer program product containing instructions.
  • a processor executes the instructions in the computer program product, it is used to perform various functions of the front-end interface card in the embodiments of the present invention.
  • the host provided by the embodiment of the present invention may be a physical host or a virtual machine (Virtual Machine, VM).
  • the front-end interface card provided by the embodiment of the present invention can directly communicate with the HBA of the host, or can communicate with the HBA of the host through a switch, which is not limited in the embodiment of the present invention.
  • the memory mentioned in the embodiments of the present invention may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory can be read-only memory (Read-Only Memory, ROM), programmable read-only memory (Programmable ROM, PROM), erasable programmable read-only memory (Erasable PROM, EPROM), and electrically available Erase programmable read-only memory (Electrically EPROM, EEPROM) or flash memory.
  • the volatile memory may be a random access memory (Random Access Memory, RAM), which is used as an external cache.
  • RAM random access memory
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • DRAM synchronous dynamic random access memory
  • DDR SDRAM double data rate synchronous dynamic random access memory
  • Enhanced SDRAM, ESDRAM enhanced synchronous dynamic random access memory
  • Synchlink DRAM, SLDRAM synchronous connection dynamic random access memory
  • DR RAM Direct Rambus RAM
  • the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component
  • the memory storage module
  • the disclosed system, device, and method may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or It can be integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • the functional units in the various embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium.
  • the technical solution of the present invention essentially or the part that contributes to the existing technology or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in each embodiment of the present invention.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk and other media that can store program code .

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Abstract

提供了一种存储系统中实现存储业务连续性的方法，所述存储系统包括前端接口卡和多个存储控制器，所述前端接口卡与所述多个存储控制器通信，所述前端接口卡与主机通信；在所述方法中，所述前端接口卡检测第一存储控制器状态；当所述第一存储控制器的状态为异常状态时，所述前端接口卡为所述主机从所述多个存储控制器中选择第二存储控制器处理所述主机的访问请求。

Description

存储系统中实现存储业务连续性的方法、前端接口卡和存储系统 技术领域
本发明涉及信息技术领域，并且更具体地，涉及存储系统中实现存储业务连续性的方法。
背景技术
如图1所示，存储系统包含存储控制器A和存储控制器B。存储控制器A包含两个前端端口，分别为端口CA1和端口CA2；存储控制器B包含两端前端端口，分别为端口CB1和端口CB2。端口CA1与交换机A的端口A2连接，端口CA2与交换机B的端口B2连接；端口CB1与交换机A的端口A3连接，端口CB2与交换机B的端口B3连接。交换机A通过端口A1与主机的主机总线适配器(Host Bus Adapter,HBA)H1连接，交换机B通过端口B1与主机的HBA H2连接。主机通过上述连接与存储系统通信。
存储控制器A变为异常状态，例于存储控制器A发生故障或存储控制器A进行升级等原因不可用或者由于存储控制器因软件原因没有响应。由于存储控制器A变为异常状态，需要由存储控制器B接替存储控制器A处理来自主机的访问请求。现有技术中，存储控制器A发生故障，端口CA1与主机的H1之间的链路断开。交换机A检测到端口CA1断开，向主机的H1通知链路断开事件。主机的H1收到该通知后，暂停向存储控制器A下发访问请求，并且启动定时。存储系统在检测到存储控制器A处于异常状态，使用端口CA1的全球唯一端口名字(World Wide Port Name,WWPN)在存储控制器B的端口CB1向交换机A注册，交换机收到该注册后，认为CA1恢复到正常状态，向主机的H1通知该链路恢复。主机的H1收到该通知后，继续发送访问请求。
现有技术存储控制器从正常状态变为异常状态后，存储系统在切换存储控制器过程中，会发生主机访问请求中断，影响业务连续性。
发明内容
本发明提供一种存储系统中实现存储业务连续性的方法，能够保证存储系统中的一个存储控制器从正常状态变为异常状态时，存储系系统切换存储控制器过程中，不发生主机访问请求中断，从而提高了业务连续性。
第一方面，提供了一种存储系统中实现存储业务连续性的方法，所述存储系统包括前端接口卡和多个存储控制器，所述前端接口卡与所述多个存储控制器通信，所述前端接口卡与主机通信；在所述方法中，所述前端接口卡检测第一存储控制器状态；其中，所述第一存储控制器为所述多个存储控制器中用于处理所述主机的访问请求的存储控制器；当所述第一存储控制器的状态为异常状态时，所述前端接口卡为所述主机从所述多个存储控制器中选择第二存储控制器处理所述主机的访问请求；所述第二存储控制器为所述多个存储控制器为不同于所述第一存储控制器的存储控制器。在本方案中，所述多个存储控制器共 享一个前端接口卡，在其中某个存储控制器从正常状态变为异常状态时，存储系统切换存储控制器时，主机不感知存储系统的存储控制器切换，主机不需要停止向存储系统发送访问请求，从而提高了业务连续性。本发明实施例也避免由于主机软件兼容性导致与存储控制器无法建立链接导致存储控制器切换失败的问题。
作为一种可选的实现方式，当所述第一存储控制器的状态为异常状态时，所述前端接口卡向所述主机发送访问请求错误信息；所述访问请求错误消息用于上报所述访问请求的错误状态；所述前端接口卡接收所述主机响应所述访问请求错误信息重新发送的访问请求。本方案可以保证在存储控制器发生切换，保证业务处理的准确性。
作为一种可选的实现方式，当所述第一存储控制器的状态为异常状态并且所述前端接口卡未获取完所述第一存储控制器处理的所述主机的访问请求的结果时，所述前端接口卡从所述第二存储控制器获取所述主机的访问请求的处理结果，并从所述主机的访问请求的处理结果中选择所述未获取完的所述第一存储控制器处理的所述主机的访问请求的结果。本方案中，前端接口卡基于处理异常状态的第一存储控制器处理主机的访问请求的情况，由切换后的第二存储控制器继续处理第一存储控制器未处理完的访问请求，从而保证业务的连续性。
作为一种可选的实现方式，当所述第一存储控制器的状态从异常状态变为正常状态，所述前端接口卡将处理所述主机的业务请求的存储控制器由所述第二存储控制器切换为所述第一存储控制器。
作为一种可选的实现方式，所述前端接口卡与所述主机通过以太网连接。
作为一种可选的实现方式，所述前端接口卡与所述主机通过以光纤通道连接。
作为一种可选的实现方式，所述前端接口卡与所述多个存储控制器通过外围组件快速互连总线连接。
作为一种可选的实现方式，所述前端接口卡为所述主机从所述多个存储控制器中选择第二存储控制器处理所述主机的访问请求，具体包括：所述前端接口卡根据所述多个存储控制器的性能选择所述第二存储控制器。本方案可以保证存储控制器切换后的存储性能。
作为一种可选的实现方式，所述第一存储控制器将所述第一存储控制器的缓存中的数据镜像到所述多个存储控制器中除所述第一存储控制器以外的至少一个存储控制器上，所述第二存储控制器是所述至少一个存储控制器中的一个。本方案可以保证所述第二存储控制器可以快速接管所述第一存储控制器的工作。
作为一种可选的实现方式，所述前端接口卡将所述主机发送给所述第一存储控制器的访问请求发送给所述多个存储控制器中除所述第一存储控制器以外的至少一个存储控制器，所述第二存储控制器是所述至少一个存储控制器中的一个。本方案可以保证所述第二存储控制器可以快速接管所述第一存储控制器的工作。
第二方面，提供一种存储系统中的前端接口卡，所述存储系统包括所述前端接口卡和多个存储控制器，所述前端接口卡包含第一接口和第二接口；所述第一接口用于与主机通信，所述第二接口用于与所述多个存储控制器通信；所述前端接口卡还包括用于执行第一方面或第一方面的任一可能的实现方式中的方法的模块。
第三方面，提供一种存储系统中的前端接口卡，所述存储系统包括所述前端接口卡和 多个存储控制器，所述前端接口卡包含第一接口和第二接口；所述第一接口用于与主机通信，所述第二接口用于与所述多个存储控制器通信；所述前端接口卡还包括处理器，所述处理器用于与所述第一接口和所述第二接口通信，所述处理器还用于执行第一方面或第一方面的任一可能的实现方式中的方法。
第四方面，提供一种芯片，所述芯片包括包含第一接口和第二接口；所述第一接口用于与主机通信，所述第二接口用于与存储系统的多个存储控制器通信；所述芯片还包括处理器，所述处理器用于与所述第一接口和所述第二接口通信，所述处理器还用于执行第一方面或第一方面的任一可能的实现方式中的方法。
第五方面，提供了一种存储系统，所述存储系统包括前端接口卡和多个存储控制器，所述前端接口卡用于与所述多个存储控制器通信以及与主机通信；其中，所述前端接口卡还用于执行第一方面或第一方面的任一可能的实现方式中的方法。
第六方面，提供一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，当处理器运行所述指令时，用于执行第一方面或第一方面的任一可能的实现方式中的方法。
第七方面，提供一种包含指令的计算机程序产品，当处理器运行所述计算机程序产品中的指令时，用于执行第一方面或第一方面的任一可能的实现方式中的方法。
附图说明
图1是现有技术存储系统与主机架构示意图；
图2是本发明实施例存储系统与主机架构示意图；
图3是本发明实施例的存储控制器的结构示意图；
图4是本发明实施例的前端接口卡的结构示意图；
图5是主机与存储系统通信示意图；
图6是本发明实施例实现存储业务连续性示意性流程图；
图7是本发明实施例提供的处理存储控制器切换过程中的主机发送的访问请求流程示意图；
图8是本发明实施例提供的前端接口卡结构示意图。
具体实施方式
下面将结合附图，对本发明实施例中的技术方案进行描述。
首先对适用于本发明实施例的存储系统进行介绍。
如图2所示，本发明实施例中的存储系统，可以为存储阵列(如
Figure PCTCN2019097260-appb-000001
的
Figure PCTCN2019097260-appb-000002
Figure PCTCN2019097260-appb-000003
系列，
Figure PCTCN2019097260-appb-000004
系列等)。存储系统包括前端接口卡、存储控制器A、存储控制器B和硬盘框。其中，前端接口卡分别与存储控制器A的接口CA1以及存储控制器B的接口CB1连接，具体可以是通过外围组件快速互连(Peripheral Component Interconnect Express,PCIE)总线连接，则存储控制器A的接口CA1、存储控制器B的接口CB1以及前端接口卡与存储控制器A和存储控制器B连接的接口为PCIe接口。存储控制器A和存储控制器B分别与硬盘框连接，硬盘框中包含多块硬盘，其中，硬盘包含固态硬 盘(Solid State Disk,SSD)和/或机械硬盘等。存储控制器A和存储控制器B分别与硬盘框之间的连接可以使用PCIe总线连接，或者使用光纤通道(Fibre Channel,FC)或者以太网连接或者无限带宽(Infiniband,IB)连接，或者使用串行小型计算机协议(Serial Attached SCSI,SAS)线缆连接。其中，以太网连接可以是使用基于融合以太网的远程直接内存访问(RDMA over Converged Ethernet,RoCE)。存储控制器A和存储控制器B基于上述连接方式可以使用SAS协议、非易失性内存标准(Non-volatile Memory Express,NVMe)协议或者私有协议等等。前端接口卡可以通过交换机A和交换机B与主机的HBA连接，前端接口卡也可以直接与主机的HBA连接。前端接口卡与主机通信的接口可以为FC接口或者以太接口，也可以为IB接口。本发明实施例中，前端接口卡为共享接口卡，即多个存储控制器连接到该前端接口卡，通过该前端接口卡与主机通信。
本发明实施例中的存储控制器的结构如图3所示，包含中央处理单元(Central Processing Unit,CPU)301、存储器302和接口303，存储器202可以用于缓存存储控制器的数据和访问指令。另外，在本发明实施例中，存储器202还用于存储前端接口卡的驱动。接口303用于和前端接口卡通信，接口303可以为支持PCIe协议的端口。存储控制器还包括用于与硬盘框通信的接口，具体可以是PCIe接口、FC接口、以太接口或IB接口等。
前端接口卡的结构如图4所示，包含处理器401、第一接口402和第二接口403。其中，第一接口402可以为FC接口、以太接口或IB接口，第一接口402用于与主机的HBA通信。第二接口402可以为PCIe接口，用于与存储控制器A和存储控制器B通信。另外，处理器401可以为现场可编程门阵列(Field Programmable Gate Array,FPGA)，或者专用集成电路(Application-specific integrated circuit,ASIC)，或者中央处理单元(Central Processing Unit,CPU)，或者其他硬件，或者，FPGA或其他硬件与CPU共同作为处理器。其中，处理器401用于实现本发明实施例中前端接口卡的各项功能。本发明实施例中第一接口402和第二接口403分别可以有一个或多个。其中，一个第一接口402与一个HBA通信。在一种实现方式中，多个HBA或交换机也可以复用一个第一接口402，即多个HBA与一个第一接口402通信。本发明实施例对此不作限定。本发明实施例中的前端接口卡的驱动程序运行在图3所示的存储控制器中。本发明实施例中的前端接口卡作为存储控制器的网络接口卡与主机通信。本发明实施例中的前端接口卡一种实现，第二接口403可以直接与存储控制器通信，交换设备连接。例如，第二接口403为PCIe接口，第二接口403与存储控制器通信不需要使用PCIe交换设备。在本发明实施例中，其中一种实现，前端接口卡不需要动态随机存储器，不需要缓存访问请求级的数据，即不需要缓存写请求携带的数据或读请求所请求的数据。
本发明实施例，如图5所示，为实现主机与存储系统的通信，包括如下步骤：
步骤501：前端接口卡与主机的HBA建立物理链路。
前端接口卡与主机的HBA建立物理链路包括进行速率协调、链路初始化等操作。
步骤502：主机的HBA向前端接口卡发送建立连接请求。
主机的HBA与前端接口卡建立物理链路后，主机的HBA向前端接口卡发送建立连接请求，该请求用于与存储系统进行通信。
步骤503：前端接口卡为主机从多个存储控制器中选择一个存储控制器作为主存储控 制器。
前端接口卡从多个存储控制器中选择一个存储控制器作为主存储控制器，用于管理存储系统与主机之间建立的连接，并将该连接同步到存储系统的其他存储控制器。结合图2所示的实施例，例如，选择存储控制器A作为主存储控制器。
一种实现方式，存储系统的存储控制器与主机HBA建立连接，即建立会话。在这种情况下，存储控制器与主机HBA直接会话。另一种实现方式，由前端接口卡与主机HBA建立连接，即建立会话，前端接口卡与每一个存储控制器建立虚拟连接，即前端接口卡代表存储控制器与主机的HBA建立连接。当前端接口卡接收到主机的HBA发送的会话通知，前端接口卡通知存储系统中的存储控制器存储系统已经与主机建立连接，即前端接口卡代表存储系统与主机建立连接。
在本发明实施例中，前端接口卡接收主机发送的访问请求，根据访问请求中携带的地址信息确定处理该访问请求的存储控制器，将访问请求发送给相应的存储控制器处理，在本发明实施例，即存储控制器A。访问请求可以是读请求、写请求或者管理请求。本发明实施例中的管理请求用于主机向存储系统发送管理命令。
本发明实施例中，一种实现方式，前端接口卡以访问请求为粒度向存储系统分发访问请求。前端接口卡以访问请求为粒度向存储系统分发访问请求是指前端接口卡为主机发送的访问请求选择相应的存储控制器。具体实现，可以根据访问请求携带的地址请求确定处理该访问请求的存储控制器。相应的处理该访问请求的存储控制器也称为归属存储控制器，这样前端接口卡可以直接将访问请求发送给相应的存储控制器，不需要存储控制器之间转发访问请求，从而提高访问请求的处理效率，减少访问请求处理时延。在这种实现方式下，前端接口卡存储有访问请求的地址信息与存储控制器的之间对应关系。在这种实现方式中，前端接口卡可以将主机下发的访问请求发送到不同的存储控制器并行处理，从而提高了访问请求的处理效率，减少访问请求处理时延。另一种实现方式，前端接口卡以链接为粒度向存储系统分发访问请求。前端接口卡以链接为粒度向存储系统分发访问请求是指前端接口卡将来自主机的同一个连链接的访问请求均由同一个存储控制器处理。即每建立一个链接，前端接口卡指定一个存储控制器处理来自该链接的所有访问请求。
如图6所示，本发明实施例中，为维护存储业务的连续性，前端接口卡执行如下操作：
步骤601：前端接口卡检测存储控制器状态。
前端接口卡检测存储控制器是否处于正常状态。存储控制器在运行过程中，由于各种原因导致由正常状态变为异常状态。例如，由于存储控制器发生故障、掉电、升级等原因变为离线状态，或者由于存储控制器软件原因导致没有响应等。
步骤602：当前端接口卡检测到存储控制器的状态为异常状态，前端接口卡为主机从多个存储控制器中选择新的存储控制器。
例如当第一存储控制器的状态为异常状态时，前端接口卡为主机从多个存储控制器中选择新的存储控制器处理主机的访问请求。
本发明实施例中，多个存储控制器共享一个前端接口卡，在其中某个存储控制器从正常状态变为异常状态时，存储系统切换存储控制器时，主机不感知存储系统的存储控制器切换。因此，主机不需要停止向存储系统发送访问请求，从而提高了业务连续性。本发明 实施例也避免由于主机软件兼容性导致与存储控制器无法建立链接导致存储控制器切换失败的问题。
基于图6所示的实施例，进一步的，前端接口卡维护存储控制器状态表，用于记录存储系统中的存储控制器的状态。进一步的，前端接口卡还可以维护存储控制器切换表，用于记录当前存储控制器如果变为异常状态，当前存储控制器的备份存储控制器。备份存储控制器即可以代替当前存储控制器的存储控制器。具体的，前端接口卡可以根据每一个存储控制器的性能、负载等决定为当前存储控制器确定备份存储控制器，或者设定备份存储控制器并在存储控制器切换表中记录备份关系。
因此，在步骤602中，前端接口卡可以根据存储控制器切换表，选择新的存储控制器，即备份存储控制器。
本发明实施例提供了多种实现方式，用于处理存储控制器切换过程中的主机发送的访问请求。本发明实施例结合图2，对各种实现方式进行说明。其中一种实现方式，如图7所示，包括：
步骤701：主机发送访问请求。
访问请求可以为读请求、写请求或者管理请求。本发明实施例以读请求为例进行说明。
步骤702：主机启动定时器用于确定是否等待超时。
主机启动定时器，用于确定存储系统是否在预定的时间内返回响应。
步骤703：前端接口卡记录访问请求信息。
本发明实施例中，访问请求信息包含访问请求的类型、发送访问请求的源地址和访问请求的目的地址中一种或多种。
步骤704：前端接口卡将访问请求发送到存储控制器A。
步骤705：存储控制器A从cache或硬盘中读取数据，将数据的描述信息发送到前端接口卡。
本发明实施例中，cache可以位于图3所示的存储器302中。硬盘参见为图2所示的硬盘。
其中，数据的描述信息包括数据在cache中的地址以及数据长度。
步骤706：前端接口卡根据数据的描述信息，以直接内存访问(Direct Memory Acess,DMA)获取数据并向主机发送数据。
步骤707：前端接口卡检测到存储控制器A变为异常状态，选择存储控制器B代替存储控制器A。
前端接口卡检测到存储控制器A变为异常状态，选择存储控制器B代替存储控制器A，即切换到存储控制器B。
步骤708：前端接口卡根据记录的访问请求信息，向主机发送访问请求错误消息。
访问请求错误消息用于上报访问请求的错误状态。在本发明实施例中，访问请求错误消息为读请求错误消息。
步骤709：响应访问请求错误消息，主机重新发送访问请求。
步骤710：前端接口卡接收主机发送的访问请求并将访问请求发送到存储控制器B。
步骤711：存储控制器B根据访问请求从cache或硬盘中读取数据，将数据的描述信息 发送到前端接口卡。
步骤712：前端接口卡根据数据的描述信息，以DMA获取数据并向主机发送数据。
步骤713：前端接口卡向主机发送访问请求正常完成响应。
在本发明实施例中，其中一种实现，前端接口卡不需要动态随机存储器，不需要缓存访问请求级的数据，即不需要缓存写请求携带的数据或读请求所请求的数据。
另外一种场景，存储控制器A接收前端接口卡发送的访问请求，但还没有执行步骤705，即存储控制器A还没有处理访问请求，或者已经从cache或硬盘读取数据，但还没有向前端接口卡发送数据的描述信息。此时，存储控制器A发生故障，后续的实现方式可参考图7实现方式的步骤707至步骤713，在此不再赘述。
另外一种实现方式，可参考图7实现方式的步骤701至步骤711。在该实现方式中，与步骤712不同的是，前端接口卡未获取完存储控制器A处理的主机的访问请求的结果时，前端接口卡从存储控制器B获取主机的访问请求的处理结果，从存储控制器B获取的主机的访问请求的处理结果中选择未获取完的存储控制器A处理的主机的访问请求的结果。前端接口卡向主机发送未获取完的存储控制器A处理的主机的访问请求的结果。由于存储控制器A变为异常状态，前端接口卡未获取完存储控制器A处理的主机的访问请求的结果，例如读数据，前端接口卡只获取了部分读数据，并向主机发送了该部分读数据。因此，在这一实现方式中，结合步骤701至步骤711，前端接口卡根据数据的描述信息，以DMA方式获取数据，前端接口卡根据已经向主机发送的部分读请求的数据，从存储控制器B获取的主机的访问的处理结果中选择出未获取完的主机的访问请求的处理结果，补齐向主机未发送完的访问请求的处理结果。当前端接口卡补齐未向主机发送的请求的数据后，向主机发送访问请求正常完成响应。例如，主机读请求的数据为000011110001，前端接口卡从存储控制器A获取到了000011，并且向主机发送了000011。前端接口卡从存储控制器B获取主机读请求的数据000011110001，由于前端接口卡已经向主机发送了000011，前端接口卡只需要从存储控制器B获取的主机读请求的数据000011110001从选择110001，向主机发送110001。
本发明实施例，前端接口卡检测存储控制器状态，当检测到存储控制器A由异常状态恢复到正常状态，可以将存储控制器B切换到存储控制器A。
本发明另一实施例提供了存储系统的前端接口卡，如图8所示，包括第一接口801、第二接口802、检测单元803和选择单元804。其中，第一接口801用于与主机通信，第二接口802用于与存储系统的多个存储控制器通信；检测单元803，用于检测第一存储控制器状态；其中，第一存储控制器为多个存储控制器中用于处理主机的访问请求的存储控制器；选择单元804，用于当第一存储控制器的状态为异常状态时，为主机从多个存储控制器中选择第二存储控制器处理主机的访问请求；第二存储控制器为多个存储控制器为不同于第一存储控制器的存储控制器。具体的，选择单元804用于根据多个存储控制器的性能选择第二存储控制器。进一步的，前端接口卡还包括发送单元和接收单元，其中，发送单元用于当第一存储控制器的状态为异常状态时，向主机发送访问请求错误信息；访问请求错误消息用于上报访问请求的错误状态；接收单元用于接收所述主机响应所述访问请求错误信息重新发送的访问请求。
基于图8所示的前端接口卡，还包括获取单元，用于当第一存储控制器的状态为异常状态并且前端接口卡未获取完第一存储控制器处理的主机的访问请求的结果时，从第二存储控制器获取主机的访问请求的处理结果；选择单元804，还用于从主机的访问请求的处理结果中选择未获取完的第一存储控制器处理的主机的访问请求的结果。
基于图8所示的前端接口卡，还包括切换单元，用于当第一存储控制器的状态从异常状态变为正常状态，将处理主机的业务请求的存储控制器器由第二存储控制器切换为第一存储控制器
在图8所示的前端接口卡，其中，第一接口801为以太接口或FC接口。在另一种实现方式中，第二接口802为PCIe接口。
在图8所示的前端接口卡，具体实现可以参考本发明实施例前面所述的前端接口卡的实现，在此不再赘述。
本发明提供了一种芯片，该芯片包含第一接口和第二接口；第一接口用于与主机通信，第二接口用于与存储系统的多个存储控制器通信；芯片还包括处理器，该处理器用于实现本发明实施例中前端接口卡的各种实现。处理器可以为现场可编程门阵列(Field Programmable Gate Array,FPGA)，或者专用集成电路(Application-specific integrated circuit,ASIC)，或者中央处理单元(Central Processing Unit,CPU)，或者其他硬件，或者，FPGA或其他硬件与CPU共同作为处理器。本发明实施例中提供的芯片，其中一种实现，第一接口、第二接口和处理器可以以知识产权核(intellectual property core)的产品形态呈现，分别对应不同的知识产权核。
本发明提供了一种计算机可读存储介质，该计算机可读存储介质中存储有指令，当处理器执行所述指令时，用于执行本发明实施例中前端接口卡的各项功能。
本发明提供了一种包含指令的计算机程序产品，当处理器执行计算机程序产品中的指令时，用于执行本发明实施例中前端接口卡的各项功能。
本发明实施例提供的主机可以是物理主机，也可以是虚拟机(Virtual Machine,VM)。本发明实施例提供的前端接口卡可以直接与主机的HBA通信，也可以通过交换机与主机的HBA通信，本发明实施例对此不作限定。
还应理解，本发明实施例中提及的存储器可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(Read-Only Memory，ROM)、可编程只读存储器(Programmable ROM，PROM)、可擦除可编程只读存储器(Erasable PROM，EPROM)、电可擦除可编程只读存储器(Electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(Random Access Memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(Static RAM，SRAM)、动态随机存取存储器(Dynamic RAM，DRAM)、同步动态随机存取存储器(Synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(Double Data Rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(Enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(Synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(Direct Rambus RAM，DR RAM)。
需要说明的是，当处理器为通用处理器、DSP、ASIC、FPGA或者其他可编程逻辑器 件、分立门或者晶体管逻辑器件、分立硬件组件时，存储器(存储模块)可以集成在处理器中。
应注意，本文描述的存储器旨在包括但不限于这些和任意其它适合类型的存储器。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本发明所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本发明各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。

Claims (32)

  1. 一种存储系统中实现存储业务连续性的方法，其特征在于，所述存储系统包括前端接口卡和多个存储控制器，所述前端接口卡与所述多个存储控制器通信，所述前端接口卡与主机通信；所述方法包括：
    所述前端接口卡检测第一存储控制器状态；其中，所述第一存储控制器为所述多个存储控制器中用于处理所述主机的访问请求的存储控制器；
    当所述第一存储控制器的状态为异常状态时，所述前端接口卡为所述主机从所述多个存储控制器中选择第二存储控制器处理所述主机的访问请求；所述第二存储控制器为所述多个存储控制器为不同于所述第一存储控制器的存储控制器。
  2. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    当所述第一存储控制器的状态为异常状态时，所述前端接口卡向所述主机发送访问请求错误信息；所述访问请求错误消息用于上报所述访问请求的错误状态；
    所述前端接口卡接收所述主机响应所述访问请求错误信息重新发送的访问请求。
  3. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    当所述第一存储控制器的状态为异常状态并且所述前端接口卡未获取完所述第一存储控制器处理的所述主机的访问请求的结果时，所述前端接口卡从所述第二存储控制器获取所述主机的访问请求的处理结果，并从所述主机的访问请求的处理结果中选择所述未获取完的所述第一存储控制器处理的所述主机的访问请求的结果。
  4. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    当所述第一存储控制器的状态从所述异常状态变为正常状态，所述前端接口卡将处理所述主机的业务请求的存储控制器由所述第二存储控制器切换为所述第一存储控制器。
  5. 根据权利要求1所述的方法，其特征在于，所述前端接口卡与所述主机通过以太网连接。
  6. 根据权利要求1所述的方法，其特征在于，所述前端接口卡与所述主机通过以光纤通道连接。
  7. 根据权利要求1所述的方法，其特征在于，所述前端接口卡与所述多个存储控制器通过外围组件快速互连总线连接。
  8. 根据权利要求1所述的方法，其特征在于，所述前端接口卡为所述主机从所述多个存储控制器中选择第二存储控制器处理所述主机的访问请求，具体包括：
    所述前端接口卡根据所述多个存储控制器的性能选择所述第二存储控制器。
  9. 一种存储系统中的前端接口卡，其特征在于，所述存储系统包括所述前端接口卡和多个存储控制器，所述前端接口卡包含第一接口和第二接口；所述第一接口用于与主机通信，所述第二接口用于与所述多个存储控制器通信；所述前端接口卡还包括：
    检测单元，用于检测第一存储控制器状态；其中，所述第一存储控制器为所述多个存储控制器中用于处理所述主机的访问请求的存储控制器；
    选择单元，用于当所述第一存储控制器的状态为异常状态时，为所述主机从所述多个存储控制器中选择第二存储控制器处理所述主机的访问请求；所述第二存储控制器为所述多个存储控制器为不同于所述第一存储控制器的存储控制器。
  10. 根据权利要求9所述的前端接口卡，其特征在于，所述前端接口卡还包括：
    发送单元，用于当所述第一存储控制器的状态为异常状态时，向所述主机发送访问请求错误信息；所述访问请求错误消息用于上报所述访问请求的错误状态；
    接收单元，用于接收所述主机响应所述访问请求错误信息重新发送的访问请求。
  11. 根据权利要求9所述的前端接口卡，其特征在于，所述前端接口卡还包括：
    获取单元，用于当所述第一存储控制器的状态为异常状态并且所述前端接口卡未获取完所述第一存储控制器处理的所述主机的访问请求的结果时，所述前端接口卡从所述第二存储控制器获取所述主机的访问请求的处理结果；
    所述选择单元，还用于从所述主机的访问请求的处理结果中选择所述未获取完的所述第一存储控制器处理的所述主机的访问请求的结果。
  12. 根据权利要求9所述的前端接口卡，其特征在于，所述前端接口卡还包括：
    切换单元，用于当所述第一存储控制器的状态从所述异常状态变为正常状态，将处理所述主机的业务请求的存储控制器由所述第二存储控制器切换为所述第一存储控制器。
  13. 根据权利要求9所述的前端接口卡，其特征在于，所述第一接口为以太接口。
  14. 根据权利要求9所述的前端接口卡，其特征在于，所述第一接口为光纤通道接口。
  15. 根据权利要求9所述的前端接口卡，其特征在于，所述第二接口为外围组件快速互连总线接口。
  16. 根据权利要求9所述的前端接口卡，其特征在于，所述选择单元，具体用于根据所述多个存储控制器的性能选择所述第二存储控制器。
  17. 一种存储系统中的前端接口卡，其特征在于，所述存储系统包括所述前端接口卡和多个存储控制器，所述前端接口卡包含第一接口和第二接口；所述第一接口用于与主机通信，所述第二接口用于与所述多个存储控制器通信；所述前端接口卡还包括处理器，所述处理器用于与所述第一接口和所述第二接口通信，所述处理器还用于：
    检测第一存储控制器状态；其中，所述第一存储控制器为所述多个存储控制器中用于处理所述主机的访问请求的存储控制器；
    当所述第一存储控制器的状态为异常状态时，为所述主机从所述多个存储控制器中选择第二存储控制器处理所述主机的访问请求；所述第二存储控制器为所述多个存储控制器为不同于所述第一存储控制器的存储控制器。
  18. 根据权利要求17所述的前端接口卡，其特征在于，所述处理器，还用于：
    当所述第一存储控制器的状态为异常状态时，向所述主机发送访问请求错误信息；所述访问请求错误消息用于上报所述访问请求的错误状态；
    接收所述主机响应所述访问请求错误信息重新发送的访问请求。
  19. 根据权利要求17所述的前端接口卡，其特征在于，所述处理器，还用于当所述第一存储控制器的状态为异常状态并且所述前端接口卡未获取完所述第一存储控制器处理的所述主机的访问请求的结果时，从所述第二存储控制器获取所述主机的访问请求的处理结果，并从所述主机的访问请求的处理结果中选择所述未获取完的所述第一存储控制器处理的所述主机的访问请求的结果。
  20. 根据权利要求17所述的前端接口卡，其特征在于，所述处理器还用于：
    当所述第一存储控制器的状态从所述异常状态变为正常状态，将处理所述主机的业务 请求的存储控制器由所述第二存储控制器切换为所述第一存储控制器。
  21. 根据权利要求17所述的前端接口卡，其特征在于，所述第一接口为以太接口。
  22. 根据权利要求17所述的前端接口卡，其特征在于，所述第一接口为光纤通道接口。
  23. 根据权利要求17所述的前端接口卡，其特征在于，所述第二接口为外围组件快速互连总线接口。
  24. 根据权利要求17所述的前端接口卡，其特征在于，所述处理器具体用于根据所述多个存储控制器的性能选择所述第二存储控制器。
  25. 一种存储系统，其特征在于，所述存储系统包括前端接口卡和多个存储控制器，所述前端接口卡用于与所述多个存储控制器通信以及与主机通信；其中，所述前端接口卡还用于：
    检测第一存储控制器状态；其中，所述第一存储控制器为所述多个存储控制器中用于处理所述主机的访问请求的存储控制器；
    当所述第一存储控制器的状态为异常状态时，为所述主机从所述多个存储控制器中选择第二存储控制器处理所述主机的访问请求；所述第二存储控制器为所述多个存储控制器为不同于所述第一存储控制器的存储控制器。
  26. 根据权利要求25所述的存储系统，其特征在于，所述前端接口卡，还用于：
    当所述第一存储控制器的状态为异常状态时，向所述主机发送访问请求错误信息；所述访问请求错误消息用于上报所述访问请求的错误状态；
    接收所述主机响应所述访问请求错误信息重新发送的访问请求。
  27. 根据权利要求25所述的存储系统，其特征在于，所述前端接口卡，还用于当所述第一存储控制器的状态为异常状态并且所述前端接口卡未获取完所述第一存储控制器处理的所述主机的访问请求的结果时，从所述第二存储控制器获取所述主机的访问请求的处理结果，并从所述主机的访问请求的处理结果中选择所述未获取完的所述第一存储控制器处理的所述主机的访问请求的结果。
  28. 根据权利要求25所述的存储系统，其特征在于，所述前端接口卡还用于：
    当所述第一存储控制器的状态从所述异常状态变为正常状态，将处理所述主机的业务请求的存储控制器由所述第二存储控制器切换为所述第一存储控制器。
  29. 根据权利要求25所述的存储系统，其特征在于，所述前端接口卡与所述主机通过以太网连接。
  30. 根据权利要求25所述的存储系统，其特征在于，所述前端接口卡与所述主机通过以光纤通道连接。
  31. 根据权利要求25所述的存储系统，其特征在于，所述前端接口卡与所述多个存储控制器通过外围组件快速互连总线连接。
  32. 根据权利要求25所述的存储系统，其特征在于，所述前端接口卡具体用于根据所述多个存储控制器的性能选择所述第二存储控制器。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115657975A (zh) * 2022-12-29 2023-01-31 浪潮电子信息产业股份有限公司 一种磁盘数据读写控制方法、相关组件及前端共享卡

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101102256A (zh) * 2006-07-04 2008-01-09 国际商业机器公司 存储区域网系统以及在存储网络中确定数据路径的方法
CN106294031A (zh) * 2016-07-29 2017-01-04 杭州宏杉科技有限公司 一种业务管理方法和存储控制器
CN107423167A (zh) * 2017-07-31 2017-12-01 郑州云海信息技术有限公司 一种基于双控存储的ISCSI target冗余控制方法和系统
US20180120918A1 (en) * 2016-10-31 2018-05-03 Samsung Electronics Co .. Ltd. Storage device and method of controlling link state thereof

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004021556A (ja) * 2002-06-14 2004-01-22 Hitachi Ltd 記憶制御装置およびその制御方法
US7213102B2 (en) * 2003-06-26 2007-05-01 International Business Machines Corporation Apparatus method and system for alternate control of a RAID array
US8595313B2 (en) 2005-11-29 2013-11-26 Netapp. Inc. Systems and method for simple scale-out storage clusters
US8266472B2 (en) * 2006-05-03 2012-09-11 Cisco Technology, Inc. Method and system to provide high availability of shared data
US7945730B2 (en) * 2006-11-13 2011-05-17 Lsi Corporation Systems and methods for recovering from configuration data mismatches in a clustered environment
US7661018B2 (en) * 2006-12-21 2010-02-09 International Business Machines Corporation Method, apparatus and program storage device for providing automatic recovery from premature reboot of a system during a concurrent upgrade
US7827441B1 (en) * 2007-10-30 2010-11-02 Network Appliance, Inc. Disk-less quorum device for a clustered storage system
US10572188B2 (en) * 2008-01-12 2020-02-25 Hewlett Packard Enterprise Development Lp Server-embedded distributed storage system
JP2012507783A (ja) * 2008-10-30 2012-03-29 エルエスアイ コーポレーション ストレージコントローラのデータ再配分
US8650328B1 (en) * 2008-12-15 2014-02-11 American Megatrends, Inc. Bi-directional communication between redundant storage controllers
US20140244936A1 (en) * 2013-02-25 2014-08-28 Lsi Corporation Maintaining cache coherency between storage controllers
US9378145B2 (en) * 2013-03-05 2016-06-28 Dot Hill Systems Corporation Storage controller cache synchronization method and apparatus
US9274901B2 (en) * 2013-11-20 2016-03-01 Avago Technologies General Ip (Singapore) Pte. Ltd. I/O request mirroring in a clustered storage system
US9348525B2 (en) * 2014-02-21 2016-05-24 Netapp, Inc. Systems and methods for a storage array-managed initiator cache
US9348715B2 (en) * 2014-03-20 2016-05-24 Netapp Inc. Storage device health status synchronization
CN105934793A (zh) 2014-12-27 2016-09-07 华为技术有限公司 一种存储系统数据分发的方法、分发装置与存储系统
US9600378B2 (en) * 2015-01-29 2017-03-21 Dell Products, Lp Efficient mechanism to replicate data for multiple controllers
US9836404B2 (en) * 2015-08-14 2017-12-05 Netapp, Inc. Write mirroring to storage class memory devices
US9836368B2 (en) * 2015-10-22 2017-12-05 Netapp, Inc. Implementing automatic switchover
US20170220249A1 (en) * 2016-01-29 2017-08-03 Netapp, Inc. Systems and Methods to Maintain Consistent High Availability and Performance in Storage Area Networks
US9864663B2 (en) * 2016-02-19 2018-01-09 Dell Products L.P. Storage controller failover system
CN107959582B (zh) 2016-10-18 2020-12-01 华为技术有限公司 一种切片实例的管理方法及装置
US10719244B2 (en) * 2016-11-18 2020-07-21 International Business Machines Corporation Multi-mode data replication for data loss risk reduction
US10554520B2 (en) * 2017-04-03 2020-02-04 Datrium, Inc. Data path monitoring in a distributed storage network
US10884888B2 (en) * 2019-01-22 2021-01-05 International Business Machines Corporation Facilitating communication among storage controllers
US11243712B2 (en) * 2019-06-28 2022-02-08 Hewlett Packard Enterprise Development Lp Local analytics for high-availability storage systems

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101102256A (zh) * 2006-07-04 2008-01-09 国际商业机器公司 存储区域网系统以及在存储网络中确定数据路径的方法
CN106294031A (zh) * 2016-07-29 2017-01-04 杭州宏杉科技有限公司 一种业务管理方法和存储控制器
US20180120918A1 (en) * 2016-10-31 2018-05-03 Samsung Electronics Co .. Ltd. Storage device and method of controlling link state thereof
CN107423167A (zh) * 2017-07-31 2017-12-01 郑州云海信息技术有限公司 一种基于双控存储的ISCSI target冗余控制方法和系统

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115657975A (zh) * 2022-12-29 2023-01-31 浪潮电子信息产业股份有限公司 一种磁盘数据读写控制方法、相关组件及前端共享卡

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