WO2021006811A1 - Device for trapping an ion, method for forming the same, and method for controlling the same - Google Patents

Abstract

According to embodiments of the present invention, a device for trapping an ion is provided. The device includes an electrode arrangement configured to generate an electric field to trap the ion, the electrode arrangement including a ground electrode configured to be connected to ground, the ground electrode having an opening defined therein, and an optical arrangement configured to transmit an output optical signal through the opening to the trapped ion. According to further embodiments of the present invention, a method for forming a device for trapping an ion and a method for controlling a device for trapping an ion are also provided.

Description

DEVICE FOR TRAPPING AN ION, METHOD FOR FORMING THE SAME, AND

METHOD FOR CONTROLLING THE SAME

Cross-Reference To Related Application

[0001] This application claims the benefit of priority of Singapore patent application No. 10201906375W, filed 10 July 2019, the content of it being hereby incorporated by reference in its entirety for all purposes.

Technical Field

[0002] Various embodiments relate to a device for trapping an ion, a method for forming a device for trapping an ion, and a method for controlling a device for trapping an ion.

Background

[0003] Quantum computing is a computation system that uses quantum-mechanical phenomena (e.g., superposition, entanglement) to perform computing operation, instead of the known Boolean logic by its classical computing counterparts. Quantum computation uses quantum bits, i.e., qubits, to represent multiple states simultaneously, which could solve large-scale quantum computers much rapidly than any classical computers. Superconducting materials, trapped ion, and single atom can be used as qubits, where trapped ion received much attention due to its exquisite coherence properties and high efficiency. Despite extensive demonstrations of quantum computing operation using trapped ions in state-of-the-art, there is still limited capability of mass- producing ion traps for quantum computing applications. To enable mass production, the fabrication of ion trap-based quantum computing devices should be compatible with known CMOS fabrication techniques.

[0004] Quantum computing operation using trapped ion requires laser optical addressing of specific wavelengths. Therefore, to realize fabrication of quantum computing devices using CMOS-compatible techniques, integration of photonics structures (e.g., grating couplers and waveguide) into the ion trap is needed. A grating coupler is needed to be placed below the trapped ion to direct light of specific wavelength towards the ion for optical addressing. To facilitate optical addressing in known methods, openings of micron size are done on RF electrodes connected to RF sources. However, the openings may potentially disrupt the RF signals needed for ion trapping, which result in high RF loss. The optical addressing via slot of opening of RF electrodes also has limited pointing angle (F).

[0005] There is therefore a need to address the above-mentioned problems associated with the prior art.

Summary

[0006] The invention is defined in the independent claims. Further embodiments of the invention are defined in the dependent claims.

[0007] According to an embodiment, a device for trapping an ion is provided. The device may include an electrode arrangement configured to generate an electric field to trap the ion, the electrode arrangement including a ground electrode configured to be connected to ground, the ground electrode having an opening defined therein, and an optical arrangement configured to transmit an output optical signal through the opening to the trapped ion.

[0008] According to an embodiment, a method for forming a device for trapping an ion is provided. The method may include forming an electrode arrangement configured to generate an electric field to trap the ion, wherein forming the electrode arrangement includes forming a ground electrode configured to be connected to ground, the ground electrode having an opening defined therein, and forming an optical arrangement configured to transmit an output optical signal through the opening to the trapped ion.

[0009] According to an embodiment, a method for controlling a device for trapping an ion is provided. The method may include generating, by means of an electrode arrangement of the device, an electric field to trap the ion, and transmitting an output optical signal through an opening defined in a ground electrode of the electrode arrangement to the trapped ion, the ground electrode being connected to ground. Brief Description of the Drawings

[0010] In the drawings, like reference characters generally refer to like parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments of the invention are described with reference to the following drawings, in which:

[0011] FIG. 1A shows a schematic perspective view of a device for trapping an ion, according to various embodiments.

[0012] FIG. IB shows a flow chart illustrating a method for forming a device for trapping an ion, according to various embodiments.

[0013] FIG. 1C shows a flow chart illustrating a method for controlling a device for trapping an ion, according to various embodiments.

[0014] FIGS. 2A to 2D show schematic diagrams of a device for trapping ion, according to various embodiments.

[0015] FIGS. 3A to 3D show schematic diagrams of the device of FIGS. 2A to 2D.

[0016] FIGS. 4A to 4C show schematic top views of devices for trapping ion, according to various embodiments.

[0017] FIGS. 5A to 5F show, as schematic views, various processing stages of a method for forming a device for trapping ion, according to various embodiments.

[0018] FIGS. 6A to 6B show simulation of ion-trap electromagnetic field and trapping potential.

[0019] FIGS. 7A to 7F show analysis of stray E-field distribution inside the ground-slot opening.

[0020] FIGS. 8 A to 8E show simulation of the effect of depth of silicon dioxide (S1O2) trench opening to stray E-field density.

[0021] FIGS. 9A and 9B show simulation of the effect of openings to the main E-field for ion- trapping.

[0022] FIGS. 10A to 10D show simulation of the effect of window opening size to light propagation.

[0023] FIGS. 11A and 11B show results for ion trap performance. FIG. 11C shows results for the trap height of devices with various RF electrode widths.

[0024] FIGS. 12A to 12C show electro-optical integration in planar ion trap and result.

[0025] FIGS. 13A to 13D show results for the photonics devices for optical addressing. [0026] FIGS. 14A to 14C show finite-difference time-domain simulation for determining the beam profile of the output light.

[0027] FIG. 15A shows scanning electron microscopy (SEM) images of a fabricated input grating coupler, while FIG. 15B shows measured and simulated loss of the grating coupler.

[0028] FIGS. 16A and 16B show simulation results respectively of an input coupler, and an output coupler.

[0029] FIGS. 17A to 171 show top view of devices for trapping ion on various substrates, and scanning electron microscopy (SEM) images illustrating magnified view of a portion of the devices and cross-sectional view of the devices.

[0030] FIGS. 18A to 18D show results for leakage current, capacitance, insertion loss and power respectively for devices on high resistivity silicon, silicon with grounding plane and glass substrates with various RF electrode widths.

[0031] FIG. 19 shows result of finite element modeling of electric pseudopotential in a surface trap with RF line width of 40 pm.

[0032] FIGS. 20 A to 20E show images of fabricated trap electrodes.

[0033] FIGS. 21 A and 2 IB show scanning electron microscopy (SEM) images of the trap electrodes in cross-sectional views.

[0034] FIG. 22 shows the results of monoatomic Ar⁺ X-ray photoelectron spectroscopy (XPS) core-level (Au 4 f, Cu 2 p) spectra of copper (Cu) and gold (Au) chemical states on a pad surface before and after total etching cycles.

[0035] FIGS. 23A to 23C shows results of X-ray photoelectron spectroscopy (XPS) depth profiling of Au/Cu-Au/Cu layers.

[0036] FIGS. 24A and 24B show the design of an ion trap with a ground plane.

[0037] FIGS. 25 A to 25D show optical images relating to the fabrication of a copper (Cu) ground plane.

[0038] FIGS. 26 A and 26B show scanning electron microscopy (SEM) images of trap electrodes with ground plane in top and cross-sectional views respectively.

[0039] FIG. 27 shows a full-wafer leakage current mapping for ion trap with ground layer.

[0040] FIG. 28 shows a setup of RF (radio frequency) resonator test with ion trap.

[0041] FIG. 29 shows resonance curves of ion traps with and without ground layer, and compared to a reference capacitor. [0042] FIGS. 30A and 30B show simulated insertion loss of ion trap without and with ground plane for trap-40 and trap-80 respectively.

Detailed Description

[0043] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments.

[0044] Embodiments described in the context of one of the methods or devices are analogously valid for the other methods or devices. Similarly, embodiments described in the context of a method are analogously valid for a device, and vice versa.

[0045] Features that are described in the context of an embodiment may correspondingly be applicable to the same or similar features in the other embodiments. Features that are described in the context of an embodiment may correspondingly be applicable to the other embodiments, even if not explicitly described in these other embodiments. Furthermore, additions and/or combinations and/or alternatives as described for a feature in the context of an embodiment may correspondingly be applicable to the same or similar feature in the other embodiments.

[0046] In the context of various embodiments, the phrase“at least substantially” may include “exactly” and a reasonable variance.

[0047] In the context of various embodiments, the term“about” or“approximately” as applied to a numeric value encompasses the exact value and a reasonable variance.

[0048] As used herein, the term“and/or” includes any and all combinations of one or more of the associated listed items.

[0049] Various embodiments may provide techniques relating to ion traps, including an ion addressing methodology by laser grating coupler via ground-slot opening of ion-traps. The ion trap may be a planar ion trap. The ion trap may include a planar electrode arrangement. [0050] Various embodiments may provide an ion trap design with electrode opening for optical addressing. For example, one or more ions may be trapped and, depending on the operation required, light may be transmitted or directed to the desired ion associated with the operation to optically address the desired ion. If another operation is subsequently required, the light may then be re-directed to another ion associated with the other operation to optically address that other ion. As a non-limiting example, the change in the direction of the light may be achieved using one or more heaters as will be described further below. Various embodiments may provide a methodology and techniques to address ions via a narrow opening of a central RF (radio frequency) ground. However, this opening may increase stray electric field (E-field) due to the built-up of fringe E-field into the exposed dielectric. To maintain phase coherence during logic operation, the ion position in the laser beam may be needed to be maintained in sub-wavelength spatial accuracy (tens to hundreds of nm). However, mechanical vibration and stray electric field may push the ion out of position, which may lead to beam pointing error. Since the ions are trapped above the opening, excessive stray E-field may also cause ions to escape from the trapping potential due to increase in micromotion and kinetic energy. The techniques disclosed herein may suppress this stray E-field while concurrently improving the Q factor. To simplify the integration of laser grating coupler into the ion-trap, the ion-trap may be optimised without the need for immediate grounding layer underneath the ion-trap metallisation. Instead, a ground metallisation at the bottom of the substrate may be implemented. This may lead to simpler fabrication process and option for the utilisation of commercially available silicon-on-insulator for the development of the laser grating structure.

[0051] To address the above mentioned issue relating to prior art, in various embodiments, grating couplers and openings may be placed or positioned under a ground electrode (e.g., a central ground electrode) for optical addressing as will be discussed further below with reference to the figures, for example, FIGS. 2A to 2D. Accessing ion via the slot opening of the (central) ground electrode may produce a simpler waveguide and laser grating coupler design. Besides, it may also exhibit higher efficiency in optical addressing due to closer proximity between the grating coupler and ion position, and more flexible pointing angle. However, there may be challenges where the slot opening into the ground electrode may introduce stray E-field due to the exposed dielectric (e.g., SiCE). This E-field may increase ion micromotion that may push the ion out of position which may lead to beam pointing error. This excessive E- field may also cause the ion to escape from the trapping potential due to increase in kinetic energy. To address such challenges, a trench may be introduced to the exposed dielectric to suppress the fringe E-field inside the slot opening of the ground electrode. At the same time, a ground plane (e.g., Cu ground plane) may be designed to be positioned below the substrate.

[0052] In various embodiments, to address parasitic coupling issue in the substrate (e.g., Si substrate), a ground plane may be introduced into the ion trap. In planar ion trap, for example, ground metallisation or ground plane may be introduced to address or minimise parasitic coupling induced by the substrate (e.g., Si substrate). Fabricating a ground plane between the substrate and the top (DC/RF) electrodes may provide challenges as doing so may cause limitations in design, and opening the ground plane positioned this way for optical addressing of ion by grating coupler may cause disruption in RF performance. As a non-limiting example, to address such challenges, the ground plane may be provided at the bottom of the substrate.

[0053] Various embodiments may provide an ion trap or a device for trapping ion with a plurality of planar electrodes, e.g., including more than 3 DC planar electrodes. Various embodiments may allow for large scale integration with the inclusion of photonics interposer for optical addressing of ion qubits, where a single light source may be needed for multiple ion qubits.

[0054] In various embodiments, the openings for optical addressing may be designed on the ground electrode, thus, there may be less disruption on RF propagation. At the same time, oxide etching may be introduced in the opening(s) to form a trench which may help to suppress stray fringe E-field. This may effectively reduce the charge accumulation around the opening(s), which may enhance the ion trapping capability of the ion trap.

[0055] In various embodiments, ion qubits may be arranged in parallel form, thus may enable simple configuration of optical addressing on each qubit without or with minimal undesirable interference from neighbouring qubits/optical addressing.

[0056] As compared to some known approaches, the usage of light source for Doppler cooling of ion qubit in various embodiments may omit the requirement for additional cryogenic system.

[0057] In the context of various embodiments, particles (e.g., atoms) may be emitted via heating of the corresponding metal at sufficient temperature, preferably, in high vacuum. As a non limiting example, strontium particles (e.g., atoms) may be emitted via heating of strontium metal at -600 °C in high vacuum. The particles may then be emitted and ionised by means of laser ionisation. The ion(s) may then be trapped on the (planar) ion trap. As a non-limiting example, metal particles for ion trapping may be generated separately or externally of the ion trap.

[0058] As a non-limiting example, the device for trapping ion may include at least one output grating coupler formed along a same axis on a substrate, an oxide layer arranged on the at least one output grating coupler, a ground electrode arranged on the oxide layer overlapping with the at least one output grating coupler and two RF electrodes each arranged adjacent to the ground electrode, at least one opening formed in the ground electrode, each opening overlapping with a corresponding output grating coupler, and at least one trench formed in the oxide layer, each trench overlapping with a corresponding opening.

[0059] FIG. 1A shows a schematic perspective view of a device 100 for trapping an ion 130, according to various embodiments. The device 100 includes an electrode arrangement 102 configured to generate an electric field to trap the ion 130, the electrode arrangement 102 including a ground electrode 108 configured to be connected to ground, the ground electrode 108 having an opening 114 defined therein, and an optical arrangement 140 configured to transmit an output optical signal (represented by arrow 131) through the opening 114 to the trapped ion 130.

[0060] In other words, a device 100 for trapping an ion 130 may be provided. The device 100 may include an electrode arrangement 102 that may generate an electric field to trap (or confine or capture) the ion 130. The electrode arrangement 102 may be or may act as an ion trap. The electrode arrangement 102 may include a ground electrode 108 that is to be connected or coupled to ground (GND). The ground electrode 108 may be arranged centrally in the electrode arrangement 102. The ground electrode 108 may have an opening (or aperture) 114 defined therein (or therethrough). The electric field may generate a minimal pseudopotential point (or minimum electric field point) where the ion 130 may be trapped. The ion 130 may be trapped above the electrode arrangement 102, for example, above or over the ground electrode 108. In various embodiments, the electrode arrangement 102 may include a plurality of electrodes including the ground electrode 108.

[0061] The device 100 may further include an optical arrangement 140 that may transmit an output optical signal (or light) 131 through the opening 114 to the trapped ion 130 (e.g., to optically address the trapped ion 130). The optical arrangement 140 may be arranged below or underneath the electrode arrangement 102. The optical arrangement 140 may be integrated with the electrode arrangement 102. The optical arrangement 140 may include a plurality of optical elements or structures. The optical arrangement 140 may be a photonics interposer. The electrode arrangement 102 and the optical arrangement 140 may be supported or arranged on a support structure.

[0062] As described above, the device 100 may include an optical arrangement 140, and an ion trap, in the form of the electrode arrangement 102.

[0063] In the context of various embodiments, the term“light” may include not only an optical signal in the visible light range but also an optical signal in the infrared range or in the ultraviolet range.

[0064] In the context of various embodiments, the opening 114 may have a size or area of at least 5x5 pm², for example, at least 10x10 pm², or at least 20x20 pm². As non-limiting examples, the opening 114 may have a size or area of 5x5 pm², 10x10 pm², 20x20 pm², 30x30 pm², 40x40 pm², or 50x50 pm².

[0065] In the context of various embodiments, the opening 114 may be of any suitable shape. As non-limiting examples, the opening 114 may be a square, a rectangle, a circle or any polygonal shape.

[0066] In the context of various embodiments, the electrode arrangement 102 may include or may be made of copper (Cu). The electrode arrangement may further include gold (Au) over Cu. It should be appreciated that that other suitable conductive materials or metals may be used, either individually or in combination with another conductive material or metal, for example, in a layered arrangement.

[0067] In the context of various embodiments, the optical arrangement 140 may include a silicon- based material.

[0068] In various embodiments, the electrode arrangement 102 may include a pair of RF electrodes configured to generate an RF (radio frequency) field, and at least one pair of DC electrodes configured to generate a DC (static) field, wherein the RF field and the DC field define the electric field. In other words, the electric field may include the RF field and the DC field. The RF field and the DC field may co-operatively act to trap the ion 130. The RF field and the DC field may co-operatively generate a minimal pseudopotential point (or minimum electric field point) where the ion 130 may be trapped. The ground electrode 108 may act as ground to the pair of RF electrodes and the at least one pair of DC electrodes. [0069] The RF electrodes may be connected to at least one RF source. Each of the pair of RF electrodes may have a width of at least 20 pm, for example, at least 40 pm or at least 80 pm. As non-limiting examples, the width of each RF electrode may be about 20 pm, 40 pm, 60 pm, 80 pm, 100 pm, or 120 pm.

[0070] At least one electrical (or DC) signal may be applied to the at least one pair of DC electrodes. In various embodiments, the electrode arrangement 102 may include a plurality of pairs of DC electrodes configured to generate the DC field. Respective electrical signals may be applied to a respective pair of DC electrodes.

[0071] The ground electrode 108 may be sandwiched between the pair of RF electrodes. The ground electrode 108 and the pair of RF electrodes may be arranged at least substantially parallel to each other. This may mean that the respective longitudinal axes of the ground electrode 108 and the pair of RF electrodes may be at least substantially parallel to each other. The ground electrode 108 and the pair of RF electrodes may be arranged between the at least one pair of DC electrodes. The ground electrode 108 and the at least one pair of DC electrodes may be arranged at least substantially perpendicular to each other. The ground electrode 108 and the pair of RF electrodes may be arranged at least substantially perpendicular to the at least one pair of DC electrodes. This may mean that the respective longitudinal axes of the ground electrode 108 and the pair of RF electrodes may be at least substantially perpendicular to the respective longitudinal axes of the at least one pair of DC electrodes.

[0072] The electrode arrangement 102 may include or may be a planar electrode arrangement. This may mean that the ground electrode 108, the pair of RF electrodes and the at least one pair of DC electrodes may be planar electrodes. The ground electrode 108, the pair of RF electrodes and the at least one pair of DC electrodes may be arranged co-planar to each other.

[0073] The device 100 may further include an insulating layer (e.g., S1O2) in between the electrode arrangement 102 and the optical arrangement 140, wherein a trench may be defined through the insulating layer at the opening 114. The trench may be defined through the entire depth of the insulating layer. The trench may be of a depth of at least 6 pm. In various embodiments, adjacent electrodes of the ground electrode 108, the pair of RF electrodes and the at least one pair of DC electrodes may be spaced apart from each other and trenches may also be defined through the insulating layer in the spacing or gap between the adjacent electrodes. For example, the ground electrode 108 may be spaced apart from each RF electrode of the pair of RF electrodes and a trench may be defined through the insulating layer in each spacing. The trench in each spacing may be defined through the entire depth of the insulating layer.

[0074] The optical arrangement 140 may include an optical output coupler to transmit the output optical signal 131, the optical output coupler being arranged optically exposed through the opening 114. Being optically exposed means that the output optical signal 131 from the optical output coupler may be transmitted through the opening 114, either directly or through an intermediate layer. The intermediate layer may be optically transparent. The optical output coupler may include an output grating.

[0075] The optical arrangement 140 may further include at least one waveguide optically coupled to the optical output coupler. The at least one waveguide may allow an optical signal (e.g., light) from an optical source or a light source to propagate within and/or through the at least one waveguide towards or to the optical output coupler.

[0076] The optical arrangement 140 may further include an optical input coupler optically coupled to the at least one waveguide, the optical input coupler being arranged to couple an optical signal (or light) from an optical (or light) source towards or into the at least one waveguide. The optical input coupler may include an input grating

[0077] The optical arrangement 140 may further include a tuning device arranged for tuning a direction (or an angle or angular direction) of the output optical signal 131.

[0078] As a non-limiting example, the tuning device may introduce a phase change to the output optical signal 131 to tune the direction of the output optical signal 131. The tuning device may include at least one heating element or heater for introducing the phase change. The at least one heating element may be provided on or adjacent to the at least one waveguide. Where there are a plurality of waveguides, for each waveguide, a respective heating element may be provided.

[0079] As another non-limiting example, the tuning device may change a refractive index of a (optical) material of at least part of the optical arrangement 140 to tune the direction of the output optical signal 131. For example, the refractive index of the material of the at least one waveguide may be changed. The tuning device may apply an electric field to change the refractive index of the material, e.g., by means of Kerr effect or quadratic electro-optic effect. As non-limiting examples, the tuning device may be an RF power generator to apply an RF field and/or a DC power supply to apply a DC field. [0080] The device 100 may further include a support structure arranged to support the electrode arrangement 102 and the optical arrangement 140, the support structure having a ground structure (e.g., a ground plane). The ground structure may include or may be made of copper (Cu). However, it should be appreciated that other suitable conductive materials or metals may be used.

[0081] In various embodiments, the ground structure may be arranged at the bottom of the support structure. In this way, a surface of the ground structure may form or define a lower or bottom surface of the support structure. The ground structure may be arranged on a side of the support structure that is opposite to the side having the electrode arrangement 102 and the optical arrangement 140.

[0082] In the context of various embodiments, the support structure may include a silicon-based substrate or a glass substrate. The support structure may further include a silicon-on-insulator (SOI) structure.

[0083] FIG. IB shows a flow chart 150 illustrating a method for forming a device for trapping an ion, according to various embodiments.

[0084] At 152, an electrode arrangement configured to generate an electric field to trap the ion is formed.

[0085] Forming the electrode arrangement may include, at 152a, forming a ground electrode configured to be connected to ground, the ground electrode having an opening defined therein.

[0086] At 154, an optical arrangement configured to transmit an output optical signal through the opening to the trapped ion is formed.

[0087] At 152, forming the electrode arrangement may further include forming a pair of RF electrodes configured to generate an RF field, and forming at least one pair of DC electrodes configured to generate a DC field. The RF field and the DC field may define the electric field.

[0088] At 152a, the ground electrode may be formed in between the pair of RF electrodes.

[0089] The method may further include forming an insulating layer in between the electrode arrangement and the optical arrangement, and forming a trench through the insulating layer at the opening.

[0090] At 154, an optical output coupler to transmit the output optical signal may be formed, the optical output coupler being arranged optically exposed through the opening.

[0091] At 154, a tuning device arranged for tuning a direction of the output optical signal may further be formed. [0092] In various embodiments, at 152, the electrode arrangement may be formed on a support structure, and at 154, the optical arrangement may be formed on the support structure. The method may further include forming a ground structure at the support structure. The ground structure may be formed at the bottom of the support structure.

[0093] FIG. 1C shows a flow chart 160 illustrating a method for controlling a device for trapping an ion, according to various embodiments.

[0094] At 162, an electric field to trap the ion is generated by means of an electrode arrangement of the device.

[0095] At 164, an output optical signal is transmitted (or directed) through an opening defined in a ground electrode of the electrode arrangement to the trapped ion, the ground electrode being connected to ground.

[0096] While the methods described above are illustrated and described as a series of steps or events, it will be appreciated that any ordering of such steps or events are not to be interpreted in a limiting sense. For example, some steps may occur in different orders and/or concurrently with other steps or events apart from those illustrated and/or described herein. In addition, not all illustrated steps may be required to implement one or more aspects or embodiments described herein. Also, one or more of the steps depicted herein may be carried out in one or more separate acts and/or phases.

[0097] It should be appreciated that descriptions in the context of the device 100 may correspondingly be applicable in relation to the method for forming a device for trapping ion described in the context of the flow chart 150 and the method for controlling a device for trapping ion described in the context of the flow chart 160.

[0098] Various embodiments or techniques will now be further described in detail based on non limiting examples and with reference to the drawings.

[0099] FIGS. 2A to 2D show schematic diagrams of a device 200 for trapping ion, according to various embodiments. FIGS. 3A to 3D show schematic diagrams of the device 200, illustrating a photonics interposer integrated with planar electrodes of the device 200. As may be observed, there may be provided output laser grating couplers via opening slots of a central ground line of the device 200.

[0100] The device (or apparatus) 200 may include an electrode arrangement 202. The electrode arrangement 202 may include a plurality of electrodes for applications of DC (direct current) and RF (radio frequency) signals. The electrode arrangement 202 may include a plurality of RF electrodes (e.g., 2 RF electrodes) 204 for electrical coupling to an RF source 205. The electrode arrangement 202 may further include a plurality of DC electrodes 206 for electrical coupling to one or more DC sources (not shown), with pairs of DC electrodes being arranged on opposite sides of the RF electrodes 204. As a non-limiting example, there may be 11 pairs of DC electrodes 206a, 206b, to 206k, where respective DC signals may be applied to. For example, a first DC signal, VDCI , may be applied to a first pair of DC electrodes 206a, VDC2, may be applied to a second pair of DC electrodes 206b, and VDCII , may be applied to an eleventh pair of DC electrodes 206k. The electrode arrangement 202 may further include a ground electrode (or ground line) 208 for electrical coupling to a ground 210. The ground electrode 208 may be a central electrode. The ground electrode 208 may be arranged adjacent to the RF electrodes 204. The ground electrode 208 may be sandwiched between the RF electrodes 204. A capacitor, C_bypass 211, may be connected between the ground electrode 208 and the ground 210. The RF electrodes 204 and the DC electrodes 206 may be arranged at least substantially perpendicular to one another, while the RF electrodes 204 and the ground electrode 208 may be arranged at least substantially parallel to one another. This may mean that the DC electrodes 206 (or their longitudinal axes) may be arranged along a first axis, while the RF electrodes 204 and the ground electrode 208 (or their longitudinal axes) may be arranged along a second axis, the first and second axes being perpendicular to each other. The RF electrodes 204, the DC electrodes 206 and the ground electrode 208 may be planar electrodes. The RF electrodes 204, the DC electrodes 206 and the ground electrode 208 may be arranged on the same plane. The electrode arrangement 202 may be made of a metal or any suitable conductive material, including, for example, copper (Cu).

[0101] The electrode arrangement 202 may be an arrangement of surface electrodes, where the plurality of RF electrodes 204, DC electrodes 206 and ground electrode 208 may be surface electrodes. This may mean that the electrode arrangement 202 may be provided on the surface of the device 200 or the surface of the support structure 220 of the device 200. The electrode arrangement 202 may be exposed. The electrode arrangement 202 may be supported on an insulator layer 222 (e.g., S1O2,) on the support structure 220. In various embodiments, the support structure 220 may include a silicon-on-insulator (SOI) 224 having a silicon substrate 225, an insulator layer, S1O2 226 on or over the substrate 225, and a silicon layer 227 on or over the insulator layer 226. The support structure 220 may further include a bottom ground element or ground plane 228, made of a metal or any suitable conductive material, including, for example, copper (Cu).

[0102] One or more openings 214 may be provided or defined in the ground electrode 208, where an (optical) output coupler 216 may be exposed or optically exposed through a respective opening 214. Being optically exposed means that an optical signal from the output coupler 216 may be transmitted through the opening 214. Each output coupler 216 may include a grating 218. As shown in FIG. 2D, the output grating 218 may be formed or defined in (or within) the silicon layer 227. Each output coupler 216 may be optically coupled to an output waveguide 217. The output couplers 216 and the corresponding output waveguides 217 may be part of an optical arrangement 340 (see FIGS. 3A and 3B). In various embodiments, a trench 215 may be defined in or for each opening 214, through the insulator layer 222. As may be observed in FIG. 2C, the trench 215 may extend through the ground electrode 208 and the insulator layer 222, and expose the support structure 220. The silicon layer 227 may be exposed and the output coupler 216, with the grating 218, may be (optically) exposed through the trench 215.

[0103] As shown in FIGS. 3A to 3D, the optical arrangement 340, for example, a photonics interposer, may be integrated with the electrode arrangement 202. The photonics interposer 340 may be arranged below the electrode arrangement 202. FIG. 3A illustrates an exploded view of the electrode arrangement 202 and the optical arrangement 340. The photonics interposer 340 may include an (optical) input coupler 342 with an input grating 344. The photonics interposer 340 may further include an input waveguide arrangement optically coupled to the input coupler 342. The input waveguide arrangement may include a plurality of input waveguides 346 optically coupled to the input coupler 342. A plurality of heating elements or heaters 348 may be provided for or with the input waveguide arrangement or the plurality of input waveguides 346.

[0104] During operation, for ion trap operation, one or more ion qubits may be trapped along the ground electrode 208, utilising both the DC and RF fields applied from the DC electrodes 206 and the RF electrodes 204. As a non-limiting example, referring to FIG. 2B, a plurality of ions (two ions are represented as 230a, 230b) may be trapped. Combining the DC and RF fields, a minimal pseudopotential point may be formed where ions 230a, 230b may be trapped. The ground electrode 208 may act as ground to the DC and RF signals or fields. The electrode arrangement 202 may be an ion trap electrode arrangement. The DC electrodes 206 and the RF electrodes 204 may be ion trap electrodes. The DC field may be applied from a portion of the DC electrodes 206 corresponding to the position of the ion 230a, 230b to be trapped. The ions 230a, 230b may be trapped over or above the ground electrode 208.

[0105] For optical addressing of ion qubits 230a, 230b, light emitted from a light source (e.g., laser) may be optically coupled into the photonics interposer 340 through the input grating 344. Light of different wavelengths may be used to address different functions, including but not limited to Doppler cooling/readout, state transition, and re-pumping. The optical addressing may achieve different roles/operations for different wavelengths of light, including changing from <0> to <1> and vice versa, cooling of the ion, repumping, etc. Light of different wavelengths may be used at different times, depending on the operation to be performed.

[0106] Subsequently, the light may propagate and the light intensity may separate equally into individual waveguides 346 with heaters 348 on top of them. Different wavelengths may propagate through different waveguides 346. The separated light may then merge and emitted out from the output grating 218 towards, for example, the trapped ion qubit 230a for optical addressing. Where another function or operation may be required, the light may be directed to, for example, the trapped ion qubit 230b to optically address the ion 230b. The heaters 348 may help in the tuning of the inclination angle of the emitted light along the ground electrode 208 through heat-induced phase change (see FIG. 2B showing tuning of the inclination angle of the emitted light as illutrated by the curved arrow) for optically addressing the plurality of trapped ion qubits 230a, 230b. Thus, it may enable higher flexibility and tunability in optical addressing of the plurality of ion qubits 230a, 230b. The light may separate into several waveguides 346 and undergo individual heating to exert phase change, which results in tuning of inclination angle at the output grating 218.

[0107] It should be appreciated that the plurality of waveguides 346 offering separated paths may be an optional feature, enabling tuning of the inclination angle of the beam coupled from the output grating 218. Without the separated paths, optical addressing may also be realised using one waveguide/path. Separated paths may enable light to propagate to separate waveguides 346. The heaters 348 on separate waveguides 346 may alter the phase of light via heating. By tuning the heaters 348, the phase of the output light beam and its corresponding inclination angle may be tuned. The heaters 348 may be operated to provide different heating levels to achieve tuning of the light beam’s angle. Such an approach is known as optical phase array (OPA), which uses controlled phase change in light to tune its inclination angle. Besides 4 separated paths, light may also be separated into, for example, 8, 16, 32 separated paths to enable fine tunable angle.

[0108] Tuning of inclination angle may allow the approach to individually“shine” laser beam on the desired trap ion, in order to achieve optical addressing. The tuning of inclination angle by phase change is based on derivatives of Snell’s Law. This results in an OPA as described above, which may be used in ion trap optical addressing. Tuning of the inclination angle may also be achieved by changing the refractive index of the materials by applying an external electric field (e.g., via Kerr’s Effect/Quadratic electro-optic effect). However, applying external electric field may present challenges as it may disrupt the DC/RF field for ion trapping. Therefore, heat- induced angle tuning may be preferable.

[0109] The device 200 of various embodiments may be expanded to multiple ion qubits systems. As shown in FIGS. 4A to 4C illustrating schematic top views of devices for trapping ion, the design may be expanded to accommodate 2, 4, and 8 qubits design, and may be further extended to higher number of qubits. FIGS. 4A to 4C show devices 400a, 400b, 400c respectively with electrode arrangements 402a, 402b, 402c and optical arrangements 440a, 440b, 440c. The device 400a may provide two output couplers for optically addressing 2 ion qubits, the device 400b may provide four output couplers for optically addressing 4 ion qubits, while the device 400c may provide eight output couplers for optically addressing 8 ion qubits.

[0110] FIGS. 5A to 5F show, as schematic views, various processing stages of a method for forming a device 500 for trapping ion, according to various embodiments. FIGS. 5 A to 5F illustrate exemplary fabrication steps of the electrode arrangement 502 and the photonics interposer 540 of the device 500.

[0111] Referring to FIG. 5A, a silicon-on-Insulator (SOI) wafer 524 may be used for fabricating the photonics interposer 540. The SOI wafer 524 may include a silicon substrate 525, a buried oxide (BOX) 526, and a silicon layer 527. For optimal performance, preferably, an SOI wafer 524 with 220 nm Si device layer 527 and 2 pm Buried Oxide (BOX) layer 526 may be used. By means of photolithography and dry etching techniques, one or more SOI waveguides (e.g., represented as 517 for one waveguide) and grating couplers (input and output couplers) (e.g., one output coupler 516 is shown in an enlarged view) may be fabricated, as shown in FIG. 5B, in the Si device layer 527. [0112] After forming the waveguides (including waveguide 517) and the couplers (including output coupler 516 with grating 518) that make up the photonics interposer 540, 1 pm of S1O2 layer (Oxide 1) 529 may be deposited, followed by a chemical mechanical polishing (CMP) process to flatten the S1O2 (Oxide 1) layer 529. The structure shown in FIG. 5C, in a cross-section view, may be obtained. Then, heater strips 548 may be patterned on top of the waveguides 346 by means of photolithography and sputtering techniques, as shown in FIG. 5D. As a non-limiting example, the heater strips 548 may be made of titanium nitride (TiN), with a thickness of about 220 nm. After the patterning of the heater strips 548, 6 pm of S1O2 layer (Oxide 2) 522 may then be deposited, followed by CMP process to flatten the S1O2 (Oxide 2) layer 529.

[0113] Thereafter, an electrode arrangement 502 of ion trap electrodes (RF electrodes 504, ground electrode 508, and DC electrodes 506) may be formed and patterned on the Oxide 2 layer 522, with openings 514 defined in the ground electrode 508 over the output couplers 516 with output gratings, as shown in FIG. 5E. As a non-limiting example, copper (Cu) may be deposited for forming the electrode arrangement 502. The Oxide 2 layer 522 exposed from the openings 514 may then be dry-etched to the depth of > 6 pm to form trenches 515, as shown in the enlarged view in FIG. 5F. In other words, thick oxide etching may be carried out at the ground-slot openings 514 to form approximately 6 pm-deep trenches 515.

[0114] FIGS. 6 A to 6B show simulation of ion-trap electromagnetic field and trapping potential, based on RF excitation and DC biasing simulation set-up similar to the electrode arrangement 202 of FIG. 2 A but without the openings 214 to characterise the E-field distribution and pseudo potential. FIG. 6A shows the E-field distribution upon RF excitation. The dashed arrows show the direction of increasing E-field. As may be observed, the E-field has minima along the center ground pad 608, thereby creating axial confinement along the ground line 608. FIG. 6B shows the trapping potential (pseudo-potential) of the designed ion-trap, showing trapping height (trapping potential of near to zero potential (0-meV)) above the center of ground electrode 608 (around 65 pm above the surface of the ground metallization or ground electrode 608). The dashed arrows in FIG. 6B show the directions of increasing potential (meV). In this case, the magnitude of the trapping potential is about 440-meV, which is the amount of kinetic energy needed by the ion to escape this pseudopotential. Ion may accumulate kinetic energy due to stray E-fields that may be stored in the space between the electrodes. [0115] FIGS. 7 A to 7F show analysis of stray E-field distribution inside the ground-slot opening. For clarity, in each of FIGS. 7A, 7B and 7C, the boundary of one opening 714 is overlaid with a dashed rectangle. FIG. 7 A shows the ion-trap design with ground-slot 708a for light through-path opening 714a (WxL) for addressing the ions. FIG. 7B shows the E-field distribution after patterning of ground metallisation 708b with opening 714b of WxL = 40x100 pm² that exposes the silicon dioxide (Si0₂). The magnitude of the stray E-field inside the ground-slot opening 714b is equal to lxlO⁵ - 2xl0⁶ V/m. As may be observed in FIG. 7B, the significant stray E-field (~lxl0⁵ - 2xl0⁶ V/m) may also be stored in the opening 714b of the ground electrode 708b. This amount of stray electric field need to be suppressed. Otherwise, the life time of the trapped-ion may be reduced, which may lower gate operation time available for quantum computation. FIG. 7C shows the introduction of trench 715c into the ground-slot opening 714c into the exposed dielectric to minimise stray E-field. The dashed arrows in FIG. 7C indicate the direction of increasing E-field from within the opening 714c / trench 715c towards the boundary of the ground electrode 708c. By increasing path length for the landing of fringe E-field, the strength of the stray electric field may be reduced. The stray E-field may drop by 10⁴ - 10⁶ with the introduction of trench 715c with a depth of about 6 pm. In other words, a trench depth equal to 6 pm or higher may suppress the stray E-field in the order of 10⁴ - 10⁶ times.

[0116] FIGS. 7D and 7E show respectively the equivalent capacitance of the ion-trap and the Q factor of the ion-trap, without opening (“Ref’), with ground slot opening (“GND-Slot”) and with the addition of trench on S1O2 (“S1O2 Trench”). In one embodiment, the trench may have a depth of at least 6 pm. The trench and the ground slot opening may have a width of at least 5 pm and a length of at least 5 pm. As may be observed in FIG. 7E, the ground slot opening and the addition of trench on S1O2 may improve the Q factor from 156 to 278 (78%), which may result in more efficient RF excitation, less leakage energy, lower power dissipation, and more efficient trapping potential. FIG. 7F shows the trapping potential (pseudo-potential) of the designed ion-trap with a 6 pm trench opening 715f through S1O2.

[0117] FIGS. 8A to 8E show simulation of the effect of depth of S1O2 trench opening to stray E- field density to illustrate the variation of stray E-field inside the window opening of the ground electrode as a function of the depth of the S1O2 trench. For clarity, the boundary of the respective openings 814a, 814b, 814c, 814d, 814e is overlaid with a dashed rectangle. FIG. 8A shows the result for an opening 814a in the ground electrode 808a but with no S1O2 trench, FIG. 8B shows the result for an opening 814b with a S1O2 trench 815b of a depth of about 1 pm in the ground electrode 808b, FIG. 8C shows the result for an opening 814c with a S1O2 trench 815c of a depth of about 2 pm in the ground electrode 808c, FIG. 8D shows the result for an opening 814d with a S1O2 trench 815d of a depth of about 4 pm in the ground electrode 808d, while FIG. 8E shows the result for an opening 814e with a S1O2 trench 815e of a depth of about 6 pm in the ground electrode 808e which illustrates significant reduction in stray E-field. The dashed arrows in FIG. 8E indicate the direction of increasing E-field from within the opening 814e / trench 815e towards the boundary of the ground electrode 808e. As may be observed, the density stray E-field gradually diminishes as the depth of the S1O2 trench increases. In this non-limiting example, the density of the stray E-electric field may be significantly reduced to a factor of 10⁴ - 10⁵ when the trench depth is set to 6 pm deep. It may be observed that the density of the stray E-field is inversely proportional to the depth of the trench.

[0118] The window opening of the ground electrode may influence the primary E-field along the confinement axis, which is used to trap the ion. The larger the opening of the ground electrode, the weaker the primary E-field and this may lead to lower pseudopotential for ion-trapping. On the other hand, the output of laser grating coupler efficiency may be lower if the area of window opening gets narrower. FIGS. 9 A and 9B show simulation of the effect of openings to the main E-field for ion-trapping. The boundary of respective openings 914a, 914b is overlaid with a dashed rectangle. FIG. 9A shows the result for an opening 914a of approximately of 20x20 pm² with a S1O2 trench 915a of a depth of about 6 pm in the ground electrode 908a, while FIG. 9B shows the result for an opening 914b of approximately of 10x10 pm² with a S1O2 trench 915b of a depth of about 6 pm in the ground electrode 908b. Based on the results, to gain a preferred or optimised trade-off between both specifications, a (window) opening of a size of 10x10 pm² to 20x20 pm² may be set to achieve acceptable laser grating efficiency of about 18% - 27% while obtaining primary E-field strength of higher than about 5xl0⁵ V/m and supressing the stray E- field inside the window opening to a value of about 10 - 50 V/m.

[0119] FIGS. 10A to 10D show simulation of the effect of window opening size to light propagation, illustrating light propagation from the grating coupler 1018a, 1018c, 1018d towards the trapped ion. The ion may be trapped at ~40 pm height from the surface of the copper (ground) electrode, as shown in FIG. 10A which illustrates propagation of light towards 40 pm height via a 20x20 pm² opening. The power efficiency distributions of the light at ~40 pm height for various copper electrode openings are shown in FIG. 10B, illustrating localised efficiencies at ~40 pm height for various opening sizes. It may be seen that a 5x5 pm² opening exhibits lower efficiency as compared to larger openings (10x10, 20x20, and 40x40 pm²). This may be due to the blocking of coupled light by the copper electrode. Magnified views (referring to the portion within the dashed rectangle indicated in FIG. 10A) of light propagation from grating couplers 1018c, 1018d with copper electrode opening sizes of approximately 5x5 pm² and 40x40 pm² are shown in FIGS. IOC and 10D. As may be observed in FIG. IOC, for a 5x5 pm² opening, coupled light may be blocked by the copper electrode layer, resulting in lower power efficiencies at ~40 pm height as compared to its 40x40 pm² counterpart as shown in FIG. 10D. Nevertheless, the minimum efficiency to enable quantum computing operation in trapped ion qubits is in ~pW range. For a laser source with -10¹ mW power range, 0.01% power efficiency may be sufficient for optical addressing. Thus, the opening size may be at least 5x5 pm².

[0120] FIG. 11A shows the results for ion trap performance, without any opening through the ground electrode. The inset shows a CCD image of a trapped ion (indicated by an arrow). As may be observed, the ion was trapped continuously for > 4 hours. In other words, without an opening, the ion trap design managed to trap the ion for more than 4 hours. FIG. 1 IB shows the results for ion trap performance, for openings of various sizes through the ground electrode. FIG. 11C shows results for the trap height (or depth) of devices with RF electrode widths of 20 pm (“V20”), 40 pm (“V40”) and 80 pm (“V80”). In FIG. 11C, the double -headed arrows show the respective trap depths of V20, V40, V80. The trap depth may determine the trap performance (e.g., lifetime). Trap depth is a physical quantity which is indicated by the pseudopotential around the trapped ion. Ions are trapped at trapping points, where the pseudopotential value is minimal. Trap depth, therefore, may refer to the pseudopotential difference between the trapping point and its surrounding. The higher the trap depth of a trap, the more“secured” the ions are in their trapping points. From simulation, traps with openings have similar trap depth as a trap without opening, and, thus similar performance may be anticipated. This means that incorporating one or more openings along the (ground) electrode may not or does not affect the trap depth, or the “secureness” of ions trapped at the trapping points.

[0121] Various embodiments may provide for electro-optics (EO) integration of planar ion trap and silicon photonics for optical addressing in quantum computing. As will be described below, feasibilities of electro-optical integration for ion-trapping in quantum computing are demonstrated. The photonics devices may exhibit -33% coupling efficiency and 1.12 dB/cm propagation loss. Further, wide positional tolerance of ± 10 pm may be obtained for optical addressing of trapped ion.

[0122] To enhance the scalability of the EO integrated quantum computing device, in various embodiments, openings on the planar electrodes may be provided to facilitate light routing from the grating coupler for optical addressing of trapped ion, as shown in FIG. 12A which illustrates a planar view of a fabricated device 1200 for trapping ion and a schematic diagram of a portion of electro-optical integration in the device 1200. The device 1200 may include an optical arrangement (e.g., photonics interposer or photonics device) 1240 and an electrode arrangement 1202 over the optical arrangement 1240. The electrode arrangement 1202 may include a pair of RF electrodes 1204, pairs of DC electrodes 1206a, 1206b, 1206c (similar to 206a, 206b, to 206k, FIG. 2A), and a ground electrode 1208. An opening 1214 may be defined in the ground electrode 1208. The optical arrangement 1240 may include an output optical coupler 1216 with a grating 1218 that may be optically exposed through the opening 1214, and an output waveguide 1217 optically coupled to the optical coupler 1216. Coupled light (represented by dashed arrow 1231) from the optical coupler 1216 may be used to address ion 1230 that is trapped by electric field generated by the electrode arrangement 1202. The fabrication of the device 1200 may be carried out by CMOS technology on 12-inch (>750 W·ah) silicon substrate. FIG. 12B shows a cross-sectional view of the fabricated device 1200. Referring to both FIGS. 12A and 12B, instead of gold electrodes which are not CMOS-compatible, the electrode arrangement 1202 may be made of copper (Cu) with gold (Au) surface finish, which is a standard back-end process in commercial CMOS fabrication. The electrode arrangement 1202 is formed over a support structure of a silicon (Si) substrate and a layer of S1O2 over the Si substrate.

[0123] As a non-limiting example, the device 1200 may be used for ⁸⁸Sr⁺ ion. By using a combination of external laser sources of various wavelengths, one single ⁸⁸Sr⁺ ion may be trapped using the fabricated structure, as displayed in the CCD image (ion indicated by an arrow) shown as an inset of FIG. 12C. To determine the z-position of the trapped ion, pseudopotential simulation may be carried out along z-axis. From FIG. 12C, it may be estimated that the ⁸⁸Sr⁺ ion may be trapped at -76 pm height above the Cu/Au electrode. The obtained position of the trapped ion may be used for the development of photonics devices in optical addressing of the trapped ⁸⁸Sr⁺ ion.

[0124] In terms of the silicon photonics devices (e.g., 1240) for optical addressing, the fabrication of the silicon photonics devices (including, e.g., waveguide and grating coupler) may be carried out on an 8-inch silicon-on-insulator (SOI) substrate (e.g., having 220 nm device layer, 2 pm BOX layer). Optimisation of the grating coupler’s design (e.g., taper shape, radius, duty cycle, pitch size, etc.) may be carried out, with the results shown in FIGS. 13A and 13B. FIGS. 13 A and 13 B show respectively the coupling loss of the grating coupler of various taper shapes and radii. Upon optimisation, a coupling efficiency of -33% may be achieved, as shown in FIG. 13C. At the same time, propagation loss of waveguide fabricated on the same platform may be determined, where mean propagation loss of 1.12 dB/cm may be obtained, as shown in FIG. 13D.

[0125] Finite-difference time-domain simulation may be carried out to determine the beam profile of the coupled light towards the trapped ion (-76 pm height, see FIG. 12C) for various opening sizes on the Cu/Au electrodes. FIG. 14A shows the localised efficiency along y-axis at 76 pm height for various opening sizes (inset: efficiency distribution in x-y plane), while FIGS. 14B and 14C show respectively the efficiency distribution in y-z plane for a 5x5 pm² opening and a 20x20 pm² opening. As shown in FIG. 14A, an electrode with a 5x5 pm² opening exhibits lower optical power on the trapped ion’s height as compared to 15x15 pm² and 20x20 pm² openings. This may be attributed to the partial blocking of Cu/Au electrode on the coupled light or laser, limiting its propagation towards the ion (see FIG. 14B). By using 0.01 efficiency as a reference or benchmark for quantum computing operation, coupling through 15x15 pm² and 20x20 pm² openings may exhibit similar positional tolerance of ± 10 pm along y-axis. To prevent or minimise compromising of ion-trapping performance, the opening size may be kept smaller than 20x20 pm² for optimal performance.

[0126] As described above, the obtained measurement simulation outcomes demonstrate the feasibility of silicon photonics devices in the optical addressing of trapped ion qubits, and the EO integration in quantum computing devices on wafer-scale platforms using commercially- available CMOS technologies. At the same time, the routing of coupled light from various opening sizes may be scalable to laser sources of various wavelengths, corresponding to specific quantum computing operations. [0127] Various embodiments may provide for development and integration of silicon photonics interposer for quantum computing system, including, for example, the design and optimisation of photonics interposer for addressing trapped ion in a quantum computing system. As will be described below, a surface electrode ion trap for the confinement of ⁸⁸Sr⁺ ion qubit may be introduced. For the computing operation of the ion qubit, a silicon photonics interposer having waveguide and grating couplers may be developed, built on commercial silicon-on-insulator (SOI) platform to be integrated with the ion trap. 1,092 nm light beam may be coupled into the input coupler and propagates along the waveguide, which may eventually be directed towards a trapped ⁸⁸Sr⁺ ion qubit. Considering the coupling efficiency of both input and output couplers, the power efficiency reaching the trapped ion may be estimated to be ~ 16%, and the output 1 ,092 nm light may be coupled onto the trapped ion qubit for addressing. From the experimental and simulation outcomes, it may be expected that the silicon photonics interposer couples 1092 nm light towards the trapped ⁸⁸Sr⁺ ion qubit with -20% coupling efficiency.

[0128] For ion trap-photonics integration, various embodiments may provide for integration between planar electrode ion trap and the photonics interposer, similar to the device 1200 of FIG. 12A. The ion trap (electrode arrangement) may adopt a 5-wire design combining both DC and RF electrodes, The photonics interposer may include an input coupler, a waveguide, and an output coupler, fabricated underneath the ion trap electrodes. The overall integration maybe carried out on commercial SOI platform with copper through silicon via (TSV) as the interconnects.

[0129] To perform any computing tasks such as Doppler cooling/readout, state transition, repumping, a light source of specific wavelength may be directed into the photonics interposer through the input coupler. The light beam may then propagate along the waveguide and couple towards the trapped ⁸⁸Sr⁺ ion qubit. To facilitate the coupling of light beam towards the trapped ion, an opening may be created on the ion trap.

[0130] For the silicon photonics interposer, light sources of 422, 674, and 1092 nm may be utilised for Doppler cooling/readout, state transition, and repumping, respectively, for the computing operation of ⁸⁸Sr⁺ qubit. Among the required light sources, 1092 nm may be selected as the preliminary wavelength for integration due to its higher transmission in Si which may enable operation on commercial 220 nm layer silicon-on-insulator (SOI) platforms. [0131] To investigate the efficiency of the grating coupler (including, for example, grating coupler loss), an input grating coupler is fabricated using electron beam lithography on 220 nm device layer on a SOI substrate. FIG. 15 A shows scanning electron microscopy (SEM) images of the fabricated input grating coupler. Its coupling efficiency for wavelength between 1470 - 1560 nm may be measured. At the same time, the coupling efficiency may also be simulated with Lumerical FDTD (finite-difference time-domain) solution to compare the simulation and experimental loss, with the results as shown in FIG. 15B. From FIG. 15B, the simulation- experimental deviation of coupling loss may be deduced to be 5 - 18%. By using this as a reference or benchmark, the efficiency of the grating coupler may be designed and optimised for a light source of 1092 nm for quantum computing operation, as will be discussed below.

[0132] Non-limiting examples of optimisation of the photonics interposer will now be described. FIGS. 16A and 16B show the simulated power distribution of input and output couplers respectively. From FIG. 16A, it may be seen that light beam may be coupled into the photonics interposer through the input coupler, then propagating along the waveguide. From the simulation results, a coupling efficiency of -20% may be determined or anticipated from the input coupler. On the other hand, FIG. 16B shows the simulated power distribution of the output coupler. From the simulation, it may be seen that light beam may be coupled from the output coupler and directed towards the trapped ion (e.g., a ⁸⁸Sr⁺ ion). From the simulation results, a coupling efficiency of -80% may be determined or anticipated from the output coupler. From the pseudopotential simulation carried out on the ion trap, the ion may be estimated to be trapped at -40 pm height (see, for example, FIG. 10A and related description). At the same time, the coupled-out laser may be estimated to be directed -22° from the normal. Utilising the estimated -40 pm height of the trapped ion, placing the output coupler -16 pm from the centre of the ion trap electrode may enable the light to shine onto the trapped ion, hence performing the desired computing tasks.

[0133] As described above, a photonics interposer may be developed and built on commercial SOI platform for quantum computing system. A 1092 nm light beam may be coupled into the input coupler and which may propagate along the waveguide, which eventually may be directed towards a trapped ⁸⁸Sr⁺ ion qubit. Considering the coupling efficiency of the input coupler and the output coupler, the overall power efficiency of laser hitting the trapped ion qubit may be estimated to be -16%. [0134] Different support structures or substrates may be used in various embodiments for forming the devices for trapping ion, including but not limited to high resistivity silicon (Si), silicon (Si) with grounding plane and glass. A performance comparison of high resistivity silicon (Si), silicon (Si) with grounding plane and glass as substrate for ion trap for quantum information processing will now be described below.

[0135] Attributing to its scalability and flexibility, surface electrode (SE) ion trap may possess promising potential in achieving large-scale quantum information processing (QIP). Co-planar metal electrodes may induce a minimum electric field point, in which ions may be dynamically trapped. In order to reduce the power dissipation and undesired heat yield, a substrate with high resistivity and low loss tangent may be required. Therefore, substrates such as sapphire, fused silica and PCB may be utilised. However, there are challenges in that the complex fabrication process may limit their further application in advanced SE ion trap featuring several hundreds of electrodes. To address this issue, the use of silicon as a substrate may be explored. By leveraging CMOS-compatible fabrication of silicon substrate, advanced interconnections such as through silicon via and multilayer metallisation may be employed. Besides, electrical and optical devices (e.g., passives and photodetector) may be monolithically integrated with ion trap, which may be suitable for scalable QIP. To minimise the RF loss issue in silicon substrates, both high-resistivity (> 750 Qm) silicon and silicon with grounding plane may be explored. Meanwhile, due to the development of glass fabrication technology in commercial foundries, glass may be a suitable substrate in microelectronics, especially for high frequency devices. Thus, ion trap on glass substrate (300 mm) may also be explored. Performance comparison of ion traps on these three different substrates (denoted as HR (high resistivity), grounding and glass traps respectively) may be conducted, as described below.

[0136] FIGS. 17A to 171 show top views of devices for trapping ion on various substrates, and scanning electron microscopy (SEM) images illustrating magnified views of a portion of the devices and cross-sectional views of the devices. The devices include respective electrode arrangements having a pair of RF electrodes 1704a, 1704d, 1704g, a pair of DC electrodes 1706a, 1706d, 1706g, and a ground electrode 1708a, 1708d, 1708g.

[0137] Referring to FIGS. 17A to 17C, in the fabrication process of the HR trap (having high resistivity silicon), the insulation layer (S1O2) between the silicon substrate and the metal electrodes (e.g., Cu/Au) may be patterned with the same geometry as the electrodes to avoid or minimise undesired dielectric charge. Referring to FIGS. 17D to 17F, for the grounding trap (having silicon with grounding plane), a 1 pm Cu damascene process may be conducted for the fabrication of the grounding plane (Cu (ground)), which may have a mesh structure (see, for example, FIG. 17E illustrating the Cu mesh structure in the background) to release the high stress due to CTE (coefficient of thermal expansion) mismatch. Referring to FIGS. 17G to 171 for the glass trap, electrode patterning (Cu/Au) may be carried out on the glass directly without the need of an insulation layer (e.g., S1O2) therebetween. Besides, based on widths of 20 pm, 40 pm and 80 pm for the radio frequency (RF) electrodes 1704a, 1704d, 1704g, three size variations of ion traps on each substrate may be designed.

[0138] For forming the overall devices for trapping ion, integrated photonics interposers may be provided, and openings may be defined on the ground electrodes 1708a, 1708d, 1708g.

[0139] FIGS. 18A to 18D show results for leakage current, capacitance, insertion loss (S21) and power respectively for devices on high resistivity silicon (“HR”), silicon with grounding plane (“grounding”) and glass substrates with various RF electrode widths (20 pm (“V20”), 40 pm (“V40”) and 80 pm (“V80”)). FIG. 18A shows that the leakage current between the RF and grounding electrodes of glass traps may be as high as 10 ⁸A, limiting the maximum RF voltage that may be applied. On the other hand, it is found that glass traps have the smallest parasitic capacitance as may be observed in FIG. 18B and superior RF performance as may be observed in FIGS. 18C and 18D. For the HR traps, despite low leakage current, the insertion loss is high, especially for larger traps. However, the grounding traps may reduce this loss by -lOdBm and maintain the low leakage current. To further improve RF performance of the grounding traps, the large parasitic capacitance may be reduced. Improvements such as increasing S1O2 thickness and/or reducing surface area may be taken. From the ion trapping experiment, two ⁸⁸Sr⁺ ions have been successfully trapped in a glass trap, where similar ion trapping test may be carried out on grounding trap. These results indicate the preferred routes to use silicon as an ion trap substrate for scalable QIP.

[0140] Various embodiments may provide one or more surface electrode ion-traps with ground structure for minimising dielectric loss in a silicon (Si) substrate. A surface electrode ion trap is one of devices in modern ion trapping apparatus to host ion qubits for quantum computing. Surface traps fabricated on silicon substrate have the versatility for complex electrode fabrication with 3D integration capability. However, Si induced dielectric loss has to be considered in trap design and a ground structure may be incorporated to mitigate this concern. As a non-limiting example, a surface electrode ion trap may be fabricated using standard copper (Cu) back end process on a 300-mm silicon (Si) wafer platform. One or more processes may be employed, including but not limited to: (1) the use of electroplated Cu/Au (copper/gold) layers using microfabrication techniques to form the surface electrodes, (2) the use of dry etching to form a fine gap oxide trench between the electrodes for reducing the charge induced stray electric field,

(3) the use of Cu mesh ground structure to enhance the resonance performance of the trap, and

(4) process optimisation to minimise the undercut in the Cu/Au electrodes. As will be described below, electrical properties determined from the fabricated ion trap show leakage current failure rate of < 10% on a 300-mm wafer. Two trap types designed with RF line widths of, for example, 80 pm and 40 pm are evaluated for their resonance performance with and without a ground plane. By incorporating a ground plane into the ion trap, resonance performances may be improved with output power increment of 11 and 13 dB and Q factor increment of 2 and 6, for the corresponding trap types.

[0141] Ion trapping devices may possess features for realising scalable quantum computers. By utilising combinations of static (DC) and radio-frequency (RF) fields, ion qubits may be physically confined in space (e.g., vacuum space) and quantum computing operations may be performed by transiting the internal atomic energy levels of the qubits using light sources (e.g., lasers) with some specific wavelengths. Ion trap devices may offer capability in precise manipulation of multiple ion qubits with high fidelity and long coherent time. In an ion trap quantum computing device, the ion qubits may be physically trapped by a set of DC and RF electrodes, which generate the trapping electric fields to confine the ion in X, Y, and Z directions. The ion qubit may be trapped at a position at the minimal pseudopotential, as illustrated in FIG. 19. FIG. 19 shows result of finite element modeling of electric pseudopotential in a surface trap with RF line width of 40 pm, illustrating pseudopotential contour in XZ-plane at Y=0. The dashed arrows show the direction of increasing pseudopotential. Trapping ion height is ~ 40 pm above the trap surface (trapped ⁸⁸Sr⁺ ion with 200 V applied RF amplitude and 2p x 56 MHz drive frequency). The trapped ion position may be determined by surface electrode geometry, where ion height may depend on RF line (electrode) width and the spacing between two RF lines (RF electrodes). [0142] As a non-limiting example, a surface trap (surface electrodes) may be fabricated using a 300-mm Si wafer in standard foundry conditions. A Cu backend process may be employed to fabricate thick and flat trap electrodes. A S1O2 insulation layer may be provided between the electrodes and may be dry etched to reduce the electrostatic charges induced stray fields. To address the parasitic coupling induced by Si substrate, a ground plane may be designed and fabricated in the ion trap. The fabricated traps may be tested to examine their compliance with the required resonance performance for proper operation of the ion-trap.

[0143] Surface electrode ion trap fabrication may be accomplished on standard 300-mm Si wafer platform. Four types of traps are designed, with different RF line widths and spacings, which may result in different trapping ion heights. TABLE 1 lists the trap geometrical specifications with simulated ion heights for each trap type.

TABLE 1 : Trap geometries and simulated ion heights

[0144] The trap fabrication may include the following process steps: (1) S1O2 insulation layer patterning and dry etch, and (2) Cu/Au metal layer patterning and electroplating. FIGS. 20A and 20B show scanning electron microscopy (SEM) images of a portion of the patterned S1O2 pads 2022 over a Si substrate 2025 in plane view and tilted view respectively. The insulation layer may be formed by 3 pm thick low-stress plasma-enhanced chemical vapor deposition (PECVD)-deposited S1O2. S1O2 in the electrode gap area 2090 may be patterned and dry-etched to reduce the effective exposed dielectric surface to the ion and the stray electric field around ion trapping region.

[0145] Cu/Au electrodes may be subsequently aligned, patterned and electroplated on top of the S1O2 pad 2022. FIG. 20C shows an optical microscopy image of the overall Cu/Au electrode pattern in plane view, while FIGS. 20D and 20E show scanning electron microscopy (SEM) images of a portion of the fabricated electrodes over the Si substrate 2025 in plane view and tilted view respectively. As may be observed in FIGS. 20C to 20E, the electrode arrangement may include a pair of RF electrodes 2004, a pair of DC electrodes 2006, and a ground electrode 2008. The metal electrodes 2004, 2006, 2008 may be recessed by 1 pm to the S1O2 pads 2022. Au may be directly deposited on the Cu layer as surface passivation layer to control the amount of Cu oxidation. The inter-diffusion of Au and Cu may be studied by X-ray photoelectron spectroscopy (XPS) analysis which will be described further below.

[0146] FIG. 21A shows a trap electrode having four layers (S1O2, Ti, Cu, Au) while FIG. 21B shows the inter-electrode gap area. In FIG. 21B,“gapl” refers to the gap between Au portions of the electrodes,“gap2” refers to the gap between Cu portions of the electrodes, while“gap3” refers to the gap between the S1O2 pads 2022. The designed and measured dimensions of the electrode layer and gap are summarised in TABLE 2.

TABLE 2: Layer and gap dimensions of trap electrodes

[0147] The S1O2 layer thickness may be optimised to be ~3 pm, as a trade-off between acceptable stress-level for full-wafer fabrication, and sufficient thickness to address the parasitic capacitance issue in the Si substrate 2025. Ti/Cu may be deposited as a barrier layer and seed layer for Cu electroplating. A thick Cu layer of > 3 pm may be electroplated to further hinder the ion sight to the exposed dielectric and also serves as an effective thermal dissipation layer to reduce the trap heating. To approximate the“gapless plane” trap geometry, the minimum inter- electrode gap in the trap center may be kept at 5 pm. From FIG. 2 IB, a slight undercut in the Cu layer may be observed due to the etching of Cu sidewalls during Cu seed wet etching process. Considering “gapl” and“gap2” in FIG. 21B, a prominent Cu undercut to Au of about 1.4 pm may be approximated. This generates the Au overhang structure which may be mechanically unstable and may cause electrical bridging issue between the electrodes. Further process improvement may be carried out to minimise the undercut width which will be described further below.

[0148] A thin layer of Au may be electroplated on top of base Cu as the surface finish layer to prevent or minimise Cu oxidation in atmospheric environment. Metal oxidation need to be minimised or avoided on the electrode surface as it may induce unwanted charges and stray electric fields, which may affect the ion trapping performance. To investigate the chemical states of the top surface metal and the interface composition of Cu-Au electrode, XPS (X-ray photoelectron spectroscopy) technique may be employed to study the layer information of Au/Au-Cu interface/Cu by using 5 keV monoatomic Ar⁺ etching cycles to etch a pad area of 1.5 mm x 1.5 mm for 54 cycles with an etching rate of 300 s/cycle.

[0149] FIG. 22 shows the results of XPS core-level spectra of Au 4/, Cu 2 p on the corresponding metal layers before and after Ar⁺ etching cycles. Au 4/ and Cu 2 p major peaks are chosen to fit the XPS models. Peak-fitting may be done by considering the doublets as a pair constrained by the full-width half maximum and the intensity ratio, in order to extract information such as binding energy and the area under the curve. From the spectra, Au 4 f and Cu 2 p are the main composition on the surface before and after etching. However, a small amount of Cu species (< 3 at%, Cu²⁺:Cu⁺ = 1.28: 1.00) may be detected on the initial surface, which is not found on the surface after the first etching cycle. The presence of these Cu species may be attributed to environmentally-induced contaminations where Cu ions in the electroplating bath may be the sources of Cu traces on the Au surface.

[0150] On the other hand, the Au and Cu evolution in terms of etching time is plotted in FIGS. 23A and 23B respectively, illustrating the evolution of Au 4/ doublets and Cu 2 p doublets respectively in terms of the etching time. In the first ~6000s of etching time, Au doublets of 4/5/2 and 4/7/2 are the main spectra peaks. As the etching continues, Cu doublets of 2pm and 2// 2/3 gradually emerge to overtake the Au doublets as the main spectra peaks. An initial energy drift of Au doublets to the higher binding energy is also observed in the first few cycles, which become relatively“stable” in the subsequent cycles. The energy drift is not detected on the Cu doublets. In FIG. 23C showing the concentration profiling of Cu 2 p and Au 4/in terms of etching time (the Au-Cu interface with Cu 2 p and Au 4/ overlapping area is shown in shade), the concentration of Au and Cu elements may be calculated by relying on relative sensitivity factor (RSF) values and the area under the curves for the peaks. The Au-Cu overlapping in the etching period of -6000 s to -10000 s is marked as the Cu-Au interface. The inter-diffusion of Cu and Au may be noticeable in the interface area with a 5-order of magnitude change in the ratio between Au and Cu. From the plot of FIG. 23C, it may be estimated that the distance between the Cu-Au interface area and the top Au surface is about 1.5 times of the distance of the whole interface area, which may be considered as a sufficiently thick layer to prevent or minimise Cu diffusion onto Au surface.

[0151] The design of a ground plane underneath the ion trap electrodes is shown in FIGS. 24A and 24B. FIG. 24A shows a schematic cross-sectional view of trap electrodes, in the form of RF electrodes 2404, ground electrode 2408 and a pair of DC electrodes 2406a, with a Cu ground 2480, while FIG. 24B shows a layout of the trap electrodes, including a pair of RF electrodes 2404, ground electrode 2408 and pairs of DC electrodes 2406a, 2406b, 2406c, over the ground plane 2480. The Cu ground 2480 may have a mesh structure 2480a. The ground plane 2480 may be formed in a S1O2 layer 2426 over a Si substrate 2425. The ground plane 2480 may be inserted between the Si substrate 2425 and the S1O2 layer 2422 to shield Si-induced RF loss. Referring to FIG. 24A, a silicon nitride (S13N4) 2481 may be provided between the Cu ground plane 2480 and the S1O2 layer 2422. The RF electrodes 2404 and the DC electrodes 2406a, 2406b, 2406c may be made of a Cu layer 2482 with a surface Au layer 2483. A titanium (Ti) layer 2484 may be provided between the S1O2 layer 2422 and the Cu layer 2482. As shown in FIGS. 24A and 24B, the mesh structure 2480a of the Cu ground 2480 may be provided on non- RF area to facilitate large area metal fabrication, and the Cu ground plate (with no mesh structure) 2480b may be provided in the central RF line area (with RF electrodes 2404). A bond pad 2488 may be designed on the top left corner of the ground layer 2480 for wire connection purpose. It should be noted that the ground layer 2480 may further reduce the exposed dielectric surface in the inter-electrode gap area and, therefore, minimise the stray field effect. While not shown, a photonics interposer layer may be provided within the S1O2 layer 2426. One or more openings may be provided along the ground electrode 2408.

[0152] For Cu ground fabrication, as a non-limiting example, Cu single damascene process may be used to fabricate the ground plane 2480. First, S1O2 layer of 2 pm thick may be deposited by PECVD on a 300-mm, p-doped, high-resistivity Si wafer (resistivity > 750 W-cm). The mesh structure of 15 pm wide strips with 15 pm separation in both X and Y direction may be patterned and etched for Cu filling. The mesh structure may be designed to meet the metal density constrains for effective chemical-mechanical polishing (CMP) steps.

[0153] FIGS. 25A to 25D show optical images relating to the fabrication of a copper (Cu) ground plane. FIG. 25A shows an image of a part of Cu ground 2580 with mesh structure 2580a fabricated with single damascene process, after CMP. As shown in FIG. 25B, an insulating S1O2 layer for the trap electrodes may then be deposited and patterned on top of the ground layer 2580 to form S1O2 pads 2522. FIG. 25C shows an image after trap electrode fabrication, where electroplated Cu/Au electrodes (RF electrodes 2504, ground electrode 2508, DC electrodes (not shown)) are formed on the S1O2 pads 2522. FIG. 25D shows an overall view of the trap geometry, having RF electrodes 2504, DC electrodes 2506a, 2506b, 2506c and a ground electrode 2508, with an underneath ground plane 2580. The ion trap shown in FIG. 25D corresponds to the trap type“Trap-20” shown in TABLE 1.

[0154] As described earlier, Cu undercut and overhanging Au may cause electrical bridging between the electrodes, which may cause adverse effects on the functionality of the ion trap. Process optimisation may be conducted by adjusting the Cu seed etching time. By fully opening the seed layer while minimising the wet etching time, the undercut of Cu to Au layer may be reduced to ~ 0.2 pm, as shown in FIGS. 26A and 26B. FIG. 26 A shows an SEM image of a portion of the trap electrodes (RF electrodes 2604, ground electrode 2608) with a ground plane 2580 in top view. A meshed structure 2580a of the ground plane 2580 may be observed. FIG. 26B shows an SEM image, in cross-sectional view, of a portion with different layers of electrode materials, insulation and ground. As may be observed, the electrodes may include Cu 2582 and Au 2583 on top of Cu layer 2582. The Cu layer 2582 may be formed over a S1O2 layer 2522 with a Ti layer 2584 therebetween. There is a Cu ground layer 2580 with a S13N4 layer 2581 in between the ground layer 2580 and the S1O2 layer 2522. There is a support structure of a S1O2 layer 2526 over a substrate 2525. It may be observed in FIG. 26B that some voiding area of the Cu ground layer 2580 under the edge of S1O2 pads 2522 exists due to seed layer etching process. However, the continuity of the ground layer 2580 is not compromised due to the minimised etching time and the sufficiently thick Cu layer. The designed and measured dimensions of layer thickness and inter-electrode distances are given in TABLE 3 below. To incorporate a ground electrode in the ion trap, it may be observed that three more layers may be added in this fabrication, with the S1O2 layer 2526 under the Cu ground 2580, the Cu ground layer 2580 and the S13N4 layer 2581 using well-established foundry processes. By optimising the Cu undercut, the leakage current performance of the trap die across the wafer may be improved.

TABLE 3: Layer and gap dimensions of trap electrodes with ground layer

[0155] The full-wafer leakage current mapping is illustrated in FIG. 27 and the good die percentage of the leakage current < 10 ⁷ A may be increased to > 90%, compared to -70% for known devices of similar trap type.

[0156] RF resonator test may be conducted to evaluate the required resonance performance of the fabricated traps for realising ion trapping. FIG. 28 shows a set-up of RF (radio frequency) resonator test with ion trap 2800. The trap 2800 may be connected as a capacitor to an external inductor (not shown) to form a series-connected LCR resonator circuit to step up the input voltage to the required RF trapping voltage (-200 V). To form the resonator circuit, the trap 2800 is packaged in a ceramic pin grid array (CPGA) package and connected to a toroidal inductor 2894 which is contained in a metal shielding box. An input RF power of -10 dBm may be supplied by a signal generator 2892. A set of capacitor dividers, first capacitor Cl 2898a and second capacitor C2 2898b (with C1:C2 = 1 :20), may be connected to the external inductor (not shown) and a signal analyzer 2896 for suppressed power readout. To generate the resonance curve, a linear frequency sweep may be conducted from 10 to 100 MHz with a step size of 1 MHz. The resonance curve may be compared to a reference curve generated by a standard capacitor of 3.3 pF to address the required resonance performance. [0157] For determination of resonance performance, two types of traps, with RF line (or RF electrodes) widths of about 40 and 80 pm (denoted as "trap-40" and "trap-80" respectively in

TABLE 1), respectively, without and with ground plane, may be examined. The resonance curves obtained are shown in FIG. 29, and compared to a reference capacitor ("Cap" in FIG. 29). The resonance frequency, fo, and the quality, Q factor (i.e., the sharpness of the curve), may be obtained from the curves by the peak power frequency and 3 dB bandwidth. The reference curve generated by a 3.3 pF standard capacitor ("Cap") is also included in the plot for comparison. The resonance results are given in TABFE 4.

TABFE 4: Resonant frequency and quality factor with/without ground

[0158] By comparing the same type of traps without and with the ground plane, there is Q factor increase of 2 and 6 for trap-40 and trap-80, respectively. The Q factor values are close to the reference Q-factor of 18.5 generated by the capacitor. Q factor is one of the parameters to be considered in the resonator circuit, because it is proportional to voltage gain on the trap electrodes and reversely proportional to power dissipation in the substrate. With a higher Q factor, the peak power of the traps with the ground plane also increases by 13 and 11 dB for trap-40 and trap-80, respectively. However, the power peak of trap-80 is still low compared to that of the reference capacitor. This may be attributed to: (1) the larger electrode area which may induce a larger parasitic capacitance, and/or (2) limited shielding effect from the ground plane on larger electrode. This observation will be described below.

[0159] Si is a high-loss material due to its finite resistivity, which may induce additional parasitic capacitance through metal-insulator-silicon structure and Si substrate itself. The parasitic components may reduce the Q factor of the trap, which may limit the required voltage step-up in the resonator circuit. To effectively eliminate or minimise the two parasitic components induced by Si, the ground plane may be inserted between Si and S1O2 insulation layer. Then, the parasitic capacitance may (only) be induced by metal-insulator-metal (ground) structure which may be dependent on S1O2 layer thickness. FIGS. 30A and 30B show the simulated insertion losses (S21) respectively for trap-40 and trap-80 types, without (results 3070a, 3072a) and with ground plane (results 3070b, 3072b). In FIG. 30B, results 3072c of further improvement of S21 for trap-80 by thickening the insulation layer 2522 is also shown. As shown in FIGS. 30A and 30B, for both trap types, the insertion losses may be reduced by adding the ground plane (see results 3070b, 3072b). The lower insertion loss may correlate to lower capacitance, higher Q factor and better resonance performance of the trap.

[0160] The ground plane may be an effective shielding layer to prevent or minimise power dissipation to Si substrate. However, the improvement in RF loss may be limited for the trap with a larger electrode area, as reflected in the simulated S21 data of FIGS. 30 A and 30B. At a resonance frequency of 40 MHz, the simulated S21 of trap-40 and trap-80 with the ground plane (see results 3070b, 3072b) are -0.05 and -0.40 dB, respectively. The larger insertion loss of trap- 80 may be attributed to the larger electrode area of trap-80 compared to that of trap-40 (see also TABLE 1). The large electrode area may result in a larger parasitic capacitance between the electrode and the ground layer. A thicker S1O2 insulation layer may effectively reduce such parasitic capacitance. From simulation, it is found that, by increasing the S1O2 thickness from 3 to 6 pm, S21 may be further improved (see results 3072c) to -0.13 dB at 40 MHz for trap-80. However, fabrication of thicker S1O2 layer may pose challenge for large-scale wafer fabrication due to the large mechanical stress that may be induced by the thicker S1O2 layer. Through-silicon- via (TSV) interconnect may be provided to eliminate the wire-bonding pad of surface trap so as to reduce the electrode area and bring about the benefit of S21 improvement, which may be an attractive alternative to improve RF loss in larger trap types such as trap-80. By employing one or more methods such as utilising a ground plane, thickening the insulation layer, and/or reducing electrode area by using TSV interconnect, the surface trap based on Si substrate may achieve the desired resonance performance, for effective ion trapping.

[0161] As described, large-scale fabrication of surface electrode ion trap on 300-mm Si wafer with Cu/Au electroplated-electrodes is demonstrated using a Cu back end process. Cu/Au electrodes may be electroplated to replace the generally used Au electrodes. Thin Au layer may form an effective passivation layer to prevent or minimise Cu oxidation. S1O2 trenches may be created in the electrode gap to reduce stray electric field. Process optimisation may be done to minimise the undercut in Cu/Au electrodes which may improve the leakage current between the fine-gap electrodes. Meshed ground structure may be fabricated using Cu single damascene process to improve the resonance performance. The fabricated surface electrode ion trap shows desirable electrical properties with a comparably high Q factor and peak power to that of the reference capacitor, which may be suitable for ion trapping functionalities.

[0162] As described above, the methodology and techniques disclosed herein may provide for addressing ion for quantum logic manipulation via one or more narrow openings of the central RF ground, which may address problems related to the prior art. The increase of the stray electric field (E-field) inside the slot (or opening) may be addressed by introducing a trench to the exposed dielectric. The techniques disclosed herein not only may suppress the stray electric field but may also improve the Q factor which may lead to more efficient RF excitation and lower power dissipation. Various embodiments of the devices may be identifiable by its physical appearance where slots or opening (e.g., of rectangular shape) may be defined or provided at the ground electrode (which, for example, may be a central conductor).

[0163] Introducing slot opening at the RF pad or DC pad, as taught in the prior art, results in lower efficiency, higher loss and higher power dissipation. The techniques disclosed herein introduce one or more openings in the ground pad or electrode, which may address problems related to the prior art. One reason being that ion addressing via the ground (slot) opening is found to be more efficient due to the close proximity of the ground pad to the trapped ion.

[0164] While the invention has been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.

Claims

1. A device for trapping an ion, comprising:

an electrode arrangement configured to generate an electric field to trap the ion, the electrode arrangement comprising a ground electrode configured to be connected to ground, the ground electrode having an opening defined therein; and

an optical arrangement configured to transmit an output optical signal through the opening to the trapped ion.

2. The device as claimed in claim 1, wherein the electrode arrangement comprises:

a pair of RF electrodes configured to generate an RF field; and

at least one pair of DC electrodes configured to generate a DC field,

wherein the RF field and the DC field define the electric field.

3. The device as claimed in claim 2, wherein the ground electrode is sandwiched between the pair of RF electrodes.

4. The device as claimed in any one of claims 1 to 3, further comprising an insulating layer in between the electrode arrangement and the optical arrangement, wherein a trench is defined through the insulating layer at the opening.

5. The device as claimed in claim 4, when dependent on claim 2,

wherein the ground electrode is spaced apart from each RF electrode of the pair of RF electrodes, and

wherein, for each spacing, a trench is defined through the insulating layer in the spacing.

6. The device as claimed in any one of claims 1 to 5, wherein the optical arrangement comprises an optical output coupler configured to transmit the output optical signal, the optical output coupler being arranged optically exposed through the opening.

7. The device as claimed in any one of claims 1 to 6, wherein the optical arrangement further comprises a tuning device arranged for tuning a direction of the output optical signal.

8. The device as claimed in claim 7, wherein the tuning device is configured to introduce a phase change to the output optical signal to tune the direction of the output optical signal.

9. The device as claimed in claim 7 or 8, wherein the tuning device is configured to change a refractive index of a material of at least part of the optical arrangement to tune the direction of the output optical signal.

10. The device as claimed in any one of claims 1 to 9, further comprising a support structure arranged to support the electrode arrangement and the optical arrangement, the support structure comprising a ground structure.

11. The device as claimed in claim 10, wherein the ground structure is arranged at the bottom of the support structure.

12. A method for forming a device for trapping an ion, the method comprising:

forming an electrode arrangement configured to generate an electric field to trap the ion, wherein forming the electrode arrangement comprises:

forming a ground electrode configured to be connected to ground, the ground electrode having an opening defined therein; and

forming an optical arrangement configured to transmit an output optical signal through the opening to the trapped ion.

13. The method as claimed in claim 12, wherein forming the electrode arrangement further comprises:

forming a pair of RF electrodes configured to generate an RF field; and

forming at least one pair of DC electrodes configured to generate a DC field, wherein the RF field and the DC field define the electric field.

14. The method as claimed in claim 13, wherein forming the electrode arrangement comprises forming the ground electrode in between the pair of RF electrodes.

15. The method as claimed in any one of claims 12 to 14, further comprising: forming an insulating layer in between the electrode arrangement and the optical arrangement; and

forming a trench through the insulating layer at the opening.

16. The method as claimed in any one of claims 12 to 15, wherein forming the optical arrangement comprises forming an optical output coupler configured to transmit the output optical signal, the optical output coupler being arranged optically exposed through the opening.

17. The method as claimed in any one of claims 12 to 16, wherein forming the optical arrangement further comprises forming a tuning device arranged for tuning a direction of the output optical signal.

18. The method as claimed in any one of claims 12 to 17,

wherein forming the electrode arrangement comprises forming the electrode arrangement on a support structure;

wherein forming the optical arrangement comprises forming the optical arrangement on the support structure; and

the method further comprises forming a ground structure at the support structure.

19. The method as claimed in claim 18, wherein forming the ground structure comprises forming the ground structure at the bottom of the support structure.

20. A method for controlling a device for trapping an ion, the method comprising:

generating, by means of an electrode arrangement of the device, an electric field to trap the ion; and

transmitting an output optical signal through an opening defined in a ground electrode of the electrode arrangement to the trapped ion, the ground electrode being connected to ground.