WO2021004635A1

WO2021004635A1 - Apparatuses and methods for performing a data conversion

Info

Publication number: WO2021004635A1
Application number: PCT/EP2019/068703
Authority: WO
Inventors: Vishnu UNNIKRISHNAN; Okko JARVINEN; Siddiqui WAQAS; Marko Kosunen; Kari Stadius; Jussi Ryynanen
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2019-07-11
Filing date: 2019-07-11
Publication date: 2021-01-14
Also published as: EP3991299A1

Abstract

Apparatuses and methods for performing a data conversion using a high time resolution for an electronic device are disclosed. High time resolution is important in many modern applications. Improved data communication networks have high data bandwidths and low latencies that require high time resolution. This can be achieved by using a cyclic coupled ring oscillator for providing the time resolution. Using a cyclic coupled ring oscillator for providing the time resolution gives a possibility to use sub-gate delay resolution.

Description

APPARATUSES AND METHODS FOR PERFORMING A DATA CONVERSION

TECHNICAL FIELD Generally, the following description relates to the field of electronic devices. More specifically, the following description relates to apparatuses and methods for performing a data conversion using an arrangement for providing a time resolution for an electronic device. BACKGROUND

High resolution timing is an important aspect in many modern integrated circuit applications. One example of an application with a need for high resolution timing is modern data communication networks. These networks involve use of high-speed and high-resolution analog-to-digital converters and time-to-digital converters. An example of such modern data communication network is so called 5G, wherein high bandwidth and latency requirements cause a need for high resolution timing.

The design of analog-to-digital converters using time-domain circuit techniques involves converting the analog input signal into a time domain signal using a voltage- to-time converter. The resulting dime-domain signal is then sampled and quantized into a digital signal using a time-to-digital converter. The resolution of a time-domain analog-to-digital converter is determined by the gain of the voltage-to-time conversion together with the resolution of the time-to-digital conversion.

Conventionally the time resolution has been depending on the delay of inverters used in the converter. Thus, the delay has been at least partially technology dependent. In order to improve the time resolution beyond the inverter delay solutions such as Vernier time-to-digital converters and pulse shrinking converters have been introduced. However, as higher bandwidths and shorter latencies are continuously demanded there is a need to improved apparatuses and methods for providing improved time resolution for data conversion.

SUMMARY

Apparatuses and methods for performing a data conversion using a high time resolution for an electronic device are disclosed. High time resolution is important in many modern applications. Improved data communication networks have high data bandwidths and low latencies together with high time resolution. This can be achieved by using a cyclic coupled ring oscillator for providing the time resolution. Using a cyclic coupled ring oscillator for providing the time resolution gives a possibility to use sub-gate delay resolution.

In an aspect an apparatus for data conversion disclosed. In the aspect the apparatus comprises a cyclic coupled ring oscillator, wherein the cyclic coupled ring oscillator comprises a number M of ring oscillators having N stages, wherein each of ring oscillators having N stages are coupled in a cyclic manner, wherein the apparatus is configured to perform data conversion with a time resolution defined by the cyclic coupled ring oscillator; and an output configured to output the converted data.

It is beneficial to use a time resolution generated using a cyclic coupled ring oscillator as it is possible to provide a high precision time resolution using the cyclic coupled ring oscillator. This provides improved accuracy in the data conversion and reduces phase noise, which helps improving the conversion accuracy further.

In an implementation of the aspect the apparatus further comprises an input configured to receive an analog signal and the output is configured to use a continuous-time integrated and quantized version of the analog input as the generated time resolution. It is beneficial to implement an apparatus so that it can receive an analog input as the input signal and convert it into continuous-time integrated and quantized version. This provides a high accuracy conversion. In an implementation of the aspect the apparatus further comprises a digital signal processor having a first input connected to the output, and the digital signal processor further comprises a second input configured to receive a pulse signal. It is beneficial to connect the cyclic coupled ring oscillator to a digital signal processor for performing high accuracy conversions using a digital signal processor.

In an implementation of the aspect the predefined time resolution is a sub-gate delay time resolution. The sub-gate delay time provides particularly improved accuracy in the data conversion.

In an implementation of the aspect the apparatus further comprises delay stage inverters in ring oscillators and coupling inverters having a weaker drive strength than delay stage inventers in the ring oscillators and wherein the coupling inverters are configured to couple ring oscillators in a cyclic manner. Using weak drive strength provides enhanced capability to achieve a desired mode of oscillation for the cyclic coupled ring oscillator.

In an implementation of the aspect the coupled N-stage oscillators oscillate in a desired mode of oscillation, wherein each possible mode corresponds to a certain distinct phase relationship between the N-stage horizontal oscillators. When coupled N-stage oscillators oscillate in desired mode of oscillation the overall arrangement is capable of better producing the desired high precision time resolution.

In an implementation of the aspect the apparatus is configured to receive a time domain signal as an input. It is beneficial to be able to receive a time domain signal as an input. This improves flexibility of the arrangement.

In an implementation of the aspect the apparatus further comprises a voltage-to- time converter and the voltage-to-time converter is configured to receive an analog input and to provide a time domain output. It is beneficial to be able to receive an analog signal as an input. This improves flexibility of the arrangement. In an implementation of the aspect the apparatus is a time-to-digital converter. It is beneficial implement a time-to-digital converter that can be used in various applications.

In an implementation of the aspect the apparatus is an analog-to-digital converter. It is beneficial implement a analog-to-digital converter that can be used in various applications.

In an implementation of the aspect the apparatus is a radio receiver. It is beneficial to use a cyclic coupled ring oscillator based data conversion apparatus in the implementation as it increases the accuracy and performance of the implementation.

In an implementation of the aspect the apparatus is an all-digital phase-locked loop. It is beneficial to use a cyclic coupled ring oscillator based data conversion apparatus in the implementation as it increases the accuracy and performance of the implementation.

In an implementation of the aspect the apparatus is a time-of-flight sensor. It is beneficial to use a cyclic coupled ring oscillator based data conversion apparatus in the implementation as it increases the accuracy and performance of the implementation.

In an implementation of the aspect the apparatus is a three-dimensional imager. It is beneficial to use a cyclic coupled ring oscillator based data conversion apparatus in the implementation as it increases the accuracy and performance of the implementation.

In an implementation of the aspect the apparatus is a radar. It is beneficial to use a cyclic coupled ring oscillator based data conversion apparatus in the implementation as it increases the accuracy and performance of the implementation. In an aspect a method for performing data conversion is disclosed. The method comprises performing a data conversion using a sub-gate-delay time resolution provided by a cyclic coupled ring oscillator , wherein the cyclic coupled ring oscillator comprises a number M of ring oscillators having N stages, wherein each of ring oscillators having N stages are coupled toin a cyclic manner.

In an implementation of the aspect the method is performed using a ring oscillator comprising delay stage inverters and coupling inverters, wherein the coupling inverters have a weaker drive strength than delay stage inventers. Using weak drive strength provides enhanced capability to achieve a desired mode of oscillation for the cyclic coupled ring oscillator.

In an implementation of the aspect the method further comprises: selecting a mode of oscillation for each of the ring oscillators. When coupled N-stage oscillators each oscillate in desired mode of oscillation the overall arrangement is capable of better producing the desired high precision time resolution.

In an implementation of the aspect the method further comprises: receiving a time domain signal as an input. It is beneficial to be able to receive a time domain signal as an input. This improves flexibility of the method.

In an implementation of the aspect the method further comprises: receiving an analog signal as an input and converting the received analog signal into time domain signal. It is beneficial to be able to receive an analog domain signal as an input. This improves flexibility of the method.

The foregoing and other objects are achieved by the subject matter of the independent claims. Further implementation forms are apparent from the dependent claims, the description and the figures. The principles discussed in the present description can be implemented in hardware and may include software controlled components. BRIEF DESCRIPTION OF THE DRAWINGS

Further example embodiments will be described with respect to the following figures, wherein: Fig. 1 a shows an example of a schematic diagram illustrating an analog to digital converter;

Fig. 1 b shows an example of an apparatus with a CCRO to realize a high-precision signal processing system that can process both analog and asynchronous-digital signals;

Fig. 1 c shows an example of an apparatus with a CCRO in an analog signal processing unit that can be implemented with digital hardware; Fig. 2 shows an example of a regular ring oscillator;

Fig. 3 shows an example of a cyclic coupled ring oscillator;

Fig. 4 shows an example of a time to digital converter using a cyclic coupled ring oscillator;

Fig. 5 shows an example of a receiver front-end for the fifth generation telecommunication network; and Fig. 6 shows an example of a high-performance frequency synthesis and all-digital phase-locked loop;

In the various figures, identical reference signs will be used for identical or at least functionally equivalent features. DETAILED DESCRIPTION OF THE EMBODIMENTS

In the following description, reference is made to the accompanying drawings, which form part of the disclosure, and in which are shown, by way of illustration, specific aspects in which the present apparatuses and methods may be placed. It is understood that other aspects may be utilized and structural or logical changes may be made without departing from the scope of the claims. Thus, the following detailed description, therefore, is not to be taken in a limiting sense.

For instance, it is understood that a disclosure in connection with a described method may also hold true for a corresponding device or system configured to perform the method and vice versa. For example, if a specific method step is described, a corresponding device may include a unit to perform the described method step, even if such unit is not explicitly described or illustrated in the figures. Further, it is understood that the features of the various exemplary aspects described herein may be combined with each other, unless specifically noted otherwise. In figure 1 a a basic implementation of an analog-to-digital converter is shown. The example analog-to-digital converter may be used as a basis for an embodiment for the described arrangements for providing a time resolution. The analog-to-digital converter of figure 1 receives an analog input 100 at a voltage-to-time converter 101. The received analog input, usually voltage-represented signal, 100 is then converted into a time-domain signal 102 using a voltage-to-time converter (VTC) 101. The resulting time-domain signal 102 is then sampled and quantized into a digital signal using a time-to-digital converter (TDC) 103 for providing a digital output 104. The resolution of a time-domain ADC is determined by the gain of the voltage- to-time conversion together with the resolution of the time-to-digital conversion. The arrangement described below in detail helps improving the resolution of the time-to- digital conversion thereby also improving the resolution of the analog-to-digital conversion. Figure 1 b shows an example of an apparatus with a CCRO 105 to realize a high- precision signal processing system that can process both analog and asynchronous-digital signals. The pulse signal input 106 can contain time-encoded analog information or an asynchronous-digital information that requires processing. The digital signal processing unit 107 can realize a variety of signal processing tasks by comparing/combining the information in the pulse signals 106 with the high- precision instantaneous phase signal provided by the CCRO 105, thereby realizing a phase-domain signal processing system. The processed signals are then provided as an output signal 108.

Figure 1 c shows an example of an apparatus with a CCRO in an analog signal processing unit that can be implemented with digital hardware. The example of figure 1 c provides opportunities in high-performance energy-efficient analog signal processing in highly-scaled semiconductor technologies (which is otherwise difficult) and design-cost saving using design automation. In the example a CCRO 1 10 is used as a time-domain integrator for analog signals 109 when the CCRO 1 10 is used as a voltage controller oscillator. The analog input 109 controls the frequency of the CCRO 1 10. The phase output of the CCRO then provides a continous-time integrated and quantized version of the analog input 1 1 1. This is a versatile signal processing unit that can find use in realizing a variety of complex signal processing tasks.

Figure 2 shows an example of a regular ring oscillator 200. A regular ring oscillator divides its phase into 2N steps where N is the number of inverters in the ring. Hence, the time resolution that is created is still in steps of inverter delays. The regular ring oscillator 200 is a regular ring oscillator with 5 inverters and the resulting phase interpolation are shown in the figure below the ring oscillator 200. The minimum inverter delay for the specific load conditions is assumed to be t_mv-mm. Note that the minimum time step possible in the circuit, f_m/n, is the same as t_mv-min.

Cyclic coupled ring oscillator refers to an arrangement where a number of ring oscillators ( M) are coupled in a cyclic fashion, forming a ring of rings. When properly designed, the individual ring oscillators establish a phase relationship among themselves such that 2xA/x/W phase steps uniformly distributed between 0 and 2p can be extracted from the structure. The resulting time step between temporally adjacent phase steps is approximately 1/M of the inverter delay. Thus, a sub-gate- delay resolution is achieved. When such an arrangement is used in a ring oscillator TDC architecture instead of employing a regular ring oscillator, a technology- independent and arbitrarily small time step can be achieved without compromising the conversion time.

In figure 3 an example of a cyclic coupled ring oscillator is shown. The cyclic coupled ring oscillator comprises three regular 5-stage ring oscillators 300 - 302. The cyclic coupled ring oscillator has five inverters 303 in each regular ring oscillator, N = 5; M = 3. The newly introduced coupling inverters 305 are marked with c. The coupling inverters are arranged into a ring 304 for coupling the regular ring oscillators 300 - 302 in a cyclic manner. The coupling inverters 305 are usually designed to have relatively weak drive strength compared to regular inverters 303.

The 5-stage oscillators 300 - 302 are cyclically coupled with coupling inverters which in turn forms a set of vertical ring oscillators. When the coupled oscillators oscillate in the desired mode of oscillation, wherein each possible mode corresponds to a certain distinct phase relationship between the 5-stage horizontal oscillators, the desired phase interpolation as shown in Fig. 3 below the cyclic coupled ring oscillator is achieved. There are usually several different modes that provide the desired phase interpolation and hence it is easy to design the structure to ensure a desired mode of oscillation. It can be seen from Fig. 3 that the minimal time step present in the circuit, t_mm is now tinv-min/M, which less than the minimum inverter delay

Thus, the desired sub-gate-delay resolution is achieved.

Figure 4 shows an example of a TDC using a cyclic coupled ring oscillator 400. A cyclic coupled ring oscillator 400 achieves an arbitrarily small sub-gate-delay phase quantization step. When a cyclic coupled ring oscillator based data converter (TDC or ADC) is implemented in a deeply-scaled semiconductor technology, the phase quantization step approaches a picosecond or even shorter. As shown in Fig. 4, the phase output of the cyclic coupled ring oscillator needs to be sampled by registers 402 and 403. The sampled phase of the oscillator is then encoded into a number inside the digital signal processor block 404 in order to generate a digital output sample. The example of figure 4 additionally shows a counter 401 that can be used for counting values of received from the cyclic coupled ring oscillator. This is just an example of an additional component that can be included in a data converter. Instead of a counter it is possible to use also other additional components in the arrangement.

In the example implementations discussed above a method for performing a data conversion may be used. In the method the data conversion is using a sub-gate- delay time resolution provided by a cyclic coupled ring oscillator, wherein the cyclic coupled ring oscillator comprises a number M of ring oscillators having N stages, wherein each of ring oscillators having N stages are coupled in a cyclic manner. In the above several examples have been discussed and the method may be used in any of the above examples or similar examples for the purpose of data conversion.

In the examples above implementations of a data converter has been discussed in detail. In the following additional use case examples are briefly discussed. As explained above data converters as such are obvious applications for the arrangements described above.

In figure 5 a receiver front-end for fifth generation telecommunication network is shown. The receiver front-end uses an RF-digitizing approach, using a high performance ADC. The receiver front end comprises a receiving section 500 for receiving analog signals. The required converter with a very high bandwidth as well as a high resolution is realized with a time-interleaved architecture where individual converters 501 - 503 are implemented with the time-domain approach to take advantage of the superior time resolution of the advanced processes. The front-end further comprises a digital signal processor 504 for processing the received and converted signal.

In figure 6 an example of a high-performance frequency synthesis and all-digital phase-locked loop (ADPLL) is shown as a use case example. All-digital phase- locked loops are gaining popularity as an attractive architecture to implement frequency synthesizers and similar applications in highly-scaled semiconductor technologies. The resolution and conversion speed of the TDC block 601 in an ADPLL is crucial in determining the performance and bandwidth of the circuit. It receives an input 600 and provides it further to a digital loop filter 602 and to a digitally controlled oscillator 604, which provides an output 606. The digitally controlled oscillator of the example is further connected back to the TDC block 601 through a divider 605. The arrangement can be useful in mitigating the performance limitations of ADPLLs and frequency synthesizers designed in modern semiconductor technologies by enabling fast and high-resolution time-to-digital conversion. Phase-locked loops and frequency synthesizers are used extensively in radio transceivers and high-speed serial communication transceivers.

Another example of a use case is a time-of-flight sensor used in radar applications. The high time resolution can also be useful in realizing high-precision time measurement required in time-of-flight (T-o-F) sensors. Time-of-flight sensors are used in a wide range of radar applications including automotive radar and other consumer electronic radar applications.

As explained above, the arrangements using a cyclic coupled ring oscillator for generating a time resolution as described above may be implemented in hardware, such as a mobile telephone, tablet computer, computer, telecommunication network base station or any other network connected device, or as a method. The method may be implemented as a computer program. The computer program is then executed in a computing device.

The apparatus, such as apparatus for transmitting signals in a communication network, is configured to perform one of the methods described above. The apparatus comprises necessary hardware components. These may include at least one processor, at least one memory, at least one network connection, a bus and similar. Instead of dedicated hardware components it is possible to share, for example, memories or processors with other components or access at a cloud service, centralized computing unit or other resource that can be used over a network connection.

The apparatus for transmitting signals in a communication network and the corresponding method have been described in conjunction with various embodiments herein. However, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word“comprising” does not exclude other elements or steps, and the indefinite article“a” or“an” does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measured cannot be used to advantage. A computer program may be stored/distributed on a suitable medium, such as an optical storage medium or a solid-state medium supplied together with or as part of other hardware, but may also be distributed in other forms, such as via the Internet or other wired or wireless telecommunication systems.

Claims

CLAIMS 1. An apparatus for data conversion, wherein the apparatus comprises:

A cyclic coupled ring oscillator, wherein the cyclic coupled ring oscillator comprises a number M of ring oscillators having N stages, wherein each of ring oscillators having N stages are coupled in a cyclic manner, wherein the apparatus is configured to perform data conversion with a time resolution defined by the cyclic coupled ring oscillator; and an output configured to output the converted data.

2. The apparatus according to claim 1 , wherein the apparatus further comprises an input configured to receive an analog signal and the output is configured to use a continuous-time integrated and quantized version of the analog input as the generated time resolution.

3. The apparatus according to claim 1 or 2, wherein the apparatus further comprises a digital signal processor having a first input connected to the output, and the digital signal processor further comprises a second input configured to receive a pulse signal.

4. The apparatus for data conversion according to any of preceding claims 1 - 3, wherein the predefined time resolution is a sub-gate delay time resolution.

5. The apparatus for data conversion according to any of preceding claims 1 - 4, wherein the apparatus further comprises delay stage inverters in ring oscillators and coupling inverters having a weaker drive strength than delay stage inventers in the ring oscillators and wherein the coupling inverters are configured to couple ring oscillators in a cyclic manner .

6. The apparatus for data conversion according to any of the preceding claims 1 - 5, wherein the coupled N-stage oscillators oscillate in a desired mode of oscillation, wherein each possible mode corresponds to a certain distinct phase relationship between the N- stage horizontal oscillators.

7. The apparatus for data conversion according to any of the preceding claims 1 - 6, wherein the apparatus is configured to receive a time domain signal as an input.

8. The apparatus for data conversion according to any of the preceding claims 1 - 6, wherein the apparatus further comprises a voltage-to-time converter and the voltage-to- time converter is configured to receive an analog input and to provide a time domain output.

9. The apparatus for data conversion according to any of claims 7, wherein the apparatus is a time-to-digital converter.

10. The apparatus for data conversion according to claim 8, wherein the apparatus is an analog-to-digital converter.

1 1. The apparatus for data conversion according to any of the preceding claims 1 - 10, wherein the apparatus is a radio receiver.

12. The apparatus for data conversion according to any of claims 1 - 10, wherein the apparatus is an all-digital phase-locked loop.

13. The apparatus for data conversion according to any of preceding claims 1 - 10, wherein the apparatus is a time-of-flight sensor.

14. The apparatus for data conversion according to any of preceding claims 1 - 10, wherein the apparatus is a three-dimensional imager.

15. The apparatus for data conversion according to any of preceding claims 1 - 10, wherein the apparatus is a radar.

16. A method for performing data conversion, wherein the method comprises:

performing a data conversion using a sub-gate-delay time resolution provided by a cyclic coupled ring oscillator , wherein the cyclic coupled ring oscillator comprises a number M of ring oscillators having N stages, wherein each of ring oscillators having N stages are coupled in a cyclic manner.

17. The method for performing data conversion according to claim 16, wherein using a ring oscillator comprising delay stage inverters and coupling inverters, wherein the coupling inverters have a weaker drive strength than delay stage inventers

18. The method for performing data conversion according to claim 16 or 17, wherein the method further comprises: selecting a mode of oscillation for each of the ring oscillators.

19. The method for performing data conversion according to any of preceding claims 16 -

18, wherein the method further comprises: receiving a time domain signal as an input.

20. The method for performing data conversion according to any of preceding claims 16 - 18, wherein the method further comprises: receiving an analog signal as an input and converting the received analog signal into time domain signal.