WO2021000259A1 - 像素驱动电路及其驱动方法、像素电路和显示面板 - Google Patents

像素驱动电路及其驱动方法、像素电路和显示面板 Download PDF

Info

Publication number
WO2021000259A1
WO2021000259A1 PCT/CN2019/094392 CN2019094392W WO2021000259A1 WO 2021000259 A1 WO2021000259 A1 WO 2021000259A1 CN 2019094392 W CN2019094392 W CN 2019094392W WO 2021000259 A1 WO2021000259 A1 WO 2021000259A1
Authority
WO
WIPO (PCT)
Prior art keywords
node
voltage
transistor
coupled
circuit
Prior art date
Application number
PCT/CN2019/094392
Other languages
English (en)
French (fr)
Inventor
董甜
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN201980000984.4A priority Critical patent/CN112449713B/zh
Priority to PCT/CN2019/094392 priority patent/WO2021000259A1/zh
Priority to US16/767,456 priority patent/US11462165B2/en
Publication of WO2021000259A1 publication Critical patent/WO2021000259A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing

Definitions

  • the present invention relates to the field of display technology. Specifically, it relates to a pixel driving circuit and a driving method thereof, a pixel circuit and a display panel.
  • organic light-emitting diode Organic Light-Emitting Diode, OLED for short
  • the pixel driving circuit uses the current provided by the driving transistor to drive the light emitting device to emit light.
  • Embodiments of the present disclosure provide a pixel driving circuit, a pixel circuit, a display panel, and a method for driving the pixel driving circuit.
  • a pixel driving circuit includes an input circuit, a reset circuit, a drive transistor, and a compensation circuit.
  • the input circuit is coupled to the gate drive signal terminal, the input signal terminal and the first node, and is configured to provide a data signal from the input signal terminal to the first node according to the gate drive signal from the gate drive signal terminal.
  • the reset circuit is coupled to the reset control signal terminal, the first voltage terminal and the second node, and is configured to provide the first voltage from the first voltage terminal to the second node according to the reset control signal from the reset control signal terminal.
  • the driving transistor includes: a first pole coupled to the second voltage terminal; a control pole coupled to the compensation circuit via the first node; and a second pole coupled to the light emitting device, and is configured to output to the light emitting device corresponding to The current that drives the voltage difference between the control electrode and the first electrode of the transistor.
  • the compensation circuit includes a reference transistor. The compensation circuit is coupled to a third voltage terminal, a second node, a first node, a control signal terminal, and a second voltage terminal, and is configured to compensate the threshold voltage of the driving transistor based on the threshold voltage of the reference transistor .
  • the compensation circuit includes a first storage circuit, a reference transistor, a second storage circuit, and a control circuit.
  • the first storage circuit is coupled between the third node and the second voltage terminal, and is configured to store the first voltage difference between the third node and the second voltage terminal.
  • the control electrode of the reference transistor is coupled to the third voltage terminal, the first electrode of the reference transistor is coupled to the first node, and the second electrode of the reference transistor is coupled to the third node, and is configured to follow the reference transistor
  • the voltage difference between the control electrode and the first electrode provides the voltage of the first node to the third node.
  • the second storage circuit is coupled between the second node and the first node, and is configured to store a second voltage difference between the second node and the first node.
  • the control circuit is coupled to the second node, the control signal terminal and the third voltage terminal, and is configured to provide the third voltage to the second node under the control of the control signal from the control signal terminal.
  • the threshold voltage of the reference transistor is the same as the threshold voltage of the driving transistor.
  • the material, structure and shape of the reference transistor and the driving transistor are the same.
  • the first storage circuit includes a first capacitor.
  • the first terminal of the first capacitor is coupled to the third node, and the second terminal of the first capacitor is coupled to the second voltage terminal.
  • the second storage circuit includes a second capacitor.
  • the first end of the second capacitor is coupled to the second node, and the second end of the second capacitor is coupled to the first node.
  • the capacitance value of the first capacitor is the same as the capacitance value of the second capacitor.
  • the control circuit includes a first transistor.
  • the control electrode of the first transistor is coupled to the control signal terminal, the first electrode of the first transistor is coupled to the third voltage terminal, and the second electrode of the first transistor is coupled to the second node.
  • the input circuit includes a second transistor.
  • the control electrode of the second transistor is coupled to the gate drive signal terminal, the first electrode of the second transistor is coupled to the input signal terminal, and the second electrode of the second transistor is coupled to the first node.
  • the reset circuit includes a third transistor.
  • the control electrode of the third transistor is coupled to the reset control signal terminal, the first electrode of the third transistor is coupled to the first voltage terminal, and the second electrode of the third transistor is coupled to the second node.
  • the first storage circuit includes a first capacitor.
  • the first terminal of the first capacitor is coupled to the third node, and the second terminal of the first capacitor is coupled to the second voltage terminal.
  • the second storage circuit includes a second capacitor. The first end of the second capacitor is coupled to the second node, and the second end of the second capacitor is coupled to the first node.
  • the capacitance value of the first capacitor is the same as the capacitance value of the second capacitor.
  • the control circuit includes a first transistor.
  • the control electrode of the first transistor is coupled to the control signal terminal, the first electrode of the first transistor is coupled to the third voltage terminal, and the second electrode of the first transistor is coupled to the second node.
  • the input circuit includes a second transistor.
  • the control electrode of the second transistor is coupled to the gate drive signal terminal, the first electrode of the second transistor is coupled to the input signal terminal, and the second electrode of the second transistor is coupled to the first node.
  • the reset circuit includes a third transistor. The control electrode of the third transistor is coupled to the reset control signal terminal, the first electrode of the third transistor is coupled to the first voltage terminal, and the second electrode of the third transistor is coupled to the second node.
  • a display panel including a pixel circuit.
  • the pixel circuit includes a pixel drive circuit according to the first aspect of the present disclosure, and a light emitting device coupled to the pixel drive circuit.
  • a method for driving the pixel driving circuit of the first aspect of the present disclosure includes: in the reset stage, according to the reset control signal, the first voltage is provided to the second node to reset the voltage of the first node; in the data input stage, the data signal is provided to the second node according to the gate drive signal A node, and store the first voltage difference between the second voltage terminal and the first node, and the second voltage difference between the first node and the second node; and in the compensation output stage, according to the control signal, the third voltage Provided to the second node to compensate the voltage of the first node based on the threshold voltage of the reference transistor to compensate the threshold voltage of the driving transistor, and to make the driving transistor send to the light emitting device according to the compensated voltage of the first node and the second voltage Provide output current.
  • the pixel driving circuit is the pixel driving circuit according to the first aspect
  • the compensation output phase includes a compensation phase and an output phase
  • the threshold voltage of the reference transistor is the same as the threshold voltage of the driving transistor.
  • the method includes: in the reset phase, according to the reset control signal, the third transistor is turned on and the first voltage is provided to the second node to reset the first node; in the data input phase, according to the gate drive signal, the second The transistor is turned on and provides the data signal to the first node, and the first capacitor stores the first voltage difference, and the second capacitor stores the second voltage difference; and in the compensation output phase, wherein, in the compensation phase, according to the control signal, the first The transistor is turned on and provides the third voltage to the second node.
  • the reference transistor In response to the voltage change of the second node, the reference transistor is turned on first, the first capacitor is connected in parallel with the second capacitor and the voltage of the first node is compensated to V3-V th , The reference transistor is then turned off, the second capacitor continues to compensate the voltage of the first node to 2Vdata-V1+V th , where V3 represents the third voltage, V1 represents the first voltage, V th threshold voltage, and Vdata represents the data signal, wherein, in the output stage, the driving transistor provides an output current to the light emitting device according to the compensated voltage 2Vdata-V1+V th of the first node and the second voltage.
  • FIG. 1 shows a schematic block diagram of a pixel driving circuit according to an embodiment of the present disclosure
  • FIG. 2 shows an exemplary circuit diagram of a pixel driving circuit according to an embodiment of the present disclosure
  • FIG. 3 shows a timing diagram of various signals during the operation of the pixel driving circuit shown in FIG. 2;
  • FIG. 4 shows a schematic flowchart of a method for driving a pixel driving circuit according to an embodiment of the present disclosure
  • FIG. 5 shows a schematic block diagram of a display panel according to an embodiment of the present disclosure.
  • the pixel driving circuit controls the current provided to the light-emitting device by controlling the voltage of the control electrode of the driving transistor DTFT, thereby controlling the light-emitting brightness of the light-emitting device.
  • the first electrode of the driving transistor DTFT is coupled to the voltage terminal of the constant voltage.
  • the driving transistor outputs a corresponding current from the second electrode according to the voltage difference V GS between the voltage of the control electrode and the constant voltage. This current is used to drive the light emitting device to emit light.
  • the current I output at the second pole of the driving transistor can be determined by formula (1):
  • the current I output from the second pole is related to the threshold voltage V th of the driving transistor DTFT. Therefore, in the pixel driving circuit of the related art, the difference in the threshold voltage of the driving transistor DTFT will directly affect the light-emitting brightness of the light-emitting device, thereby affecting the brightness uniformity of the entire display device. Therefore, in order to meet the requirements for the uniformity of the light emission of the display panel, it is necessary to improve the uniformity of the electrical characteristics such as the threshold voltage of the driving transistor. In the prior art, an internal compensation method or an external compensation method can be used to improve the consistency of the electrical characteristics of the driving transistor.
  • the DTFT needs to be powered on in advance to sense the threshold voltage of the DTFT, and then the DTFT can be effectively compensated for the threshold voltage based on the sensed threshold voltage.
  • this method will disadvantageously increase the operating time of the DTFT outside of normal display, thereby degrading the performance of the DTFT, and thereby reducing the service life of the display device.
  • embodiments of the present disclosure provide a pixel driving circuit, which can not only perform threshold voltage compensation on the voltage of the control electrode of the driving transistor to solve the problem of brightness uniformity caused by the difference in the threshold voltage of the driving transistor Problems, and can avoid unnecessary increase in driving transistor operating time.
  • Embodiments of the present disclosure provide a pixel driving circuit and a driving method thereof, a pixel circuit, and a display panel.
  • the embodiments and examples of the present disclosure will be described in detail below with reference to the accompanying drawings.
  • FIG. 1 shows a schematic block diagram of a pixel driving circuit according to an embodiment of the present disclosure.
  • the pixel driving circuit 100 may include an input circuit 110, a reset circuit 120, a driving transistor DTFT, and a compensation circuit 130. It will be described in detail below with reference to the drawings.
  • the input circuit 110 may be coupled to the gate driving signal terminal, the input signal terminal and the first node J 1 .
  • the input circuit 110 may receive the gate driving signal Scan from the gate driving signal terminal and the data signal Vdata from the input signal terminal.
  • the input circuit 110 provides the data signal Vdata to the first node J 1 according to the gate driving signal Scan.
  • the reset circuit 120 is coupled to the reset control signal terminal, the first voltage terminal and the second node J 2 .
  • the reset circuit 120 receives the reset control signal Rest from the reset control signal terminal, and receives the first voltage V1 from the first voltage terminal.
  • the reset circuit 120 provides the first voltage V1 to the second node J 2 according to the reset control signal Rest, so that the first node J 1 can be reset.
  • the control electrode of the driving transistor DTFT and the compensation circuit 130 are both coupled to the first node J 1. Therefore, the control electrode of the driving transistor DTFT can be coupled to the compensation circuit 130 via the first node J 1 .
  • the first pole of the driving transistor DTFT is coupled to the second voltage terminal, and the second pole is coupled to the light emitting device 200.
  • the driving transistor DTFT outputs a current signal corresponding to the voltage difference between the control electrode and the first electrode.
  • the light emitting device may be an organic light emitting diode.
  • the compensation circuit 130 includes a reference transistor Tc, and is coupled to the third voltage terminal, the second node J 2 , the first node J 1 , the control signal terminal, and the second voltage terminal.
  • the compensation circuit 130 receives the third voltage V3 from the third voltage terminal, the control signal CTR from the control signal terminal, and the second voltage V2 from the second voltage terminal, and according to the control signal CTR, the third voltage V3 and the second voltage V2,
  • the threshold voltage V th of the driving transistor DTFT is compensated based on the threshold voltage of the reference transistor Tc.
  • the reference transistor Tc and the driving transistor DTFT have the same threshold voltage, that is, V th .
  • the reference transistor Tc and the driving transistor DTFT may have the same material, structure and shape. It should be understood that in the actual production process, due to the limitation of the manufacturing process itself, the threshold voltage of the reference transistor Tc and the driving transistor DTFT may have a certain difference. In the embodiment of the present disclosure, the third voltage V3 is less than the first voltage V1.
  • the compensation circuit 130 includes a first storage circuit 1310, a reference transistor Tc, a second storage circuit 1320, and a control circuit 1330.
  • the first storage circuit 1310 is coupled between the third node J 3 and the second voltage terminal, and stores the first voltage difference between the third node J 3 and the second voltage terminal.
  • Tc reference transistor control electrode is coupled to the third voltage terminal, a first electrode of the reference transistor Tc and J 1 is coupled to a first node, a second electrode of the reference transistor Tc and J 3 is coupled to the third node, and a third the voltage difference between the voltage V3 and the voltage of the first node J 1, the first node voltage supplied to the third node J 1 J 3.
  • the second storage circuit 1320 is coupled between the second node J 2 and the first node J 1 and stores the second voltage difference between the second node J 2 and the first node J 1 .
  • the control circuit 1330 is coupled to the second node J 2 , the control signal terminal and the third voltage terminal.
  • the control circuit 1330 receives the control signal CTR from the control signal terminal, receives the third voltage V3 from the third voltage terminal, and provides the third voltage V3 to the second node J 2 according to the control signal CTR.
  • FIG. 2 shows an exemplary circuit diagram of the pixel driving circuit 100 according to an embodiment of the present disclosure.
  • the pixel driving circuit 100 may include a reference transistor Tc, a first transistor T1 to a third transistor T3, a first capacitor C1 and a second capacitor C2, and a driving transistor DTFT.
  • the first transistor T1 to the third transistor T3 are all switching transistors.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or other active devices with the same or similar characteristics.
  • a thin film transistor is taken as an example for description.
  • the source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be structurally indistinguishable.
  • the gate of the transistor is referred to as a control electrode, and the two poles other than the gate are referred to as a first pole and a second pole, respectively.
  • a P-type enhancement type transistor is taken as an example for description. Those skilled in the art can understand that other types of transistors are also applicable.
  • the first storage circuit 1310 includes a first capacitor C1.
  • the second storage circuit 1320 includes a second capacitor C2.
  • the control circuit 1330 includes a first transistor T1.
  • the first storage circuit 1310, the second storage circuit 1320, and the control circuit 1330 in the compensation circuit 130 will be described in detail with reference to the drawings.
  • the first terminal of the first capacitor C1 is coupled to the third node J 3
  • the second terminal is coupled to the second voltage terminal to store the voltage difference between the third node J 3 and the second voltage terminal.
  • the first terminal of the second capacitor C2 is coupled to the second node J 2 , and the second terminal is coupled to the first node J 1 to store the voltage difference between the second node J 2 and the first node J 1 .
  • the capacitance value C of the first capacitor C1 and the capacitance value C. 1 2 is the same as the second capacitor C2.
  • the voltage of the second node J 2 is changed and the first node J being lifted. 1, since the voltage across the capacitor characteristics can not be mutated, the same amount of change in the charge across the second capacitor C2.
  • the first node J 1 When the voltage of the second node J 2 changes and the first node J 1 is in a floating state, since the voltage difference stored by the second capacitor C2 does not change (that is, the equivalent potential jump effect of the capacitor), the first node J 1 The amount of change in voltage is the same as that of the second node J 2 .
  • the control electrode of the first transistor T1 is coupled to the control signal terminal to receive the control signal CTR.
  • the first electrode of the first transistor T1 is coupled to the second node J 2 .
  • the second electrode of the first transistor T1 is coupled to the third voltage terminal to receive the third voltage V3.
  • the control signal CTR when the control signal CTR is at a low level, the first transistor T1 is turned on, and the received third voltage V3 is provided to the second node J 2 .
  • the input circuit 110 includes a second transistor T2.
  • the control electrode of the second transistor T2 is coupled to the gate driving signal terminal to receive the gate driving signal Scan.
  • the first electrode of the second transistor T2 is coupled to the input signal terminal to receive the data signal Vdata.
  • the second electrode of the second transistor T2 is coupled to the first node J 1 .
  • the gate driving signal Scan is at a low level, the second transistor T2 is turned on, and the data signal Vdata is provided to the first node J 1 .
  • the data signal Vdata cannot turn on the driving transistor DTFT, that is, the voltage difference between the data signal Vdata and the second voltage V2 is greater than the threshold voltage V th . Therefore, the data signal Vdata should satisfy: Vdata>V2+V th .
  • the reset circuit 120 includes a third transistor T3.
  • the control electrode of the third transistor T3 is coupled to the reset control signal terminal to receive the reset control signal Rest.
  • the first electrode of the third transistor T3 is coupled to the first voltage terminal to receive the first voltage V1.
  • the second electrode of the third transistor T3 is coupled to the second node J 2 .
  • the reference transistor Tc, the first to third transistors T1 to T3, and the driving transistor DTFT may be P-type transistors.
  • the reference transistor Tc, the first transistor T1 to the third transistor T3, and the driving transistor DTFT may also be N-type transistors.
  • FIG. 3 shows a timing diagram of various signals during the operation of the pixel driving circuit 100 shown in FIG. 2. It can be understood that the signal voltage in the signal timing diagram shown in FIG. 3 is only schematic, and does not represent a true voltage value.
  • the third transistor T3 is turned on.
  • the received first voltage V1 is provided to the second node J 2 , and the voltage of the first node J 1 is reset to VJ 10 .
  • the voltage difference between the VJ 10 and the second voltage V2 should be greater than the threshold voltage V th of the driving transistor DTFT, so that the driving transistor DTFT is turned off.
  • the second transistor T2 In the data input phase P2, when a low-level gate driving signal Scan is provided at the gate driving signal terminal, the second transistor T2 is turned on.
  • the received data voltage Vdata is provided to the first node J 1 .
  • the reference transistor Tc under the control of the third voltage V3, the reference transistor Tc is turned on, i.e., the third voltage V3 and the voltage difference between the first node is equal to J 1 is less than the threshold voltage V th. Therefore, the data signal Vdata should satisfy: Vdata ⁇ V3-V th .
  • the first capacitor C1 stores a second voltage V2 and the first voltage between the first node J 1 difference, i.e. V2-Vdata.
  • the second capacitor C2 stores the first node J 1 J a second voltage difference, i.e., Vdata-V3 between the second node.
  • the compensation output stage P3 includes a compensation stage P31 and an output stage P32.
  • the compensation phase P31 when a low-level control signal CRT is provided at the control signal terminal, the first transistor T1 is turned on, and the received third voltage V3 is provided to the second node J 2 . 2 node J voltage from the first voltage V1 is equal to the third voltage V3.
  • the control electrode of the reference transistor Tc receives the third voltage V3 and the voltage difference between the voltage of the first point J 1 is less than equal to the threshold voltage V th, the reference transistor Tc is turned on.
  • the first capacitor C1 and the second capacitor C2 are connected in parallel.
  • the first voltage V1 is greater than the third voltage V3, and therefore a voltage of the first point J decreased.
  • the control electrode of the transistor Tc receives the third voltage V3 and the voltage difference between the voltage of the first point J 1 becomes greater than the threshold voltage V th, so that the reference transistor Tc is turned off.
  • the second node voltage change amount J 2 is equal to the voltage variation of the first node J 1.
  • the voltage of the first node J 1 at the moment when the reference transistor Tc is switched from on to off state is VJ 11 , which can be calculated by the following formula:
  • VJ 11 V3-V th formula (2)
  • the charge variation ⁇ Q 1 of the first terminal of the second capacitor C2 coupled to the second node J 2 can be calculated by the following formula :
  • ⁇ V1 (C 1 +C 2 )/C 2 *(VJ 11 -Vdata), in this embodiment, the capacitance values of the first capacitor C 1 and the second capacitor C 2 are the same, so
  • the reference transistor Tc is turned off. Assuming that after the reference transistor Tc is turned off, the voltage change of the second node J 2 is ⁇ V2, and the stable voltage of the first node J 1 is VJ 12 . After the reference transistor Tc is turned off, the first node J 1 is in a floating state. Based on the equipotential jump effect of the second capacitor C2, the voltage change of the first node J 1 is equal to the voltage change ⁇ V2 of the second node J 2 , which is:
  • V3-V1 ⁇ V1+ ⁇ V2
  • VJ 12 2Vdata-V1+V th formula (8)
  • the driving transistor DTFT can provide an output current I to the light emitting device, so 2Vdata-V1 + Vth-V2 ⁇ Vth, so that the data signal Vdata should meet Vdata ⁇ 1 / 2 (V1 + V2) .
  • VJ 12 based on the voltage and the third voltage V3, the reference transistor Tc is turned off, so V3- (2Vdata-V1 + Vth) > Vth, so that the data signal Vdata should satisfy Vdata ⁇ 1/2 (V1 + V3) -Vth.
  • the current I output from the second pole of the driving transistor DTFT can be calculated, as shown in formula (9):
  • K K(2Vdata-V1-V2) 2 Formula (9) where K represents a coefficient.
  • the current I output at the second pole of the driving transistor DTFT has nothing to do with its threshold voltage V th . Therefore, the brightness of the light-emitting device is independent of the threshold voltage V th , and the brightness uniformity of the display panel is not affected by the threshold voltage V th of the driving transistor DTFT.
  • the compensation process does not increase the number of times the driving transistor DTFT is turned on or the operating time outside of normal display. Therefore, the compensation process does not reduce the service life of the display device.
  • FIG. 4 shows a schematic flowchart of a method for a pixel driving circuit according to an embodiment of the present disclosure.
  • the pixel driving circuit may be any applicable pixel driving circuit based on the embodiments of the present disclosure.
  • step 410 the reset phase P1, a control signal according to the reset Rest, the first voltage V1 to the second node J 2.
  • the reset circuit 120 provides the received first voltage V1 to the second node J 2 according to the reset control signal Rest, and then resets the first node J 1 . Further, according to the reset control signal Rest, the third transistor T3 is turned on and the first voltage V1 to the second node J2, to reset the voltage of the first point J 1.
  • step 420 in the data input stage P2, the data signal Vdata is provided to the first node J 1 according to the gate drive signal Scan, and the first voltage difference between the second voltage terminal and the first node J 1 is stored, and The second voltage difference between the first node J 1 and the second node J 2 .
  • the input circuit 110 provides the data signal Vdata to the first node J 1 according to the low-level gate driving signal Scan. Further, according to the gate driving signal Scan, the second transistor T2 is turned on and provides the data signal Vdata to the first node J1.
  • the compensation circuit 130 since the control transistor Tc of the reference electrode of the third voltage V3 received by the first node and the voltage difference is smaller than the threshold value J, J is the voltage of the first node 1 to the third node J 3.
  • the first storage circuit 1310 stores the second terminal voltage compensation circuit 130 and the first voltage between the first node J 1 difference. Further, the first capacitor C1 stores the first voltage difference.
  • the second storage circuit 1330 in the compensation circuit 130 stores the second voltage difference between the first node J 1 and the second node J 2 . Further, the second capacitor C2 stores the second voltage difference.
  • step 430 the compensated output stage P3, the control signal the CRT, the third voltage V3 to the second node J 2, based on the reference transistor Tc is the threshold voltage V th, the threshold voltage V th of the driving transistor DTFT compensate , and the driving transistor according to a first node DTFT compensated voltage VJ 12 and the second voltage V2, providing an output current to the light emitting device 200 I.
  • the compensation phase P31 according to the control signal CRT, the first transistor T1 is turned on and the third voltage V3 is provided to the second node J 2 .
  • the compensation circuit 130 compensates the threshold voltage V th of the driving transistor DTFT in response to the change of the first voltage V1 to the third voltage V3 of the second node J 2 .
  • the first voltage V1 is greater than the third voltage V3.
  • the threshold voltage V th of the driving transistor DTFT can be compensated sequentially through the following steps. First, the reference transistor Tc is turned on. Therefore, with respect to the first node J 1 , the first capacitor C1 and the second capacitor C2 are connected in parallel. Since the voltage at both ends of the second capacitor C2 cannot change suddenly, the amount of charge change at the second end of the second capacitor C2 is the same as that of the first end. As described above, in the present embodiment, the first voltage V1 is greater than the third voltage V3, thus reducing the voltage of the first node J 1, until the first transistor T1 is turned off.
  • the driving transistor based on the voltage VJ 12 DTFT and the second voltage V2, providing an output current to the light emitting device I.
  • the output current I can be calculated. This current I is independent of its threshold voltage V th . Therefore, the brightness of the light-emitting device is independent of the threshold voltage V th , and the brightness uniformity of the display panel is not affected by the threshold voltage V th of the driving transistor.
  • FIG. 5 shows a schematic block diagram of a display panel 600 according to an embodiment of the present disclosure.
  • the display panel 600 includes a pixel circuit 500.
  • the pixel circuit 500 includes the pixel driving circuit 100 according to an embodiment of the present disclosure and the light emitting device 200 coupled with the pixel driving circuit 100.
  • the display panel 600 provided by the embodiment of the present invention can be used in any display device.
  • the display device can be any product or component with a display function, such as an LCD panel, an LCD TV, a display, an OLED panel, an OLED TV, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, etc.

Abstract

一种像素驱动电路（100），其包括输入电路（110）、复位电路（120）、驱动晶体管（DTFT）和补偿电路（130）。输入电路（110）被配置为根据来自栅极驱动信号端的栅极驱动信号（Scan）将来自输入信号端的数据电压（Vdata）提供给第一节点（J 1）。复位电路（120）被配置为根据来自复位控制信号端的复位控制信号（Rest）将来自第一电压端的第一电压（V1）提供给第二节点（J 2）。驱动晶体管（DTFT）被配置为向发光器件（200）输出对应于控制极与第一极之间的电压差的电流。补偿电路（130）被配置为基于参考晶体管（Tc）的阈值电压对驱动晶体管（DTFT）的阈值电压进行补偿。

Description

像素驱动电路及其驱动方法、像素电路和显示面板 技术领域
本发明涉及显示技术领域。具体地，涉及像素驱动电路及其驱动方法、像素电路和显示面板。
背景技术
在显示领域中，有机发光二极管(Organic Light-Emitting Diode，简称OLED)显示装置具有可视角度广和响应速度快的特点，因此得到广泛的应用。在OLED显示装置中，像素驱动电路利用驱动晶体管提供的电流来驱动发光器件发光。
发明内容
本公开的实施例提供了像素驱动电路、像素电路、显示面板以及用于驱动像素驱动电路的方法。根据本公开的第一方面，提供了一种像素驱动电路。像素驱动电路包括输入电路、复位电路、驱动晶体管和补偿电路。输入电路耦接栅极驱动信号端、输入信号端和第一节点，并被配置为根据来自栅极驱动信号端的栅极驱动信号将来自输入信号端的数据信号提供给该第一节点。复位电路耦接复位控制信号端、第一电压端和第二节点，并被配置为根据来自复位控制信号端的复位控制信号将来自第一电压端的第一电压提供给第二节点。驱动晶体管包括：与第二电压端耦接的第一极；经由第一节点与补偿电路耦接的控制极；以及与发光器件耦接的第二极，并被配置为向发光器件输出对应于驱动晶体管的控制极与第一极之间的电压差的电流。补偿电路包括参考晶体管，补偿电路耦接第三电压端、第二节点、第一节点、控制信号端和第二电压端，并被配置为基于参考晶体管的阈值电压对驱动晶体管的阈值电压进行补偿。
在本公开的实施例中，补偿电路包括第一存储电路、参考晶体管、第二存储电路和控制电路。第一存储电路耦接第三节点与第二电压端之间， 被配置为存储第三节点与第二电压端之间的第一电压差。参考晶体管的控制极与第三电压端耦接，参考晶体管的第一极与所述第一节点耦接，参考晶体管的第二极与所述第三节点耦接，并被配置为根据参考晶体管的控制极与第一极之间的电压差，将第一节点的电压提供给第三节点。第二存储电路耦接在第二节点与第一节点之间，并被配置为存储第二节点与第一节点之间的第二电压差。控制电路耦接第二节点、控制信号端和第三电压端，并被配置为在来自控制信号端的控制信号的控制下，将第三电压提供给第二节点。
在本公开的实施例中，参考晶体管的阈值电压与驱动晶体管的阈值电压相同。
在本公开的实施例中，参考晶体管与驱动晶体管的材料、结构和形状均相同。
在本公开的实施例中，第一存储电路包括第一电容。第一电容的第一端与第三节点耦接，第一电容的第二端与第二电压端耦接。
在本公开的实施例中，第二存储电路包括第二电容。第二电容的第一端与第二节点耦接，第二电容的第二端与第一节点耦接。
在本公开的实施例中，第一电容的电容值与第二电容的电容值相同。
在本公开的实施例中，控制电路包括第一晶体管。第一晶体管的控制极与控制信号端耦接，第一晶体管的第一极与第三电压端耦接，第一晶体管的第二极与第二节点耦接。
在本公开的实施例中，输入电路包括第二晶体管。第二晶体管的控制极与栅极驱动信号端耦接，第二晶体管的第一极与输入信号端耦接，第二晶体管的第二极与第一节点耦接。
在本公开的实施例中，复位电路包括第三晶体管。第三晶体管的控制极与复位控制信号端耦接，第三晶体管的第一极与第一电压端耦接，第三晶体管的第二极与第二节点耦接。
在本公开的实施例中，第一存储电路包括第一电容。第一电容的第一端与第三节点耦接，第一电容的第二端与第二电压端耦接。第二存储电路 包括第二电容。第二电容的第一端与第二节点耦接，第二电容的第二端与第一节点耦接。第一电容的电容值与第二电容的电容值相同。控制电路包括第一晶体管。第一晶体管的控制极与控制信号端耦接，第一晶体管的第一极与第三电压端耦接，第一晶体管的第二极与第二节点耦接。输入电路包括第二晶体管。第二晶体管的控制极与栅极驱动信号端耦接，第二晶体管的第一极与输入信号端耦接，第二晶体管的第二极与第一节点耦接。复位电路包括第三晶体管。第三晶体管的控制极与复位控制信号端耦接，第三晶体管的第一极与第一电压端耦接，第三晶体管的第二极与第二节点耦接。
根据本公开的第二方面，提供了一种显示面板，该显示面板包括像素电路。该像素电路包括根据本公开的第一方面的像素驱动电路，以及与该像素驱动电路耦接的发光器件。
根据本公开的第三方面，提供了一种用于驱动本公开的第一方面的像素驱动电路的方法。该方法包括：在复位阶段，根据复位控制信号，将第一电压提供给第二节点，以对第一节点的电压进行复位；在数据输入阶段，根据栅极驱动信号，将数据信号提供给第一节点，并存储第二电压端与第一节点之间的第一电压差，以及第一节点与第二节点之间第二电压差；以及在补偿输出阶段，根据控制信号，将第三电压提供给第二节点，以基于参考晶体管的阈值电压补偿第一节点的电压来对驱动晶体管的阈值电压进行补偿，并使驱动晶体管根据补偿后的第一节点的电压和第二电压，向发光器件提供输出电流。
在本公开的实施例中，像素驱动电路为根据第一方面的像素驱动电路，补偿输出阶段包括补偿阶段和输出阶段，且参考晶体管的阈值电压与驱动晶体管的阈值电压相同。该方法包括：在复位阶段，根据复位控制信号，第三晶体管导通并将第一电压提供给第二节点，以对第一节点进行复位；在数据输入阶段，根据栅极驱动信号，第二晶体管导通并将数据信号提供给第一节点，并且第一电容存储第一电压差，第二电容存储第二电压差；以及在补偿输出阶段，其中，在补偿阶段，根据控制信号，第一晶体管导 通并将第三电压提供给第二节点，响应于第二节点的电压变化，参考晶体管首先导通，第一电容与第二电容并联并将第一节点的电压补偿为V3-V th，参考晶体管然后关断，第二电容继续将第一节点的电压补偿为2Vdata-V1+V th，其中，V3表示第三电压，V1表示第一电压，V th阈值电压，Vdata表示数据信号，其中，在输出阶段，驱动晶体管根据补偿后的第一节点的电压2Vdata-V1+V th和第二电压，向发光器件提供输出电流。
附图说明
为了更清楚地说明本公开的技术方案，下面将对实施例的附图进行简单说明。应当知道，以下描述的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。在附图中：
图1示出了根据本公开的实施例的像素驱动电路的示意性框图；
图2示出了根据本公开的实施例的像素驱动电路的示例性电路图；
图3示出了如图2所示的像素驱动电路的操作过程中各信号的时序图；
图4示出了根据本公开的实施例的用于驱动像素驱动电路的方法的示意性流程图；以及
图5示出了根据本公开的实施例的显示面板的示意性框图。
具体实施方式
为了使本公开的实施例的技术方案和优点更加清楚，下面将结合附图，对本公开的实施例的技术方案进行清楚、完整的描述。显然，所描述的实施例仅仅是本公开的一部分实施例，而并非全部的实施例。基于所描述的实施例，本领域的普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，也都属于本公开的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内技术人员所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而 是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“耦接”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，并且可以是直接连接也可以通过中间介质间接连接。
在OLED显示装置中，像素驱动电路通过控制驱动晶体管DTFT的控制极的电压，来控制向发光器件提供的电流，从而控制发光器件的发光亮度。具体地，驱动晶体管DTFT的第一极与恒定电压的电压端耦接。驱动晶体管根据控制极的电压与该恒定电压之间的电压差V GS，从第二极输出对应的电流。使用该电流来驱动发光器件发光。在驱动晶体管的第二极输出的电流I可通过公式(1)确定：
I＝K(V GS-V th) 2   公式(1)其中，K表示系数，V th表示驱动晶体管的阈值电压。
因此，从公式(1)可以看出，从第二极输出的电流I与驱动晶体管DTFT的阈值电压V th有关。因此，在相关技术的像素驱动电路中，驱动晶体管DTFT的阈值电压的差异会直接影响发光器件的发光亮度，从而影响整个显示装置的亮度均匀性。因此，为了满足对显示面板的发光的均匀性要求，需要提高驱动晶体管的诸如阈值电压等的电学特性的一致性。在现有技术中，可以采用内部补偿方式或外部补偿方式来提高驱动晶体管的电学特性的一致性。
在常规的内部补偿方法中，需要预先对DTFT进行上电以感测DTFT的阈值电压，然后才能基于感测的阈值电压对DTFT进行有效的阈值电压补偿。然而，这种方法会不利地增加DTFT在正常显示之外的操作时间，从而劣化DTFT的性能，进而降低显示装置的使用寿命。
针对上述准确性问题，本公开的实施例提供了一种像素驱动电路，其不仅能够对驱动晶体管的控制极的电压进行阈值电压补偿以解决由驱动晶体管的阈值电压的差异造成的亮度均匀性的问题，并且能够避免不必要地增加驱动晶体管操作时间。
本公开的实施例提供了像素驱动电路及其驱动方法、像素电路以及显示面板。下面结合附图对本公开的实施例及其示例进行详细说明。
图1示出了根据本公开的实施例的像素驱动电路的示意性框图。如图1所示，像素驱动电路100可包括输入电路110、复位电路120、驱动晶体管DTFT、补偿电路130。下面参照附图，对其进行详细描述。
输入电路110可与栅极驱动信号端、输入信号端和第一节点J 1耦接。输入电路110可从栅极驱动信号端接收栅极驱动信号Scan，从输入信号端接收数据信号Vdata。并且，输入电路110根据栅极驱动信号Scan将数据信号Vdata提供给第一节点J 1。
复位电路120与复位控制信号端、第一电压端和第二节点J 2耦接。复位电路120从复位控制信号端接收复位控制信号Rest，从第一电压端接收第一电压V1。此外，复位电路120根据复位控制信号Rest将第一电压V1提供给第二节点J 2，以便第一节点J 1可以被复位。
驱动晶体管DTFT的控制极和补偿电路130均与第一节点J 1耦接，因此，驱动晶体管DTFT的控制极可以经由第一节点J 1与补偿电路130耦接。驱动晶体管DTFT的第一极与第二电压端耦接，第二极与发光器件200耦接。驱动晶体管DTFT输出对应于在控制极与第一极之间的电压差的电流信号。在实施例中，发光器件可以是有机发光二极管。
补偿电路130包括参考晶体管Tc，并与第三电压端、第二节点J 2、第一节点J 1、控制信号端和第二电压端耦接。补偿电路130从第三电压端接收第三电压V3，从控制信号端接收控制信号CTR，从第二电压端接收第二电压V2，并根据控制信号CTR、第三电压V3和第二电压V2，基于参考晶体管Tc的阈值电压对驱动晶体管DTFT的阈值电压V th进行补偿。在本公开的实施例中，参考晶体管Tc与驱动晶体管DTFT具有相同的阈值电压，即V th。进一步地，参考晶体管Tc与驱动晶体管DTFT可以具有相同的材料、结构和形状。应该理解，在实际生产过程中，由于制造工艺本身的限制，参考晶体管Tc与驱动晶体管DTFT的阈值电压可以存在一定的差异。在本公开的实施例中，第三电压V3小于第一电压V1。
进一步地，补偿电路130包括第一存储电路1310、参考晶体管Tc、第二存储电路1320、控制电路1330。具体地，第一存储电路1310耦接在第三节点J 3与第二电压端之间，并存储第三节点J 3与第二电压端之间的第一电压差。参考晶体管Tc的控制极与第三电压端耦接，参考晶体管Tc的第一极与第一节点J 1耦接，参考晶体管Tc的第二极与第三节点J 3耦接，并根据第三电压V3与第一节点J 1的电压之间的电压差，将第一节点J 1的电压提供给第三节点J 3。第二存储电路1320耦接在第二节点J 2与第一节点J 1之间，并存储第二节点J 2与第一节点J 1之间的第二电压差。控制电路1330与第二节点J 2、控制信号端和第三电压端耦接。控制电路1330从控制信号端接收控制信号CTR，从第三电压端接收第三电压V3，并根据控制信号CTR，将第三电压V3提供给第二节点J 2。
以下通过示例性电路结构来对本公开的实施例提供的像素驱动电路进行描述。图2示出了根据本公开的实施例的像素驱动电路100的示例性电路图。如图2所示，像素驱动电路100可以包括参考晶体管Tc、第一晶体管T1至第三晶体管T3、第一电容C1和第二电容C2以及驱动晶体管DTFT。
第一晶体管T1至第三晶体管T3均为开关晶体管。
需要说明的是，本公开的实施例中采用的晶体管可以为薄膜晶体管或其它特性相同或类似的有源器件。本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，晶体管的栅极被称为控制极，除了栅极之外的两极被分别称为第一极和第二极。为了便于理解，在本公开的实施例中以P型增强型晶体管为示例进行描述，本领域的技术人员可以理解，其他类型的晶体管同样适用。
如图2所示，第一存储电路1310包括第一电容C1。第二存储电路1320包括第二电容C2。控制电路1330包括第一晶体管T1。下面，参照附图对补偿电路130中的第一存储电路1310、第二存储电路1320和控制电路1330进行具体描述。
第一电容C1的第一端耦接第三节点J 3，第二端耦接第二电压端，以存 储第三节点J 3与第二电压端之间的电压差。
第二电容C2的第一端耦接第二节点J 2，第二端耦接第一节点J 1，以存储第二节点J 2与第一节点J 1之间的电压差。在本实施例中，第一电容C1的电容值C 1和第二电容C2的电容值C 2相同。在实施例中，当第二节点J 2的电压改变且第一节点J 1不悬空时，由于电容两端的电压不能突变的特性，第二电容C2两端的电荷变化量相同。当第二节点J 2的电压改变且第一节点J 1处于悬空状态时，由于第二电容C2所存储的电压差不变(即，电容的等势跳变作用)，第一节点J 1的电压的变化量与第二节点J 2的电压变化量相同。
第一晶体管T1的控制极耦接控制信号端，以接收控制信号CTR。第一晶体管T1的第一极耦接第二节点J 2。第一晶体管T1的第二极耦接第三电压端，以接收第三电压V3。在本实施例中，当控制信号CTR为低电平时，第一晶体管T1导通，所接收的第三电压V3被提供给第二节点J 2。
如图2所示，输入电路110包括第二晶体管T2。第二晶体管T2的控制极耦接栅极驱动信号端，以接收栅极驱动信号Scan。第二晶体管T2的第一极耦接输入信号端，以接收数据信号Vdata。第二晶体管T2的第二极耦接第一节点J 1。当栅极驱动信号Scan为低电平时，第二晶体管T2导通，数据信号Vdata被提供给第一节点J 1。在本实施例中，数据信号Vdata不能使驱动晶体管DTFT导通，也就是说，数据信号Vdata与第二电压V2之间的电压差大于阈值电压V th。因此，数据信号Vdata应满足：Vdata>V2+V th。
如图2所示，复位电路120包括第三晶体管T3。第三晶体管T3的控制极耦接复位控制信号端，以接收复位控制信号Rest。第三晶体管T3的第一极耦接第一电压端，以接收第一电压V1。第三晶体管T3的第二极耦接第二节点J 2。当复位控制信号Rest为低电平时，第三晶体管T3导通，第一电压V1被提供给第二节点J 2。
在图2所示的实施例中，参考晶体管Tc、第一晶体管T1至第三晶体管T3以及驱动晶体管DTFT可以是P型晶体管。本领域的技术人员知道，参考晶体管Tc、第一晶体管T1至第三晶体管T3以及驱动晶体管DTFT也 可以是N型晶体管。
下面结合图3中的信号时序图，对图2中所示的像素驱动电路100的操作过程进行说明。
图3示出了如图2所示的像素驱动电路100的操作过程中各信号的时序图。可以理解的是，图3所示的信号时序图中的信号电压只是示意性的，不代表真实电压值。
如图3所示，在复位阶段P1，在复位控制信号端提供低电平的复位控制信号Rest时，第三晶体管T3导通。所接收的第一电压V1被提供给第二节点J 2，进而将第一节点J 1的电压复位为VJ 10。在本公开的实施例中，VJ 10与第二电压V2之间的电压差应大于驱动晶体管DTFT的阈值电压V th，以使得驱动晶体管DTFT关断。将在下文结合复位前的补偿输出阶段来详细描述该复位过程。
在数据输入阶段P2，在栅极驱动信号端提供低电平的栅极驱动信号Scan时，第二晶体管T2导通。所接收的数据电压Vdata被提供给第一节点J 1。另外，在第三电压V3的控制下，参考晶体管Tc导通，也就是说，第三电压V3与第一节点J 1之间的电压差小于等于阈值电压V th。因此，数据信号Vdata应满足：Vdata≥V3-V th。第一电容C1存储第二电压V2与第一节点J 1之间的第一电压差，即V2-Vdata。第二电容C2存储第一节点J 1与第二节点J 2之间的第二电压差，即Vdata-V3。
补偿输出阶段P3包括补偿阶段P31和输出阶段P32。在补偿阶段P31，在控制信号端提供低电平的控制信号CRT时，第一晶体管T1导通，所接收的第三电压V3被提供给第二节点J 2。第二节点J 2的电压从第一电压V1变为第三电压V3。在参考晶体管Tc的控制极所接收的第三电压V3与第一节点J 1的电压之间的电压差小于等于阈值电压V th时，参考晶体管Tc导通。针对第一节点J 1，第一电容C1与第二电容C2并联。响应于第二节点J 2的电压的由第一电压V1变为第三电压V3，第二电容C2的第一端与第二端的电荷变化量相同。如前所述，在本实施例中，第一电压V1大于第三电压V3，因此第一节点J 1的电压降低。然后，参考晶体管Tc的控制极所 接收的第三电压V3与第一节点J 1的电压之间的电压差变为大于阈值电压V th，使得参考晶体管Tc关断。基于第二电容C2的等势跳变作用，第二节点J 2的电压变化量等于第一节点J 1的电压变化量。在参考晶体管Tc由导通切换为关断状态的即刻第一节点J 1的电压为VJ 11，其可以通过下式来计算：
VJ 11＝V3-V th   公式(2)
假设在参考晶体管Tc导通期间，第二节点J 2的电压变化量为ΔV1，则与第二节点J 2耦接的第二电容C2的第一端的电荷变化量ΔQ 1可以通过以下公式计算：
ΔQ 1＝ΔV1*C 2   公式(3)
如前所述，针对第一节点J 1，第一电容C1与第二电容C2并联，因此与第一节点J 1耦接的第二电容C2的第二端的电荷变化量ΔQ 2可以通过下式计算：
ΔQ 2＝(C 1+C 2)*(VJ 11-Vdata)   公式(4)
第二电容C2的第一端的电荷变化量ΔQ 1应等于第二电容C2的第二端的电荷变化量ΔQ 2。因此，通过公式(3)和公式(4)可以获得在参考晶体管Tc导通到关断期间，第二节点J 2的电压变化量ΔV1为：
ΔV1＝(C 1+C 2)/C 2*(VJ 11-Vdata)，在本实施例中，第一电容C 1与第二电容C 2的电容值相同，因此
ΔV1＝2(VJ 11-Vdata)   公式(5)
然后，参考晶体管Tc关断。假设在参考晶体管Tc关断后，第二节点J 2的电压变化量为ΔV2，第一节点J 1的稳定电压为VJ 12。在参考晶体管Tc关断后，第一节点J 1处于悬浮状态，基于第二电容C2的等势跳变作用，第一节点J 1的电压变化量等于第二节点J 2的电压变化量ΔV2，即：
ΔV2＝VJ 12-VJ 11   公式(6)
因此，第二节点J 2的总的电压变化量V3-V1应满足以下关系式：
V3-V1＝ΔV1+ΔV2
＝2(VJ 11-Vdata)+VJ 12-VJ 11
＝VJ 11-2Vdata+VJ 12   公式(7)
结合公式(2)，可以得到：
VJ 12＝2Vdata-V1+V th   公式(8)
在输出阶段P32，向驱动晶体管DTFT的控制极提供电压VJ 12＝2Vdata-V1+Vth。基于电压VJ 12和第二电压V2，驱动晶体管DTFT可以向发光器件提供输出电流I，因此2Vdata-V1+Vth-V2≤Vth，从而数据信号Vdata应满足Vdata≤1/2(V1+V2)。基于电压VJ 12和第三电压V3，参考晶体管Tc关断，因此V3-(2Vdata-V1+Vth)>Vth，从而数据信号Vdata还应满足Vdata<1/2(V1+V3)-Vth。此时根据公式(1)可以计算从驱动晶体管DTFT的第二极输出的电流I，如公式(9)所示：
I＝K(V GS-V th) 2
＝K[((2Vdata-V1+V th)-V2-V th] 2
＝K(2Vdata-V1-V2) 2   公式(9)其中，K表示系数。
根据公式(9)可以得出，在驱动晶体管DTFT的第二极输出的电流I与其阈值电压V th无关。因此，发光器件的亮度与阈值电压V th无关，进而显示面板的亮度均匀性不受驱动晶体管DTFT的阈值电压V th的影响。另外，补偿过程没有增加驱动晶体管DTFT的开启次数或正常显示外的操作时间，因此，该补偿过程不会降低显示装置的使用寿命。
然后，为下一数据信号的输入做准备，进入复位阶段。此过程与补偿阶段中的补偿过程相反。具体地，在复位阶段，在复位控制信号端提供低电平的复位控制信号Rest时，第三晶体管T3导通。所接收的第一电压V1 被提供给第二节点J 2。第二节点J 2的电压从第三电压V3变为第一电压V1。在参考晶体管Tc的控制极所接收的第三电压V3与第一节点J 1的电压之间的电压差大于阈值电压V th时，参考晶体管Tc关断。由于第二电容C2的等势跳变作用，第一节点J 1的电压变化量与第二节点J 2的电压变化量相同。如前所述，在本实施例中，第一电压V1大于第三电压V3，因此第一节点J 1的电压升高。然后，所接收的第三电压V3与第一节点J 1的电压之间的电压差变为小于等于阈值电压V th，使得参考晶体管Tc导通。对于第一节点J 1，第一电容C1与第二电容C2并联。由于第二电容C2两端的电荷变化量相同，因此，第一节点J 1的电压继续升高。此过程与补偿阶段P31中的过程相反，可以计算出第一节点J 1复位后的电压为数据电压Vdata，即VJ 10＝Vdata，在此不再赘述。
此外，本公开的实施例还提供了用于像素驱动电路的方法。图4示出了根据本公开的实施例的用于像素驱动电路的方法的示意性流程图。像素驱动电路可以是基于本公开的实施例的任何可适用的像素驱动电路。
在步骤410，在复位阶段P1，根据复位控制信号Rest，将第一电压V1提供给第二节点J 2。在实施例中，复位电路120根据复位控制信号Rest，将所接收的第一电压V1提供给第二节点J 2，进而对第一节点J 1进行复位。进一步地，根据复位控制信号Rest，第三晶体管T3导通并将第一电压V1提供给第二节点J2，以对第一节点J 1的电压进行复位。
在步骤420，在数据输入阶段P2，根据栅极驱动信号Scan，将数据信号Vdata提供给第一节点J 1，并存储第二电压端与第一节点J 1之间的第一电压差，以及第一节点J 1与第二节点J 2之间的第二电压差。在实施例中，输入电路110根据低电平的栅极驱动信号Scan，将数据信号Vdata提供给第一节点J 1。进一步地，根据栅极驱动信号Scan，第二晶体管T2导通并将数据信号Vdata提供给第一节点J1。然后，由于补偿电路130中的参考晶体管Tc的控制极所接收的第三电压V3与第一节点J 1的电压差小于阈值，将第一节点J 1的电压提供给第三节点J 3。补偿电路130中的第一存储电路1310存储第二电压端与第一节点J 1之间的第一电压差。进一步地，第 一电容C1存储第一电压差。补偿电路130中的第二存储电路1330存储第一节点J 1与第二节点J 2之间的第二电压差。进一步地，第二电容C2存储第二电压差。
在步骤430，在补偿输出阶段P3，根据控制信号CRT，将第三电压V3提供给第二节点J 2，以基于参考晶体管Tc的阈值电压V th，对驱动晶体管DTFT的阈值电压V th进行补偿，并使驱动晶体管DTFT根据补偿后的第一节点的电压VJ 12和第二电压V2，向发光器件200提供输出电流I。其中，在补偿阶段P31，根据控制信号CRT，第一晶体管T1导通并将第三电压V3提供给第二节点J 2。补偿电路130响应于第二节点J 2第一电压V1到第三电压V3的变化，对驱动晶体管DTFT的阈值电压V th进行补偿。如前所述，在本实施例中，第一电压V1大于第三电压V3。可以顺序通过以下步骤来对驱动晶体管DTFT的阈值电压V th进行补偿。首先，参考晶体管Tc导通。因此，相对于第一节点J 1，第一电容C1与第二电容C2并联。基于第二电容C2两端的电压不能突变，因此第二电容C2的第二端与第一端的电荷变化量相同。如前所述，在本实施例中，第一电压V1大于第三电压V3，因此第一节点J 1的电压降低，直到第一晶体管T1关断。如上所述，J 1点的电压为V3-V th；然后，在参考晶体管Tc变为关断，基于第二电容C2的等势跳变作用，第一节点J 1的电压继续降低。根据公式(8)，可以得出第一节点J 1的电压被补偿为VJ 12＝2Vdata-V1+Vth。在输出阶段P32，驱动晶体管DTFT根据电压VJ 12和第二电压V2，向发光器件提供输出电流I。根据公式(9)可以计算输出电流I。该电流I与其阈值电压V th无关。因此，发光器件的亮度与阈值电压V th无关，进而显示面板的亮度均匀性不受驱动晶体管的阈值电压V th的影响。
本领域技术人员可以理解，以上各步骤虽然按顺序描述，但并不构成对方法顺序的限定，本公开的实施例也可以以任何其它合适顺序实施。
此外，本公开的实施例还提供了显示面板。图5示出了根据本公开的实施例的显示面板600的示意性框图。如图5所示，显示面板600包括像素电路500。像素电路500包括根据本公开的实施例所述的像素驱动电路 100和与像素驱动电路100耦接的发光器件200。本发明的实施例提供的显示面板600可以用于任何显示装置。显示装置可以为液晶面板、液晶电视、显示器、OLED面板、OLED电视、电子纸显示装置、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。以上对本公开的若干实施方式进行了详细描述，但本公开的保护范围并不限于此。显然，对于本领域的普通技术人员来说，在不脱离本公开的精神和范围的情况下，可以对本公开的实施例进行各种修改、替换或变形。本公开的保护范围由所附权利要求限定。

Claims (14)

  1. 一种像素驱动电路，包括：输入电路、复位电路、驱动晶体管和补偿电路，其中：
    所述输入电路耦接栅极驱动信号端、输入信号端和第一节点，并被配置为根据来自所述栅极驱动信号端的栅极驱动信号将来自所述输入信号端的数据信号提供给所述第一节点；
    所述复位电路耦接复位控制信号端、第一电压端和第二节点，并被配置为根据来自所述复位控制信号端的复位控制信号将来自所述第一电压端的第一电压提供给所述第二节点；
    所述驱动晶体管包括：与第二电压端耦接的第一极；经由第一节点与所述补偿电路耦接的控制极；以及与发光器件耦接的第二极，并被配置为向所述发光器件输出对应于所述驱动晶体管的所述控制极与所述第一极之间的电压差的电流；
    所述补偿电路包括参考晶体管，所述补偿电路耦接第三电压端、所述第二节点、所述第一节点、控制信号端和所述第二电压端，被配置为基于所述参考晶体管的阈值电压对所述驱动晶体管的阈值电压进行补偿。
  2. 根据权利要求1所述的像素驱动电路，所述补偿电路包括第一存储电路、参考晶体管、第二存储电路和控制电路，其中：
    所述第一存储电路耦接第三节点与所述第二电压端之间，被配置为存储所述第三节点与所述第二电压端之间的第一电压差；
    所述参考晶体管的控制极与所述第三电压端耦接，所述参考晶体管的第一极与所述第一节点耦接，所述参考晶体管的第二极与所述第三节点耦接，并被配置为根据所述参考晶体管的所述控制极与所述第一极之间的电压差，将所述第一节点的电压提供给所述第三节点；
    所述第二存储电路耦接在所述第二节点与所述第一节点之间，并被配置为存储所述第二节点与所述第一节点之间的第二电压差；以及
    所述控制电路耦接所述第二节点、控制信号端和所述第三电压端，并被配置为在来自所述控制信号端的控制信号的控制下，将所述第三电压提 供给所述第二节点。
  3. 根据权利要求2所述的像素电路，其中，所述参考晶体管的阈值电压与所述驱动晶体管的阈值电压相同。
  4. 根据权利要求3所述的像素电路，其中，所述参考晶体管与所述驱动晶体管的材料、结构和形状均相同。
  5. 根据权利要求2所述的像素驱动电路，其中，所述第一存储电路包括第一电容，所述第一电容的第一端与所述第三节点耦接，所述第一电容的第二端与所述第二电压端耦接。
  6. 根据权利要求5中所述的像素驱动电路，其中，所述第二存储电路包括第二电容，所述第二电容的第一端与所述第二节点耦接，所述第二电容的第二端与所述第一节点耦接。
  7. 根据权利要求6中所述的像素驱动电路，其中，所述第一电容的电容值与所述第二电容的电容值相同。
  8. 根据权利要求2中所述的像素驱动电路，其中，所述控制电路包括第一晶体管，所述第一晶体管的控制极与所述控制信号端耦接，所述第一晶体管的第一极与所述第三电压端耦接，所述第一晶体管的第二极与所述第二节点耦接。
  9. 根据权利要求1至8中任一项所述的像素驱动电路，其中，所述输入电路包括第二晶体管，所述第二晶体管的控制极与所述栅极驱动信号端耦接，所述第二晶体管的第一极与所述输入信号端耦接，所述第二晶体管的第二极与所述第一节点耦接。
  10. 根据权利要求1至8中任一项所述像素驱动电路，其中，所述复位电路包括第三晶体管，所述第三晶体管的控制极与所述复位控制信号端耦接，所述第三晶体管的第一极与所述第一电压端耦接，所述第三晶体管的第二极与所述第二节点耦接。
  11. 根据权利要求2所述像素驱动电路，其中：
    所述第一存储电路包括第一电容，所述第一电容的第一端与所述第三节点耦接，所述第一电容的第二端与所述第二电压端耦接；
    所述第二存储电路包括第二电容，所述第二电容的第一端与所述第二节点耦接，所述第二电容的第二端与所述第一节点耦接，其中，所述第一电容的电容值与所述第二电容的电容值相同；
    所述控制电路包括第一晶体管，所述第一晶体管的控制极与所述控制信号端耦接，所述第一晶体管的第一极与所述第三电压端耦接，所述第一晶体管的第二极与所述第二节点耦接；
    所述输入电路包括第二晶体管，所述第二晶体管的控制极与所述栅极驱动信号端耦接，所述第二晶体管的第一极与所述输入信号端耦接，所述第二晶体管的第二极与所述第一节点耦接；以及
    所述复位电路包括第三晶体管，所述第三晶体管的控制极与所述复位控制信号端耦接，所述第三晶体管的第一极与所述第一电压端耦接，所述第三晶体管的第二极与所述第二节点耦接。
  12. 一种显示面板，包括像素电路，其中，所述像素电路包括：
    如权利要求1至11中任一项所述的像素驱动电路；以及
    与所述像素驱动电路耦接的发光器件。
  13. 一种用于驱动如权利要求1至11中任一项所述的像素驱动电路的方法，所述方法包括：
    在复位阶段，根据复位控制信号，将第一电压提供给第二节点，以对第一节点的电压进行复位；
    在数据输入阶段，根据栅极驱动信号，将数据信号提供给所述第一节点，并存储第二电压端与所述第一节点之间的第一电压差，以及所述第一节点与所述第二节点之间的第二电压差；以及
    在补偿输出阶段，根据控制信号，将第三电压提供给所述第二节点，以基于所述参考晶体管的阈值电压补偿所述第一节点的电压来对所述驱动晶体管的阈值电压进行补偿，并使所述驱动晶体管根据补偿后的所述第一节点的电压和第二电压，向发光器件提供输出电流。
  14. 根据权利要求13所述的一种用于驱动像素驱动电路的方法，其中，所述像素驱动电路为如权利要求11所述的像素驱动电路，所述补偿输出阶 段包括补偿阶段和输出阶段，所述参考晶体管的阈值电压与所述驱动晶体管的阈值电压相同，所述方法包括：
    在所述复位阶段，根据所述复位控制信号，所述第三晶体管导通并将所述第一电压提供给所述第二节点，以对所述第一节点的电压进行复位；
    在所述数据输入阶段，根据所述栅极驱动信号，所述第二晶体管导通并将所述数据信号提供给所述第一节点，并且所述第一电容存储所述第一电压差，所述第二电容存储所述第二电压差；以及
    在所述补偿输出阶段，其中：
    在所述补偿阶段，根据所述控制信号，所述第一晶体管导通并将所述第三电压提供给所述第二节点，响应于所述第二节点的电压变化，所述参考晶体管首先导通，所述第一电容与所述第二电容并联并将所述第一节点的电压补偿为V3-V th，所述参考晶体管然后关断，所述第二电容继续将所述第一节点的电压补偿为2Vdata-V1+V th，其中，V3表示所述第三电压，V1表示所述第一电压，V th表示阈值电压，Vdata表示所述数据信号；以及
    在所述输出阶段，所述驱动晶体管根据补偿后的所述第一节点的电压2Vdata-V1+V th和所述第二电压，向所述发光器件提供所述输出电流。
PCT/CN2019/094392 2019-07-02 2019-07-02 像素驱动电路及其驱动方法、像素电路和显示面板 WO2021000259A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201980000984.4A CN112449713B (zh) 2019-07-02 2019-07-02 像素驱动电路及其驱动方法、像素电路和显示面板
PCT/CN2019/094392 WO2021000259A1 (zh) 2019-07-02 2019-07-02 像素驱动电路及其驱动方法、像素电路和显示面板
US16/767,456 US11462165B2 (en) 2019-07-02 2019-07-02 Pixel driving circuit, related driving method, pixel circuit, and display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2019/094392 WO2021000259A1 (zh) 2019-07-02 2019-07-02 像素驱动电路及其驱动方法、像素电路和显示面板

Publications (1)

Publication Number Publication Date
WO2021000259A1 true WO2021000259A1 (zh) 2021-01-07

Family

ID=74100484

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/094392 WO2021000259A1 (zh) 2019-07-02 2019-07-02 像素驱动电路及其驱动方法、像素电路和显示面板

Country Status (3)

Country Link
US (1) US11462165B2 (zh)
CN (1) CN112449713B (zh)
WO (1) WO2021000259A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111063305A (zh) * 2020-01-07 2020-04-24 深圳市华星光电半导体显示技术有限公司 像素电路、显示面板及像素电路基准电压的补偿方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140118328A1 (en) * 2012-10-25 2014-05-01 Innolux Corporation Pixel driving circuit of an active-matrix organic light-emitting diode and a method of driving the same
CN104680981A (zh) * 2015-03-26 2015-06-03 京东方科技集团股份有限公司 Oled像素驱动电路及驱动方法、oled显示装置
CN104835453A (zh) * 2015-05-28 2015-08-12 京东方科技集团股份有限公司 一种像素电路、驱动方法及显示装置
CN105845081A (zh) * 2016-06-12 2016-08-10 京东方科技集团股份有限公司 像素电路、显示面板及驱动方法
CN107103880A (zh) * 2017-06-16 2017-08-29 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、阵列基板以及显示装置
CN107256694A (zh) * 2017-07-31 2017-10-17 武汉华星光电半导体显示技术有限公司 显示装置、像素驱动方法及像素驱动电路

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103310728B (zh) * 2013-05-29 2015-05-20 京东方科技集团股份有限公司 发光二极管像素单元电路和显示面板
CN104658481B (zh) * 2015-03-11 2017-03-22 京东方科技集团股份有限公司 一种像素补偿电路、显示装置和驱动方法
CN106710516A (zh) * 2015-08-26 2017-05-24 上海和辉光电有限公司 显示装置、像素驱动电路及其驱动方法
CN110070825B (zh) * 2018-06-14 2020-10-09 友达光电股份有限公司 像素电路

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140118328A1 (en) * 2012-10-25 2014-05-01 Innolux Corporation Pixel driving circuit of an active-matrix organic light-emitting diode and a method of driving the same
CN104680981A (zh) * 2015-03-26 2015-06-03 京东方科技集团股份有限公司 Oled像素驱动电路及驱动方法、oled显示装置
CN104835453A (zh) * 2015-05-28 2015-08-12 京东方科技集团股份有限公司 一种像素电路、驱动方法及显示装置
CN105845081A (zh) * 2016-06-12 2016-08-10 京东方科技集团股份有限公司 像素电路、显示面板及驱动方法
CN107103880A (zh) * 2017-06-16 2017-08-29 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、阵列基板以及显示装置
CN107256694A (zh) * 2017-07-31 2017-10-17 武汉华星光电半导体显示技术有限公司 显示装置、像素驱动方法及像素驱动电路

Also Published As

Publication number Publication date
CN112449713B (zh) 2022-06-03
CN112449713A (zh) 2021-03-05
US20210407417A1 (en) 2021-12-30
US11462165B2 (en) 2022-10-04

Similar Documents

Publication Publication Date Title
CN113192460B (zh) 一种显示面板和显示装置
TWI425472B (zh) 像素電路及其驅動方法
WO2018129932A1 (zh) 移位寄存器单元电路及其驱动方法、栅极驱动电路和显示装置
CN107464526B (zh) 一种像素补偿电路、其驱动方法及显示装置
WO2021143930A1 (zh) 像素电路、显示装置及驱动方法
CN109523952B (zh) 一种像素电路及其控制方法、显示装置
WO2020181515A1 (zh) 像素电路及其驱动方法、显示装置
WO2020181512A1 (zh) 像素电路及其驱动方法、显示装置
CN107369413B (zh) 一种像素补偿电路、其驱动方法、显示面板及显示装置
WO2020107830A1 (zh) 像素电路及显示装置
WO2015143835A1 (zh) 像素补偿电路、阵列基板及显示装置
US20180247592A1 (en) Pixel Driving Circuit and Driving Method Thereof, Array Substrate, and Display Device
WO2023011333A1 (zh) 像素驱动电路及其驱动方法、显示面板
US11222594B2 (en) Digital pixel driving circuit and digital pixel driving method
WO2022016706A1 (zh) 像素电路、其驱动方法及显示装置
US20230230547A1 (en) Display panel and display device
WO2019114573A1 (zh) 电路驱动补偿方法、电路驱动方法及装置、显示装置
CN108470541B (zh) 像素电路及其驱动方法、显示面板及显示装置
WO2021184192A1 (zh) 像素电路及其驱动方法和显示装置
WO2022095044A1 (zh) 显示面板及其驱动方法、显示装置
WO2021000259A1 (zh) 像素驱动电路及其驱动方法、像素电路和显示面板
WO2024001065A1 (zh) 像素电路及显示面板
WO2022226727A1 (zh) 像素电路、像素驱动方法和显示装置
CN108831383B (zh) 像素电路及其驱动方法、显示面板及显示装置
US20210358412A1 (en) Pixel circuit and driving method thereof, display panel

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19935965

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19935965

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 19935965

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 03.08.2022)

122 Ep: pct application non-entry in european phase

Ref document number: 19935965

Country of ref document: EP

Kind code of ref document: A1