WO2020258813A1 - 一种加速度计、环境传感器的集成芯片及其制造方法 - Google Patents

一种加速度计、环境传感器的集成芯片及其制造方法 Download PDF

Info

Publication number
WO2020258813A1
WO2020258813A1 PCT/CN2019/130101 CN2019130101W WO2020258813A1 WO 2020258813 A1 WO2020258813 A1 WO 2020258813A1 CN 2019130101 W CN2019130101 W CN 2019130101W WO 2020258813 A1 WO2020258813 A1 WO 2020258813A1
Authority
WO
WIPO (PCT)
Prior art keywords
varistor
mass
sensitive film
cantilever beam
integrated chip
Prior art date
Application number
PCT/CN2019/130101
Other languages
English (en)
French (fr)
Inventor
李向光
付博
方华斌
Original Assignee
潍坊歌尔微电子有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 潍坊歌尔微电子有限公司 filed Critical 潍坊歌尔微电子有限公司
Publication of WO2020258813A1 publication Critical patent/WO2020258813A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
    • G01P1/00—Details of instruments
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
    • G01P15/00—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
    • G01P15/02—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses
    • G01P15/08—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
    • G01P15/12—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values by alteration of electrical resistance

Definitions

  • the present invention relates to the field of integrated chips, and more specifically, to a chip in which an accelerometer and an environmental sensor are integrated; the present invention also relates to a manufacturing method of the integrated chip.
  • sensors are no longer limited to mobile phone applications, and have been widely used in wearable devices, smart homes, smart transportation, industrial manufacturing and other fields.
  • inertial devices and environmental sensors mostly use different process flows, so only two different chips can be used to detect inertial signals and environmental signals. This not only increases the cost of manufacturing, but also also increases the use area of the chip. Moreover, the manufacturing process of each sensor is relatively mature, and the process capability is close to the limit, and it is difficult to further reduce the size of the chip according to the requirements of the system manufacturer.
  • An object of the present invention is to provide a new technical solution for an integrated chip of accelerometer and environmental sensor.
  • an integrated chip of an accelerometer and an environmental sensor which includes a support part, and a mass connected to the support part through a cantilever beam; a first A varistor; the first varistor is configured to detect the degree of deformation of the cantilever beam when the mass is affected by acceleration;
  • the mass block has a groove; further comprising a sensitive film arranged on the mass block and covering the groove; the sensitive film is sensitive to the environment; a second varistor is arranged on the sensitive film; the The second varistor is configured to detect the degree to which the sensitive film is deformed by environmental changes.
  • each cantilever beam corresponds to at least one first varistor; the plurality of first varistors form a Wheatstone bridge.
  • the plurality of second varistors form a Wheatstone bridge.
  • the first varistor is arranged at a position where the cantilever beam is connected to the support part, and a part of the first varistor is located at the cantilever beam position and the other part is located on the support part.
  • a part of the second varistor is arranged at a position corresponding to the groove on the sensitive film, and the other part is arranged at a position corresponding to the mass block on the sensitive film.
  • the cantilever beam and the sensitive film are made of the same material and manufactured by the same process.
  • the sensitive membrane is sensitive to pressure
  • the cavity enclosed by the sensitive membrane and the groove is a vacuum chamber.
  • it further includes a substrate, and the bottom end of the support part is connected to the substrate and encloses a space for accommodating the mass with the substrate.
  • the back side of the first wafer is etched to form a mass in the middle, a supporting part on the outside of the mass, and release the mass and the cantilever beam.
  • the step of bonding the supporting part to the substrate is further included.
  • integrating the accelerometer and the environmental sensor in the same chip can greatly reduce the space occupied by the chip, which is conducive to the miniaturization of electronic devices.
  • Figure 1 is a top view of the integrated chip of the present invention.
  • Figure 2 is a cross-sectional view of the integrated chip of the present invention.
  • Fig. 3 is a schematic diagram of the integrated chip in Fig. 1 under acceleration.
  • Fig. 4 is a schematic diagram of the integrated chip in Fig. 1 when subjected to pressure changes.
  • 5a to 5e are flow charts of the manufacturing process of the integrated chip of the present invention.
  • the present invention provides an integrated chip of an accelerometer and an environmental sensor, comprising a substrate 1 and a supporting portion 2 supported on the substrate 1, and connected to the supporting portion 2 through a cantilever beam 3 The quality block 4.
  • the bottom end of the supporting part 2 is connected to the substrate 1 and surrounds the substrate 1 with a space for accommodating the mass 4.
  • the supporting part 2 plays a role of supporting and receiving.
  • the mass 4 is supported on the supporting part 2 through the cantilever beam 3 so that the mass 4 can be displaced in a direction perpendicular to the mass 4 when subjected to external acceleration.
  • one end of the four cantilever beams 3 are respectively connected to the center positions of the four side walls of the mass 4, and the other end is connected to the supporting portion 2, so that the mass 4 can be stably supported.
  • a first varistor 6 is provided on the cantilever beam 3, and the first varistor 6 can be provided on the cantilever beam 3 in a manner well known to those skilled in the art.
  • the resistance value of the first varistor 6 will change with the deformation, for example, the resistance value increases or decreases, which can characterize the degree of deformation of the cantilever beam.
  • the number of the first varistor 6 can be multiple.
  • the four first varistors 6 constitute a Wheatstone bridge, so that the first varistor can detect the deformation information of the cantilever 3 when the mass 4 is accelerated.
  • each cantilever beam 3 may also be provided with multiple first varistors 6, which will not be described in detail here.
  • the mass 4 when affected by the downward acceleration, the mass 4 will drive the four cantilever beams 3 to deform downward, thereby changing the resistance of the first varistor 6 on the cantilever beam 3, thereby passing the first A Wheatstone bridge composed of a varistor 6 detects the changing electrical signal to characterize the deformation state of the cantilever beam 3.
  • the resistance change of one pair of first varistors is opposite to the resistance change of the other pair of first varistors.
  • the resistance change of the other pair of first varistors decreases.
  • the varistors with different variations can be manufactured by a process well known to those skilled in the art, and will not be described in detail here.
  • the first varistor 6 is arranged at a position where the cantilever beam 3 is connected to the support part 2. Referring to FIG. 1, a part of the first varistor 6 is located at the position of the cantilever beam 3 and the other part is located on the support part 2. When the cantilever beam 3 deforms, the deformation at the connection position of the cantilever beam 3 with the support portion 2 is the largest. Setting the first varistor 6 at this position can improve the sensitivity of the first varistor 6.
  • the integrated chip of the present invention is provided with grooves on the mass block 4; further comprising a sensitive film 5 arranged on the mass block 4 and covering the grooves.
  • the sensitive film 5 can be attached to the end face of the mass 4 and cover the groove.
  • the sensitive film 5 can be made of different materials according to different detection environment information.
  • the environmental sensor is a temperature sensor
  • the sensitive film 5 uses a temperature-sensitive material.
  • the environmental sensor is a humidity sensor or a gas sensor
  • the sensitive film 5 is made of materials sensitive to humidity or gas.
  • the environmental sensor is an air pressure sensor
  • the sensitive film 5 is made of a material sensitive to pressure.
  • the cavity enclosed by the sensitive film 5 and the groove on the mass 4 is a vacuum cavity 8, refer to FIG. 3.
  • a second varistor 7 is provided on the sensitive film 5.
  • the working principle of the second varistor 7 is the same as that of the first varistor 6.
  • the second varistor 7 can be used to detect that the sensitive film 5 is subjected to The degree of pressure deformation to characterize the size of the external pressure.
  • the second varistor 7 can be provided on the sensitive film 5 by means of ion implantation well known to those skilled in the art.
  • the number of the second piezoresistors 7 can be set in multiples. In the embodiment of FIG. 1 and FIG. 2, there are four second piezoresistors 7 which are evenly distributed on the sensitive film 5.
  • the four second varistors 7 constitute a Wheatstone bridge through which the deformation of the sensitive film 5 when it is pressed is detected.
  • the differential output of the bridge is 0; when the external air pressure acts on the membrane, the membrane will be deformed due to the pressure difference inside and outside the cavity, and the stress generated by the deformation will act on the second pressure sensitive membrane.
  • the resistance value of the second varistor 7 is changed ( ⁇ R), and the differential output of the bridge is a non-zero value.
  • the resistance change of one pair of second varistors is opposite to the resistance change of the other pair of second varistors.
  • the resistance of one pair of second varistors becomes larger, while the resistance of the other pair of second varistors decreases.
  • the varistors with different variations can be manufactured by a process well known to those skilled in the art, and will not be described in detail here.
  • a part of the second varistor 7 is arranged at a position corresponding to the groove on the sensitive film 5, and the other part is arranged at a position corresponding to the mass 4 on the sensitive film 5.
  • the sensitive film 5 in the suspended position is deformed, the deformation at the boundary between it and the mass 4 is the largest. Placing the second varistor 7 at this position can improve the sensitivity of the second varistor 7.
  • the cantilever beam 3 and the sensitive film 5 of the present invention are located on the same layer and are made of the same material. Both can be manufactured through the same process, which improves the manufacturing efficiency.
  • the present invention also provides a method for manufacturing the integrated chip of the accelerometer and environmental sensor, which includes the following steps:
  • a groove 13 is formed on the first wafer 10 by etching.
  • a silicon dioxide layer 11 can be grown on both sides of the first wafer 10, and a window can be opened on the silicon dioxide layer 11 on one side to form an etching window 12. 5a.
  • the first wafer 10 is etched through the etching window 12 to form the groove 13.
  • the etching method may be, for example, a deep reactive ion etching (DRIE) technique.
  • DRIE deep reactive ion etching
  • other methods for forming the groove 13 on the first wafer 10 can also be selected, which will not be described in detail here.
  • the second wafer is bonded to the side of the first wafer 10 on which the groove 13 is provided by bonding, so that the second wafer bonded on the surface of the first wafer 10 covers the groove 13.
  • the above-mentioned bonding can be completed in a vacuum environment, so that the second wafer and the groove 13 enclose the vacuum chamber 8, refer to FIG. 5c.
  • the second wafer is ground to form a thin film 14 bonded on the first wafer 10.
  • the specific grinding method belongs to the common knowledge of those skilled in the art, and will not be described in detail here.
  • a first varistor and a second varistor are formed on the film by ion implantation.
  • a first piezoresistor 6 and a second piezoresistor 7 are formed at corresponding positions of the thin film 14 by means of ion implantation.
  • the number, type and position of the first varistor 6 and the second varistor 7 are determined according to the specific structure.
  • connecting wires are formed on the thin film 14 by ion implantation, and the plurality of first varistors 6 form a Wheatstone bridge through these wires, and the plurality of second varistors 7 form a Wheatstone bridge.
  • the film is etched to form a cantilever beam and a sensitive film.
  • the film is etched at the corresponding position of the film to form the cantilever beam 3 and the sensitive film 5 above the first wafer 10.
  • the back surface of the first wafer 10 is etched to form a mass 4 located in the middle, and a supporting portion 2 located outside the mass 4, and release the mass 4 and the cantilever 3.
  • the back surface of the first wafer 10 may be etched by deep reactive ion etching (DRIE) technology to form the structure of the mass 4, and the portion of the first wafer 10 corresponding to the underside of the cantilever 3 is etched After being dropped, the cantilever beam 3 is released, and a supporting portion 2 supporting the cantilever beam 3 is formed.
  • DRIE deep reactive ion etching
  • the bottom end of the first wafer 10 is bonded to the substrate 1.
  • the bottom end of the supporting portion 2 is bonded to the substrate 1 to form an integrated chip as shown in FIG. 2.
  • the method for manufacturing the above-mentioned integrated chip provided by the present invention can be applied to the MEMS process with low manufacturing cost and high efficiency. For those skilled in the art, it can also be carried out by depositing a sacrificial layer, etching the sacrificial layer, etc., which will not be described in detail here.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Pressure Sensors (AREA)
  • Micromachines (AREA)

Abstract

一种加速度计、环境传感器的集成芯片，包括支撑部（2），以及通过悬臂梁（3）连接在支撑部（2）上的质量块（4）；在悬臂梁（3）上设置有第一压敏电阻（6）；第一压敏电阻（6）被配置为检测质量块（4）在受到加速度影响时悬臂梁（3）的形变程度；质量块（4）上具有凹槽（13）；还包括设置在质量块（4）上且覆盖凹槽（13）的敏感膜（5）；在敏感膜（5）上设置有第二压敏电阻（7）；第二压敏电阻（7）被配置为检测敏感膜（5）受到环境变化发生形变的程度。将加速度计和环境传感器集成在同一芯片内，可以大大降低了芯片占用的空间，利于电子器件的小型化发展。

Description

一种加速度计、环境传感器的集成芯片及其制造方法 技术领域
本发明涉及集成芯片领域，更具体地，涉及一种加速度计和环境传感器集成在一起的芯片；本发明还涉及该集成芯片的制造方法。
背景技术
近年来，随着科学技术的发展，电子产品的体积在不断减小，而且人们对这些便携电子产品的性能要求也越来越高，这就要求与之配套的电子零部件的体积也必须随之减小。
随着工业数字化、智能化发展，传感器已经不再局限于手机的应用，而且在可穿戴设备、智能家居、智慧交通、工业制造等领域中得到了广泛的应用。
但是在现有的工艺结构中，惯性器件和环境传感器大多采用不同的工艺流程，所以只能通过两颗不同的芯片来分别实现惯性信号和环境信号的检测，这不但增加了制造的成本，同时也增大了芯片的使用面积。而且现在各传感器的制造工艺已经比较成熟，工艺能力已经接近极限，很难再根据系统厂商的要求进一步缩减芯片的尺寸。
发明内容
本发明的一个目的是提供一种加速度计、环境传感器的集成芯片的新技术方案。
根据本发明的第一方面，提供了一种加速度计、环境传感器的集成芯片，包括支撑部，以及通过悬臂梁连接在所述支撑部上的质量块；在所述悬臂梁上设置有第一压敏电阻；所述第一压敏电阻被配置为检测质量块在受到加速度影响时悬臂梁的形变程度；
所述质量块上具有凹槽；还包括设置在质量块上且覆盖所述凹槽的敏 感膜；所述敏感膜对环境敏感；在所述敏感膜上设置有第二压敏电阻；所述第二压敏电阻被配置为检测敏感膜受到环境变化发生形变的程度。
可选地，所述悬臂梁设置有多个，分布在质量块的周向上；每个悬臂梁上对应至少一个第一压敏电阻；多个第一压敏电阻构成惠斯通电桥。
可选地，所述第二压敏电阻设置有多个，均匀分布在敏感膜上，该多个第二压敏电阻构成惠斯通电桥。
可选地，所述第一压敏电阻设置在悬臂梁与支撑部连接的位置，所述第一压敏电阻的一部分位于悬臂梁位置，另一部分位于支撑部上。
可选地，所述第二压敏电阻的一部分设置在敏感膜上对应凹槽的位置，另一部分设置在敏感膜上对应质量块的位置。
可选地，所述悬臂梁与敏感膜采用相同的材质，且通过相同的工艺制造。
可选地，所述敏感膜对压力敏感，所述敏感膜与凹槽围成的腔体为真空腔。
可选地，还包括衬底，所述支撑部的底端连接在所述衬底上，并与衬底围成了用于容纳质量块的空间。
根据本发明的另一方面，还提供了一种上述集成芯片的制造方法，包括以下步骤：
在第一晶圆上通过刻蚀形成凹槽；
将第二晶圆键合在第一晶圆上且覆盖所述凹槽；
研磨第二晶圆至预定的厚度，形成薄膜；
在薄膜上相应的位置通过离子注入的方式形成第一压敏电阻、第二压敏电阻；
对薄膜相应的位置进行刻蚀，形成悬臂梁和敏感膜；
对第一晶圆的背面进行刻蚀，从而形成位于中部的质量块，位于质量块外侧的支撑部，并将质量块、悬臂梁释放。
可选地，在形成质量块、支撑部之后，还包括将支撑部键合在衬底上的步骤。
根据本公开的一个实施例，将加速度计和环境传感器集成在同一芯片 内，可以大大降低了芯片占用的空间，利于电子器件的小型化发展。
通过以下参照附图对本发明的示例性实施例的详细描述，本发明的其它特征及其优点将会变得清楚。
附图说明
被结合在说明书中并构成说明书的一部分的附图示出了本发明的实施例，并且连同其说明一起用于解释本发明的原理。
图1是本发明集成芯片的俯视图。
图2是本发明集成芯片的剖视图。
图3是图1中集成芯片在受到加速度时的示意图。
图4是图1中集成芯片在受到压力变化时的示意图。
图5a至图5e是本发明集成芯片的制造工艺流程图。
具体实施方式
现在将参照附图来详细描述本发明的各种示例性实施例。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不限制本发明的范围。
以下对至少一个示例性实施例的描述实际上仅仅是说明性的，决不作为对本发明及其应用或使用的任何限制。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为说明书的一部分。
在这里示出和讨论的所有例子中，任何具体值应被解释为仅仅是示例性的，而不是作为限制。因此，示例性实施例的其它例子可以具有不同的值。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步讨论。
参考图1、图2，本发明提供了一种加速度计、环境传感器的集成芯片，包括衬底1以及支撑在该衬底1上的支撑部2，以及通过悬臂梁3连 接在支撑部2上的质量块4。支撑部2的底端连接在衬底1上，并与衬底1围成了用于容纳质量块4的空间。
支撑部2起到支撑、承接的作用，质量块4通过悬臂梁3支撑在支撑部2上，使得质量块4在受到外界的加速度时，可以在垂直于质量块4的方向上发生位移。悬臂梁3可以设置有多个，例如可设置有四个，均匀分布在质量块的周向方向上。例如当质量块选择矩形结构时，四个悬臂梁3的一端分别连接质量块4的四个侧壁的中心位置，另一端连接在支撑部2上，使得可以将质量块4稳定地支撑起来。
在悬臂梁3上设置有第一压敏电阻6，可通过本领域技术人员所熟知的方式在悬臂梁3上设置第一压敏电阻6。当悬臂梁3发生形变后，第一压敏电阻6的阻值会随着该形变而发生变化，例如阻值增大或者减小，以此可以表征悬臂梁形变的程度。
第一压敏电阻6的数量可以设置多个，在图1、图2的实施例中，第一压敏电阻6设置有四个，每个悬臂梁3各设置有一个。四个第一压敏电阻6构成惠斯通电桥，以使得第一压敏电阻可以检测质量块4在受到加速度时悬臂梁3的形变信息。
当然对于本领域的技术人员而言，每个悬臂梁3也可以设置多个第一压敏电阻6，在此不再具体说明。
参考图3，当受到向下的加速度影响时，质量块4会带动四个悬臂梁3向下发生形变，由此可改变悬臂梁3上的第一压敏电阻6的阻值，从而通过第一压敏电阻6构成的惠斯通电桥检测出变化的电信号，以表征悬臂梁3的形变状态。
在惠斯通全桥电路中，其中一对第一压敏电阻的阻值变化与另一对第一压敏电阻的阻值变化相反。例如其中一对第一压敏电阻的阻值变大时，而另一对第一压敏电阻的阻值减小。这种不同变化的压敏电阻可以通过本领域技术人员所熟知的工艺制造，在此不再具体说明。
可选地，第一压敏电阻6设置在悬臂梁3与支撑部2连接的位置，参考图1,第一压敏电阻6的一部分位于悬臂梁3位置，另一部分位于支撑部2上。当悬臂梁3发生形变时，其与支撑部2连接位置的形变是最大的。 将第一压敏电阻6设置在该位置，可以提高第一压敏电阻6的灵敏度。
本发明的集成芯片，在质量块4上开设有凹槽；还包括设置在质量块4上且覆盖凹槽的敏感膜5。该敏感膜5可以贴附在质量块4的端面上，且将凹槽覆盖起来。
该敏感膜5可以根据其检测环境信息的不同而选用不同的材料。例如该环境传感器为温度传感器时，则敏感膜5选用对温度敏感的材料。当该环境传感器为湿度传感器或者气体传感器时，则敏感膜5选用对湿度或者气体敏感的材料。
在本发明一个具体的实施方式中，该环境传感器为气压传感器，则该敏感膜5选用对压力敏感的材质。为了形成气压传感器，敏感膜5与质量块4上的凹槽围成的腔体为真空腔8，参考图3。
在敏感膜5上设置有第二压敏电阻7，第二压敏电阻7的工作原理与第一压敏电阻6的工作原理相同，可通过该第二压敏电阻7来检测敏感膜5受到压力发生形变的程度，以表征外界压力的大小。
可通过本领域技术人员所熟知的离子注入等方式在敏感膜5上设置第二压敏电阻7。第二压敏电阻7的数量可以设置多个，在图1、图2的实施例中，第二压敏电阻7设置有四个，均匀分布在敏感膜5上。四个第二压敏电阻7构成惠斯通电桥，通过该惠斯通电桥来检测敏感膜5受压时的形变。
当没有气压作用在敏感膜5上时，电桥的差分输出为0；当外界气压作用在薄膜上时，由于腔内外存在气压差，会使薄膜变形，变形产生的应力作用在第二压敏电阻7上，使第二压敏电阻7的阻值发生改变(ΔR)，电桥的差分输出为非0值，参考图4。
在惠斯通全桥电路中，其中一对第二压敏电阻的阻值变化与另一对第二压敏电阻的阻值变化相反。例如其中一对第二压敏电阻的阻值变大，而另一对第二压敏电阻的阻值减小。这种不同变化的压敏电阻可以通过本领域技术人员所熟知的工艺制造，在此不再具体说明。
可选地，第二压敏电阻7的一部分设置在敏感膜5上对应凹槽的位置，另一部分设置在敏感膜5上对应质量块4的位置。当悬空位置的敏感膜5 发生形变时，其与质量块4交界位置的形变是最大的，将第二压敏电阻7设置在该位置，可以提高第二压敏电阻7的灵敏度。
可选地，本发明的悬臂梁3与敏感膜5位于同一层上，且采用相同的材质，二者可通过相同的工艺制造，提高了制造的效率。
本发明还提供了一种制造上述加速度计、环境传感器的集成芯片的方法，其包括以下步骤：
首先，在第一晶圆10上通过刻蚀形成凹槽13。
具体在制造的时候，首先可在第一晶圆10的两侧各生长一层二氧化硅层11，并在其中一侧的二氧化硅层11上进行开窗，形成蚀刻窗口12，参考图5a。
参考图5b，通过蚀刻窗口12对第一晶圆10进行刻蚀形成凹槽13，刻蚀的方式例如可以通过深反应离子刻蚀(DRIE)技术。当然，对于本领域的技术人员而言，还可以选择其它可在第一晶圆10上形成凹槽13的方法，在此不再具体说明。
将第二晶圆键合在第一晶圆上且覆盖所述凹槽，研磨第二晶圆至预定的厚度，形成薄膜。
将第二晶圆通过键合的方式与第一晶圆10设置凹槽13的一侧结合在一起，使得键合在第一晶圆10表面上的第二晶圆将凹槽13覆盖起来。在本发明一个具体的实施方式中，可在真空环境中完成上述的键合，以使得第二晶圆与凹槽13围成了真空腔8，参考图5c。
研磨第二晶圆，以形成键合在第一晶圆10上的薄膜14。具体研磨的方式属于本领域技术人员的公知常识，在此不再具体说明。
在薄膜上通过离子注入的方式形成第一压敏电阻、第二压敏电阻。
参考图5d，通过离子注入的方式在薄膜14的相应位置形成第一压敏电阻6、第二压敏电阻7。第一压敏电阻6、第二压敏电阻7的数量、类型及位置根据具体结构而定。同时通过离子注入的方式在薄膜14上形成连接的导线，通过这些导线将多个第一压敏电阻6构成惠斯通电桥，并将多个第二压敏电阻7构成惠斯通电桥。
对薄膜进行刻蚀，形成悬臂梁和敏感膜。
按照集成芯片的结构，在薄膜的相应位置对薄膜进行刻蚀，以形成位于第一晶圆10上方的悬臂梁3和敏感膜5。
对第一晶圆10的背面进行刻蚀，从而形成位于中部的质量块4，位于质量块4外侧的支撑部2，并将质量块4、悬臂梁3释放。
参考图5e，例如可通过深反应离子刻蚀(DRIE)技术刻蚀第一晶圆10的背面，以形成质量块4的结构，将与悬臂梁3下方对应的第一晶圆10部分刻蚀掉后，从而将悬臂梁3释放出来，并形成了支撑悬臂梁3的支撑部2。
最后，将第一晶圆10的底端键合到衬底1上。具体地，将支撑部2的底端键合到衬底1上，形成了如图2所示的集成芯片。
本发明提供的一种制造上述集成芯片的方法，可以应用于MEMS工艺，其制造成本低，而且效率高。对于本各领域的技术人员而言，还可以通过沉积牺牲层、腐蚀牺牲层等方法进行，在此不再具体说明。
虽然已经通过例子对本发明的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上例子仅是为了进行说明，而不是为了限制本发明的范围。本领域的技术人员应该理解，可在不脱离本发明的范围和精神的情况下，对以上实施例进行修改。本发明的范围由所附权利要求来限定。

Claims (10)

  1. 一种加速度计、环境传感器的集成芯片，其特征在于：包括支撑部，以及通过悬臂梁连接在所述支撑部上的质量块；在所述悬臂梁上设置有第一压敏电阻；所述第一压敏电阻被配置为检测质量块在受到加速度影响时悬臂梁的形变程度；
    所述质量块上具有凹槽；还包括设置在质量块上且覆盖所述凹槽的敏感膜；所述敏感膜对环境敏感；在所述敏感膜上设置有第二压敏电阻；所述第二压敏电阻被配置为检测敏感膜受到环境变化发生形变的程度。
  2. 根据权利要求1所述的集成芯片，其特征在于：所述悬臂梁设置有多个，分布在质量块的周向上；每个悬臂梁上对应至少一个第一压敏电阻；多个第一压敏电阻构成惠斯通电桥。
  3. 根据权利要求1所述的集成芯片，其特征在于：所述第二压敏电阻设置有多个，均匀分布在敏感膜上，该多个第二压敏电阻构成惠斯通电桥。
  4. 根据权利要求1所述的集成芯片，其特征在于：所述第一压敏电阻设置在悬臂梁与支撑部连接的位置，所述第一压敏电阻的一部分位于悬臂梁位置，另一部分位于支撑部上。
  5. 根据权利要求1所述的集成芯片，其特征在于：所述第二压敏电阻的一部分设置在敏感膜上对应凹槽的位置，另一部分设置在敏感膜上对应质量块的位置。
  6. 根据权利要求1所述的集成芯片，其特征在于：所述悬臂梁与敏感膜采用相同的材质，且通过相同的工艺制造。
  7. 根据权利要求1所述的集成芯片，其特征在于：所述敏感膜对压力敏感，所述敏感膜与凹槽围成的腔体为真空腔。
  8. 根据权利要求1所述的集成芯片，其特征在于：还包括衬底，所述支撑部的底端连接在所述衬底上，并与衬底围成了用于容纳质量块的空间。
  9. 一种根据权利要求1至8任一项所述集成芯片的制造方法，其特 征在于，包括以下步骤：
    在第一晶圆上通过刻蚀形成凹槽；
    将第二晶圆键合在第一晶圆上且覆盖所述凹槽；
    研磨第二晶圆至预定的厚度，形成薄膜；
    在薄膜上相应的位置通过离子注入的方式形成第一压敏电阻、第二压敏电阻；
    对薄膜相应的位置进行刻蚀，形成悬臂梁和敏感膜；
    对第一晶圆的背面进行刻蚀，从而形成位于中部的质量块，位于质量块外侧的支撑部，并将质量块、悬臂梁释放。
  10. 根据权利要求9所述的制造方法，其特征在于，在形成质量块、支撑部之后，还包括将支撑部键合在衬底上的步骤。
PCT/CN2019/130101 2019-06-26 2019-12-30 一种加速度计、环境传感器的集成芯片及其制造方法 WO2020258813A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910562061.X 2019-06-26
CN201910562061.XA CN110346602A (zh) 2019-06-26 2019-06-26 一种加速度计、环境传感器的集成芯片及其制造方法

Publications (1)

Publication Number Publication Date
WO2020258813A1 true WO2020258813A1 (zh) 2020-12-30

Family

ID=68183172

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/130101 WO2020258813A1 (zh) 2019-06-26 2019-12-30 一种加速度计、环境传感器的集成芯片及其制造方法

Country Status (2)

Country Link
CN (1) CN110346602A (zh)
WO (1) WO2020258813A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110346602A (zh) * 2019-06-26 2019-10-18 歌尔股份有限公司 一种加速度计、环境传感器的集成芯片及其制造方法
CN110988395B (zh) * 2019-12-02 2022-08-19 青岛歌尔智能传感器有限公司 加速度传感器及其制备方法
CN113567707A (zh) * 2021-08-26 2021-10-29 维沃移动通信有限公司 加速度检测装置、检测系统、电子设备和加速度检测方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004245760A (ja) * 2003-02-17 2004-09-02 Wacoh Corp 圧力と加速度との双方を検出するセンサおよびその製造方法
CN1715838A (zh) * 2005-06-30 2006-01-04 西安交通大学 一种多传感器集成芯片
CN1847857A (zh) * 2005-04-15 2006-10-18 威海双丰电子集团有限公司 一种电容式mems加速度传感器
CN103245377A (zh) * 2012-02-14 2013-08-14 亚太优势微系统股份有限公司 单体化复合传感器及其封装品
CN105043439A (zh) * 2015-05-29 2015-11-11 歌尔声学股份有限公司 传感器集成装置及其生产方法
CN108507709A (zh) * 2018-03-14 2018-09-07 合肥工业大学 一种谐振式压力传感器的制备方法
CN110346602A (zh) * 2019-06-26 2019-10-18 歌尔股份有限公司 一种加速度计、环境传感器的集成芯片及其制造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102298074B (zh) * 2011-05-23 2012-08-15 西安交通大学 一种孔缝双桥式加速度传感器芯片及其制备方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004245760A (ja) * 2003-02-17 2004-09-02 Wacoh Corp 圧力と加速度との双方を検出するセンサおよびその製造方法
CN1847857A (zh) * 2005-04-15 2006-10-18 威海双丰电子集团有限公司 一种电容式mems加速度传感器
CN1715838A (zh) * 2005-06-30 2006-01-04 西安交通大学 一种多传感器集成芯片
CN103245377A (zh) * 2012-02-14 2013-08-14 亚太优势微系统股份有限公司 单体化复合传感器及其封装品
CN105043439A (zh) * 2015-05-29 2015-11-11 歌尔声学股份有限公司 传感器集成装置及其生产方法
CN108507709A (zh) * 2018-03-14 2018-09-07 合肥工业大学 一种谐振式压力传感器的制备方法
CN110346602A (zh) * 2019-06-26 2019-10-18 歌尔股份有限公司 一种加速度计、环境传感器的集成芯片及其制造方法

Also Published As

Publication number Publication date
CN110346602A (zh) 2019-10-18

Similar Documents

Publication Publication Date Title
US7305890B2 (en) Micro-electromechanical sensor
WO2020258813A1 (zh) 一种加速度计、环境传感器的集成芯片及其制造方法
Eaton et al. Micromachined pressure sensors: review and recent developments
Esashi et al. Vacuum-sealed silicon micromachined pressure sensors
CN105842476B (zh) 用于风速计的系统和方法
US6272928B1 (en) Hermetically sealed absolute and differential pressure transducer
US7998777B1 (en) Method for fabricating a sensor
US7487681B1 (en) Pressure sensor adjustment using backside mask
US7597005B2 (en) Pressure sensor housing and configuration
US20050241400A1 (en) Combined absolute-pressure and relative-pressure sensor
US9686864B2 (en) Device including interposer between semiconductor and substrate
US20020011114A1 (en) Capacitive vacuum sensor
CN109489843B (zh) 高灵敏度传感器及其制备方法
CN107209077B (zh) 具有改进的凹部或者空腔结构的微型机械装置
US9395259B2 (en) Piezoresistive transducer with low thermal noise
TW201302598A (zh) 量測環境力的裝置與製造該裝置的方法
JP2008517254A (ja) 微小電気機械圧力センサ
WO2012121030A1 (ja) 絶対圧力センサ
KR100552480B1 (ko) 마이크로 가속도계
Duqi et al. A piezoresistive MEMS barometer with thermomecanical stress rejection
Wang et al. Contamination-insensitive differential capacitive pressure sensors
US6308575B1 (en) Manufacturing method for the miniaturization of silicon bulk-machined pressure sensors
WO2007083546A1 (ja) 触覚センサ装置
EP4266020A1 (en) Three-dimensional stress-sensitive device
US20150191349A1 (en) Semiconductor secured to substrate via hole in substrate

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19935160

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19935160

Country of ref document: EP

Kind code of ref document: A1