WO2020253482A1 - 驱动电路、电子设备以及控制充电方法 - Google Patents

驱动电路、电子设备以及控制充电方法 Download PDF

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Publication number
WO2020253482A1
WO2020253482A1 PCT/CN2020/092596 CN2020092596W WO2020253482A1 WO 2020253482 A1 WO2020253482 A1 WO 2020253482A1 CN 2020092596 W CN2020092596 W CN 2020092596W WO 2020253482 A1 WO2020253482 A1 WO 2020253482A1
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WIPO (PCT)
Prior art keywords
direct current
current signal
capacitor
diode
signal
Prior art date
Application number
PCT/CN2020/092596
Other languages
English (en)
French (fr)
Inventor
刘绍斌
田晨
卜昌军
张俊
Original Assignee
Oppo广东移动通信有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oppo广东移动通信有限公司 filed Critical Oppo广东移动通信有限公司
Priority to EP20827510.7A priority Critical patent/EP3972079A4/en
Publication of WO2020253482A1 publication Critical patent/WO2020253482A1/zh
Priority to US17/540,161 priority patent/US20220094293A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P27/00—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
    • H02P27/04—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage
    • H02P27/06—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters
    • H02P27/08—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters with pulse width modulation
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/007—Regulation of charging or discharging current or voltage
    • H02J7/00711—Regulation of charging or discharging current or voltage with introduction of pulses during the charging process
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H03F3/2171—Class D power amplifiers; Switching amplifiers with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/08—Duration or width modulation ; Duty cycle modulation
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators

Definitions

  • the embodiments of the present application relate to the field of charging technology, in particular to a driving circuit, an electronic device, and a method for controlling charging.
  • the embodiments of the present application provide a driving circuit, an electronic device, and a charging control method to solve the charging problem in the related art.
  • the present application provides a drive circuit, the drive circuit is located on the main board of an electronic device, the electronic device further includes a MOS tube and a microcontroller unit MCU, the drive circuit includes: a first interface, and an external power supply Device connection, used to receive the direct current signal input by the external power supply device; the second interface, connected to the MCU, used to receive at least two pulse width modulation PWM signals input by the MCU; The first interface and the second interface are connected, and are used to superimpose and rectify the direct current signal and the at least two PWM signals to obtain a first direct current signal, and output the first direct current signal to the The gate of the MOS tube, so that the voltage of the gate of the MOS tube is greater than the first threshold.
  • the present application provides an electronic device, including a first interface connected to an external power supply device, and used to receive a direct current signal input by the external power supply device; a micro-control unit MCU; and a second interface connected to the MCU connection, used to receive at least two pulse width modulation PWM signals input by the MCU; a field effect tube MOS tube; a processing circuit, respectively connected to the first interface and the second interface, for connecting the direct current
  • the signal and the at least two PWM signals are superimposed and rectified to obtain a first direct current signal, and output the first direct current signal to the gate of the MOS tube, so that the voltage of the gate of the MOS tube is greater than The first threshold.
  • the present application provides a method for controlling charging.
  • the method includes: superimposing and rectifying a direct current signal input from an external power supply device through a first interface and at least two PWM signals input from an MCU through a second interface. To obtain the first direct current signal; and output the first direct current signal to the gate of the MOS tube, so that the voltage of the gate of the MOS tube is greater than the first threshold.
  • this application provides a computer-readable storage medium for storing a computer program that enables a computer to execute the method described in the third aspect or any one of its implementation manners.
  • the method of the third aspect includes superimposing and rectifying the direct current signal input by the external power supply device through the first interface and at least two PWM signals input through the second interface based on the MCU to obtain the first direct current signal; A direct current signal is output to the gate of the MOS tube, so that the voltage of the gate of the MOS tube is greater than the first threshold.
  • the present application provides a computer program product characterized by including computer program instructions that cause a computer to execute the method described in the third aspect or any one of its implementation manners.
  • the method of the third aspect includes superimposing and rectifying the direct current signal input by the external power supply device through the first interface and at least two PWM signals input through the second interface based on the MCU to obtain the first direct current signal; A direct current signal is output to the gate of the MOS tube, so that the voltage of the gate of the MOS tube is greater than the first threshold.
  • the driving circuit provided by the embodiment of the present application superimposes the direct current signal input from the external power supply device through the first interface with at least two PWM signals input from the MCU through the second interface, and then undergoes rectification processing and outputs to the charging inside the electronic device
  • the gate of the MOS tube in the path because at least two PWM signals are input to the driving circuit through the second interface based on the MCU, the driving voltage generated by the driving circuit can be increased, thereby increasing the gate between the MOS tubes
  • the voltage between the VGS and the source can therefore avoid the decrease in charging efficiency caused by the excessively low voltage of VGS and the reduction of the fast charging current or exiting the fast charging mode.
  • Fig. 1 is a schematic diagram of a diode provided by an embodiment of the present application.
  • FIGS 2a and 2b are schematic diagrams of MOS transistors provided by embodiments of the present application.
  • Figure 3 is a schematic diagram of a fast path provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a fast path provided by an embodiment of the present application.
  • FIG. 5 is a diagram of the relationship between the drain current and the drain-source voltage of the same MOS transistor under different gate-source voltages according to an embodiment of the present application;
  • FIG. 6 is a schematic diagram of a driving circuit provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a fast charging path provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a fast charging path provided by another embodiment of the present application.
  • FIG. 9 is a schematic diagram of a driving path provided by another embodiment of the present application.
  • FIG. 10 is a schematic diagram of a driving circuit provided by another embodiment of the present application.
  • FIG. 11 is a schematic diagram of a driving circuit provided by still another embodiment of the present application.
  • FIG. 12 is a schematic diagram of a driving circuit provided by still another embodiment of the present application.
  • FIG. 13 is a schematic diagram of a driving circuit provided by still another embodiment of the present application.
  • FIG. 14 is a schematic diagram of a driving circuit provided by still another embodiment of the present application.
  • FIG. 15 is a schematic diagram of a fast charging path provided by another embodiment of the present application.
  • FIG. 16 is a schematic diagram of a fast charging path provided by still another embodiment of the present application.
  • FIG. 17 is a schematic diagram of a PWM signal provided by an embodiment of the present application.
  • FIG. 18 is a schematic diagram of an electronic device provided by an embodiment of the present application.
  • FIG. 19 is a schematic flowchart of a method for controlling charging according to an embodiment of the present application.
  • FIG. 20 is a schematic flowchart of a method for controlling charging according to another embodiment of the present application.
  • FIG. 21 is a schematic flowchart of a method for controlling charging according to another embodiment of the present application.
  • FIG. 22 is a schematic structural diagram of a wired charging system provided by an embodiment of the present application.
  • FIG. 23 is a schematic structural diagram of a wired charging system provided by another embodiment of the present application.
  • the driving circuit 610 is applied to electronic equipment.
  • the electronic equipment also includes a field effect tube MOS tube and a microcontroller unit MCU.
  • the driving circuit 610 includes a first interface 610 connected to an external power supply device for receiving external power.
  • a direct current signal input by the device a second interface 620, connected to the MCU, for receiving at least two pulse width modulation PWM signals input by the MCU; a processing circuit 630, connected to the first interface 610 and the second interface 620, respectively, for The direct current signal and the at least two PWM signals are superimposed and rectified to obtain the first direct current signal, and the first direct current signal is output to the gate of the MOS transistor, so that the voltage of the gate of the MOS transistor is greater than the first threshold.
  • the processing circuit 630 is further configured to: superimpose the direct current signal and one of the at least two PWM signals to obtain the first PWM signal, and compare the first PWM signal Rectification is performed to obtain the second direct current signal; the second direct current signal is superimposed and rectified with the remaining PWM signals in the at least two PWM signals to obtain the first direct current signal.
  • the processing circuit 630 is further configured to: filter the second direct current signal to obtain a filtered second direct current signal; and combine the filtered second direct current signal with at least two PWM channels. The remaining PWM signal in the signal is superimposed and rectified to obtain the first direct current signal.
  • the processing circuit 630 is further configured to: superimpose the DC signal and one of the at least two PWM signals to obtain the first PWM signal; The remaining PWM signal in the rectifier is rectified to obtain the third direct current signal, and the third direct current signal and the first PWM signal are superimposed and rectified to obtain the first direct current signal.
  • the processing circuit 630 is further configured to: filter the third direct current signal to obtain a filtered third direct current signal; combine the filtered third direct current signal with the first PWM signal Perform superposition and rectification to obtain the first direct current signal.
  • the processing circuit 630 is further used to filter the direct current signal input by the external power supply device through the first interface 610.
  • the processing circuit 630 includes a capacitor C5, a capacitor C1, a diode D4, and a diode D2.
  • One end of the capacitor C5 is connected to the second port 620; one end of the capacitor C1 is connected to the second port 620; the anode of the diode D4 is connected to the first port 610 and the other end of the capacitor C5, and the cathode of the diode D4 is connected to the other end of the capacitor C1 Connected to rectify the first PWM signal to obtain the second direct current signal; the anode of diode D2 is connected to the cathode of diode D4 and the other end of capacitor C1, and the cathode of diode D2 is connected to the MOS tube V1 and MOS tube V2.
  • the gate connection is used to rectify the signal after the superimposition of the second direct current signal and the remaining PWM signal output by the MCU to obtain the first direct current signal; wherein the capacitor C5 is used to correct one of the at least two PWM signals in Before being superimposed, the DC signal is removed, and the capacitor C1 is used to remove the DC signal from the remaining PWM signals in the at least two PWM signals before being superimposed.
  • the processing circuit 630 further includes a diode D1 and a diode D5.
  • the anode and cathode of the diode D1 are respectively connected to the first interface 610 and the other end of the capacitor C5; the anode of the diode D5 is connected to the cathode of the diode D4, and the cathode of the diode D5 is connected to the other end of the capacitor C1.
  • the processing circuit 630 further includes a capacitor C3 and a capacitor C6.
  • One end of the capacitor C3 is connected to the first interface 610, and the other end of the capacitor C3 is grounded for filtering the DC signal output from the first interface 610;
  • one end of the capacitor C6 is connected to the cathode of the diode D4, and the other end of the capacitor C6 is grounded , Used to filter the second direct current signal output from the diode D4.
  • the processing circuit 630 includes a capacitor C5, a capacitor C1, a diode D4, and a diode D2.
  • One end of the capacitor C5 is connected to the second port 620; one end of the capacitor C1 is connected to the second port 620; the anode of the diode D4 is connected to the other end of the capacitor C1, and the cathode of the diode D4 is connected to the first port 610 and the other end of the capacitor C5 , Used to rectify the remaining PWM signals in the at least two PWM signals to obtain the third direct current signal;
  • the anode of the diode D2 is connected to the cathode of the diode D4, the first interface 610 and the other end of the capacitor C5, and the cathode of the diode D2 Connected to the gates of the MOS tube V1 and the MOS tube V2, and used to rectify the superimposed signal of the third direct current signal and the first PWM signal to obtain the first direct current signal;
  • the processing circuit 630 further includes a diode D1 and a diode D5.
  • the anode and cathode of the diode D1 are respectively connected to the first interface 610 and the other end of the capacitor C5; the anode of the diode D5 is connected to the other end of the capacitor C5 and the cathode of the diode D1, and the cathode of the diode D5 is connected to the cathode of the diode D4.
  • the processing circuit 630 further includes a capacitor C3 and a capacitor C6.
  • One end of the capacitor C3 is connected to the first interface 610, and the other end of the capacitor C3 is grounded for filtering the DC signal output from the first interface 610;
  • one end of the capacitor C6 is connected to the cathode of the diode D4, and the other end of the capacitor C6 is grounded , Used to filter the third direct current signal output from the diode D4.
  • the electronic device 1800 of the embodiment of the present application includes a first interface 1810, a micro-control unit MCU 1820, a second interface 1830, a processing circuit 1840, and a field effect transistor MOS tube 1850.
  • the first interface 1810 is connected to an external power supply device and is used to receive the DC signal input by the external power supply device;
  • the second interface 1830 is connected to the MCU1820 and is used to receive at least two pulse width modulation PWM signals input by the MCU1820;
  • processing circuit 1840 respectively connected to the first interface 610 and the second interface 620, used to superimpose and rectify the direct current signal and at least two PWM signals to obtain the first direct current signal, and output the first direct current signal to the gate of the MOS tube So that the voltage of the gate of the MOS tube is greater than the first threshold.
  • the processing circuit 630 is further configured to: superimpose the direct current signal and one of the at least two PWM signals to obtain the first PWM signal, and compare the first PWM signal Rectification is performed to obtain the second direct current signal; the second direct current signal is superimposed and rectified with the remaining PWM signals in the at least two PWM signals to obtain the first direct current signal.
  • the processing circuit 630 is further configured to: filter the second direct current signal to obtain a filtered second direct current signal; and combine the filtered second direct current signal with at least two PWM channels. The remaining PWM signal in the signal is superimposed and rectified to obtain the first direct current signal.
  • the processing circuit 630 is further configured to: superimpose the DC signal and one of the at least two PWM signals to obtain the first PWM signal; The remaining PWM signal in the rectifier is rectified to obtain the third direct current signal, and the third direct current signal and the first PWM signal are superimposed and rectified to obtain the first direct current signal.
  • the processing circuit 630 is further configured to: filter the third direct current signal to obtain a filtered third direct current signal; combine the filtered third direct current signal with the first PWM signal Perform superposition and rectification to obtain the first direct current signal.
  • the processing circuit 630 is further used to filter the direct current signal input by the external power supply device through the first interface 610.
  • the processing circuit 630 includes a capacitor C5, a capacitor C1, a diode D4, and a diode D2.
  • One end of the capacitor C5 is connected to the second port 620; one end of the capacitor C1 is connected to the second port 620; the anode of the diode D4 is connected to the first port 610 and the other end of the capacitor C5, and the cathode of the diode D4 is connected to the other end of the capacitor C1 Connected to rectify the first PWM signal to obtain the second direct current signal; the anode of diode D2 is connected to the cathode of diode D4 and the other end of capacitor C1, and the cathode of diode D2 is connected to the MOS tube V1 and MOS tube V2.
  • the gate connection is used to rectify the signal after the superimposition of the second direct current signal and the remaining PWM signal output by the MCU to obtain the first direct current signal; wherein the capacitor C5 is used to correct one of the at least two PWM signals in Before being superimposed, the DC signal is removed, and the capacitor C1 is used to remove the DC signal from the remaining PWM signals in the at least two PWM signals before being superimposed.
  • the processing circuit 630 further includes a diode D1 and a diode D5.
  • the anode and cathode of the diode D1 are respectively connected to the first interface 610 and the other end of the capacitor C5; the anode of the diode D5 is connected to the cathode of the diode D4, and the cathode of the diode D5 is connected to the other end of the capacitor C1.
  • the processing circuit 630 further includes a capacitor C3 and a capacitor C6.
  • One end of the capacitor C3 is connected to the first interface 610, and the other end of the capacitor C3 is grounded for filtering the DC signal output from the first interface 610;
  • one end of the capacitor C6 is connected to the cathode of the diode D4, and the other end of the capacitor C6 is grounded , Used to filter the second direct current signal output from the diode D4.
  • the processing circuit 630 includes a capacitor C5, a capacitor C1, a diode D4, and a diode D2.
  • One end of the capacitor C5 is connected to the second port 620; one end of the capacitor C1 is connected to the second port 620; the anode of the diode D4 is connected to the other end of the capacitor C1, and the cathode of the diode D4 is connected to the first port 610 and the other end of the capacitor C5 , Used to rectify the remaining PWM signals in the at least two PWM signals to obtain the third direct current signal;
  • the anode of the diode D2 is connected to the cathode of the diode D4, the first interface 610 and the other end of the capacitor C5, and the cathode of the diode D2 Connected to the gates of the MOS tube V1 and the MOS tube V2, and used to rectify the superimposed signal of the third direct current signal and the first PWM signal to obtain the first direct current signal;
  • the processing circuit 630 further includes a diode D1 and a diode D5.
  • the anode and cathode of the diode D1 are respectively connected to the first interface 610 and the other end of the capacitor C5; the anode of the diode D5 is connected to the other end of the capacitor C5 and the cathode of the diode D1, and the cathode of the diode D5 is connected to the cathode of the diode D4.
  • the processing circuit 630 further includes a capacitor C3 and a capacitor C6.
  • One end of the capacitor C3 is connected to the first interface 610, and the other end of the capacitor C3 is grounded for filtering the DC signal output from the first interface 610;
  • one end of the capacitor C6 is connected to the cathode of the diode D4, and the other end of the capacitor C6 is grounded , Used to filter the third direct current signal output from the diode D4.
  • the method 1900 for controlling charging in the embodiment of the present application includes step 1910: superimposing and rectifying the direct current signal input from the external power supply device through the first interface and the at least two PWM signals input from the MCU through the second interface. , To obtain the first direct current signal; Step 1920: output the first direct current signal to the gate of the MOS tube, so that the voltage of the gate of the MOS tube is greater than the first threshold.
  • step 1910 includes: superimposing the direct current signal input from the external power supply device through the first interface with one of the at least two PWM signals to obtain the first PWM signal and The PWM signal is rectified to obtain a second direct current signal; the second direct current signal is superimposed and rectified with the remaining PWM signals in the at least two PWM signals to obtain the first direct current signal.
  • the method 1900 further includes: filtering the second direct current signal to obtain a filtered second direct current signal; and combining the second direct current signal with the remaining PWM signals in the at least two PWM signals.
  • the signal is superimposed and rectified to obtain the first direct current signal, including: superimposing and rectifying the filtered second direct current signal and the remaining PWM signals in the at least two PWM signals to obtain the first direct current signal.
  • step 1910 includes: superimposing the DC signal input from the external power supply device through the first interface and one of the at least two PWM signals to obtain the first PWM signal Rectify the remaining PWM signals in the at least two PWM signals to obtain a third direct current signal, and superimpose and rectify the third direct current signal with the first PWM signal to obtain the first direct current signal.
  • the method 1900 further includes: filtering the third direct current signal to obtain a filtered third direct current signal; superimposing and rectifying the third direct current signal and the first PWM signal, Obtaining the first direct current signal includes: superimposing and rectifying the filtered third direct current signal and the first PWM signal to obtain the first direct current signal.
  • the method 1900 may further include step 1930: filtering the direct current signal input by the power supply device through the first interface.
  • the method 1900 may further include step 1940: separately performing processing to remove the direct current signal before the at least two PWM signals are superimposed.
  • the computer-readable storage medium of the present application stores computer-executable instructions, and the computer-executable instructions are configured to execute any one of the methods 1900 described above.
  • the computer-executable instructions are configured to perform the following steps: superimpose and rectify the direct current signal input from the external power supply device through the first interface and at least two PWM signals input from the MCU through the second interface to obtain the first direct current signal;
  • the first direct current signal is output to the gate of the MOS tube, so that the voltage of the gate of the MOS tube is greater than the first threshold.
  • the computer executable instructions are configured to perform the following steps: superimpose the direct current signal input by the external power supply device through the first interface with one of the at least two PWM signals to obtain the first PWM Signal and rectify the first PWM signal to obtain a second direct current signal; superimpose and rectify the second direct current signal with the remaining PWM signals in the at least two PWM signals to obtain the first direct current signal.
  • the computer-executable instructions are configured to perform the following steps: filter the second direct current signal to obtain a filtered second direct current signal; combine the filtered second direct current signal with at least two PWM signals The remaining PWM signal is superimposed and rectified to obtain the first direct current signal.
  • the computer-executable instructions are configured to perform the following steps: superimpose the DC signal input by the external power supply device through the first interface and one of the at least two PWM signals to obtain the first PWM Signal; rectify the remaining PWM signals in the at least two PWM signals to obtain a third direct current signal, and superimpose and rectify the third direct current signal with the first PWM signal to obtain the first direct current signal.
  • the computer-executable instructions are configured to perform the following steps: filter the third direct current signal to obtain a filtered third direct current signal; superimpose the filtered third direct current signal with the first PWM signal And rectification to obtain the first direct current signal.
  • the computer-executable instructions are configured to perform the following steps: filtering the direct current signal input by the power supply device through the first interface.
  • the computer-executable instructions are configured to perform the following steps: before at least two PWM signals are superimposed, the processing of removing the direct current signal is performed respectively.
  • the computer program product of the present application includes computer program instructions that cause the computer to execute any one of the foregoing methods 1900.
  • the computer program instructions cause the computer to perform the following steps: superimpose and rectify the direct current signal input from the external power supply device through the first interface and at least two PWM signals input from the MCU through the second interface to obtain the first direct current signal;
  • the first direct current signal is output to the gate of the MOS tube, so that the voltage of the gate of the MOS tube is greater than the first threshold.
  • the computer program instructions cause the computer to perform the following steps: superimpose the direct current signal input from the external power supply device through the first interface with one of the at least two PWM signals to obtain the first PWM Signal and rectify the first PWM signal to obtain a second direct current signal; superimpose and rectify the second direct current signal with the remaining PWM signals in the at least two PWM signals to obtain the first direct current signal.
  • the computer program instructions cause the computer to perform the following steps: filter the second direct current signal to obtain a filtered second direct current signal; combine the filtered second direct current signal with at least two PWM signals The remaining PWM signal is superimposed and rectified to obtain the first direct current signal.
  • the computer program instructions cause the computer to perform the following steps: superimpose the DC signal input by the external power supply device through the first interface and one of the at least two PWM signals to obtain the first PWM Signal; rectify the remaining PWM signals in the at least two PWM signals to obtain a third direct current signal, and superimpose and rectify the third direct current signal with the first PWM signal to obtain the first direct current signal.
  • the computer program instructions cause the computer to perform the following steps: filter the third direct current signal to obtain the filtered third direct current signal; superimpose the filtered third direct current signal with the first PWM signal And rectification to obtain the first direct current signal.
  • the computer program instructions cause the computer to perform the following steps: filtering the direct current signal input by the power supply device through the first interface.
  • the computer program instructions cause the computer to perform the following steps: before at least two PWM signals are superimposed, the DC signal is removed.
  • FIG. 1 shows a schematic diagram of a Schottky diode.
  • the Schottky diode is not made using the principle of forming a PN junction between a P-type semiconductor and an N-type semiconductor, but is made using the principle of a metal-semiconductor junction formed by contact between a metal and a semiconductor , Has the advantages of high switching frequency and reduced forward voltage.
  • MOS transistors are metal, oxide, semiconductor field effect transistors, or metal-insulators, semiconductors.
  • the MOS tube includes an N-channel MOS tube and a P-channel MOS tube.
  • Figs. 2a and 2b are schematic diagrams of an N-channel MOS tube and a P-channel MOS tube, respectively. In the figure, D is the drain, S is the source, G is the gate, and the arrow in the middle indicates the substrate.
  • the MOS tube may include an N-channel MOS tube and a P-channel MOS tube.
  • the drain and source will be turned on. Due to a small resistance, current flows from the drain to the source; if the voltage between the gate and the source is low, that is, VGS ⁇ 0, the drain and the source will be cut off. There is a large resistance between the electrode and the source, and the current cannot flow between the drain and the source.
  • Fig. 3 is a schematic diagram of the fast path applying the embodiment of the present application.
  • the fast path schematic diagram may include: a battery 310, a MOS tube 320, a universal serial bus interface (USB interface) 330, a data line 340, and a power supply device 350, an application processor 360 (Application Processor, AP), a micro-controller unit 370 (Micro-controller Unit, MCU), and a driving circuit 380.
  • the power supply device 350 in the embodiment of the present application may be an adapter, a mobile power supply, or the like.
  • the MCU370 in the embodiment of this application can control the closing or opening of the fast charging channel, and can also output multiple pulse width modulation (PWM) signals.
  • PWM pulse width modulation
  • the AP360 in the embodiment of this application can control the closing or opening of the fast charging channel. Disconnected, in some embodiments, MCU370 and AP360 may be the same.
  • a battery 310 and a MOS tube 320 are provided in the mobile phone, and the power supply device 350 is connected to the mobile phone through a USB interface 330.
  • the USB interface 330 may be a Micro USB interface or a Type-c USB interface.
  • the data line in the USB interface is used for two-way communication between the power supply device and the mobile phone.
  • the data line can be the D+ line and/or D- line in the USB interface.
  • the so-called two-way communication can refer to the information between the power supply device and the mobile phone.
  • the MOS tube, drive circuit, MCU, and AP can be located on the motherboard inside the mobile phone.
  • the power supply device 350 in the embodiment of the present application supports a normal charging mode and a fast charging mode, and the charging speed of the fast charging mode is greater than that of the normal charging mode.
  • the charging current in the fast charging mode is greater than the charging current in the normal charging mode and/or the charging voltage in the fast charging mode is higher than the charging voltage in the normal charging mode.
  • the normal charging mode means that the power supply device outputs a relatively small current value (usually less than 2.5A) or uses a relatively small power (usually less than 15W) to charge the battery in an electronic device. It usually takes several hours to fully charge a larger capacity battery (such as a 3000 mAh battery) in the mode; while in the fast charging mode, the power supply device can output a relatively large current, ( Usually greater than 2.5A, such as 4.5A, 5A or even higher) or relatively large power (usually greater than or equal to 15W) to charge the battery in electronic equipment, compared to the normal charging mode, the power supply device In the fast charging mode, the charging time required to fully charge the battery of the same capacity can be significantly shortened and the charging speed is faster.
  • the fast charging mode can also be divided into multiple fast charging stages according to the impedance of the charging circuit, wherein as the impedance increases, the current in the fast charging stage shows a decreasing trend.
  • the current driving voltage output by the driving circuit is used to control the gate voltage of the field effect (Metal Oxide Semiconductor, MOS) tube on the fast charging loop.
  • MOS Metal Oxide Semiconductor
  • the driving voltage output by the current driving circuit is relatively low. It is small, which makes the impedance between the drain and source of the MOS tube larger when it is turned on. On the one hand, it causes serious heating of the MOS tube and reduces the charging efficiency; The impedance of the charging circuit is too large, which reduces the fast charging current or exits the fast charging mode.
  • the mobile phone terminal sends the battery voltage V1 near the power terminal to the power supply device through the D+ and D- signals on the data line on the data line in real time.
  • the specific impedance control method can be as shown in Table 1:
  • the current I1 is used for fast charging; when the impedance increases to satisfy R1 ⁇ R ⁇ R2, the current of the charging circuit is controlled to decrease to I2 for fast charging (I2 ⁇ I1); if the impedance continues Increase to meet R2 ⁇ R ⁇ R3, control the current of the charging loop to decrease to I3 for fast charging (I3 ⁇ I2); if the impedance continues to increase to meet R>R3, exit the fast charging mode, and use the normal charging mode to charge the phone Recharge.
  • the MCU in the embodiment of the present application can control the turn-on and turn-off of the MOS transistor, thereby realizing the entry and exit of the fast charging mode.
  • the power supply device of the present application will be described with an adapter as an example.
  • Fig. 4 is a schematic structural diagram of a fast path, where the MCU in the embodiment of the present application can realize the entry and exit of fast charging by controlling the level of the output.
  • the embodiment of this application takes an N-channel MOS transistor as an example.
  • the MCU When the MCU outputs a high level, since the gate voltage of the N-channel MOS transistor V3 is lower than the source voltage, the MOS transistor V3 is in the on state, and the adapter output The voltage Vbus and the PWM signal voltage output by the MCU are grounded through the MOS tube V3; if the MCU outputs a low level, since the gate voltage of the N-channel MOS tube V3 is higher than the source voltage, the MOS tube V3 is in an off state, and the adapter outputs The voltage Vbus charges the battery.
  • the MOS tube V3 When the MCU outputs a low level, the MOS tube V3 is in an off state, and the voltage Vbus on the adapter reaches between the diode D1 and the diode D2 through the resistor R1 and the diode D1.
  • the MCU controls the output signal voltage Vclk through the charge and discharge on the capacitor C1. Between diode D1 and diode D2. Because the resistance of resistor R3 is relatively large, the current flowing through resistors R1, R2, and R3 is very small, and the voltage drop across resistors R1, R2, and R3 is also very small.
  • the diode D1 can avoid the reverse voltage flow in the above circuit, so as to avoid the leakage phenomenon caused by the increase of the voltage Vm at the m point between the diode D1 and the diode D2, that is, due to the diode D1 and the diode
  • the voltage Vm at the m point between D2 is greater than the output voltage of the adapter, which may cause the current to be transmitted to the adapter through the resistor R1 in the reverse direction. Therefore, the diode D1 can prevent the reverse charging of the current; the diode D2 can rectify the AC to DC, because the adapter output
  • the voltage Vbus is a DC voltage
  • the signal voltage Vclk output by the MCU is an AC PWM signal voltage.
  • the displayed voltage is also an AC voltage. Therefore, after rectification by the diode D2, the alternating current is rectified into direct current.
  • the impedance RDS between the drain and the source of the MOS tube in the charging circuit is relatively large.
  • the relationship between the drain current ID and the voltage VDS between the drain and the source can be shown in FIG. 5.
  • the embodiments of the present application provide the following solutions, which can avoid the decrease in charging efficiency caused by the excessively low voltage of VGS, and can also avoid the rapid decrease of the fast charging current or the fast charging current caused by the excessively large impedance when the MOS tube is turned on. The problem of exiting the fast charging mode.
  • the driving circuit 600 provided in the embodiment of the present application may include a first interface 610, a second interface 620, and a processing circuit 630.
  • the first interface 610 is connected to the adapter, and is used to receive the direct current signal input by the adapter.
  • the second interface 620 is connected to the MCU and is used to receive at least two pulse width modulation PWM signals input by the MCU.
  • the MCU is a micro-control unit, and the MCU can control the turning on or off of other devices inside the electronic device.
  • the MOS tube can be controlled to turn on or off by the level signal output by the MCU pin. .
  • the PWM signal in the embodiment of the present application is a signal output by the MCU, and may be a square wave signal or other signals.
  • the duty cycle of the PWM signal in the embodiment of the present application may be 50%, 20%, or others, which is not specifically limited in the present application.
  • the processing circuit 630 is respectively connected to the first interface 610 and the second interface 620, and is used to superimpose and rectify the direct current signal and the at least two PWM signals to obtain the first direct current signal, and The first direct current signal is output to the gate of the MOS transistor, so that the voltage of the gate of the MOS transistor is greater than a first threshold.
  • the at least two PWM signals received through the second interface 620 are AC signals. After being superimposed with the DC signal input by the adapter through the first interface 610, the superimposed PWM signals are also AC signals, which are different from the second Compared with at least two PWM signals input by the interface, the frequency of the superimposed PWM signal does not change, but the amplitude increases.
  • the at least two PWM signals received by the MCU through the second interface 620 may be two PWM signals input from the same pin in the MCU through changes in the drive circuit, or directly from different pins in the MCU. At least two PWM signals input through the second interface 620. It can be understood that if the at least two PWM signals are at least two PWM signals directly input by different pins in the MCU through the second interface 620, the PWM signals output by the two pins have the same frequency.
  • the embodiment of the application does not specifically limit the form of the processing circuit 630, as long as the circuit that can superimpose and rectify the direct current signal and at least two PWM signals and output the first direct current signal can be applied to the embodiment of the present application.
  • the processing circuit 630 superimposes and rectifies the DC signal input from the adapter and at least two PWM signals to obtain the first DC signal, and outputs the obtained first DC signal to the gate of the MOS tube inside the electronic device. So that the voltage of the gate of the MOS tube is greater than the first threshold.
  • the first threshold may be 8.6V, so the gate voltage of the MOS transistor is greater than 8.6, and the embodiments of this application can be applied.
  • the processing circuit 630 in the embodiment of the present application can be a Schottky diode or a circuit with a rectification function.
  • This application is not specifically limited, as long as the PWM signal can be rectified into a direct current signal can be applied In the examples of this application.
  • the circuit with the rectification function may be a rectification circuit (such as half-wave rectification, full-wave rectification, bridge rectification, etc.), or other types of rectification circuits.
  • the driving circuit 600 in the embodiment of the present application may be the driving circuit 380 in FIG. 3 described above.
  • the driving circuit 600 provided by the embodiment of the present application superimposes and rectifies the direct current signal input from the adapter through the first interface 610 with at least two PWM signals input from the MCU through the second interface 620, and then outputs them to the electronic device for charging.
  • the gate of the MOS tube in the path because at least two PWM signals are input to the driving circuit through the second interface based on the MCU, the driving voltage generated by the driving circuit can be increased, thereby increasing the gate between the MOS tubes
  • the voltage between the VGS and the source can avoid the decrease of the charging efficiency caused by the low voltage of VGS, and it can also avoid the rapid decrease of the fast charging current or withdrawal of the fast charging caused by the excessive impedance when the MOS tube is turned on. mode.
  • each signal superposition in the embodiment of the present application is a superposition of a DC signal and a PWM signal or a PWM signal and a PWM signal.
  • Superposition of signals Regarding the superposition of the PWM signal and the PWM signal, taking into account the influence of the PWM signal on the signal, the PWM signal and the PWM signal should be superimposed to maintain the same frequency, and the bandwidth of the high level of the PWM signal of one of them should be less than the other The high-level bandwidth of a PWM signal.
  • the processing circuit 630 is further configured to superimpose the direct current signal and one of the at least two PWM signals to obtain the first PWM signal, and to compare the first PWM signal to the first PWM signal.
  • a PWM signal is rectified to obtain a second direct current signal; the second direct current signal is superimposed and rectified with the remaining PWM signals in the at least two PWM signals to obtain the first direct current signal.
  • the processing circuit 630 may first superimpose the DC signal input from the adapter through the first interface 610 with one of the PWM signals of at least two PWM signals input through the second interface 620 based on the MCU to obtain the first PWM signal, and rectify the obtained first PWM signal to obtain a second direct current signal, and then superimpose and rectify the second direct current signal and the remaining PWM signal in at least two PWM signals to obtain the first direct current signal ,
  • the first direct current signal is output to the gate of the MOS tube on the charging path to increase the gate voltage of the MOS tube.
  • Figure 7 is a schematic diagram of the fast path provided by an embodiment of the application. It can be seen from the figure that the DC signal input by the adapter and one of the at least two PWM signals input based on the MCU are at point m. Superimpose to obtain the first PWM signal, which is rectified by the second rectifier D4 to obtain the second direct current signal. The second direct current signal is superimposed with the remaining PWM signals in the at least two PWM signals at point p and rectified by the first rectifier D2 The first direct current signal can be obtained.
  • the DC signal input by the adapter is superimposed on the PWM signal of the MCU through the capacitor C5 at point m.
  • the PWM signal based on MCU through capacitor C1 it is superimposed with the DC signal through diode D5 at point p, at this point point p
  • the voltage of Vp (Vbus-3Vd)+2clk, and then rectified by diode D2
  • the voltage drop of the diode is relatively small, generally 0.1V to 0.2V, and the signal voltage Vclk output by the MCU is generally about 4V.
  • the adapter output voltage is 5V
  • the MCU output signal voltage is 4V
  • the diode voltage is 0.2V
  • the impedance between the drain and the source when the MOS tube V2 is turned on can further prevent the MOS tube V1 and the MOS tube V2 from heating and the charging circuit impedance is too large to reduce the current or exit the fast charging mode.
  • the gate voltage of the MOS transistor V1 and the MOS transistor V2 can be increased by increasing the signal voltage Vclk output by the MCU control.
  • the signal voltage output by the MCU can be controlled to 5V. , which can increase the gate voltage of the MOS tube, thereby reducing the impedance between the drain and the source when the MOS tube V1 and the MOS tube V2 are turned on, and further avoiding the heating and charging circuit of the MOS tube V1 and the MOS tube V2 The impedance is too large to reduce the current or exit the fast charging mode.
  • the voltage drop of the diodes D1, D2, D4, or D5 can also be reduced to increase the gate voltages of the MOS transistors V1 and V2, thereby reducing the time when the MOS transistors V1 and V2 are turned on.
  • the impedance between the drain and the source of the MOS tube can further prevent the heating of the MOS tube V1 and the MOS tube V2 and the excessive impedance of the charging circuit, which reduces the current or exits the fast charging mode.
  • the second DC signal mentioned above is obtained by rectifying the first PWM signal. Since the DC signal obtained by rectification may have relatively large pulsation (ripple), that is, there are still small peaks and valleys, so It needs to be filtered, so that the signal waveform obtained after filtering is smoother and the voltage quality is higher.
  • the processing circuit 630 is further configured to: filter the second direct current signal to obtain the filtered second direct current signal; and combine the filtered second direct current signal with at least two The remaining PWM signals in the PWM signal are superimposed and rectified to obtain the first direct current signal.
  • the processing circuit 630 may rectifies the first PWM signal to obtain the second direct current signal, since the second direct current signal may be mixed with signals of other frequencies, the second direct current signal can be filtered In order to get a smooth DC signal. Further, the processing circuit 630 may superimpose and rectify the filtered second direct current signal with the remaining PWM signals in the at least two PWM signals, so as to obtain the first direct current signal.
  • the filtering of the second DC signal in the embodiment of the present application may be a filter capacitor or some filter circuit with a filtering function. This application does not specifically limit the time, as long as it can filter out the ripples in the second DC signal.
  • a filter or a filter circuit that smoothes the waveform of the second direct current signal can be applied to the embodiments of the present application.
  • the superimposed PWM signal can be rectified and then superimposed with the PWM signal. It is also possible to rectify the PWM signal before being superimposed and then superimpose it with the superimposed PWM signal.
  • the processing circuit 630 is further configured to: superimpose the direct current signal and one of the at least two PWM signals to obtain the first PWM signal;
  • the PWM signal is rectified to obtain a third direct current signal, and the third direct current signal and the first PWM signal are superimposed and rectified to obtain the first direct current signal.
  • the processing circuit 630 may first superimpose the DC signal input from the adapter through the first interface 610 with one of the PWM signals of at least two PWM signals input through the second interface 620 based on the MCU to obtain the first PWM signal, then rectify the remaining PWM signals in the at least two PWM signals to obtain a third direct current signal, and superimpose and rectify the third direct current signal with the first PWM signal to obtain the first direct current signal.
  • the first PWM signal in the embodiment of the present application is obtained by superimposing the direct current signal input through the first interface 610 with one of the at least two PWM signals. Therefore, the superimposed PWM signal can also be combined with at least two PWM signals.
  • the remaining PWM signal of the PWM signal is superimposed and rectified by the third DC signal obtained after rectification by the processing circuit 630, thereby obtaining the first DC signal.
  • Figure 8 is a schematic diagram of a fast path provided by an embodiment of the application. It can be seen from the figure that the DC signal input by the adapter and one of the at least two PWM signals input based on the MCU are at point m
  • the first PWM signal is obtained by superimposing, and the remaining PWM signals in the at least two PWM signals are rectified by the third rectifier D4 and superimposed with the first PWM signal at point p and rectified by D2 to obtain the first direct current signal.
  • the DC signal input by the adapter and the PWM signal of the MCU through the capacitor C5 are superimposed at point m.
  • the PWM signal is superimposed at point p.
  • the superimposed PWM signal is rectified by diode D2 to obtain the first direct current signal.
  • the processing circuit 630 is further configured to: filter the third direct current signal to obtain a filtered third direct current signal; and combine the filtered third direct current signal with the first PWM signal Perform superposition and rectification to obtain the first direct current signal.
  • the third direct current signal obtained after the processing circuit 630 rectifies the remaining PWM signals in the at least two PWM signals may contain signals of other frequencies. Therefore, the third direct current signal can be processed Filtering. After filtering the third direct current signal, the processing circuit 630 may superimpose and rectify the filtered third direct current signal and the first PWM signal to obtain the first direct current signal.
  • the filtering of the third DC signal in the embodiment of this application can be a filter capacitor or some filter circuit with filtering function. This application does not specifically limit the time, as long as it can filter out the ripples in the third DC signal.
  • a filter or a filter circuit that smoothes the waveform of the third direct current signal can be applied to the embodiments of the present application.
  • the direct current signal input by the adapter through the first interface can also be filtered.
  • the processing circuit 630 is further configured to filter the direct current signal input by the adapter through the first interface.
  • the DC signal input by the adapter through the first interface 610 can be filtered by a filter capacitor or some filter circuit with a filtering function.
  • This application does not specifically limit the frequency, as long as it can filter out Filters or filter circuits that smooth the waveform of the DC signal by ripples in the DC signal input from the first interface can be applied to the embodiments of the present application.
  • the processing circuit 630 may include a first capacitor C5, a capacitor C1, a diode D4, and a diode D2.
  • a capacitor C5 one end of the capacitor C5 is connected to the second interface
  • a capacitor C1, one end of the capacitor C1 is connected to the second interface;
  • a diode D4 the anode of the diode D4 is connected to the first interface and the other end of the capacitor C5, and the cathode of the diode D4 is connected to the other end of the capacitor C1, and is used to connect the first PWM The signal is rectified to obtain the second direct current signal;
  • a diode D2 the anode of the diode D2 is connected to the cathode of the diode D4 and the other end of the capacitor C1, and the cathode of the diode D2 is connected to the gates of the MOS transistor V1 and the MOS transistor V2 for Rectifying a signal obtained by superimposing the second direct current signal and the remaining PWM signal output by the MCU to obtain the first direct current signal;
  • the capacitor C5 is used to perform processing for removing the direct current signal from one of the at least two PWM signals before being superimposed
  • the capacitor C1 is used to perform processing on the remaining PWM signals in the at least two PWM signals.
  • the signal is processed to remove the direct current signal before being superimposed.
  • the capacitor C5, the capacitor C1, the diode D4, and the diode D2 in the embodiment of the present application may be the capacitor C5, the capacitor C1, the diode D4, and the diode D2 in FIG. 7.
  • the specific process can be seen in FIG. 7, which is not described in detail in this application.
  • the capacitor C5 and the capacitor C1 can be used to process the PWM signal output through the second interface to remove the direct current signal.
  • the processing circuit 630 may further include a diode D1 and a diode D5.
  • a diode D1, the anode and the cathode of the diode D1 are respectively connected to the first interface and the other end of the capacitor C5;
  • a diode D5 the anode of the diode D5 is connected to the cathode of the diode D4, and the cathode of the diode D5 is connected to the other end of the capacitor C1.
  • the diode D1 and the diode D5 in the embodiment of the present application may be the diode D1 and the diode D5 in FIG. 7.
  • the specific process can be seen in FIG. 7, which will not be described in detail in this application.
  • the processing circuit 630 may further include a capacitor C3 and a capacitor C6.
  • a capacitor C3, one end of the capacitor C3 is connected to the first interface, and the other end of the capacitor C3 is grounded, and is used to filter the direct current signal output from the first interface;
  • a capacitor C6 one end of the capacitor C6 is connected to the cathode of the diode D4, and the other end of the capacitor C6 is grounded, and is used for filtering the second direct current signal output from the diode D4.
  • the DC signal input by the adapter through the first interface may contain noise. Therefore, the DC signal can be filtered through the capacitor C3.
  • the DC signal input through the first interface and the MCU pass through the second interface.
  • the superimposed and rectified signal of one of the PWM signals in the input PWM signal may contain noise. Therefore, it can be filtered by the capacitor C6.
  • the superimposed PWM signal can be rectified and then superimposed with the PWM signal. It is also possible to rectify the PWM signal before being superimposed and then superimpose it with the superimposed PWM signal.
  • the processing circuit 630 may include a capacitor C5, a capacitor C1, a diode D4, and a diode D2.
  • a capacitor C5 one end of the capacitor C5 is connected to the second interface
  • a capacitor C1, one end of the capacitor C1 is connected to the second interface;
  • a diode D4 the anode of the diode D4 is connected to the other end of the capacitor C1, and the cathode of the diode is connected to the first interface and the other end of the capacitor C5, and is used to connect the at least two PWM signals Rectify the remaining PWM signal in, to obtain the third direct current signal;
  • a diode D2 the anode of the diode D2 is connected to the cathode of the diode D4, the first interface and the other end of the capacitor C5, and the cathode of the diode D2 is connected to the gates of the MOS transistor V1 and the MOS transistor V2 , For rectifying the signal after the superposition of the third direct current signal and the first PWM signal to obtain the first direct current signal;
  • the capacitor C5 is used to perform processing for removing the direct current signal from one of the at least two PWM signals before being superimposed
  • the capacitor C1 is used to perform processing on the remaining PWM signals in the at least two PWM signals.
  • the signal is processed to remove the direct current signal before being superimposed.
  • the capacitor C5, the capacitor C1, the diode D4, and the diode D2 in the embodiment of the present application may be the capacitor C5, the capacitor C1, the diode D4, and the diode D2 in FIG. 8.
  • the specific process can be seen in FIG. 8, and this application will not describe it in detail.
  • the processing circuit 630 may further include a diode D1 and a diode D5.
  • a diode D1, the anode and the cathode of the diode D1 are respectively connected to the first interface and the other end of the capacitor C5;
  • a diode D5 the anode of the diode D5 is connected to the other end of the capacitor C5 and the cathode of the diode D1, and the cathode of the diode D5 is connected to the cathode of the diode D4.
  • the diode D1 and the diode D5 in the embodiment of the present application may be the diode D1 and the diode D5 in FIG. 8.
  • the specific process can be seen in FIG. 8, and this application will not describe it in detail.
  • the processing circuit 630 may further include a capacitor C3 and a capacitor C6.
  • a capacitor C3, one end of the capacitor C3 is connected to the first interface, and the other end of the capacitor C3 is grounded, and is used to filter the direct current signal output from the first interface;
  • a capacitor C6 one end of the capacitor C6 is connected to the cathode of the diode D4, and the other end of the capacitor C6 is grounded, and is used for filtering the third direct current signal output from the diode D4.
  • the DC signal input by the adapter through the first interface may contain noise, so the DC signal can be filtered through the capacitor C3.
  • the PWM signal input by the MCU through the second interface may contain noise. Therefore, it can be filtered by capacitor C6.
  • the second interface in the embodiments of the present application may receive multiple PWM signals.
  • FIG. 15 is a schematic structural diagram of a fast charging path provided by an embodiment of the application, the DC signal output by the adapter and the PWM signal passing through the capacitor C5 are superimposed at point m to obtain the first A PWM signal, the first PWM signal is rectified by D4 to output a second direct current signal, the second direct current signal is superimposed with the PWM signal through capacitor C1 at point p to obtain the PWM signal, and then with the direct current signal obtained by rectification of D6
  • the first direct current signal can be obtained by superimposing at point s and rectifying by D2.
  • the processing circuit 630 may first superimpose and then rectify the multiple PWM signals received through the second interface with other DC signals, or it may first be rectified and then superimposed with other PWM signals, which is not specifically limited in this application. .
  • diodes D1 or D5 there may also be multiple diodes D1 or D5, wherein the diode D1 and the diode D5 may be the same type of diode or different types of diodes.
  • D5 can be located at the position shown in FIG. 15 to avoid the phenomenon of voltage back pressure caused by the increase of the voltage at point p.
  • the diode D5 in the embodiment of the present application may also be located before the diode D4, and the present application can be applied as long as the phenomenon of voltage back pressure caused by the increase of the voltage at point p can be avoided.
  • diodes there may also be multiple diodes in the embodiment of the present application. As shown in FIG. 15, in the embodiment of the present application, there may also be a diode D7 between the node p and the node s, so as to avoid the voltage caused by the increase of the voltage at point s. Back pressure phenomenon. It should be understood that the MCU in the embodiment of the present application can output multiple PWM signals through the second interface, and the diode can also be located in the circuit where each PWM signal of the multiple PWM signals is located after each superimposition and before the next superimposition. on.
  • the first interface 610 may be connected to the diode D1.
  • the superimposed signal voltage is greater than the DC signal voltage input by the adapter through the first interface, which may cause back pressure. Therefore, the diode D1 can avoid the back pressure phenomenon caused by the superposition of the DC signal output by the adapter and the PWM signal based on the MCU output .
  • the diode D5 can avoid the back pressure phenomenon caused by the increase of the voltage at the point p.
  • the PWM signal input through the second interface 620 based on the MCU may be at least two PWM signals, and the at least two PWM signals may be the same signal.
  • the at least two PWM signals may also be different signals.
  • Fig. 16 a schematic diagram of a fast path provided by an embodiment of this application. It can be seen from the figure that the direct current signal output by the adapter and the multiple PWM signals output based on the MCU are superimposed at point m to obtain the first PWM signal, the first PWM signal is rectified by the diode D2 to obtain the first direct current signal.
  • the voltage drop of the diode is relatively small, generally 0.1V to 0.2V, and the signal voltage Vclk output by the MCU is generally about 4V.
  • the adapter output voltage is 5V
  • the MCU output signal voltage is 4V
  • the diode voltage is 0.2V
  • the PWM signal voltages Vclk1 and Vclk2 output by the two pins of the MCU have the same frequency.
  • the superposition of the two PWM signal voltages can realize the gates of the MOS transistor V1 and the MOS transistor V2. The increase in pole voltage.
  • the parallel connection of the capacitor banks may affect the signal voltage output by the MCU, it is possible to input the original signal voltage Vclk1 for a period of time, and then output the signal voltage Vclk2 at the pin of the MCU. In other words, it is equivalent to adding the signal voltage of a branch newly and will not affect the original signal voltage Vclk1.
  • the time of the rising edge in the newly added PWM signal 2 is greater than the time of the rising edge in the original PWM signal 1.
  • the new PWM signal can be controlled.
  • the width of the high level of the added PWM signal is smaller than the width of the high level of the original PWM signal.
  • PWM signal 1 is the original signal in the driving circuit
  • PWM signal 2 is a newly added signal.
  • the frequencies of the PWM signal 1 and the PWM signal 2 are the same, that is, the periods of the two signals are the same, and both are from t1 to t4 in the figure.
  • PWM signal 1 it changes from low to high at t2
  • PWM signal 2 changes from low to high at t3
  • PWM signal 2 changes from low level to high level.
  • PWM signal 1 is basically in a completely stable state
  • the addition of PWM signal 2 will not Affect PWM signal 1.
  • the driving circuit 600 provided by the embodiment of the present application superimposes the direct current signal input from the adapter through the first interface 610 with at least two PWM signals input from the MCU through the second interface 620, and then undergoes rectification processing and outputs to the internal charging of the electronic device.
  • the gate of the MOS tube in the path because at least two PWM signals are input to the driving circuit through the second interface based on the MCU, which can increase the driving voltage generated by the driving circuit, thereby increasing the MOS tube V1 and the MOS tube V2
  • the voltage between the gate and the source of the MOS tube can avoid the decrease in charging efficiency caused by the low voltage between the gate and the source of the MOS tube V1 and MOS tube V2, and it can also prevent the MOS tube from turning on When the impedance is too large, the problem of rapidly reducing the fast charging current or exiting the fast charging mode.
  • FIG. 18 is a schematic block diagram of an electronic device 1800 according to an embodiment of the present application.
  • the electronic device may include a first interface 1810, a micro control unit MCU 1820, a second interface 1830, a processing circuit 1840, and a field effect transistor MOS tube 1850.
  • the first interface 1810 is connected to an external power supply device, and is used to receive a direct current signal input by the external power supply device;
  • the second interface 1830 connected to the MCU 1820, is used to receive at least two pulse width modulation PWM signals input by the MCU 1820;
  • MOS tube 1850
  • the processing circuit 1840 is respectively connected to the first interface 1810 and the second interface 1830, and is used to superimpose and rectify the direct current signal and the at least two PWM signals to obtain the first direct current signal, and
  • the first direct current signal is output to the gate of the MOS transistor, so that the voltage of the gate of the MOS transistor is greater than a first threshold.
  • the processing circuit 1840 can be any of the above-mentioned processing circuits 600, and for the sake of brevity, it will not be repeated here.
  • the processing circuit 1840 is further configured to: superimpose the direct current signal and one of the at least two PWM signals to obtain the first PWM signal, and The first PWM signal is rectified to obtain a second direct current signal; and the second direct current signal is superimposed and rectified with the remaining PWM signals in the at least two PWM signals to obtain the first direct current signal.
  • the processing circuit 1840 is further configured to: filter the second direct current signal to obtain the filtered second direct current signal; and filter the filtered second direct current signal The signal is superimposed and rectified with the remaining PWM signal in the at least two PWM signals to obtain the first direct current signal.
  • the processing circuit 1840 is further configured to: superimpose the direct current signal and one of the at least two PWM signals to obtain the first PWM signal; The remaining PWM signal in the PWM signal is rectified to obtain a third direct current signal, and the third direct current signal is superimposed and rectified with the first PWM signal to obtain the first direct current signal.
  • the processing circuit 1840 is further configured to: filter the third direct current signal to obtain the filtered third direct current signal; and filter the filtered third direct current signal The signal is superimposed and rectified with the first PWM signal to obtain the first direct current signal.
  • the processing circuit 1840 is further configured to: filter the direct current signal input by the external power supply device through the first interface.
  • the processing circuit 1840 includes: a capacitor C5, one end of the capacitor C5 is connected to the second interface; a capacitor C1, one end of the capacitor C1 is connected to the second interface; a diode; D4, the anode of the diode D4 is connected to the first interface and the other end of the capacitor C5, and the cathode of the diode D4 is connected to the other end of the capacitor C1, and is used to respond to the first PWM signal Rectification is performed to obtain the second direct current signal; a diode D2, the anode of the diode D2 is connected to the cathode of the diode D4 and the other end of the capacitor C1, and the cathode of the diode D2 is connected to the MOS tube V1 and The gate of the MOS tube V2 is connected to rectify the signal obtained by superimposing the second direct current signal and the remaining PWM signal output by the MCU to obtain the first direct current signal; wherein, the capacitor C5 is used for Before
  • the processing circuit 1840 further includes: a diode D1, the anode and cathode of the diode D1 are respectively connected to the first interface and the other end of the capacitor C5; a diode D5, the diode The anode of D5 is connected to the cathode of the diode D4, and the cathode of the diode D5 is connected to the other end of the capacitor C1.
  • the processing circuit 1840 further includes: a capacitor C3, one end of the capacitor C3 is connected to the first interface, the other end of the capacitor C3 is grounded, and is used to The DC signal output by the interface is filtered; the capacitor C6, one end of the capacitor C6 is connected to the cathode of the diode D4, and the other end of the capacitor C6 is grounded, and is used to perform the second DC signal output from the diode D4 Filtering.
  • the processing circuit 1840 includes: a capacitor C5, one end of the capacitor C5 is connected to the second interface; a capacitor C1, one end of the capacitor C1 is connected to the second interface; a diode; D4, the anode of the diode D4 is connected to the other end of the capacitor C1, and the cathode of the diode is connected to the first interface and the other end of the capacitor C5, and is used to connect the at least two PWM signals Rectify the remaining PWM signal to obtain the third direct current signal; diode D2, the anode of the diode D2 is connected to the cathode of the diode D4, the first interface and the other end of the capacitor C5, the The cathode of the diode D2 is connected to the gates of the MOS transistor V1 and the MOS transistor V2, and is used to rectify the signal obtained by superimposing the third direct current signal and the first PWM signal to obtain the first direct current signal; wherein The capacitor C5 is used to remove the DC
  • the processing circuit 1840 further includes: a diode D1, the anode and cathode of the diode D1 are respectively connected to the first interface and the other end of the capacitor C5; a diode D5, the diode The anode of D5 is connected to the other end of the capacitor C5 and the cathode of the diode D1, and the cathode of the diode D5 is connected to the cathode of the diode D4.
  • the processing circuit 1840 further includes: a capacitor C3, one end of the capacitor C3 is connected to the first interface, the other end of the capacitor C3 is grounded, and is used to The direct current signal output by the interface is filtered; a capacitor C6, one end of the capacitor C6 is connected to the cathode of the diode D4, and the other end of the capacitor C6 is grounded for filtering the third direct current signal output from the diode D4.
  • FIG. 19 shows a method 1900 for controlling charging provided by an embodiment of the application.
  • the method 1900 may include steps 1910-1920.
  • the direct current signal output by the external power supply device through the first interface and at least two PWM signals output by the MCU through the second interface are superimposed and rectified to obtain the first direct current signal signal , Including: superimposing the direct current signal input by the external power supply device through the first interface with one of the at least two PWM signals to obtain a first PWM signal, and compare the first The PWM signal is rectified to obtain a second direct current signal; the second direct current signal is superimposed and rectified with the remaining PWM signal in the at least two PWM signals to obtain the first direct current signal.
  • the method 1900 further includes: filtering the second direct current signal to obtain the filtered second direct current signal; and combining the second direct current signal with the Superimposing and rectifying the remaining PWM signals in the at least two PWM signals to obtain the first direct current signal includes: performing the filtering of the filtered second direct current signal with the remaining PWM signals in the at least two PWM signals Superimposing and rectifying to obtain the first direct current signal.
  • the direct current signal output by the external power supply device through the first interface and at least two PWM signals input from the MCU through the second interface are superimposed and rectified to obtain the first direct current signal
  • the method includes: superimposing the direct current signal input by the external power supply device through the first interface and one of the at least two PWM signals to obtain the first PWM signal; and comparing the at least two PWM signals The remaining PWM signal of is rectified to obtain a third direct current signal, and the third direct current signal is superimposed and rectified with the first PWM signal to obtain the first direct current signal.
  • the method 1900 further includes: filtering the third direct current signal to obtain the filtered third direct current signal; and combining the third direct current signal with the Superimposing and rectifying the first PWM signal to obtain the first direct current signal includes: superimposing and rectifying the filtered third direct current signal and the first PWM signal to obtain the first direct current signal Direct current signal.
  • the method 1900 may further include step 1930.
  • the method 1900 further includes step 1940.
  • the embodiment of the present application also provides a computer-readable storage medium that stores computer-executable instructions, and the computer-executable instructions are configured to execute any one of the aforementioned methods 1900.
  • the embodiments of the present application also provide a computer program product.
  • the computer program product includes a computer program stored on a computer-readable storage medium.
  • the computer program includes program instructions. When the program instructions are executed by a computer, the computer program The computer executes any of the methods 1900 described above.
  • FIG. 22 is a schematic structural diagram of a charging system provided by an embodiment of the present application.
  • the charging system includes a power supply device 10, a battery management circuit 20 and a battery 30.
  • the battery management circuit 20 can be used to manage the battery 30.
  • the battery management circuit 20 can manage the charging process of the battery 30, such as selecting the charging channel, controlling the charging voltage and/or charging current, etc.; as another example, the battery management circuit 20 can perform the charging process of the battery 30 Management, such as balancing the voltage of the battery cells in the battery 30.
  • the battery management circuit 20 may include a first charging channel 21 and a communication control circuit 23.
  • the first charging channel 21 can be used to receive the charging voltage and/or charging current provided by the power supply device 10 and load the charging voltage and/or charging current on both ends of the battery 30 to charge the battery 30.
  • the first charging channel 21 may be, for example, a wire, and some other circuit devices that are not related to the conversion of the charging voltage and/or the charging current may also be provided on the first charging channel 21.
  • the power management circuit 20 includes a first charging channel 21 and a second charging channel, and a switching device for switching between charging channels may be provided on the first charging channel 21 (see the description of FIG. 23 for details).
  • the type of the power supply device 10 is not specifically limited.
  • the power supply device 10 may be a device specially used for charging such as an adapter and a power bank, or may be a computer and other devices capable of providing power and data services.
  • the first charging channel 21 may be a direct charging channel, and the charging voltage and/or charging current provided by the power supply device 10 may be directly loaded on both ends of the battery 30.
  • the embodiment of the present application introduces a control circuit with a communication function, that is, the communication control circuit 23, into the battery management circuit 20.
  • the communication control circuit 23 can maintain communication with the power supply device 10 during the direct charging process to form a closed-loop feedback mechanism, so that the power supply device 10 can learn the status of the battery in real time, thereby continuously adjusting the charging voltage and the charging voltage injected into the first charging channel. /Or the charging current to ensure that the charging voltage and/or the charging current provided by the power supply device 10 match the current charging stage of the battery 30.
  • the communication control circuit 23 can communicate with the power supply device 10 when the voltage of the battery 30 reaches the charging cut-off voltage corresponding to the constant current stage, so that the power supply device 10 converts the charging process of the battery 30 from constant current charging to constant current charging. Pressure charging.
  • the communication control circuit 23 can communicate with the power supply device 10 when the charging current of the battery 30 reaches the charging cut-off current corresponding to the constant voltage stage, so that the power supply device 10 converts the charging process of the battery 30 from constant voltage charging Charge for constant current.
  • the communication control circuit 23 in the embodiment of the present application may be the aforementioned driving circuit.
  • the battery management circuit provided in the embodiment of the present application can directly charge the battery.
  • the battery management circuit provided in the embodiment of the present application is a battery management circuit that supports a direct charge architecture. In the direct charge architecture, there is no need for a direct charge channel.
  • the conversion circuit is provided to reduce the heat generation of the device to be charged during the charging process.
  • the battery management circuit 20 may further include a second charging channel 24.
  • a boost circuit 25 is provided on the second charging channel 24.
  • the boost circuit 25 can be used to receive the initial voltage provided by the power supply device 10, boost the initial voltage to a target voltage, and provide the battery based on the target voltage.
  • 30 charging wherein the initial voltage is less than the total voltage of the battery 30, and the target voltage is greater than the total voltage of the battery 30; the communication control circuit 23 can also be used to control the switching between the first charging channel 21 and the second charging channel 24.
  • the second charging channel 24 can be compatible with a common power supply device to charge the battery 30, which solves the problem that the common power supply device cannot charge multiple batteries.
  • the battery management circuit 20 may also include an equalization circuit 22, referring to the above description, the equalization circuit 22 can be used to balance the multiple cells during the charging process and/or discharging process of the battery The voltage of the core.
  • the embodiment of the present application does not limit the specific form of the boost circuit 25.
  • a Boost boost circuit can be used, or a charge pump can be used for boosting.
  • the second charging channel 24 may adopt a traditional charging channel design method, that is, a conversion circuit (such as a charging IC) is provided on the second charging channel 24.
  • the conversion circuit can perform constant voltage and constant current control on the charging process of the battery 30, and adjust the initial voltage provided by the power supply device 10 according to actual needs, such as step-up or step-down.
  • the embodiment of the present application can utilize the boost function of the conversion circuit to boost the initial voltage provided by the power supply device 10 to the target voltage.
  • the communication control circuit 23 can switch between the first charging channel 21 and the second charging channel 24 through a switching device.
  • a switch tube Q5 may be provided on the first charging channel 21.
  • the switch tube Q5 in the embodiment of the present application may be a MOS tube or a switch.
  • a circuit or device for step-down can also be provided on the second charging channel 24, and when the voltage provided by the power supply device is higher than the required voltage of the battery 30, the step-down process can be performed.
  • the circuit or module included in the second charging channel 24 is not limited.
  • the computer program product includes one or more computer instructions.
  • the computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.
  • the computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website, computer, server, or data center.
  • the computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or a data center integrated with one or more available media.
  • the usable medium may be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a digital video disc (DVD)), or a semiconductor medium (for example, a solid state disk (SSD)), etc.
  • the disclosed system, device, and method may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or It can be integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • first, second, etc. may be used in this application to describe various devices, these devices should not be limited by these terms. These terms are only used to distinguish one device from another.
  • the first device can be called the second device, and similarly, the second device can be called the first device, as long as all occurrences of "first device” are renamed consistently and all occurrences Just rename the "second device” consistently.
  • the first device and the second device are both devices, but they may not be the same device.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • each unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.

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Abstract

一种驱动电路(380)、电子设备(1800)以及控制充电方法(1900)，包括：第一接口(610)，用于接收外部电源提供装置输入的直流电信号；第二接口(620)，用于接收MCU输入的至少两路脉冲宽度调制PWM信号；处理电路(630)，用于将直流电信号和至少两路PWM信号进行叠加和整流，以获取第一直流电信号，并将第一直流电信号输出至MOS管的栅极。该驱动电路能够提高驱动电路所产生的驱动电压，从而能够增大MOS管之间的栅极和源极之间的电压，因此能够避免因为VGS的电压过低而导致的充电效率降低以及降低快充电流或退出快速充电模式。

Description

驱动电路、电子设备以及控制充电方法
优先权信息
本申请请求2019年6月19日向中国国家知识产权局提交的、专利申请号为201910532974.7的专利申请的优先权和权益，并且通过参照将其全文并入此处。
技术领域
本申请实施例涉及充电技术领域，具体涉及一种驱动电路、电子设备以及控制充电方法。
背景技术
随着电子设备(如手机、pad、手环等)的普及，电子设备的功能不断丰富，有些厂商推出了支持快速充电模式的电子设备，快充技术大大缩短了电子设备的充电时间，受到用户的广泛青睐。
发明内容
本申请实施例提供一种驱动电路、电子设备以及控制充电方法，以解决相关技术中的充电问题。
第一方面，本申请提供一种驱动电路，所述驱动电路位于电子设备的主板，所述电子设备还包括MOS管和微控制单元MCU，所述驱动电路包括：第一接口，与外部电源提供装置连接，用于接收所述外部电源提供装置输入的直流电信号；第二接口，与所述MCU连接，用于接收所述MCU输入的至少两路脉冲宽度调制PWM信号；处理电路，分别与所述第一接口和所述第二接口连接，用于将所述直流电信号和所述至少两路PWM信号进行叠加和整流，以获取第一直流电信号，并将所述第一直流电信号输出至所述MOS管的栅极，以使得所述MOS管的栅极的电压大于第一阈值。
第二方面，本申请提供一种电子设备，包括第一接口，与外部电源提供装置连接，用于接收所述外部电源提供装置输入的直流电信号；微控制单元MCU；第二接口，与所述MCU连接，用于接收所述MCU输入的至少两路脉冲宽度调制PWM信号；场效应管MOS管；处理电路，分别与所述第一接口和所述第二接口连接，用于将所述直流电信号和所述至少两路PWM信号进行叠加和整流，以获取第一直流电信号，并将所述第一直流电信号输出至所述MOS管的栅极，以使得所述MOS管栅极的电压大于第一阈值。
第三方面，本申请提供一种控制充电方法，所述方法包括：将外部电源提供装置通过第一接口输入的直流电信号和基于MCU通过第二接口输入的至少两路PWM信号进行叠加和整流，以获取第一直流电信号；并将所述第一直流电信号输出至MOS管的栅极，以使得所述MOS管的栅极的电压大于第一阈值。
第四方面，本申请提供一种计算机可读存储介质，用于存储计算机程序，所述计算机程序使得计算机执行上述第三方面或其各实现方式中任一项所述的方法。第三方面的方法包括将外部电源提供装置通过第一接口输入的直流电信号和基于MCU通过第二接口输入的至少两路PWM信号进行叠加和整流，以获取第一直流电信号；并将所述第一直流电信号输出至MOS管的栅极，以使得所述MOS管的栅极的电压大于第一阈值。
第五方面，本申请提供一种计算机程序产品，其特征在于，包括计算机程序指令，该计算机程序指令使得计算机执行上述第三方面或其各实现方式中任一项所述的方法。第三方面的方法包括将外部电源提供装置通过第一接口输入的直流电信号和基于MCU通过第二接口输入的至少两路PWM信号进行叠加和整流，以获取第一直流电信号；并将所述第一直流电信号输出至MOS管的栅极，以使得所述MOS管的栅极的电压大于第一阈值。
本申请实施例提供的驱动电路，通过将外部电源提供装置通过第一接口输入的直流电信号与基于MCU通过第二接口输入的至少两路PWM信号叠加后经过整流处理，输出至电子设备内部的充电通路中的MOS管的栅极，由于基于MCU通过第二接口输入至驱动电路中的是至少两路PWM信号，能够提高驱动电路所产生的驱动电压，从而能够增大MOS管之间的栅极和源极之间的电压，因此能够避免因为VGS的电压过低而导致的充电效率降低以及降低快充电流或退出快速充电模式。
本申请的实施方式的附加方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本申请的实施方式的实践了解到。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例中所需要使用的附图作简单地介绍， 显而易见地，下面所描述的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的二极管的示意图；
图2a和图2b是本申请实施例提供的MOS管的示意图；
图3是本申请实施例提供的快速通路的示意图；
图4是本申请一个实施例提供的一种快速通路的示意性结构图；
图5是本申请实施例提供的同一MOS管在不同栅源极电压下的漏极电流与漏源极电压之间的关系图；
图6是本申请一个实施例提供的一种驱动电路的示意性图；
图7是本申请一个实施例提供的一种快充通路的示意性图；
图8是本申请另一个实施例提供的一种快充通路的示意性图；
图9是本申请另一个实施例提供的一种驱动通路的示意性图；
图10是本申请又一个实施例提供的一种驱动电路的示意性图；
图11是本申请再一个实施例提供的一种驱动电路的示意性图；
图12是本申请再一个实施例提供的一种驱动电路的示意性图；
图13是本申请再一个实施例提供的一种驱动电路的示意性图；
图14是本申请再一个实施例提供的一种驱动电路的示意性图；
图15是本申请又一个实施例提供的一种快充通路的示意性图；
图16是本申请再一个实施例提供的一种快充通路的示意性图；
图17是本申请一个实施例提供的PWM信号的示意性图；
图18是本申请实施例提供的一种电子设备的示意性图；
图19本申请一个实施例提供的一种控制充电方法的示意性流程图；
图20本申请另一个实施例提供的一种控制充电方法的示意性流程图；
图21本申请又一个实施例提供的一种控制充电方法的示意性流程图；
图22是本申请一个实施例提供的有线充电系统的示意性结构图；和
图23是本申请又一个实施例提供的有线充电系统的示意性结构图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
为了更加清楚地理解本申请，先对本申请实施例中的二极管和MOS管的工作原理进行简单介绍，便于后续理解本申请的方案。但应理解，以下介绍的内容仅仅是为了更好的理解本申请，不应对本申请造成特别限定。
请参阅图6，驱动电路610应用于电子设备，电子设备还包括场效应管MOS管和微控制单元MCU，驱动电路610包括：第一接口610，与外部电源提供装置连接，用于接收外部电源提供装置输入的直流电信号；第二接口620，与MCU连接，用于接收MCU输入的至少两路脉冲宽度调制PWM信号；处理电路630，分别与第一接口610和第二接口620连接，用于将直流电信号和至少两路PWM信号进行叠加和整流，以获取第一直流电信号，并将第一直流电信号输出至MOS管的栅极，以使得MOS管栅极的电压大于第一阈值。
请参阅图6，在某些实施方式中，处理电路630进一步用于：将直流电信号和至少两路PWM信号中的其中一路PWM信号进行叠加，以获取第一PWM信号，并对第一PWM信号进行整流，以获取第二直流电信号；将第二直流电信号与至少两路PWM信号中的剩余PWM信号进行叠加和整流，以获取第一直流电信号。
请参阅图6，在某些实施方式中，处理电路630进一步用于：对第二直流电信号进行滤波，以获取滤波后的第二直流电信号；将滤波后的第二直流电信号与至少两路PWM信号中的剩余PWM信号进行叠加和整流，以获取第一直流电信号。
请参阅图6，在某些实施方式中，处理电路630进一步用于：将直流电信号和至少两路PWM信号中的其中一路PWM信号进行叠加，以获取第一PWM信号；对至少两路PWM信号中的剩余PWM信号进行整流，以获取第三直流电信号，并将第三直流电信号与第一PWM信号进行叠加和整流，以获取第一直流电信号。
请参阅图6，在某些实施方式中，处理电路630进一步用于：对第三直流电信号进行滤波，以获取滤波后的 第三直流电信号；将滤波后的第三直流电信号与第一PWM信号进行叠加和整流，以获取第一直流电信号。
请参阅图6，在某些实施方式中，处理电路630进一步用于：对外部电源提供装置通过第一接口610输入的直流电信号进行滤波。
请参阅图11，在某些实施方式中，处理电路630包括电容C5、电容C1、二极管D4和二极管D2。电容C5的一端与第二接口620连接；电容C1的一端与第二接口620连接；二极管D4的正极分别与第一接口610和电容C5的另一端连接，二极管D4的负极与电容C1的另一端连接，用于对第一PWM信号进行整流，以获取第二直流电信号；二极管D2的正极分别与二极管D4的负极和电容C1的另一端连接，二极管D2的负极与MOS管V1和MOS管V2的栅极连接，用于对第二直流电信号与MCU输出的剩余PWM信号叠加后的信号进行整流，以获取第一直流电信号；其中，电容C5用于对至少两路PWM信号的其中一路PWM信号在被叠加之前进行去除直流电信号的处理，电容C1用于对至少两路PWM信号中的剩余PWM信号在被叠加之前进行去除直流电信号的处理。
请参阅图11，在某些实施方式中，处理电路630还包括二极管D1和二极管D5。二极管D1的正极和负极分别与第一接口610和电容C5的另一端连接；二极管D5的正极与二极管D4的负极连接，二极管D5的负极和电容C1的另一端连接。
请参阅图11，在某些实施方式中，处理电路630还包括电容C3和电容C6。电容C3的一端与第一接口610连接，电容C3的另一端接地，用于对从第一接口610输出的直流电信号进行滤波；电容C6的一端与二极管D4的负极连接，电容C6的另一端接地，用于对从二极管D4输出的第二直流电信号进行滤波。
请参阅图12，在某些实施方式中，处理电路630包括电容C5、电容C1、二极管D4和二极管D2。电容C5的一端与第二接口620连接；电容C1的一端与第二接口620连接；二极管D4的正极与电容C1的另一端连接，二极管D4的负极与第一接口610和电容C5的另一端连接，用于对至少两路PWM信号中的剩余PWM信号进行整流，以获取第三直流电信号；二极管D2的正极与二极管D4的负极、第一接口610以及电容C5的另一端连接，二极管D2的负极与MOS管V1和MOS管V2的栅极连接，用于对第三直流电信号与第一PWM信号叠加后的信号进行整流，以获取第一直流电信号；其中，电容C5用于对至少两路PWM信号的其中一路PWM信号在被叠加之前进行去除直流电信号的处理，电容C1用于对至少两路PWM信号中的剩余PWM信号在被叠加之前进行去除直流电信号的处理。
请参阅图13，在某些实施方式中，处理电路630还包括二极管D1和二极管D5。二极管D1的正极和负极分别与第一接口610和电容C5的另一端连接；二极管D5的正极与电容C5的另一端和二极管D1的负极连接，二极管D5的负极和二极管D4的负极连接。
请参阅图14，在某些实施方式中，处理电路630还包括电容C3和电容C6。电容C3的一端与第一接口610连接，电容C3的另一端接地，用于对从第一接口610输出的直流电信号进行滤波；电容C6的一端与二极管D4的负极连接，电容C6的另一端接地，用于对从二极管D4输出的第三直流电信号进行滤波。
请参阅图6和图18，本申请实施方式的电子设备1800包括第一接口1810，微控制单元MCU1820，第二接口1830，处理电路1840以及场效应管MOS管1850。第一接口1810，与外部电源提供装置连接，用于接收外部电源提供装置输入的直流电信号；第二接口1830，与MCU1820连接，用于接收MCU1820输入的至少两路脉冲宽度调制PWM信号；处理电路1840，分别与第一接口610和第二接口620连接，用于将直流电信号和至少两路PWM信号进行叠加和整流，以获取第一直流电信号，并将第一直流电信号输出至MOS管的栅极，以使得MOS管栅极的电压大于第一阈值。
请参阅图6，在某些实施方式中，处理电路630进一步用于：将直流电信号和至少两路PWM信号中的其中一路PWM信号进行叠加，以获取第一PWM信号，并对第一PWM信号进行整流，以获取第二直流电信号；将第二直流电信号与至少两路PWM信号中的剩余PWM信号进行叠加和整流，以获取第一直流电信号。
请参阅图6，在某些实施方式中，处理电路630进一步用于：对第二直流电信号进行滤波，以获取滤波后的第二直流电信号；将滤波后的第二直流电信号与至少两路PWM信号中的剩余PWM信号进行叠加和整流，以获取第一直流电信号。
请参阅图6，在某些实施方式中，处理电路630进一步用于：将直流电信号和至少两路PWM信号中的其中一路PWM信号进行叠加，以获取第一PWM信号；对至少两路PWM信号中的剩余PWM信号进行整流，以获取第三直流电信号，并将第三直流电信号与第一PWM信号进行叠加和整流，以获取第一直流电信号。
请参阅图6，在某些实施方式中，处理电路630进一步用于：对第三直流电信号进行滤波，以获取滤波后的 第三直流电信号；将滤波后的第三直流电信号与第一PWM信号进行叠加和整流，以获取第一直流电信号。
请参阅图6，在某些实施方式中，处理电路630进一步用于：对外部电源提供装置通过第一接口610输入的直流电信号进行滤波。
请参阅图11，在某些实施方式中，处理电路630包括电容C5、电容C1、二极管D4和二极管D2。电容C5的一端与第二接口620连接；电容C1的一端与第二接口620连接；二极管D4的正极分别与第一接口610和电容C5的另一端连接，二极管D4的负极与电容C1的另一端连接，用于对第一PWM信号进行整流，以获取第二直流电信号；二极管D2的正极分别与二极管D4的负极和电容C1的另一端连接，二极管D2的负极与MOS管V1和MOS管V2的栅极连接，用于对第二直流电信号与MCU输出的剩余PWM信号叠加后的信号进行整流，以获取第一直流电信号；其中，电容C5用于对至少两路PWM信号的其中一路PWM信号在被叠加之前进行去除直流电信号的处理，电容C1用于对至少两路PWM信号中的剩余PWM信号在被叠加之前进行去除直流电信号的处理。
请参阅图11，在某些实施方式中，处理电路630还包括二极管D1和二极管D5。二极管D1的正极和负极分别与第一接口610和电容C5的另一端连接；二极管D5的正极与二极管D4的负极连接，二极管D5的负极和电容C1的另一端连接。
请参阅图11，在某些实施方式中，处理电路630还包括电容C3和电容C6。电容C3的一端与第一接口610连接，电容C3的另一端接地，用于对从第一接口610输出的直流电信号进行滤波；电容C6的一端与二极管D4的负极连接，电容C6的另一端接地，用于对从二极管D4输出的第二直流电信号进行滤波。
请参阅图12，在某些实施方式中，处理电路630包括电容C5、电容C1、二极管D4和二极管D2。电容C5的一端与第二接口620连接；电容C1的一端与第二接口620连接；二极管D4的正极与电容C1的另一端连接，二极管D4的负极与第一接口610和电容C5的另一端连接，用于对至少两路PWM信号中的剩余PWM信号进行整流，以获取第三直流电信号；二极管D2的正极与二极管D4的负极、第一接口610以及电容C5的另一端连接，二极管D2的负极与MOS管V1和MOS管V2的栅极连接，用于对第三直流电信号与第一PWM信号叠加后的信号进行整流，以获取第一直流电信号；其中，电容C5用于对至少两路PWM信号的其中一路PWM信号在被叠加之前进行去除直流电信号的处理，电容C1用于对至少两路PWM信号中的剩余PWM信号在被叠加之前进行去除直流电信号的处理。
请参阅图13，在某些实施方式中，处理电路630还包括二极管D1和二极管D5。二极管D1的正极和负极分别与第一接口610和电容C5的另一端连接；二极管D5的正极与电容C5的另一端和二极管D1的负极连接，二极管D5的负极和二极管D4的负极连接。
请参阅图14，在某些实施方式中，处理电路630还包括电容C3和电容C6。电容C3的一端与第一接口610连接，电容C3的另一端接地，用于对从第一接口610输出的直流电信号进行滤波；电容C6的一端与二极管D4的负极连接，电容C6的另一端接地，用于对从二极管D4输出的第三直流电信号进行滤波。
请参阅图19，本申请实施方式的控制充电的方法1900包括步骤1910：将外部电源提供装置通过第一接口输入的直流电信号和基于MCU通过第二接口输入的至少两路PWM信号进行叠加和整流，以获取第一直流电信号；步骤1920：将第一直流电信号输出至MOS管的栅极，以使得MOS管的栅极的电压大于第一阈值。
在某些实施方式中，步骤1910包括：将外部电源提供装置通过第一接口输入的直流电信号和至少两路PWM信号中的其中一路PWM信号进行叠加，以获取第一PWM信号，并对第一PWM信号进行整流，以获取第二直流电信号；将第二直流电信号与至少两路PWM信号中的剩余PWM信号进行叠加和整流，以获取第一直流电信号。
请参阅图19，在某些实施方式中，方法1900还包括：对第二直流电信号进行滤波，以获取滤波后的第二直流电信号；将第二直流电信号与至少两路PWM信号中的剩余PWM信号进行叠加和整流，以获取第一直流电信号，包括：将滤波后的第二直流电信号与至少两路PWM信号中的剩余PWM信号进行叠加和整流，以获取第一直流电信号。
请参阅图19，在某些实施方式中，步骤1910包括：对外部电源提供装置通过第一接口输入的直流电信号和至少两路PWM信号中的其中一路PWM信号进行叠加，以获取第一PWM信号；对至少两路PWM信号中的剩余PWM信号进行整流，以获取第三直流电信号，并将第三直流电信号与第一PWM信号进行叠加和整流，以获取第一直流电信号。
请参阅图19，在某些实施方式中，方法1900还包括：对第三直流电信号进行滤波，以获取滤波后的第三直 流电信号；将第三直流电信号与第一PWM信号进行叠加和整流，以获取第一直流电信号，包括：将滤波后的第三直流电信号与第一PWM信号进行叠加和整流，以获取第一直流电信号。
请参阅图20，在某些实施方式中，方法1900还可以包括步骤1930：对电源提供装置通过第一接口输入的直流电信号进行滤波。
请参阅图21，在某些实施方式中，方法1900还可以包括步骤1940：分别对在至少两个PWM信号被叠加之前进行去除直流电信号的处理。
请参阅图19，本申请的计算机可读存储介质，存储有计算机可执行指令，计算机可执行指令设置为执行上述方法1900的任何一种方法。计算机可执行指令设置为执行以下步骤：将外部电源提供装置通过第一接口输入的直流电信号和基于MCU通过第二接口输入的至少两路PWM信号进行叠加和整流，以获取第一直流电信号；将第一直流电信号输出至MOS管的栅极，以使得MOS管的栅极的电压大于第一阈值。
在某些实施方式中，计算机可执行指令设置为执行以下步骤：将外部电源提供装置通过第一接口输入的直流电信号和至少两路PWM信号中的其中一路PWM信号进行叠加，以获取第一PWM信号，并对第一PWM信号进行整流，以获取第二直流电信号；将第二直流电信号与至少两路PWM信号中的剩余PWM信号进行叠加和整流，以获取第一直流电信号。
在某些实施方式中，计算机可执行指令设置为执行以下步骤：对第二直流电信号进行滤波，以获取滤波后的第二直流电信号；将滤波后的第二直流电信号与至少两路PWM信号中的剩余PWM信号进行叠加和整流，以获取第一直流电信号。
在某些实施方式中，计算机可执行指令设置为执行以下步骤：对外部电源提供装置通过第一接口输入的直流电信号和至少两路PWM信号中的其中一路PWM信号进行叠加，以获取第一PWM信号；对至少两路PWM信号中的剩余PWM信号进行整流，以获取第三直流电信号，并将第三直流电信号与第一PWM信号进行叠加和整流，以获取第一直流电信号。
在某些实施方式中，计算机可执行指令设置为执行以下步骤：对第三直流电信号进行滤波，以获取滤波后的第三直流电信号；将滤波后的第三直流电信号与第一PWM信号进行叠加和整流，以获取第一直流电信号。
在某些实施方式中，计算机可执行指令设置为执行以下步骤：对电源提供装置通过第一接口输入的直流电信号进行滤波。
在某些实施方式中，计算机可执行指令设置为执行以下步骤：分别对在至少两个PWM信号被叠加之前进行去除直流电信号的处理。
请参阅图19，本申请的计算机程序产品包括计算机程序指令，该计算机程序指令使得计算机执行上述方法1900的的任何一种方法。该计算机程序指令使得计算机执行以下步骤：将外部电源提供装置通过第一接口输入的直流电信号和基于MCU通过第二接口输入的至少两路PWM信号进行叠加和整流，以获取第一直流电信号；将第一直流电信号输出至MOS管的栅极，以使得MOS管的栅极的电压大于第一阈值。
在某些实施方式中，该计算机程序指令使得计算机执行以下步骤：将外部电源提供装置通过第一接口输入的直流电信号和至少两路PWM信号中的其中一路PWM信号进行叠加，以获取第一PWM信号，并对第一PWM信号进行整流，以获取第二直流电信号；将第二直流电信号与至少两路PWM信号中的剩余PWM信号进行叠加和整流，以获取第一直流电信号。
在某些实施方式中，该计算机程序指令使得计算机执行以下步骤：对第二直流电信号进行滤波，以获取滤波后的第二直流电信号；将滤波后的第二直流电信号与至少两路PWM信号中的剩余PWM信号进行叠加和整流，以获取第一直流电信号。
在某些实施方式中，该计算机程序指令使得计算机执行以下步骤：对外部电源提供装置通过第一接口输入的直流电信号和至少两路PWM信号中的其中一路PWM信号进行叠加，以获取第一PWM信号；对至少两路PWM信号中的剩余PWM信号进行整流，以获取第三直流电信号，并将第三直流电信号与第一PWM信号进行叠加和整流，以获取第一直流电信号。
在某些实施方式中，该计算机程序指令使得计算机执行以下步骤：对第三直流电信号进行滤波，以获取滤波后的第三直流电信号；将滤波后的第三直流电信号与第一PWM信号进行叠加和整流，以获取第一直流电信号。
在某些实施方式中，该计算机程序指令使得计算机执行以下步骤：对电源提供装置通过第一接口输入的直流电信号进行滤波。
在某些实施方式中，该计算机程序指令使得计算机执行以下步骤：分别对在至少两个PWM信号被叠加之前 进行去除直流电信号的处理。
如图1所示为肖特基二极管的示意图，肖特基二极管不是利用P型半导体与N型半导体接触形成PN结原理制作的，而是利用金属与半导体接触形成的金属－半导体结原理制作的，具有开关频率高和正向压降低等优点。
MOS管是金属(metal)、氧化物(oxide)、半导体(semiconductor)场效应晶体管，或者称是金属—绝缘体(insulator)、半导体。MOS管包括N沟道MOS管和P沟道MOS管，如图2a和图2b所示分别为N沟道MOS管和P沟道MOS管的示意图。图中D是漏极，S是源极，G是栅极，中间的箭头表示衬底。MOS管可以包括N沟道MOS管和P沟道MOS管。
以N沟道MOS管为例，若栅极和源极之间的电压为高电平，即VGS>0，则漏极和源极就会导通，此时漏极和源极之间相当于一个很小的电阻，电流从漏极流向源极；若栅极和源极之间的电压为低电平，即VGS<0，则漏极和源极之间就会截止，此时漏极和源极之间相当于一个很大的电阻，电流无法在漏极和源极之间流通。
相反地，对于P沟道MOS管，若栅极和源极之间的电压为低电平，即VGS<0，则漏极和源极就会导通，此时漏极和源极之间相当于一个很小的电阻，电流从源极流向漏极；若栅极和源极之间的电压为高电平，即VGS>0，则漏极和源极之间就会截止，此时漏极和源极之间相当于一个很大的电阻，电流无法在漏极和源极之间流通。
如图3所示为应用本申请实施例的快速通路的示意图，该快速通路示意图中可以包括：电池310，MOS管320，通用串行总线接口(USB接口)330，数据线340，电源提供装置350，应用处理器360(Application Processor，AP)，微控制单元370(Micro-controller Unit，MCU)以及驱动电路380。本申请实施例中的电源提供装置350可以为适配器、移动电源等。本申请实施例中的MCU370能够控制快充通路的闭合或断开，也能够输出多路脉冲宽度调制(Pulse Width Modulation，PWM)信号，本申请实施例中的AP360可以控制快充通路的闭合或断开，在一些实施例中，MCU370和AP360可以为同一个。
以手机为例，手机中设置有电池310和MOS管320，电源提供装置350与手机通过USB接口330相连，该USB接口330可以是Micro USB接口，也可以是Type-c USB接口。其中，USB接口中的数据线用于电源提供装置和手机进行双向通信，该数据线可以是USB接口中的D+线和/或D-线，所谓双向通信可以指电源提供装置和手机双方进行信息的交互，其中，MOS管、驱动电路、MCU、AP可以位于手机内部的主板上。
本申请实施例中的电源提供装置350支持普通充电模式和快速充电模式，快速充电模式的充电速度大于普通充电模式的充电速度。快速充电模式的充电电流大于普通充电模式的充电电流和/或快速充电模式的充电电压高于普通充电模式的充电电压。
一般而言，普通充电模式是指电源提供装置输出相对较小的电流值(通常小于2.5A)或者以相对较小的功率(通常小于15W)来对电子设备中的电池进行充电，在普通充电模式下想要完全充满一较大容量电池(如3000毫安时容量的电池)，通常需要花费数个小时的时间；而在快速充电模式下，电源提供装置能够输出相对较大的电流，(通常大于2.5A，比如4.5A，5A甚至更高)或者以相对较大的功率(通常大于或等于15W)来对电子设备中的电池进行充电，相较于普通充电模式而言，电源提供装置在快速充电模式下完全充满相同容量电池所需要的充电时间能够明显缩短、充电速度更快。快速充电模式也可以根据充电回路的阻抗的不同分为多个快速充电阶段，其中，随着阻抗的增加，快速充电阶段的电流呈递减趋势。
在对电子设备进行快速充电时，目前通过驱动电路输出的驱动电压来控制快充回路上的场效应(Metal Oxide Semiconductor，MOS)管的栅极电压，然而目前采用的驱动电路输出的驱动电压较小，使得MOS管在导通时的漏极和源极之间的阻抗较大，一方面导致MOS管的发热严重，充电效率降低；另一方面由于MOS导通时的阻抗过大，造成整个充电回路的阻抗过大，从而使得快充电流降低或退出快速充电模式。
以手机为例，利用快速充电模式对手机进行充电的过程中，手机端实时将靠近电源端的电池电压V1通过数据线上的数据线上的D+、D-信号发送给电源提供装置，电源提供装置通过将V1与自己输出的电压V0进行比较，再除以充电电流I可得到充电回路的阻抗R，即R＝(V0-V1)/I。在一个实施例中，阻抗的具体管控方法可如表1所示：
表1
回路阻抗 R≤R1 R1<R≤R2 R2<R≤R3 R>R3
快充电流 I1 I2 I3 退出快充
当充电回路的阻抗R小于R1时，使用电流I1进行快充；当阻抗增大至满足R1<R≤R2时，控制充电回路 的电流降低至I2进行快充(I2<I1)；若阻抗继续增大至满足R2<R≤R3，控制充电回路的电流降低至I3进行快充(I3<I2)；若阻抗继续增大至满足R>R3，退出快速充电模式，使用普通充电模式对手机进行充电。
本申请实施例中的MCU能够控制MOS管的导通和关闭，从而实现快速充电模式的进入和退出。
为了便于简洁，以下实施例中，本申请的电源提供装置将以适配器为例进行说明。
如图4所示为一种快速通路的示意性结构图，其中，本申请实施例中的MCU能够通过控制输出的电平的高低来实现快速充电的进入和退出。本申请实施例以N沟道MOS管为例，当MCU输出高电平时，由于N沟道MOS管V3的栅极电压低于源极电压，MOS管V3处于导通状态，此时适配器输出的电压Vbus和MCU输出的PWM信号电压通过MOS管V3接地；若MCU输出低电平时，由于N沟道MOS管V3的栅极电压高于源极电压，MOS管V3处于截止状态，此时适配器输出的电压Vbus对电池充电。
在MCU输出低电平时，MOS管V3处于截止状态，适配器上的电压Vbus通过电阻R1、二极管D1到达二极管D1和二极管D2之间，MCU控制输出的信号电压Vclk通过在电容C1上的充放电加到二极管D1和二极管D2之间。由于电阻R3的阻抗比较大，流经电阻R1、R2以及R3的电流很小，在电阻R1、R2以及R3的压降也很小，在这种情况下，二极管D1和二极管D2之间的电压Vm＝(Vbus-Vd)+Vclk，再经过二极管D2的整流，则二极管D2与电阻R2之间的电压Vn＝(Vbus-2Vd)+Vclk，其中，Vd表示二极管D1和二极管D2上的压降。
其中，二极管D1在上述电路中可以避免电压的反向流动，从而可以避免由于二极管D1和二极管D2之间的m点的电压Vm增大而导致的漏电现象，也就是说，由于二极管D1和二极管D2之间的m点的电压Vm大于适配器输出电压，有可能会导致电流反向经过电阻R1传输至适配器，因此二极管D1可以防止电流的反充；二极管D2可以将交流整流为直流，由于适配器输出电压Vbus是直流电压，MCU控制输出的信号电压Vclk是交流PWM信号电压，在适配器输出电压Vbus和MCU控制输出的信号电压Vclk到达二极管D1和D2之间时，所呈现的电压也为交流电压，因此在经过二极管D2的整流后，将交流电整流为直流电。
上述过程中，由于电阻R2的阻抗较大，流经电阻R2的电流较小，在电阻R2上的压降也很小，因此，对于MOS管V1和MOS管V2来说，其栅极电压基本等于二极管D2与电阻R2之间的n点的电压Vn，即VG＝Vn＝(Vbus-2Vd)+Vclk。此时，对于MOS管V2来说，栅极和源极之间的电压为VGS2＝Vclk-2Vd；对于MOS管V1来说，栅极和源极之间的电压为VGS1＝(Vbus-2Vd)+Vclk-Vbat，其中，Vbat表示MOS管V1的输出电压。
对于上述图4中的电路，MOS管V2上的栅极和源极之间的压差为VGS2＝Vclk-2Vd，由于Vclk的电压受到快充MCU的控制，且一般情况下手机MCU的供电电压只有4V左右，产生的Vclk电压也只有4V左右，因此加在MOS管V2上栅极和源极之间的电压VGS2通常低于4V。而在MOS管上的栅极和源极之间的电压VGS较低时，MOS管在充电回路中的漏极和源极之间的阻抗RDS比较大，具体的对于同一MOS管，不同VGS下，漏极电流ID与漏极和源极之间的电压VDS之间的关系可以如图5所示。
从图5中可以看出，对于同一MOS管而言，VGS越低，MOS管导通时的漏极和源极之间的阻抗RDS会越大，特别地，在VGS过低会造成MOS管导通时的阻抗RDS过大，根据P＝I2*R可知，一部分电量会以热量的形式消耗在MOS管上，导致MOS管发热严重，充电效率降低；另外由于MOS管导通时的阻抗RDS过大，会造成整个充电回路的阻抗过大，按照上述表1中的阻抗的管控方法，会很快控制快充电流降低或退出快速充电模式。
因此，本申请实施例提供了以下的方案，能够避免因为VGS的电压过低而导致的充电效率降低，同时也能够避免由于MOS管导通时的阻抗过大而导致的快速降低快充电流或退出快速充电模式的问题。
下面结合图6，对本申请实施例提供的驱动电路进行详细说明。
本申请实施例提供的驱动电路600可以包括第一接口610、第二接口620、处理电路630。
第一接口610，与适配器连接，用于接收所述适配器输入的直流电信号。
第二接口620，与MCU连接，用于接收MCU输入的至少两路脉冲宽度调制PWM信号。
本申请实施例中，MCU为微控制单元，MCU可以控制电子设备内部的其它器件的开通或关断，例如，可以通过MCU引脚输出的电平信号的高低来控制MOS管的闭合或关断。
本申请实施例中的PWM信号是通过MCU输出的信号，可以为方波信号或其它信号等。本申请实施例中的PWM信号的占空比可以为50％，也可以为20％或其它等，本申请对此不作具体限定。
处理电路630，分别与所述第一接口610和所述第二接口620连接，用于将所述直流电信号和所述至少两路PWM信号进行叠加和整流，以获取第一直流电信号，并将所述第一直流电信号输出至所述MOS管的栅极，以使得所述MOS管栅极的电压大于第一阈值。
本申请实施例中，通过第二接口620接收的至少两路PWM信号为交流信号，在与适配器通过第一接口610输入的直流电信号叠加后，叠加后的PWM信号也为交流信号，与第二接口输入的至少两路PWM信号相比，叠加后的PWM信号的频率没有变化，幅值有所增加。
本申请实施例中，基于MCU通过第二接口620接收的至少两路PWM信号可以是MCU中的同一引脚通过驱动电路的变化输入的两路PWM信号，也可以是MCU中的不同引脚直接通过第二接口620输入的至少两路PWM信号。可以理解的是，若至少两路PWM信号是MCU中的不同引脚直接通过第二接口620输入的至少两路PWM信号，则这两个引脚输出的PWM信号的频率相同。
申请实施例对处理电路630的形式不做具体限定，只要能够将直流电信号和至少两路PWM信号进行叠加和整流后并输出第一直流电信号的电路均可应用于本申请实施例。
本申请实施例中，处理电路630对适配器输入的直流电信号和至少两路PWM信号进行叠加和整流后得到第一直流电信号，并将得到的第一直流电信号输出至电子设备内部的MOS管的栅极，以使得MOS管栅极的电压大于第一阈值。
在一种实施例中，第一阈值可以为8.6V，那么MOS管的栅极电压大于8.6均可应用本申请实施例。
应理解，本申请实施例中的数值仅为举例说明，也可以为其它数值，不应对本申请造成特别限定。
本申请实施例的处理电路630中的具有整流作用的可以是肖特基二极管，也可以是具有整流功能的电路，本申请对此不作具体限定，只要能够将PWM信号整流成为直流电信号均可应用于本申请实施例。其中，例如，具有整流功能的电路可以是整流电路(如半波整流，全波整流，桥式整流等)，还可以是其他类型的整流电路。
其中，本申请实施例中的驱动电路600可以为上述图3中的驱动电路380。
本申请实施例提供的驱动电路600，通过将适配器通过第一接口610输入的直流电信号与基于MCU通过第二接口620输入的至少两路PWM信号叠加和整流处理后，输出至电子设备内部的充电通路中的MOS管的栅极，由于基于MCU通过第二接口输入至驱动电路中的是至少两路PWM信号，能够提高驱动电路所产生的驱动电压，从而能够增大MOS管之间的栅极和源极之间的电压，因此能够避免因为VGS的电压过低而导致的充电效率降低，同时也可以避免由于MOS管导通时的阻抗过大而导致的快速降低快充电流或退出快速充电模式。
应理解，由于具有共同节点的直流电信号与直流电信号的叠加不是简单的电压数值的相加，因此，本申请实施例中每一次信号的叠加是直流电信号与PWM信号的叠加或者是PWM信号与PWM信号的叠加。对于PWM信号与PWM信号的叠加，考虑到PWM信号之间对信号会有影响，因此PWM信号与PWM信号在叠加是应保持频率一致，且其中一路的PWM信号的高电平的带宽应该小于另一路的PWM信号的高电平的带宽。
可选地，在一些实施例中，处理电路630进一步用于将所述直流电信号和所述至少两路PWM信号中的其中一路PWM信号进行叠加，以获取第一PWM信号，并对所述第一PWM信号进行整流，以获取第二直流电信号；将所述第二直流电信号与所述至少两路PWM信号中的剩余PWM信号进行叠加和整流，以获取所述第一直流电信号。
本申请实施例中，处理电路630可以先将适配器通过第一接口610输入的直流电信号和基于MCU通过第二接口620输入的至少两路PWM信号中的其中一路PWM信号进行叠加，以获取第一PWM信号，并对获取的第一PWM信号进行整流，以获取第二直流电信号，再将第二直流电信号和与至少两路PWM信号中的剩余PWM信号进行叠加和整流，以得到第一直流电信号，第一直流电信号输出至充电通路上的MOS管的栅极以提高MOS管的栅极电压。
如图7所示为本申请一实施例提供的快速通路的示意图，从图中可以看出，适配器输入的直流电信号与基于MCU输入的至少两路PWM信号中的其中一路PWM信号在m点处叠加，得到第一PWM信号，经过第二整流器D4的整流得到第二直流电信号，第二直流电信号与至少两路PWM信号中的剩余PWM信号在p点处叠加并经过第一整流器D2的整流后可以得到第一直流电信号。
具体地，对于m点来说，适配器输入的直流电信号与MCU通过电容C5的PWM信号在m点叠加，此时m点的电压Vm＝(Vbus-Vd)+Vclk，之后通过二极管D4整流，则n点的电压Vn＝(Vbus-2Vd)+Vclk，再经过二极管D5到达p点；对于基于MCU通过电容C1的PWM信号，在p点处与经过二极管D5的直流电信号进行叠加，此时p点的电压为Vp＝(Vbus-3Vd)+2clk，再经过二极管D2的整流，q点的电压为Vq＝(Vbus-4Vd)+2Vclk，即MOS管V1的栅极电压为Vo＝Vq＝(Vbus-4Vd)+2Vclk。
一般情况下，二极管的压降比较小，一般为0.1V～0.2V，而MCU输出的信号电压Vclk一般为4V左右。例如，在一种实施例中，适配器输出的电压为5V，MCU输出的信号电压为4V，二极管的电压为0.2V，则o点的 电压，即MOS管V1和MOS管V2的栅极电压VG＝Vo＝(Vbus-2Vd)+Vclk＝5-0.4+4＝8.6V；另一种实施例中，由于增加了一路PWM信号电压，如图7所示，此时则MOS管栅极电压VG＝Vo＝(Vbus-4Vd)+2Vclk＝5-0.8+8＝12.2V。
这种情况下，MOS管V1的栅极电压增加了V增加＝Vclk-2Vd＝3.6V，因此，本申请实施例能够提高MOS管V1和MOS管V2的栅极电压，从而可以减少MOS管V1和MOS管V2导通时漏极和源极之间的阻抗，进一步能够避免MOS管V1和MOS管V2的发热和充电回路阻抗过大而降低电流或退出快速充电模式。
当然，可选地，在一些实施例中，也可以通过提高MCU控制输出的信号电压Vclk的大小来提高MOS管V1和MOS管V2的栅极电压，例如，MCU输出的信号电压可以控制为5V，即能够提高MOS管的栅极电压，从而可以减少MOS管V1和MOS管V2导通时的漏极和源极之间的阻抗，进一步能够避免MOS管V1和MOS管V2的发热和充电回路阻抗过大而降低电流或退出快速充电模式。
或者，在一些实施例中，也可以通过降低二极管D1、D2、D4或D5的压降来提高MOS管V1和MOS管V2的栅极电压，从而可以减少MOS管V1和MOS管V2导通时的漏极和源极之间的阻抗，进一步能够避免MOS管V1和MOS管V2的发热和充电回路阻抗过大而降低电流或退出快速充电模式。
上文提到的第二直流电信号是对第一PWM信号进行整流得到的，由于经过整流得到的直流电信号可能具有比较大的脉动性(纹波)，也就是还存在小小的波峰波谷，因此需要对其进行滤波，这样的话经过滤波后得到的信号波形比较平滑，电压的质量更高。
可选地，在一些实施例中，处理电路630进一步用于：对所述第二直流电信号进行滤波，以获取滤波后的所述第二直流电信号；将滤波后的第二直流电信号与至少两路PWM信号中的剩余PWM信号进行叠加和整流，以获取第一直流电信号。
本申请实施例中，在处理电路630对第一PWM信号进行整流得到第二直流电信号后，由于第二直流电信号中可能会夹杂着一些其它频率的信号，因此可以对第二直电流信号进行滤波以得到平稳的直流电信号。进一步地，处理电路630可以将滤波后的第二直流电信号与至少两路PWM信号中剩余PWM信号进行叠加和整流，从而获取第一直流电信号。
本申请实施例中的对第二直流电信号进行滤波的可以为滤波电容，也可以为一些具有滤波作用的滤波电路，本申请对次不做具体限定，只要能够滤除第二直流电信号中的纹波使得第二直流电信号的波形平滑的滤波器或滤波电路均可应用于本申请实施例。
由于信号的叠加是直流电信号和PWM信号的叠加或者是PWM信号与PWM信号的叠加，因此，对于直流电信号与PWM信号的叠加，可以是对叠加后的PWM信号进行整流后再与PWM信号叠加，也可以是对未叠加之前的PWM信号先进行整流再与叠加后的PWM信号进行叠加。
可选地，在一些实施中，处理电路630进一步用于：将直流电信号和至少两路PWM信号中的其中一路PWM信号进行叠加，以获取第一PWM信号；对至少两路PWM信号中的剩余PWM信号进行整流，以获取第三直流电信号，并将第三直流电信号与第一PWM信号进行叠加和整流，以获取第一直流电信号。
本申请实施例中，处理电路630可以先将适配器通过第一接口610输入的直流电信号和基于MCU通过第二接口620输入的至少两路PWM信号中的其中一路PWM信号进行叠加，以获取第一PWM信号，再对至少两路PWM信号中的剩余PWM信号进行整流，得到第三直流电信号，并将第三直流电信号与第一PWM信号进行叠加和整流，得到第一直流电信号。本申请实施例中的第一PWM信号为通过第一接口610输入的直流电信号与至少两路PWM信号中的其中一路PWM信号叠加后得到的，因此，也可以将叠加后的PWM信号与至少两路PWM信号的剩余PWM信号经过处理电路630整流后得到的第三直流电信号进行叠加和整流，从而获取第一直流电信号。
如图8所示为本申请实施例提供的一个快速通路的示意图，从图中可以看出，适配器输入的直流电信号与基于MCU输入的至少两路PWM信号中的其中一路PWM信号在m点处叠加，得到第一PWM信号，至少两路PWM信号中的剩余PWM信号经过第三整流器D4的整流再与第一PWM信号在p点处叠加并经过D2的整流后可以得到第一直流电信号。
具体地，对于m点来说，适配器输入的直流电信号与MCU通过电容C5的PWM信号在m点叠加，此时m点的电压Vm＝(Vbus-Vd)+Vclk，之后与经过二极管D4整流的PWM信号在p点叠加，此时p点的电压Vp＝(Vbus-3Vd)+2Vclk，叠加后的PWM信号经过二极管D2的整流，得到第一直流电信号，此时q点的电压为Vq＝(Vbus-4Vd)+2Vclk。
例如，适配器输出的电压为5V，MCU输出的信号电压为4V，二极管的电压为0.2V，则MOS管栅极电压为Vo＝(Vbus-2Vd)+Vclk＝5-0.4+4＝8.6V；本申请实施例中，由于增加了一路PWM信号电压，如图8所示，此时则MOS管V1和MOS管V2的栅极电压VG＝Vo＝(Vbus-4Vd)+2Vclk＝5-0.8+8＝12.2V，MOS管V1和MOS管V2的栅极电压可以增加3.6V。
可选地，在一些实施例中，处理电路630进一步用于：对第三直流电信号进行滤波，以获取滤波后的第三直流电信号；将滤波后的所述第三直流电信号与第一PWM信号进行叠加和整流，以获取第一直流电信号。
本申请实施例中，在处理电路630对至少两路PWM信号中的剩余PWM信号进行整流后所获取的第三直流电信号中，可能会夹杂一些其它频率的信号，因此可以对第三直流电信号进行滤波。在对第三直流电信号滤波后，处理电路630可以将滤波后的第三直流电信号与第一PWM信号进行叠加和整流以获取第一直流电信号。
本申请实施例中的对第三直流电信号进行滤波的可以为滤波电容，也可以为一些具有滤波作用的滤波电路，本申请对次不做具体限定，只要能够滤除第三直流电信号中的纹波使得第三直流电信号的波形平滑的滤波器或滤波电路均可应用于本申请实施例。
当然，也可以对适配器通过第一接口输入的直流电信号进行滤波。可选地，在一些实施例中，处理电路630进一步用于：对适配器通过第一接口输入的直流电信号进行滤波。
本申请实施例中的对适配器通过第一接口610输入的直流电信号进行滤波的可以为滤波电容，也可以为一些具有滤波作用的滤波电路，本申请对次不做具体限定，只要能够滤除通过第一接口输入的直流电信号中的纹波使得直流电信号的波形平滑的滤波器或滤波电路均可应用于本申请实施例。
可选地，在一些实施例中，如图9所示，处理电路630可以包括第一电容C5、电容C1、二极管D4以及二极管D2。
电容C5，所述电容C5的一端与所述第二接口连接；
电容C1，所述电容C1的一端与所述第二接口连接；
二极管D4，所述二极管D4的正极分别与所述第一接口和所述电容C5的另一端连接，所述二极管D4的负极与所述电容C1的另一端连接，用于对所述第一PWM信号进行整流，以获取所述第二直流电信号；
二极管D2，所述二极管D2的正极分别与所述二极管D4的负极和所述电容C1的另一端连接，所述二极管D2的负极与MOS管V1和MOS管V2的栅极连接，用于对所述第二直流电信号与所述MCU输出的剩余PWM信号叠加后的信号进行整流，以获取所述第一直流电信号；
其中，所述电容C5用于对所述至少两路PWM信号的其中一路PWM信号在被叠加之前进行去除直流电信号的处理，所述电容C1用于对所述至少两路PWM信号中的剩余PWM信号在被叠加之前进行去除直流电信号的处理。
本申请实施例中的电容C5、电容C1、二极管D4以及二极管D2可以是图7中的电容C5、电容C1、二极管D4以及二极管D2。为了简洁，具体的过程可以参见图7，本申请不再详细说明。
本申请实施例中，由于基于MCU通过第二接口输入的PWM信号有可能包括直流电信号，因此可以利用电容C5和电容C1对通过第二接口输出的PWM信号进行去直流电信号的处理。
可选地，在一些实施例中，如图10所示，处理电路630还可以包括二极管D1和二极管D5。
二极管D1，所述二极管D1的正极和负极分别与所述第一接口和所述电容C5的另一端连接；
二极管D5，所述二极管D5的正极与所述二极管D4的负极连接，所述二极管D5的负极和所述电容C1的另一端连接。
本申请实施例中的二极管D1和二极管D5可以是图7中的二极管D1和二极管D5。为了简洁，具体的过程可以参见图7，本申请不再详细说明。
可选地，在一些实施例中，如图11所示，处理电路630还可以包括电容C3和电容C6。
电容C3，所述电容C3的一端与所述第一接口连接，所述电容C3的另一端接地，用于对从所述第一接口输出的直流电信号进行滤波；
电容C6，所述电容C6的一端与二极管D4的负极连接，所述电容C6的另一端接地，用于对从所述二极管D4输出的所述第二直流电信号进行滤波。
本申请实施例中，适配器通过第一接口输入的直流电信号可能带有杂波，因此可以通过电容C3对直流电信号进行滤波处理，类似地，通过第一接口输入的直流电信号与MCU通过第二接口输入的PWM信号中的其中一路PWM信号经过叠加以及整流后的信号可能带有杂波，因此，可以通过电容C6对其进行滤波。
由于信号的叠加是直流电信号和PWM信号的叠加或者是PWM信号与PWM信号的叠加，因此，对于直流电信号与PWM信号的叠加，可以是对叠加后的PWM信号进行整流后再与PWM信号叠加，也可以是对未叠加之前的PWM信号先进行整流再与叠加后的PWM信号进行叠加。
可选地，在一些实施例中，如图12所示，处理电路630可以包括电容C5、电容C1、二极管D4以及二极管D2。
电容C5，所述电容C5的一端与所述第二接口连接；
电容C1，所述电容C1的一端与所述第二接口连接；
二极管D4，所述二极管D4的正极与所述电容C1的另一端连接，所述二极管的负极与所述第一接口和所述电容C5的另一端连接，用于对所述至少两路PWM信号中的剩余PWM信号进行整流，以获取所述第三直流电信号；
二极管D2，所述二极管D2的正极与所述二极管D4的负极、所述第一接口以及所述电容C5的另一端连接，所述二极管D2的负极与MOS管V1和MOS管V2的栅极连接，用于对所述第三直流电信号与所述第一PWM信号叠加后的信号进行整流，以获取所述第一直流电信号；
其中，所述电容C5用于对所述至少两路PWM信号的其中一路PWM信号在被叠加之前进行去除直流电信号的处理，所述电容C1用于对所述至少两路PWM信号中的剩余PWM信号在被叠加之前进行去除直流电信号的处理。
本申请实施例中的电容C5、电容C1、二极管D4以及二极管D2可以是图8中的电容C5、电容C1、二极管D4以及二极管D2。为了简洁，具体的过程可以参见图8，本申请不再详细说明。
可选地，在一些实施例中，如图13所示，处理电路630还可以包括二极管D1和二极管D5。
二极管D1，所述二极管D1的正极和负极分别与所述第一接口和所述电容C5的另一端连接；
二极管D5，所述二极管D5的正极与所述电容C5的另一端和所述二极管D1的负极连接，所述二极管D5的负极和所述二极管D4的负极连接。
本申请实施例中的二极管D1和二极管D5可以是图8中的二极管D1和二极管D5。为了简洁，具体的过程可以参见图8，本申请不再详细说明。
可选地，在一些实施例中，如图14所示，处理电路630还可以包括电容C3和电容C6。
电容C3，所述电容C3的一端与所述第一接口连接，所述电容C3的另一端接地，用于对从所述第一接口输出的直流电信号进行滤波；
电容C6，所述电容C6的一端与二极管D4的负极连接，所述电容C6的另一端接地，用于对从所述二极管D4输出的第三直流电信号进行滤波。
本申请实施例中，适配器通过第一接口输入的直流电信号可能带有杂波，因此可以通过电容C3对直流电信号进行滤波处理，类似地，MCU通过第二接口输入PWM信号可能带有杂波，因此，可以通过电容C6对其进行滤波。
可选地，在一些实施例中，本申请实施例中的第二接口可以接收多路PWM信号。以接收三路PWM信号为例，如图15所示为本申请实施例提供的一种快充通路的示意性结构图，适配器输出的直流电信号与经过电容C5的PWM信号在m点叠加得到第一PWM信号，第一PWM信号经过D4的整流输出第二直流电信号，第二直流电信号与经过电容C1的PWM信号在p点处叠加得到的PWM信号，再与经过D6的整流得到的直流电信号在s点处进行叠加并经过D2的整流可以得到第一直流电信号。
本申请实施中，处理电路630对于通过第二接口接收的多个PWM信号可以与其它直流电信号先进行叠加再整流，也可以先整流后再与其它PWM信号进行叠加，本申请对此不作具体限定。
本申请实施例中，也可以存在多个二极管D1或二极管D5，其中二极管D1和二极管D5可以为同一个类型的二极管，也可以为不同类型的二极管。
具体地，如图15所示，对于图中的p点，以二极管D5为例，D5可以位于如图15所示的位置，以避免由于p点电压的增加而导致的电压反压的现象。本申请实施例中的二极管D5也可以位于二极管D4之前，只要能够避免由于p点电压的增加而导致的电压反压的现象均可应用本申请。
本申请实施例中也可以存在多个二极管，如图15所示，本申请实施例中，在节点p和节点s之间也可以存在二极管D7，以避免由于s点的电压增加而导致的电压反压现象。应理解，本申请实施例中MCU通过第二接口可以输出多路PWM信号，二极管也可以位于该多路PWM信号中的每一路PWM信号在每一次叠加之后且未 进行下一次叠加之前所在的电路上。
本申请实施例中，第一接口610可以与二极管D1连接，由于适配器通过第一接口输入的直流电信号和基于MCU通过第二接口输入的至少两路PWM信号中的其中一路PWM信号进行叠加后，叠加后的信号电压大于适配器通过第一接口输入的直流电信号电压，可能会产生反压现象，因此二极管D1能够避免由于适配器输出的直流电信号与基于MCU输出的PWM信号的叠加而导致的反压现象。类似地，二极管D5能够避免由于p点电压的增加而导致的反压现象。
前面讲述了基于MCU通过第二接口620输入的PWM信号可以是至少两路PWM信号，其中，至少两路PWM信号可以为相同的信号。本申请实施例中，该至少两路PWM信号也可以为不同的信号。但应理解，在至少两路PWM信号为不同的PWM信号时，其频率相同，但高电平的带宽的长度和高电平的上升沿的时间是不同的。
如图16所示，为本申请实施例提供的一种快速通路的示意图，从图中可以看出，适配器输出的直流电信号与基于MCU输出的多个PWM信号在m点处叠加，得到第一PWM信号，第一PWM信号经过二极管D2的整流得到第一直流电信号。
在这种情况下，m点的电压为Vm＝(Vbus-Vd)+Vclk1+Vclk2，再经过二极管D2的整流到达n点，此时n点的电压Vn＝(Vbus-2Vd)+Vclk1+Vclk2，即MOS管V1和MOS管V2的栅极电压为VG＝Vo＝Vn＝(Vbus-2Vd)+Vclk1+Vclk2。
一般情况下，二极管的压降比较小，一般为0.1V～0.2V，而MCU输出的信号电压Vclk一般为4V左右。例如，在一种实施例中，适配器输出的电压为5V，MCU输出的信号电压为4V，二极管的电压为0.2V，则o点的电压，即MOS管V1和MOS管V2的栅极电压VG＝Vo＝(Vbus-2Vd)+Vclk＝5-0.4+4＝8.6V；另一种实施例中，由于增加了一路PWM信号电压，此时则MOS管栅极电压VG＝Vo＝(Vbus-2Vd)+Vclk1+Vclk2＝5-0.4+8＝12.6V。
相比于第一种实施例，MOS管V1和MOS管V2的栅极电压增加了V增加＝Vclk2＝4V，因此，本申请实施例能够提高MOS管V1和MOS管V2的栅极电压，从而可以减少MOS管V1和MOS管V2导通时漏极和源极之间的阻抗，进一步能够避免MOS管V1和MOS管V2的发热和充电回路阻抗过大而降低电流或退出快速充电模式。
本申请实施例中，MCU的两个引脚输出的PWM信号的电压Vclk1和Vclk2的频率相同，在这种情况下，这两个PWM信号电压的叠加能够实现MOS管V1和MOS管V2的栅极电压的提高。
本申请实施例中，由于电容组的并联可能会影响MCU控制输出的信号电压，因此可以在原有的信号电压Vclk1输入一段时间后，MCU的引脚再输出信号电压Vclk2，此时对于m点来说，相当于新加入了一个支路的信号电压，不会影响原有的信号电压Vclk1。
可选地，在一些实施例中，如图17所示，新增加的PWM信号2中的上升沿的时间大于原有的PWM信号1中的上升沿的时间。
可以理解的是，由于基于MCU输出的新增加的PWM信号的上升沿的时间晚于原有PWM信号的上升沿的时间，同时需要保证这两个的PWM信号的频率相同，因此，可以控制新加入的PWM信号的高电平的宽度小于原有PWM信号的高电平的宽度。
例如，如图17所示，PWM信号1为驱动电路中原有的信号，PWM信号2为新增加的信号。从图中可以看出，PWM信号1和PWM信号2的频率相同，即两个信号的周期相同，均是从图中的t1到t4。对于PWM信号1来说，在t2时间从低电平变为高电平，而PWM信号2是在t3时间从低电平变为高电平，也就是说，在PWM信号1从低电平变为高电平持续了(t3-t2)时间后，PWM信号2才从低电平变为高电平，此时由于PWM信号1已经基本处于完全稳定状态，因此PWM信号2的加入不会影响PWM信号1。
本申请实施例提供的驱动电路600，通过将适配器通过第一接口610输入的直流电信号与基于MCU通过第二接口620输入的至少两路PWM信号叠加后经过整流处理，输出至电子设备内部的充电通路中的MOS管的栅极，由于基于MCU通过第二接口输入至驱动电路中的是至少两路PWM信号，能够提高驱动电路所产生的驱动电压，从而增大了MOS管V1和MOS管V2的栅极和源极之间的电压，因此能够避免因为MOS管V1和MOS管V2的栅极和源极之间的电压过低而导致的充电效率降低，同时也可以避免由于MOS管导通时的阻抗过大而导致的快速降低快充电流或退出快速充电模式的问题。
图18是本申请实施例的一种电子设备1800的示意性框图，该电子设备可以包括第一接口1810，微控制单元MCU1820，第二接口1830，处理电路1840以及场效应管MOS管1850。
第一接口1810，与外部电源提供装置连接，用于接收所述外部电源提供装置输入的直流电信号；
MCU1820；
第二接口1830，与所述MCU1820连接，用于接收所述MCU1820输入的至少两路脉冲宽度调制PWM信号；
MOS管1850；
处理电路1840，分别与所述第一接口1810和所述第二接口1830连接，用于将所述直流电信号和所述至少两路PWM信号进行叠加和整流，以获取第一直流电信号，并将所述第一直流电信号输出至所述MOS管的栅极，以使得所述MOS管栅极的电压大于第一阈值。
该处理电路1840可以为上述处理电路600中的任何一种电路，为了简洁，在此不再赘述。
可选地，在一些实施例中，处理电路1840进一步用于：将所述直流电信号和所述至少两路PWM信号中的其中一路PWM信号进行叠加，以获取第一PWM信号，并对所述第一PWM信号进行整流，以获取第二直流电信号；将所述第二直流电信号与所述至少两路PWM信号中的剩余PWM信号进行叠加和整流，以获取所述第一直流电信号。
可选地，在一些实施例中，处理电路1840进一步用于：对所述第二直流电信号进行滤波，以获取滤波后的所述第二直流电信号；将所述滤波后的所述第二直流电信号与所述至少两路PWM信号中的剩余PWM信号进行叠加和整流，以获取所述第一直流电信号。
可选地，在一些实施例中处理电路1840进一步用于：将所述直流电信号和所述至少两路PWM信号中的其中一路PWM信号进行叠加，以获取第一PWM信号；对所述至少两路PWM信号中的剩余PWM信号进行整流，以获取第三直流电信号，并将所述第三直流电信号与所述第一PWM信号进行叠加和整流，以获取所述第一直流电信号。
可选地，在一些实施例中，处理电路1840进一步用于：对所述第三直流电信号进行滤波，以获取滤波后的所述第三直流电信号；将所述滤波后的所述第三直流电信号与所述第一PWM信号进行叠加和整流，以获取所述第一直流电信号。
可选地，在一些实施例中，处理电路1840进一步用于：对所述外部电源提供装置通过所述第一接口输入的直流电信号进行滤波。
可选地，在一些实施例中，处理电路1840包括：电容C5，所述电容C5的一端与所述第二接口连接；电容C1，所述电容C1的一端与所述第二接口连接；二极管D4，所述二极管D4的正极分别与所述第一接口和所述电容C5的另一端连接，所述二极管D4的负极与所述电容C1的另一端连接，用于对所述第一PWM信号进行整流，以获取所述第二直流电信号；二极管D2，所述二极管D2的正极分别与所述二极管D4的负极和所述电容C1的另一端连接，所述二极管D2的负极与MOS管V1和MOS管V2的栅极连接，用于对所述第二直流电信号与所述MCU输出的剩余PWM信号叠加后的信号进行整流，以获取所述第一直流电信号；其中，所述电容C5用于对所述至少两路PWM信号的其中一路PWM信号在被叠加之前进行去除直流电信号的处理，所述电容C1用于对所述至少两路PWM信号中的剩余PWM信号在被叠加之前进行去除直流电信号的处理。
可选地，在一些实施例中，处理电路1840还包括：二极管D1，所述二极管D1的正极和负极分别与所述第一接口和所述电容C5的另一端连接；二极管D5，所述二极管D5的正极与所述二极管D4的负极连接，所述二极管D5的负极和所述电容C1的另一端连接。
可选地，在一些实施例中，处理电路1840还包括：电容C3，所述电容C3的一端与所述第一接口连接，所述电容C3的另一端接地，用于对从所述第一接口输出的直流电信号进行滤波；电容C6，所述电容C6的一端与二极管D4的负极连接，所述电容C6的另一端接地，用于对从所述二极管D4输出的所述第二直流电信号进行滤波。
可选地，在一些实施例中，处理电路1840包括：电容C5，所述电容C5的一端与所述第二接口连接；电容C1，所述电容C1的一端与所述第二接口连接；二极管D4，所述二极管D4的正极与所述电容C1的另一端连接，所述二极管的负极与所述第一接口和所述电容C5的另一端连接，用于对所述至少两路PWM信号中的剩余PWM信号进行整流，以获取所述第三直流电信号；二极管D2，所述二极管D2的正极与所述二极管D4的负极、所述第一接口以及所述电容C5的另一端连接，所述二极管D2的负极与MOS管V1和MOS管V2的栅极连接，用于对所述第三直流电信号与所述第一PWM信号叠加后的信号进行整流，以获取所述第一直流电信号；其中，所述电容C5用于对所述至少两路PWM信号的其中一路PWM信号在被叠加之前进行去除直流电信号的处理，所述电容C1用于对所述至少两路PWM信号中的剩余PWM信号在被叠加之前进行去除直流电信号的处理。
可选地，在一些实施例中，处理电路1840还包括：二极管D1，所述二极管D1的正极和负极分别与所述第 一接口和所述电容C5的另一端连接；二极管D5，所述二极管D5的正极与所述电容C5的另一端和所述二极管D1的负极连接，所述二极管D5的负极和所述二极管D4的负极连接。
可选地，在一些实施例中，处理电路1840还包括：电容C3，所述电容C3的一端与所述第一接口连接，所述电容C3的另一端接地，用于对从所述第一接口输出的直流电信号进行滤波；电容C6，所述电容C6的一端与二极管D4的负极连接，所述电容C6的另一端接地，用于对从所述二极管D4输出的第三直流电信号进行滤波。
上文结合图1-图18，详细描述了本申请实施例的装置实施例，下面结合图19-图23，描述本申请实施例的方法实施例，方法实施例与装置实施例相互对应，因此未详细描述的部分可参见前面各部分装置实施例。
如图19所示为本申请实施例提供的一种控制充电的方法1900，该方法1900可以包括步骤1910-1920。
1910，将外部电源提供装置通过所述第一接口输入的直流电信号和基于所述MCU通过所述第二接口输入的至少两路PWM信号进行叠加和整流，以获取第一直流电信号。
1920，将所述第一直流电信号输出至所述MOS管的栅极，以使得所述MOS管的栅极的电压大于第一阈值。
可选地，在一些实施中，所述将外部电源提供装置通过第一接口输出的直流电信号和基于MCU通过第二接口输出的至少两路PWM信号进行叠加和整流，以获取第一直流电信号信号，包括：将所述外部电源提供装置通过所述第一接口输入的直流电信号和所述至少两路PWM信号中的其中一路PWM信号进行叠加，以获取第一PWM信号，并对所述第一PWM信号进行整流，以获取第二直流电信号；将所述第二直流电信号与所述至少两路PWM信号中的剩余PWM信号进行叠加和整流，以获取所述第一直流电信号。
可选地，在一些实施中，所述方法1900还包括：对所述第二直流电信号进行滤波，以获取滤波后的所述第二直流电信号；所述将所述第二直流电信号与所述至少两路PWM信号中的剩余PWM信号进行叠加和整流，以获取第一直流电信号，包括：将所述滤波后的所述第二直流电信号与所述至少两路PWM信号中的剩余PWM信号进行叠加和整流，以获取所述第一直流电信号。
可选地，在一些实施中，所述将外部电源提供装置通过第一接口输出的直流电信号和基于MCU通过第二接口输入的至少两路PWM信号进行叠加和整流，以获取第一直流电信号，包括：对所述外部电源提供装置通过第一接口输入的直流电信号和所述至少两路PWM信号中的其中一路PWM信号进行叠加，以获取第一PWM信号；对所述至少两路PWM信号中的剩余PWM信号进行整流，以获取第三直流电信号，并将所述第三直流电信号与所述第一PWM信号进行叠加和整流，以获取所述第一直流电信号。
可选地，在一些实施中，所述方法1900还包括：对所述第三直流电信号进行滤波，以获取滤波后的所述第三直流电信号；所述将所述第三直流电信号与所述第一PWM信号进行叠加和整流，以获取所述第一直流电信号，包括：将所述滤波后的所述第三直流电信号与所述第一PWM信号进行叠加和整流，以获取所述第一直流电信号。
可选地，在一些实施中，如图20所示，所述方法1900还可以包括步骤1930。
1930，对所述电源提供装置通过所述第一接口输入的直流电信号进行滤波。
可选地，在一些实施中，如图21所示，所述方法1900还包括步骤1940。
1940，分别对在所述至少两个PWM信号被叠加之前进行去除直流电信号的处理。
本申请实施例还提供了一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令设置为执行上述方法1900的任何一种方法。
本申请实施例还提供了一种计算机程序产品，所述计算机程序产品包括存储在计算机可读存储介质上的计算机程序，所述计算机程序包括程序指令，当所述程序指令被计算机执行时，使所述计算机执行上述方法1900中的任何一种方法。
本申请实施例的方案可以应用在有线充电过程中。
下面结合图22-图23，对本申请实施例应用的有线充电过程进行描述。
图22是本申请实施例提供的一种充电系统的示意性结构图。该充电系统包括电源提供装置10、电池管理电路20和电池30。电池管理电路20可用于对电池30进行管理。
作为一个示例，电池管理电路20可以对电池30的充电过程进行管理，比如选择充电通道、控制充电电压和/或充电电流等；作为另一个示例，电池管理电路20可以对电池30的电芯进行管理，如均衡电池30中的电芯的电压等。
电池管理电路20可以包括第一充电通道21和通信控制电路23。
第一充电通道21可用于接收电源提供装置10提供的充电电压和/或充电电流，并将充电电压和/或充电电流加载在电池30的两端，为电池30进行充电。
第一充电通道21例如可以是一根导线，也可以在第一充电通道21上设置一些与充电电压和/或充电电流变换无关的其他电路器件。例如，电源管理电路20包括第一充电通道21和第二充电通道，第一充电通道21上可以设置用于充电通道间切换的开关器件(具体参见图23的描述)。
本申请实施例中，对电源提供装置10的类型不做具体限定。例如，该电源提供装置10可以是适配器和移动电源(power bank)等专门用于充电的设备，也可以是电脑等能够提供电源和数据服务的其他设备。
第一充电通道21可以为直充通道，可以将电源提供装置10提供的充电电压和/或充电电流直接加载在电池30的两端。为了实现直充充电方式，本申请实施例在电池管理电路20中引入了具有通信功能的控制电路，即通信控制电路23。该通信控制电路23可以在直充过程中与电源提供装置10保持通信，以形成闭环反馈机制，使得电源提供装置10能够实时获知电池的状态，从而不断调整向第一充电通道注入的充电电压和/或充电电流，以保证电源提供装置10提供的充电电压和/或充电电流的大小与电池30当前所处的充电阶段相匹配。
例如，该通信控制电路23可以在电池30的电压达到恒流阶段对应的充电截止电压时，与电源提供装置10进行通信，使得电源提供装置10对电池30的充电过程从恒流充电转换为恒压充电。又例如，该通信控制电路23可以在电池30的充电电流达到恒压阶段对应的充电截止电流时，与电源提供装置10进行通信，使得电源提供装置10对电池30的充电过程从恒压充电转换为恒流充电。其中，本申请实施例中的通信控制电路23可以为上述提到的驱动电路。
本申请实施例提供的电池管理电路能够对电池进行直充，换句话说，本申请实施例提供的电池管理电路是支持直充架构的电池管理电路，在直充架构中，直充通道上无需设置变换电路，从而能够降低待充电设备在充电过程的发热量。可选地，在一些实施例中，如图23所示，电池管理电路20还可包括第二充电通道24。第二充电通道24上设置有升压电路25。在电源提供装置10通过第二充电通道24为电池30充电的过程中，升压电路25可用于接收电源提供装置10提供的初始电压，将初始电压升压至目标电压，并基于目标电压为电池30充电，其中初始电压小于电池30的总电压，目标电压大于电池30的总电压；通信控制电路23还可用于控制第一充电通道21和第二充电通道24之间的切换。
假设该电池30包括多节电芯，该第二充电通道24能够兼容普通的电源提供装置为该电池30进行充电，解决了普通电源提供装置无法为多节电池进行充电的问题。
对于包含多节电芯的电池30来说，电池管理电路20还可以包括均衡电路22，参见上文的描述，该均衡电路22可用于在电池的充电过程和/或放电过程中均衡多节电芯的电压。
本申请实施例对升压电路25的具体形式不作限定。例如，可以采用Boost升压电路，还可以采用电荷泵进行升压。可选地，在一些实施例中，第二充电通道24可以采用传统的充电通道设计方式，即在第二充电通道24上设置变换电路(如充电IC)。该变换电路可以对电池30的充电过程进行恒压、恒流控制，并根据实际需要对电源提供装置10提供的初始电压进行调整，如升压或降压。本申请实施例可以利用该变换电路的升压功能，将电源提供装置10提供的初始电压升压至目标电压。
通信控制电路23可以通过开关器件实现第一充电通道21和第二充电通道24之间的切换。具体地，如图23所示，第一充电通道21上可以设置有开关管Q5，当通信控制电路23控制开关管Q5导通时，第一充电通道21工作，对电池30进行直充；当通信控制电路23控制开关管Q5关断时，第二充电通道24工作，采用第二充电通道24对电池30进行充电。其中，本申请实施例中的开关管Q5可以为MOS管，也可以为开关。
在另外一些实施例中，也可在第二充电通道24上设置用于降压的电路或器件，当电源提供装置提供的电压高于电池30的需求电压时，可进行降压处理。本申请实施例，对第二充电通道24包含的电路或模块不进行限制。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其他任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本发明实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(digital subscriber line，DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质(例如，软盘、硬盘、磁带)、光介质(例如数字视 频光盘(digital video disc，DVD))、或者半导体介质(例如固态硬盘(solid state disk，SSD))等。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
当用于本申请中时，虽然术语“第一”、“第二”等可能会在本申请中使用以描述各设备，但这些设备不应受到这些术语的限制。这些术语仅用于将一个设备与另一个设备区别开。比如，在不改变描述的含义的情况下，第一设备可以叫做第二设备，并且同样地，第二设备可以叫做第一设备，只要所有出现的“第一设备”一致重命名并且所有出现的“第二设备”一致重命名即可。第一设备和第二设备都是设备，但可以不是相同的设备。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (32)

  1. 一种驱动电路，其特征在于，所述驱动电路应用于电子设备，所述电子设备还包括场效应管MOS管和微控制单元MCU，
    所述驱动电路包括：
    第一接口，与外部电源提供装置连接，用于接收所述外部电源提供装置输入的直流电信号；
    第二接口，与所述MCU连接，用于接收所述MCU输入的至少两路脉冲宽度调制PWM信号；
    处理电路，分别与所述第一接口和所述第二接口连接，用于将所述直流电信号和所述至少两路PWM信号进行叠加和整流，以获取第一直流电信号，并将所述第一直流电信号输出至所述MOS管的栅极，以使得所述MOS管栅极的电压大于第一阈值。
  2. 根据权利要求1所述的驱动电路，其特征在于，所述处理电路进一步用于：
    将所述直流电信号和所述至少两路PWM信号中的其中一路PWM信号进行叠加，以获取第一PWM信号，并对所述第一PWM信号进行整流，以获取第二直流电信号；
    将所述第二直流电信号与所述至少两路PWM信号中的剩余PWM信号进行叠加和整流，以获取所述第一直流电信号。
  3. 根据权利要求2所述的驱动电路，其特征在于，所述处理电路进一步用于：
    对所述第二直流电信号进行滤波，以获取滤波后的所述第二直流电信号；
    将所述滤波后的所述第二直流电信号与所述至少两路PWM信号中的剩余PWM信号进行叠加和整流，以获取所述第一直流电信号。
  4. 根据权利要求1所述的驱动电路，其特征在于，所述处理电路进一步用于：
    将所述直流电信号和所述至少两路PWM信号中的其中一路PWM信号进行叠加，以获取第一PWM信号；
    对所述至少两路PWM信号中的剩余PWM信号进行整流，以获取第三直流电信号，并将所述第三直流电信号与所述第一PWM信号进行叠加和整流，以获取所述第一直流电信号。
  5. 根据权利要求4所述的驱动电路，其特征在于，所述处理电路进一步用于：
    对所述第三直流电信号进行滤波，以获取滤波后的所述第三直流电信号；
    将所述滤波后的所述第三直流电信号与所述第一PWM信号进行叠加和整流，以获取所述第一直流电信号。
  6. 根据权利要求1至5中任一项所述的驱动电路，其特征在于，所述处理电路进一步用于：
    对所述外部电源提供装置通过所述第一接口输入的直流电信号进行滤波。
  7. 根据权利要求2或3所述的驱动电路，其特征在于，所述处理电路包括：
    电容C5，所述电容C5的一端与所述第二接口连接；
    电容C1，所述电容C1的一端与所述第二接口连接；
    二极管D4，所述二极管D4的正极分别与所述第一接口和所述电容C5的另一端连接，所述二极管D4的负极与所述电容C1的另一端连接，用于对所述第一PWM信号进行整流，以获取所述第二直流电信号；
    二极管D2，所述二极管D2的正极分别与所述二极管D4的负极和所述电容C1的另一端连接，所述二极管D2的负极与MOS管V1和MOS管V2的栅极连接，用于对所述第二直流电信号与所述MCU输出的剩余PWM信号叠加后的信号进行整流，以获取所述第一直流电信号；
    其中，所述电容C5用于对所述至少两路PWM信号的其中一路PWM信号在被叠加之前进行去除直流电信号的处理，所述电容C1用于对所述至少两路PWM信号中的剩余PWM信号在被叠加之前进行去除直流电信号的处理。
  8. 根据权利要求7所述的驱动电路，其特征在于，所述处理电路还包括：
    二极管D1，所述二极管D1的正极和负极分别与所述第一接口和所述电容C5的另一端连接；
    二极管D5，所述二极管D5的正极与所述二极管D4的负极连接，所述二极管D5的负极和所述电容C1的另一端连接。
  9. 根据权利要求7或8所述的驱动电路，其特征在于，所述处理电路还包括：
    电容C3，所述电容C3的一端与所述第一接口连接，所述电容C3的另一端接地，用于对从所述第一接口输出的直流电信号进行滤波；
    电容C6，所述电容C6的一端与二极管D4的负极连接，所述电容C6的另一端接地，用于对从所述二极管D4输出的所述第二直流电信号进行滤波。
  10. 根据权利要求4或5所述的驱动电路，其特征在于，所述处理电路包括：
    电容C5，所述电容C5的一端与所述第二接口连接；
    电容C1，所述电容C1的一端与所述第二接口连接；
    二极管D4，所述二极管D4的正极与所述电容C1的另一端连接，所述二极管D4的负极与所述第一接口和所述电容C5的另一端连接，用于对所述至少两路PWM信号中的剩余PWM信号进行整流，以获取所述第三直流电信号；
    二极管D2，所述二极管D2的正极与所述二极管D4的负极、所述第一接口以及所述电容C5的另一端连接，所述二极管D2的负极与MOS管V1和MOS管V2的栅极连接，用于对所述第三直流电信号与所述第一PWM信号叠加后的信号进行整流，以获取所述第一直流电信号；
    其中，所述电容C5用于对所述至少两路PWM信号的其中一路PWM信号在被叠加之前进行去除直流电信号的处理，所述电容C1用于对所述至少两路PWM信号中的剩余PWM信号在被叠加之前进行去除直流电信号的处理。
  11. 根据权利要求10所述的驱动电路，其特征在于，所述处理电路还包括：
    二极管D1，所述二极管D1的正极和负极分别与所述第一接口和所述电容C5的另一端连接；
    二极管D5，所述二极管D5的正极与所述电容C5的另一端和所述二极管D1的负极连接，所述二极管D5的负极和所述二极管D4的负极连接。
  12. 根据权利要求10或11所述的驱动电路，其特征在于，所述处理电路还包括：
    电容C3，所述电容C3的一端与所述第一接口连接，所述电容C3的另一端接地，用于对从所述第一接口输出的直流电信号进行滤波；
    电容C6，所述电容C6的一端与二极管D4的负极连接，所述电容C6的另一端接地，用于对从所述二极管D4输出的第三直流电信号进行滤波。
  13. 一种电子设备，其特征在于，包括：
    第一接口，与外部电源提供装置连接，用于接收所述外部电源提供装置输入的直流电信号；
    微控制单元MCU；
    第二接口，与所述MCU连接，用于接收所述MCU输入的至少两路脉冲宽度调制PWM信号；
    场效应管MOS管；
    处理电路，分别与所述第一接口和所述第二接口连接，用于将所述直流电信号和所述至少两路PWM信号进行叠加和整流，以获取第一直流电信号，并将所述第一直流电信号输出至所述MOS管的栅极，以使得所述MOS管栅极的电压大于第一阈值。
  14. 根据权利要求13所述的电子设备，其特征在于，所述处理电路进一步用于：
    将所述直流电信号和所述至少两路PWM信号中的其中一路PWM信号进行叠加，以获取第一PWM信号，并对所述第一PWM信号进行整流，以获取第二直流电信号；
    将所述第二直流电信号与所述至少两路PWM信号中的剩余PWM信号进行叠加和整流，以获取所述第一直流电信号。
  15. 根据权利要求14所述的电子设备，其特征在于，所述处理电路进一步用于：
    对所述第二直流电信号进行滤波，以获取滤波后的所述第二直流电信号；
    将所述滤波后的所述第二直流电信号与所述至少两路PWM信号中的剩余PWM信号进行叠加和整流，以获取所述第一直流电信号。
  16. 根据权利要求13所述的电子设备，其特征在于，所述处理电路进一步用于：
    将所述直流电信号和所述至少两路PWM信号中的其中一路PWM信号进行叠加，以获取第一PWM信号；
    对所述至少两路PWM信号中的剩余PWM信号进行整流，以获取第三直流电信号，并将所述第三直流电信号与所述第一PWM信号进行叠加和整流，以获取所述第一直流电信号。
  17. 根据权利要求16所述的电子设备，其特征在于，所述处理电路进一步用于：
    对所述第三直流电信号进行滤波，以获取滤波后的所述第三直流电信号；
    将所述滤波后的所述第三直流电信号与所述第一PWM信号进行叠加和整流，以获取所述第一直流电信号。
  18. 根据权利要求13至17中任一项所述的电子设备，其特征在于，所述处理电路进一步用于：
    对所述外部电源提供装置通过所述第一接口输入的直流电信号进行滤波。
  19. 根据权利要求14或15所述的电子设备，其特征在于，所述处理电路包括：
    电容C5，所述电容C5的一端与所述第二接口连接；
    电容C1，所述电容C1的一端与所述第二接口连接；
    二极管D4，所述二极管D4的正极分别与所述第一接口和所述电容C5的另一端连接，所述二极管D4的负极与所述电容C1的另一端连接，用于对所述第一PWM信号进行整流，以获取所述第二直流电信号；
    二极管D2，所述二极管D2的正极分别与所述二极管D4的负极和所述电容C1的另一端连接，所述二极管D2的负极与MOS管V1和MOS管V2的栅极连接，用于对所述第二直流电信号与所述MCU输出的剩余PWM信号叠加后的信号进行整流，以获取所述第一直流电信号；
    其中，所述电容C5用于对所述至少两路PWM信号的其中一路PWM信号在被叠加之前进行去除直流电信号的处理，所述电容C1用于对所述至少两路PWM信号中的剩余PWM信号在被叠加之前进行去除直流电信号的处理。
  20. 根据权利要求19所述的电子设备，其特征在于，所述处理电路还包括：
    二极管D1，所述二极管D1的正极和负极分别与所述第一接口和所述电容C5的另一端连接；
    二极管D5，所述二极管D5的正极与所述二极管D4的负极连接，所述二极管D5的负极和所述电容C1的另一端连接。
  21. 根据权利要求19或20所述的电子设备，其特征在于，所述处理电路还包括：
    电容C3，所述电容C3的一端与所述第一接口连接，所述电容C3的另一端接地，用于对从所述第一接口输出的直流电信号进行滤波；
    电容C6，所述电容C6的一端与二极管D4的负极连接，所述电容C6的另一端接地，用于对从所述二极管D4输出的所述第二直流电信号进行滤波。
  22. 根据权利要求16或17所述的电子设备，其特征在于，所述处理电路包括：
    电容C5，所述电容C5的一端与所述第二接口连接；
    电容C1，所述电容C1的一端与所述第二接口连接；
    二极管D4，所述二极管D4的正极与所述电容C1的另一端连接，所述二极管的负极与所述第一接口和所述电容C5的另一端连接，用于对所述至少两路PWM信号中的剩余PWM信号进行整流，以获取所述第三直流电信号；
    二极管D2，所述二极管D2的正极与所述二极管D4的负极、所述第一接口以及所述电容C5的另一端连接，所述二极管D2的负极与MOS管V1和MOS管V2的栅极连接，用于对所述第三直流电信号与所述第一PWM信号叠加后的信号进行整流，以获取所述第一直流电信号；
    其中，所述电容C5用于对所述至少两路PWM信号的其中一路PWM信号在被叠加之前进行去除直流电信号的处理，所述电容C1用于对所述至少两路PWM信号中的剩余PWM信号在被叠加之前进行去除直流电信号的处理。
  23. 根据权利要求22所述的电子设备，其特征在于，所述处理电路还包括：
    二极管D1，所述二极管D1的正极和负极分别与所述第一接口和所述电容C5的另一端连接；
    二极管D5，所述二极管D5的正极与所述电容C5的另一端和所述二极管D1的负极连接，所述二极管D5的负极和所述二极管D4的负极连接。
  24. 根据权利要求22或23所述的电子设备，其特征在于，所述处理电路还包括：
    电容C3，所述电容C3的一端与所述第一接口连接，所述电容C3的另一端接地，用于对从所述第一接口输出的直流电信号进行滤波；
    电容C6，所述电容C6的一端与二极管D4的负极连接，所述电容C6的另一端接地，用于对从所述二极管D4输出的第三直流电信号进行滤波。
  25. 一种控制充电的方法，其特征在于，所述方法包括：
    将外部电源提供装置通过第一接口输入的直流电信号和基于MCU通过第二接口输入的至少两路PWM信号进行叠加和整流，以获取第一直流电信号；
    将所述第一直流电信号输出至MOS管的栅极，以使得所述MOS管的栅极的电压大于第一阈值。
  26. 根据权利要求25所述的方法，其特征在于，所述将外部电源提供装置通过第一接口输出的直流电信号和基于MCU通过第二接口输出的至少两路PWM信号进行叠加和整流，以获取第一直流电信号信号，包括：
    将所述外部电源提供装置通过所述第一接口输入的直流电信号和所述至少两路PWM信号中的其中一路PWM信号进行叠加，以获取第一PWM信号，并对所述第一PWM信号进行整流，以获取第二直流电信号；
    将所述第二直流电信号与所述至少两路PWM信号中的剩余PWM信号进行叠加和整流，以获取所述第一直流电信号。
  27. 根据权利要求26所述的方法，其特征在于，所述方法还包括：
    对所述第二直流电信号进行滤波，以获取滤波后的所述第二直流电信号；
    所述将所述第二直流电信号与所述至少两路PWM信号中的剩余PWM信号进行叠加和整流，以获取第一直流电信号，包括：
    将所述滤波后的所述第二直流电信号与所述至少两路PWM信号中的剩余PWM信号进行叠加和整流，以获取所述第一直流电信号。
  28. 根据权利要求25所述的方法，其特征在于，所述将外部电源提供装置通过第一接口输出的直流电信号和基于MCU通过第二接口输入的至少两路PWM信号进行叠加和整流，以获取第一直流电信号，包括：
    对所述外部电源提供装置通过第一接口输入的直流电信号和所述至少两路PWM信号中的其中一路PWM信号进行叠加，以获取第一PWM信号；
    对所述至少两路PWM信号中的剩余PWM信号进行整流，以获取第三直流电信号，并将所述第三直流电信号与所述第一PWM信号进行叠加和整流，以获取所述第一直流电信号。
  29. 根据权利要求28所述的方法，其特征在于，所述方法还包括：
    对所述第三直流电信号进行滤波，以获取滤波后的所述第三直流电信号；
    所述将所述第三直流电信号与所述第一PWM信号进行叠加和整流，以获取所述第一直流电信号，包括：
    将所述滤波后的所述第三直流电信号与所述第一PWM信号进行叠加和整流，以获取所述第一直流电信号。
  30. 根据权利要求25至29中任一项所述的方法，其特征在于，所述方法还包括：
    对所述外部电源提供装置通过所述第一接口输入的直流电信号进行滤波。
  31. 根据权利要求25至30中任一项所述的方法，其特征在于，所述方法还包括：
    分别对在所述至少两个PWM信号被叠加之前进行去除直流电信号的处理。
  32. 一种计算机可读存储介质，其特征在于，用于存储计算机程序，所述计算机程序使得计算机执行如权利要求25至31中任一项所述的方法。
PCT/CN2020/092596 2019-06-19 2020-05-27 驱动电路、电子设备以及控制充电方法 WO2020253482A1 (zh)

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