WO2020248125A1

WO2020248125A1 - Circuit board and electronic apparatus

Info

Publication number: WO2020248125A1
Application number: PCT/CN2019/090732
Authority: WO
Inventors: 熊琳
Original assignee: 华为技术有限公司
Priority date: 2019-06-11
Filing date: 2019-06-11
Publication date: 2020-12-17
Also published as: CN113906830B; CN113906830A

Abstract

Provided are a circuit board and an electronic apparatus. The circuit board is used to connect a first chip and a second chip, and comprises two wiring layers. A first pin group and a second pin group are arranged at the two wiring layers. The first pin group is used to provide an interface for accessing multiple function regions in the first chip. The second pin group is used to provide an interface for accessing multiple function regions in the second chip. A signal line, ground wires and a power wire are further arranged at the two wiring layers. The signal line is used to connect pins in corresponding function regions of the first chip and the second chip. The ground wires are respectively arranged adjacent to two sides of the signal line. The invention meets the requirements of normal connection and transmission rate between chips while effectively reducing the costs of manufacturing a circuit board used to connect the chips.

Description

Circuit boards and electronic equipment

Technical field

This application relates to electronic technology, in particular to a circuit board and electronic equipment.

Background technique

With the development of chip technology, various types of chips have been widely used in the realization of related functions of electronic devices. For example, the fourth-generation low-power double-rate memory (Low Power Double Data Rate 4/4X, referred to as LPDDR4/4X) has been It is widely used in the memory of electronic devices.

In the prior art, in order to achieve communication and transmission between chips, such as transmission between a memory chip and a system chip, a multilayer circuit board structure is usually used to establish connections between chips. For example, in order to realize the connection between LPDDR4/4X and external devices, it is necessary to first mount the LPDDR4/4X on the circuit board to form a memory module, and then connect the memory module to the System-on-a-Chip (System-on-a-Chip) Soc) Establish a connection to form a memory system.

However, the existing circuit boards used to realize the connection between the chips need to provide power supply, signal communication and signal communication protection for the chips, and usually need to be provided with a separate power layer, ground layer and signal layer. Therefore, the circuit board needs to have a relatively high Multiple wiring layers. For example, in the prior art, the circuit boards used to realize the LPDDR4/4X connection all adopt a six-layer board structure. However, the six-layer board has more wiring board layers, which leads to a problem of higher manufacturing costs.

Summary of the invention

The embodiments of the present application provide a circuit board and electronic equipment, which not only meet the requirements of normal connection between chips and transmission rate, but also effectively reduce the manufacturing cost of the circuit board that realizes the function of connecting between chips.

In a first aspect, an embodiment of the present application provides a circuit board for connecting a first chip and a second chip. The circuit board includes: two wiring layers; a first pin group is arranged on the two wiring layers And a second pin group, wherein the first pin group is used to provide access interfaces for multiple functional areas inside the first chip, and the second pin group is used to provide access to multiple functional areas inside the second chip Interface; And, there are also signal lines, ground lines and power lines arranged on the two wiring layers; wherein the signal lines are used to connect the pins of the corresponding functional areas of the first chip and the second chip, and the two sides of a single signal line are respectively Ground wires are arranged adjacently.

In the embodiment of the present application, a first pin group, a second pin group and signal lines are arranged on the two-layer wiring board of the circuit board, and the first pin group is used to provide an access interface for the internal functional area of the first chip , The second pin group is used to provide access interface for the internal function area of the second chip, the signal line realizes the connection between the first chip and the second chip by connecting the first pin group and the second pin group, in the circuit The power lines arranged on the two-layer wiring board of the board provide power drives for the pins that need to be powered, and the ground wires are arranged adjacent to each other on both sides of each signal line on the two-layer wiring layers of the circuit board. A single signal line provides an effective return path or reference plane to ensure that no crosstalk or coupling occurs between the signal lines arranged on the circuit board. In addition, the circuit board provided by the embodiment of the present application has both the ground wire and the power wire arranged in two wiring layers, avoiding the setting of an additional separate power layer or ground layer, thereby meeting the requirements of normal connection between chips and transmission rate. At the same time, it also effectively reduces the manufacturing cost of the circuit board that realizes the connection function between the chips.

Optionally, the signal line includes a differential signal line group, the two sides of the differential signal line group are respectively adjacently arranged with ground lines, and the differential signal line group includes two coupled signal lines.

In the embodiment of the present application, by arranging ground wires on both sides of the differential signal wire group adjacent to each other, it is ensured that the two signal wires in the differential signal wire group can be normally coupled, and the differential signal wire is connected to other external signal wires. No crosstalk will occur.

Optionally, multiple functional areas include: address command signal functional area and data signal functional area, the first pin group and the second pin group respectively include: address command signal pin group and data signal pin group, signal line Including address command signal line and data signal line; the address command signal pin group is used to provide access interface for the address command signal function area, the address command signal line is used to connect the address command signal pin group of the first pin group and the second pin group The address command signal pin group of the pin group; the data signal pin is used to provide an access interface for the data signal function area, and the data signal line is used to connect the data signal pin group of the first pin group and the second pin group Data signal pin group.

In the embodiment of the present application, the address command signal pin group of the first pin group is connected to the address command signal pin group of the second pin group through the address command signal line, and the first pin group is connected through the data signal line The data signal pin group of the data signal pin group and the data signal pin group of the second pin group, so as to use the circuit board provided by the embodiment of the present application to establish the gap between the first chip and the second chip address command signal functional area and the data signal functional area connection.

Optionally, the first pin group is arranged in the first pin group area, the second pin group is arranged in the second pin group area, and the address command signal pin group of the first pin group is arranged on the first pin The first side of the group area, the first side is the side of the first pin group area away from the second pin group area; the address command signal line is fanned out from the first side and bypassed the first pin group area, A connection is established with the address command signal pin group in the second pin group area.

In the embodiment of the present application, by fanning out the address command signal line from the first side and bypassing the first pin group area, a connection is established with the address command pin group in the second pin group area. On the premise that the address command signal line does not cross other signal lines during fan-out, the wiring distance of the address command signal line is minimized, thereby further improving the transmission rate of the address command signal line.

Optionally, after the data signal line is fanned out from the second side of the first pin group area, a connection is established with the data signal pins of the second pin group area, where the second side is the first pin group area close to One side of the second pin group area.

In the embodiment of the present application, the data signal line is fanned out from the second side of the first pin group area to ensure that it does not interfere with the fan-out of the address command signal line, and from the second side of the first pin group area. After the side fanout, a connection is established with the data signal pin of the second pin group area, so that the connection between the first chip and the second chip data signal pin group can be established, and the wiring distance of the data signal line can be minimized. In turn, the transmission rate of the data signal line is improved.

Optionally, the power line is arranged between the address command signal pin group of the first pin group and the data signal pin group of the first pin group.

In the embodiment of the present application, by arranging the power line between the address command signal pin group of the first pin group and the data signal pin group of the first pin group, the power line located in the middle can be positioned at both ends. The address command signal pin group and the data signal pin group on the side are respectively routed out to provide power drive for the corresponding pins to make the power line wiring more regular and compact.

Optionally, the first pin group includes a first data signal pin group and a second data signal pin group, and the address command pin group of the first pin group is arranged in the first data pin group and the second data pin group. Between the pin groups; the second pin group includes a third data pin group and a fourth data pin group, and the third data pin group and the fourth data pin group are arranged adjacently.

Optionally, the first chip is a fourth-generation low-power dual-rate memory, and the second chip is a system chip SOC.

In the embodiment of the present application, the two-layer wiring layer structure of the circuit board provided by the embodiment of the present application realizes the connection of the fourth-generation low-power dual-rate memory and the system chip SOC, and meets the requirements of the fourth-generation low-power dual-rate While the normal connection between the memory and the system chip SOC and the transmission rate requirements, it also effectively reduces the manufacturing cost of the circuit board that realizes the connection function between the fourth-generation low-power dual-rate memory and the system chip SOC.

Optionally, the differential signal line group includes: at least one of a data differential signal line group or a clock differential signal line group.

In the embodiment of the present application, by arranging ground wires adjacent to each other on both sides of the data differential signal line group or the clock differential signal line group, it is ensured that the two signals inside the data differential signal line group or the clock differential signal line group are The lines can be coupled normally, and the data differential signal line group or the clock differential signal line group and other external signal lines will not crosstalk.

Optionally, the signal line includes at least one of a clockwise enable signal line, an on-chip termination resistance signal line, a chip selection signal line, a data mask inversion signal line, or a reset signal line.

In the embodiment of the present application, the ground wires are arranged adjacently on both sides of the clockwise enable signal line, the on-chip termination resistance signal line, the chip select signal line, the data mask inversion signal line, or the reset signal line to ensure that The clockwise enable signal line, on-chip termination resistance signal line, chip select signal line, data mask inversion signal line or reset signal line and other external signal lines will not crosstalk.

In a second aspect, an embodiment of the present application also provides a memory module, including a memory chip and a circuit board, the circuit board is used to connect the memory chip and the system chip;

The circuit board includes: two wiring layers;

A first pin group and a second pin group are arranged on the two wiring layers. The first pin group is used to provide access interfaces for multiple functional areas inside the memory chip, and the second pin group is used for the internal system chip. Multiple functional areas provide access interfaces;

Signal wires, ground wires and power wires are also arranged on the two wiring layers;

Among them, the signal wire is used to connect the pins of the memory chip and the corresponding functional area of the system chip, and the two sides of the single signal wire are respectively arranged with ground wires adjacent to each other.

Optionally, multiple functional areas include: address command signal functional area and data signal functional area, the first pin group and the second pin group respectively include: address command signal pin group and data signal pin group, signal line Including address command signal line and data signal line;

The address command signal pin group is used to provide an access interface for the address command signal function area, and the address command signal line is used to connect the address command signal pin group of the first pin group and the address command signal pin group of the second pin group ；

The data signal pin is used to provide an access interface for the data signal functional area, and the data signal line is used to connect the data signal pin group of the first pin group and the data signal pin group of the second pin group.

Optionally, the first pin group is arranged in the first pin group area, the second pin group is arranged in the second pin group area, and the address command signal pin group of the first pin group is arranged on the first pin The first side of the group area, where the first side is the side of the first pin group area away from the second pin group area;

After the address command signal line is fanned out from the first side and bypassed the first pin group area, a connection is established with the address command signal pin group in the second pin group area.

Optionally, the first pin group includes a first data signal pin group and a second data signal pin group, and the address command pin group of the first pin group is arranged in the first data pin group and the second data pin group. Between feet

The second pin group includes a third data pin group and a fourth data pin group, and the third data pin group and the fourth data pin group are arranged adjacently.

Optionally, the memory chip is a fourth-generation low-power dual-rate memory, and the system chip is a system chip SOC.

In a third aspect, an embodiment of the present application also provides a memory system, including: a memory chip, a system chip, and a circuit board;

The memory chip and the system chip are connected through a circuit board.

The circuit board includes: two wiring layers;

In a fourth aspect, an embodiment of the present application also provides an electronic device, including: a memory chip, a system chip, and a circuit board;

The memory chip and the system chip are connected through a circuit board.

The circuit board includes: two wiring layers;

The circuit board and electronic equipment provided by the embodiments of the present application establish the first chip and the second chip on the circuit board through the first pin group, the second pin group and the signal line arranged on the two-layer wiring board of the circuit board. The connection between the two chips is through the power lines arranged on the two-layer wiring board of the circuit board, in order to provide power drive for the pins that need to be powered, and by arranging the ground wires on the two wiring layers of the circuit board, and make The two sides of each signal line are arranged with ground wires adjacent to each other to provide an effective return path or reference plane for each signal line to ensure that the signal lines arranged on the circuit board will not occur during work. Crosstalk, and affect normal operation. In addition, the circuit board provided by the embodiment of the present application has both the ground wire and the power wire arranged in two wiring layers, avoiding the setting of an additional separate power layer or ground layer, thereby meeting the requirements of normal connection between chips and transmission rate. At the same time, it also effectively reduces the manufacturing cost of the circuit board that realizes the connection function between the chips.

Description of the drawings

FIG. 1 is a schematic diagram of an exemplary circuit board wiring structure provided by an embodiment of the present application;

FIG. 2 is a schematic diagram of a two-layer laminate structure of the circuit board shown in FIG. 1;

Figure 3 is a schematic diagram of an exemplary LPDDR4/4X six-layer board wiring architecture;

4 is a schematic diagram of the six-layer board laminated structure of the circuit board shown in FIG. 3;

FIG. 5 is a schematic diagram of an exemplary LPDDR4/4X two-layer board wiring structure provided by an embodiment of the present application;

FIG. 6 is a schematic diagram of a two-layer laminate structure of the circuit board shown in FIG. 5;

FIG. 7 is a schematic diagram of an exemplary address and command signal pin group wiring on the front wiring layer of a circuit board provided by an embodiment of the present application;

FIG. 8 is a schematic diagram of an exemplary address and command signal pin group wiring of the wiring layer on the reverse side of the circuit board provided by an embodiment of the present application;

9 is a schematic diagram of an exemplary data signal pin group wiring on the front wiring layer of a circuit board provided by an embodiment of the present application;

FIG. 10 is a schematic diagram of an exemplary data signal pin group wiring of a wiring layer on the reverse side of a circuit board provided by an embodiment of the present application;

FIG. 11 is a schematic diagram of an exemplary layout of power lines on a circuit board provided by an embodiment of the present application.

Detailed ways

FIG. 1 is a schematic diagram of an exemplary circuit board wiring structure provided by an embodiment of the present application, and FIG. 2 is a schematic diagram of a two-layer laminate structure of the circuit board shown in FIG. 1. As shown in FIG. 1 to FIG. 2, the circuit board provided by the embodiment of the present application includes two wiring layers, which may specifically be a stacked front wiring layer (Top surface) and a reverse wiring layer (Bottom surface). Among them, in order to connect the printed wiring of the Top surface and the Bottom surface, a via can also be opened at a position where the Top surface and the Bottom surface need to be connected.

In addition, the circuit board provided by the embodiment of the present application is used to connect the first chip and the second chip, where the first chip may be a fourth-generation low-power dual-rate memory or other forms of memory, and the second chip may be It is a system-on-chip SOC, that is, in a possible situation, the circuit board provided in the embodiment of this application can be used to connect the fourth-generation low-power dual-rate memory and the system-on-chip SOC. However, it should be noted that the specific forms of the first chip and the second chip are not limited in this embodiment.

In order to establish the connection between the chip and the circuit board provided in the embodiment of the application, a first pin group and a second pin group are arranged on the two wiring layers, wherein the first pin group is used for the first Multiple functional areas inside the chip provide access interfaces, and the second pin group is used for multiple functional areas inside the second chip to provide access interfaces.

In order to supply power to the chip, a power driver must be provided in the circuit board. In the prior art, a separate power wiring layer is usually provided to provide power to pins on other wiring layers. However, the method of providing a separate power wiring layer will result in more wiring layers of the circuit board, which will increase the manufacturing cost. In the circuit board provided by the embodiment of the present application, in order to provide power drive for the pins that need to be powered, the power lines can be arranged on two wiring layers. Specifically, it can be through the wiring on the Top surface and the Bottom surface. The input power is respectively led to the pins that need to be driven by the power, and in this embodiment, the specific arrangement of the power lines in the circuit board is not specifically limited.

In addition, in order to establish the connection between the first chip and the second chip through the circuit board provided by the embodiments of the present application, signal lines are also arranged on the two wiring layers, and the signal lines are used to connect the first chip and the second chip. The second chip corresponds to the pins of the functional area, so that a communication connection can be established between the first chip and the second chip, and data exchange between the two can be realized.

In addition, when signals are transmitted on signal lines, undesired noise voltage signals are generated between adjacent signals due to the mutual coupling of electromagnetic fields, and there is crosstalk between signal lines, which affects signal quality. Therefore, for the signal lines working on the circuit board, in order to prevent crosstalk between the signal lines, it is also necessary to set a return path or reference plane for them. In the prior art, in order to satisfy that the signal line has a return path or reference plane, the adjacent wiring layer of the signal line is usually set as a separate ground layer, so as to provide a return path or reference plane for the signal line. However, the method of providing a separate ground layer will result in more wiring layers of the circuit board, thereby increasing the manufacturing cost. In the circuit board provided by the embodiment of the present application, in order to provide a return path or a reference plane for the signal line, it is also necessary to arrange a ground wire on the two wiring layers of the circuit board. In addition, ground wires are arranged adjacent to both sides of each signal wire, that is, each signal wire is covered with a ground wire at both ends, so as to provide an effective return path or reference plane for each signal wire, and avoid the signal wire. Coupling or crosstalk between to ensure that the signal line can work normally.

Optionally, the signal line in the embodiment of the present application may be a single signal line, such as an address command signal line or a data signal line, or multiple associated signal lines, such as two coupled signal lines , Such as a differential signal line group.

In a possible situation, the signal line in the embodiment of the present application may include a differential signal line group. It should be understood that differential transmission is a signal transmission technology, which is different from the traditional way of one signal wire and one ground wire. Differential transmission transmits signals on both wires. Among them, the amplitude of the two signals Same but opposite in phase. The signals transmitted on these two wires are differential signals, and the two coupled signal wires constitute the aforementioned differential signal wire group. In order to ensure that the two signal lines inside the differential signal line group can be normally coupled, and the differential signal line does not crosstalk with other external signal lines, ground wires can be arranged adjacent to each other on both sides of the differential signal line group, or There are ground wires on both sides of the differential signal line group to provide a return path or reference plane for the differential signal line group.

In the embodiment of the present application, a first pin group, a second pin group and signal lines are arranged on the two-layer wiring board of the circuit board, and the first pin group is used to provide an access interface for the internal functional area of the first chip. The second pin group is used to provide an access interface for the internal functional area of the second chip, and the signal line realizes the connection between the first chip and the second chip by connecting the first pin group and the second pin group. The power lines arranged on the two-layer wiring board provide power drives for the pins that need to be powered, and there are ground wires arranged adjacent to each other on both sides of each signal line on the two-layer wiring layer of the circuit board. The signal line provides an effective return path or reference plane to ensure that crosstalk or coupling does not occur between the signal lines arranged on the circuit board. In addition, the circuit board provided by the embodiment of the present application has both the ground wire and the power wire arranged in two wiring layers, avoiding the setting of an additional separate power layer or ground layer, thereby meeting the requirements of normal connection between chips and transmission rate. At the same time, it also effectively reduces the manufacturing cost of the circuit board that realizes the connection function between the chips.

On the basis of the foregoing embodiments, optionally, the first chip may be a fourth-generation low-power dual-rate memory LPDDR4/4X, and the second chip may be a system chip SOC. It is worth noting that LPDDR4/4X has two 16-bit-data signal (Data-Quality, DQ for short) channels, which can be named A channel CHA-DQ and B channel CHB-DQ respectively to form a 32-bit-DQ dual channel. In addition, each channel has independent address and command signal (Command&Address, CA), DQ, data strobe signal (Data Strobe, DQS), data mask inversion signal (Data Mask Inversion, DMI), clock signal (Clock, CK for short), chip select signal (Chip Select, CS for short), clock enable signal (Clock Enable, CKE for short), and on-die-termination resistance signal (On-Die-Termination, for short ODT).

Among them, FIG. 3 is a schematic diagram of an exemplary LPDDR4/4X six-layer board wiring structure, and FIG. 4 is a schematic diagram of the six-layer board stack structure of the circuit board shown in FIG. 3. As shown in Figure 3-Figure 4, the circuit board used to realize the connection between LPDDR4/4X and SOC adopts a six-layer board structure, with the first wiring layer Layer1, the second wiring layer Layer2, and the third wiring layered in sequence. Layer 3, fourth wiring layer Layer4, fifth wiring layer Layer5, and sixth wiring layer Layer6. Specifically, the six-layer board structure in the prior art is to arrange the power supply on the top wiring layer Layer 1 and the bottom wiring layer Layer 6 of the circuit board, and both Layer 2 and Layer 5 are set as the ground layer, so that the channel B data of the Layer 3 part The signal line CHB-DQ and the channel A address command signal line CHA-CA refer to Layer 2, and the channel A data signal line CHA-DQ and the channel B address command signal line CHB-CA of the Layer 4 part refer to Layer 5.

It can be seen that the six-layer board structure used to realize the LPDDR4/4X connection requires more wiring board layers, which leads to the problem of higher manufacturing cost of the circuit board for the connection function.

Therefore, in order to solve the problem of high manufacturing cost for implementing LPDDR4/4X, an embodiment of the present application also provides a circuit board for establishing a connection between LPDDR4/4X and SOC, and meeting the LPDDR4/4X transmission rate requirement of 3200Mbps .

Specifically, FIG. 5 is a schematic diagram of an exemplary LPDDR4/4X two-layer board wiring structure shown in an embodiment of the present application, and FIG. 6 is a schematic diagram of a two-layer board laminate structure of the circuit board shown in FIG. 5. As shown in FIG. 5 to FIG. 6, the circuit board provided by the embodiment of the present application includes two wiring layers, which may specifically be a stacked front wiring layer (Top side) and a back side wiring layer (Bottom side).

In order to establish the connection between the LPDDR4/4X and the SOC and the circuit board provided by the embodiment of the application, a first pin group and a second pin group are arranged on two wiring layers, wherein the first pin group is used To provide access interfaces for multiple functional areas inside LPDDR4/4X, and the second pin group is used to provide access interfaces for multiple functional areas inside SOC.

Optionally, the aforementioned multiple functional areas include: an address command signal functional area and a data signal functional area, the first pin group and the second pin group respectively include: address command signal pin group (CA pin group) and Data signal pin group (DQ pin group, including: A channel-data signal pin group: CHA-DQ pin group and B channel-data signal pin group: CHB-DQ pin group), and the signal line includes Address command signal line and data signal line.

Among them, the CA pin group is used to provide an access interface for the address command signal function area, the address command signal line is used to connect the CA pin group of the first pin group and the CA pin group of the second pin group, and the DQ lead The pin group is used to provide an access interface for the data signal function area, and the data signal line is used to connect the DQ pin group of the first pin group and the DQ pin group of the second pin group.

Optionally, the first pin group may also include a first data signal pin group and a second data signal pin group, where, as shown in FIG. 3, the first data signal pin group and the second data signal pin group The group can be the CHB-DQ pin group and the CHA-DQ pin group on the LPDDR4/4X side, and the CA pin group in the first pin group is arranged in the CHB-DQ pin group and the CHA-DQ pin Between groups. In addition, correspondingly, the second pin group includes a third data pin group and a fourth data pin group, and the third data pin group and the fourth data pin group are arranged adjacently, as shown in FIG. 3, The third data pin group and the fourth data pin group may be the CHB-DQ pin group and the CHA-DQ pin group on the SOC side.

3 and 5, the first pin group is arranged in the first pin group area, and the second pin group is arranged in the second pin group area. It is worth understanding, please refer to Figure 3 first, according to the grain area layout characteristics of LPDDR4/4X, the CA pin group in the first pin group will be set to one side in the first pin group, because the first pin group The CA pin group in the six-layer structure can be directly connected to the CA pin group in the SOC through the CA signal line in a wiring layer in the six-layer structure. Therefore, the side of the CA pin group can be biased closer to the second pin Set on one side of the group area, and then after the CA signal line is fanned out from the side close to the second pin group area, connect to the CA pin group in the SOC to establish a connection. However, since the circuit board provided by the embodiment of the present application only includes two wiring layers, if the CA signal line is fanned out from the side close to the second pin group area, it will cause and be used to connect the first pin group. The CHA-DQ pin group in the second pin group crosses the DQ signal line of the CHA-DQ pin group of the second pin group. Therefore, the CA signal line in the first pin group cannot be directly connected to the second pin group area. Side fan out.

Therefore, in order to achieve a smooth fan-out of the CA signal line, it is necessary to adjust the fan-out method of the CA signal line of the CA pin group in the first pin group, which can be fan-out from the side far from the area of the second pin group Then, bypassing the first pin group area, and establishing a connection with the CA pin group in the second pin group.

Optionally, the area layout of the first pin group shown in FIG. 3 may be flipped 180 degrees to obtain the area layout of the first pin group shown in FIG. 5. Wherein, the CA pin group in the first pin group area as shown in FIG. 5 is arranged on the first side of the first pin group area, and the first side is the first pin group area away from the second pin group One side of the area. Then, the CA signal line is fanned out from the first side, and after bypassing the first pin group area, a connection is established with the CA pin group in the second pin group area.

It can be seen that the CA pin group in the first pin group area shown in FIG. 5 is arranged on the first side of the first pin group area, when the CA signal line fan out from the first side and bypass the first pin After the group area, establish a connection with the CA pin group in the second pin group area, which can minimize the wiring distance of the CA signal line while ensuring that the CA signal line does not cross other signal lines during fan-out. The transmission rate of the CA signal line is further improved. It is worth mentioning that under the same conditions, the shorter the wiring distance of the CA signal line, the faster the corresponding transmission rate.

In addition, in order to adapt to the arrangement of the CHB-DQ pin group and the CHA-DQ pin group in the first pin group shown in Figure 5, the CHB-DQ pin group and the CHA-DQ pin group in the second pin group The pin group also needs to be adjusted to correspond to the CHB-DQ pin group and CHA-DQ pin group in the first pin group. It is worth noting that because there is no difference between the two sets of DQ channels in the SOC chip, the upper DQ pin group can be used to connect to the CHA-DQ in the memory chip, and it can also be used to connect to the CHB-DQ in the memory chip. Connection, the corresponding DQ pin group located at the lower part can be used to connect with the CHB-DQ in the memory chip, or can be used to connect with the CHA-DQ in the memory chip. In this embodiment, in order to adapt the DQ pin group in the second pin group to the arrangement of the CHB-DQ pin group and the CHA-DQ pin group in the first pin group, and make the DQ signal line smooth For fan-out, you can select the upper DQ pin group as the CHB-DQ pin group, and the lower DQ pin group as the CHA-DQ pin group.

Then, the DQ signal lines drawn from the CHA-DQ pin group and the CHB-DQ pin group are fanned out from the second side of the first pin group area, respectively, and the CHA-DQ pin group in the second pin group area And the CHB-DQ pin group is connected, wherein the second side is the side of the first pin group area close to the second pin group area.

In addition, in order to supply power to the LPDDR4/4X, a power driver must be provided in the circuit board. In order to provide power drive to the pins that need to be powered, power lines can be arranged on the two wiring layers. Specifically, the input power can be led to the power drive through the wiring on the Top and Bottom surfaces. Pin, and in this embodiment, the specific arrangement of the power cord in the circuit board is not specifically limited. Among them, the CHB-DQ pin group, CHA-DQ pin group, and CA pin group in the first pin group need to be connected to the power supply, in order to make the CHB-DQ pin group and CHA-DQ pin group in the first pin group The pin group and the CA pin group are conveniently connected to the power supply, and the power line can be arranged between the CA pin group of the first pin group and the DQ pin group of the first pin group. Optionally, the power cord can be introduced from the first side of the first pin group area, through the area between the CHB-DQ pin group and the CA pin group, and then transferred to the CA pin group and CHA-DQ The area between pin groups. Wherein, by arranging the power line between the address command signal pin group of the first pin group and the data signal pin group of the first pin group, the power line located in the middle can transmit the address command signal to the address command signal on both sides. The pin group and the data signal pin group respectively lead out to provide power drive for the corresponding pins, so that the power line wiring is more regular and compact.

Optionally, the signal line in the embodiment of the present application may be a single signal line, such as address command signal line CA, data signal DQ, clock enable signal line CKE, on-chip termination resistance signal line ODT, chip selection signal line CS At least one of the data mask inversion signal DMI line or the reset signal line (Reset, RST for short). In addition, the signal line can also be a differential signal line group, such as at least one of a data differential signal line group or a clock differential signal line group. Optionally, the data differential signal line group includes data strobes that require T\C coupling. The negative terminal signal DQS-C and the data strobe positive terminal signal DQS-T, the clock differential signal line group includes the clock differential negative terminal signal CK-C and the clock differential positive terminal signal CK-T that need to be T\C coupled.

In a possible situation, the signal line in the embodiment of the present application may include a differential signal line group. It should be understood that differential transmission is a signal transmission technology, which is different from the traditional way of one signal wire and one ground wire. Differential transmission transmits signals on both wires. Among them, the amplitude of the two signals Same but opposite in phase. The signals transmitted on these two wires are differential signals, and the two coupled signal wires constitute the aforementioned differential signal wire group. In order to ensure that the two signal lines inside the differential signal line group can be normally coupled, and the differential signal line and other external signal lines will not crosstalk, it can be achieved by arranging grounding adjacent to both sides of the differential signal line group. The line method provides a return path or reference plane for the differential signal line group.

On the basis of the embodiment shown in FIG. 3, the implementation principle of the circuit board provided in the embodiment of the present application will be described in detail below in conjunction with an exemplary wiring manner of the circuit board.

Wherein, FIG. 7 is an exemplary wiring diagram of the address and command signal pin groups on the front wiring layer of the circuit board provided by the embodiment of the present application. As shown in Figure 7, the small circles in the figure represent single-board vias, the large circles represent pins, the thin solid lines represent the front signal wiring, and the thick solid lines represent the ground. 8-12 are the numbers of the columns of the circuit board, and G-V are the numbers of the rows of the circuit board.

Specifically, CK-CA and CK-TA, CK-CB and CK-TB are two sets of differential signal lines, using the ground pins of K9 and N9 and the ground between rows N and K to carry out two signal lines Both sides are wrapped and processed, and the differential signal line is fanned out to the left. It is worth noting that the ground pin of K9 is a ground pin with row label K and column label 9, and N9 is a ground pin with row label N and column label 9. In addition, it is worth noting that CK-CA is the negative end signal of the clock differential signal line group corresponding to channel A, and CK-TA is the positive end signal of the clock differential signal line group corresponding to channel A. Both need to be T\ C coupling, and CK-CB is the negative end signal of the clock differential signal line group corresponding to the B channel, and CK-TB is the positive end signal of the clock differential signal line group corresponding to the B channel, the two also need to be T\C coupling . It is worth understanding that all of the following A or B marked at the end of each pin number represent the pins belonging to the A channel or the B channel respectively.

In addition, for RST-N, CA5-B, CA4-B, CA3-B, CA2-B, CA2-A, and CA4-A, use the ground pins of V12, T12, P12, J12, G12, N11, K11 and Pave the ground and wrap the ground on both sides of a single signal line to make the signal line fan out to the left.

FIG. 8 is an exemplary wiring diagram of the address and command signal pin groups of the wiring layer on the reverse side of the circuit board provided by an embodiment of the present application. As shown in Figure 8, small circles represent single-board vias, large circles represent pins, thin solid lines represent front-side signal wiring, and dotted lines represent back-side signal wiring.

Specifically, for ODT-B, CA0-B, CS0-B, CS1-B, CKE0-B, CKE1-B, CA1-B, CA1-A, CKE0-A, CKE1-A, CS0-A, CS1- A, CA0-A, ODT-A, CA4-A, CA5-A, after the signal lines are arranged as shown in Figure 8, the ground pins on the back and the ground between the signal lines are connected together, and the signal lines are to the left Fan out from the side or below, so as to achieve the effect of a single signal covering both sides;

FIG. 9 is a schematic diagram of an exemplary data signal pin group wiring on the front wiring layer of a circuit board provided by an embodiment of the present application. As shown in Figure 9, the small circles in the figure represent single-board vias, the large circles represent pins, the thin solid lines represent the front signal wiring, and the thick solid lines represent the ground.

Specifically, for DQ11-A, DQ10-A, DQ9-A, DQ8-A, DQ15-A, DQ14-A, use the ground pins of E12, C12, A10, and C8 and the grounding of a single signal line on both sides of the ground Processing, the signal line fan out downward;

For the differential signal line group: DQS1-T-A, DQS1-C-A, use the ground pins of K9 and N9 to wrap the ground on both sides of a single signal line, and the signal line will fan out downward;

For DQ2-A and DQ3-A, use the ground pins of E1 and G1 and the grounding of a single signal line to wrap the ground on both sides, and the signal line will fan out to the right;

For the differential signal line group: DQS0-TA, DQS0-CA, use the ground pins of E1 and C1 to wrap the ground on both sides of a single signal line, and the signal line will fan out to the right. It is worth noting that DQS0-CA corresponds to channel A One of the negative end signals of the data differential signal group, and DQS0-TA is the positive end signal of one of the data differential signal groups corresponding to the A channel, and the two need to be T\C coupled;

For DQ11-B, DQ10-B, DQ9-B, use the ground pins of V12, Y12 and the grounding of a single signal line to wrap the ground on both sides, and the signal line will fan out upward;

For the differential signal line group: DQS1-T-B, DQS1-C-B, use the ground pin of AB10 and the grounding single signal line to wrap the ground on both sides, and the signal line will fan out upward;

For DQ4-B, DQ3-B, DQ2-B, use the ground pins of V5, T5, V1, and T1 to wrap the ground on both sides of a single signal line, and the signal line will fan out to the right;

For differential signal line groups: DQS0-TB, DQS0-CB, use the ground pins of Y1 and V1 to wrap the ground on both sides of a single signal line, and the signal line will fan out to the right. It is worth noting that DQS0-CB corresponds to channel B One of the negative end signals of the data differential signal group, and DQS0-TB is the positive end signal of one of the data differential signal groups corresponding to the B channel, and the two need to be T\C coupled.

FIG. 10 is a schematic diagram of an exemplary data signal pin group wiring on the back side wiring layer of the circuit board provided by an embodiment of the present application. As shown in Figure 10, the small circles in the figure represent single-board vias, the large circles represent pins, the thin solid lines represent the front signal wiring, and the thick solid lines represent the ground.

Specifically, for DQ8-B, DQ15-B, DQ14-B, DMI1-B, DQ12-B, DQ13-B, DQ5-B, DQ6-B, DQ7-B, DMI0-B, DQ0-B, DQ1- B, DQ12-A, DQ13-A, DMI1-A, DQ5-A, DQ6-A, DQ7-A, DMI0-A, DQ1-A, DQ0-A, the signal lines are arranged as shown in Figure 8 , The ground pin on the back and the ground between the wires are connected into one piece, and the signal wire is fanned out to the right, above or below, so as to achieve the effect of a single signal wire with ground on both sides. It is worth explaining that DMI0-A and DQ0-A DQ7-A is a set of data buses, DMI1-A and DQ8-A to DQ15-A are a set of data buses, DMI0-B and DQ0-B to DQ7-B are a set of data buses, DMI1-B and DQ8-B To DQ15-B is a set of data buses.

FIG. 11 is a schematic diagram of an exemplary layout of power lines on a circuit board provided by an embodiment of the present application. As shown in Figure 11, the small circles represent single-board vias, the large circles represent pins, the thick solid lines represent the front 1.1V power line wiring, the thick dashed lines or boxes represent the back 1.1V power line wiring, and the thin solid lines represent the front 1.8V. Power cord wiring, thin dotted lines represent 1.8V power cord wiring on the back.

In the embodiments of the present application, a fan-out method of signal wires, power wires, and ground wires is adopted to realize a single signal wire covering the ground, and the signal wires are arranged to ensure that the input power meets the requirements. The layer structure not only meets the normal connection between the chips and the transmission rate requirements, but also effectively reduces the manufacturing cost of the circuit board that realizes the connection function between LPDDR4/4X and SOC.

In addition, an embodiment of the present application also provides an electronic device, including: a memory chip, a system chip, and the circuit board provided in any of the foregoing embodiments, wherein the memory chip and the system chip are connected through the circuit board. Optionally, the memory chip is LPDDR4/4X.

The electronic device may be an electronic device with data processing and storage functions, such as a smart TV, a set-top box, a monitoring device, a smart phone, a tablet computer, and a personal computer.

The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention. It should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

A circuit board, characterized in that the circuit board is used to connect a first chip and a second chip, and the circuit board includes: two wiring layers;

A first pin group and a second pin group are arranged on the two wiring layers, the first pin group is used to provide access interfaces for multiple functional areas inside the first chip, and the second The pin group is used for multiple functional areas inside the second chip to provide access interfaces;

Signal wires, ground wires and power wires are also arranged on the two-layer wiring layer;

Wherein, the signal wire is used to connect the pins of the corresponding functional areas of the first chip and the second chip, and the ground wires are arranged adjacent to each other on both sides of the single signal wire.
The circuit board according to claim 1, wherein the signal line includes a differential signal line group, and the ground line is adjacently arranged on both sides of the differential signal line group, and the differential signal line group includes Two coupled signal lines.
The circuit board according to claim 1 or 2, wherein the multiple functional areas include: an address command signal functional area and a data signal functional area, the first pin group and the second pin group Each includes: an address command signal pin group and a data signal pin group, and the signal lines include an address command signal line and a data signal line;

The address command signal pin group is used to provide an access interface for the address command signal functional area, and the address command signal line is used to connect the address command signal pin group of the first pin group and the second pin group. The address command signal pin group of the pin group;

The data signal pin is used to provide an access interface for the data signal functional area, and the data signal line is used to connect the data signal pin group of the first pin group and the data of the second pin group Signal pin group.
The circuit board according to any one of claims 1 to 3, wherein the first pin group is arranged in a first pin group area, and the second pin group is arranged in a second pin group area , The address command signal pin group of the first pin group is arranged on the first side of the first pin group area, and the first side is the first pin group area away from the second lead One side of the foot group area;

After the address command signal line is fanned out from the first side and bypassed the first pin group area, it establishes a connection with the address command signal pin group in the second pin group area.
4. The circuit board according to claim 4, wherein after the data signal line is fanned out from the second side of the first pin group area, it is connected with the data signal pin of the second pin group area. A connection is established, wherein the second side is a side of the first pin group area close to the second pin group area.
The circuit board according to any one of claims 3-5, wherein the power line is arranged in the address command signal pin group of the first pin group and the data of the first pin group Between signal pin groups.
The circuit board according to any one of claims 3-6, wherein the first pin group comprises a first data signal pin group and a second data signal pin group, and the first pin group The address command pin group of the group is arranged between the first data pin group and the second data pin group;

The second pin group includes a third data pin group and a fourth data pin group, and the third data pin group and the fourth data pin group are arranged adjacently.
The circuit board according to any one of claims 1-7, wherein the first chip is a fourth-generation low-power dual-rate memory, and the second chip is a system chip SOC.
The circuit board according to any one of claims 2 to 8, wherein the differential signal line group includes at least one of a data differential signal line group or a clock differential signal line group.
The circuit board according to any one of claims 1-9, wherein the signal line comprises a clockwise enable signal line, an on-chip termination resistance signal line, a chip select signal line, a data mask inversion signal line or At least one of the reset signal lines.
An electronic device, characterized by comprising: a memory chip, a system chip, and the circuit board according to any one of claims 1-10;

The memory chip and the system chip are connected through the circuit board.