WO2020237682A1

WO2020237682A1 - Content-addressable storage apparatus and method, and related device

Info

Publication number: WO2020237682A1
Application number: PCT/CN2019/089687
Authority: WO
Inventors: 杨兵
Original assignee: 华为技术有限公司
Priority date: 2019-05-31
Filing date: 2019-05-31
Publication date: 2020-12-03
Also published as: CN113966532A

Abstract

Disclosed in embodiments of the present application are a content-addressable storage apparatus and method, and a related device, wherein the content-addressable storage apparatus may comprise: a memory used for storing data to be matched; a comparator comprising N comparison units, the N comparison units being respectively coupled to the memory; a scheduler used for acquiring K pieces of search data and for scheduling the K pieces of search data to K target comparison units among the N comparison units respectively, the target comparison units being comparison units in an idle state; a controller used for controlling the memory to read out the data to be matched and send same to the K target comparison units respectively; and each target comparison unit among the K target comparison units is used for comparing corresponding search data with the data to be matched, and outputting a corresponding matching result according to the comparison result. By employing the present application, the low power consumption and flexibility of a content-addressable storage device may be ensured.

Description

Content addressable storage device, method and related equipment

Technical field

This application relates to the field of memory technology, and in particular to a content addressable storage device, method and related equipment.

Background technique

Content addressable memory (Content Addressable Memory, CAM) is a content-addressable memory, which is a special storage array random access memory (Random Access Memory, RAM). In addition to reading and writing like traditional RAM, it can also perform search operations. Its search mechanism is to compare an input data item with all data items stored in the CAM, and distinguish the input data item from the data stored in the CAM. Whether the data item matches, and output the matching information corresponding to the data item. As shown in FIG. 1A, FIG. 1A is a schematic diagram of the functional difference between RAM and CAM in the prior art. RAM searches for corresponding data according to the input address, and CAM can search for the corresponding address according to input data.

As shown in Fig. 1B, Fig. 1B is a schematic diagram of a typical CAM structure in the prior art. CAM mainly consists of the following parts: CAM array (M array), sensitive amplifier (SA), search line drivers (Search Line drivers) , SL drivers) and encoders. The CAM array in FIG. 1B includes (W×K) CAM memory cells M, and each memory cell M is responsible for storing data and comparing the stored data with external search data. Among them, a row of memory cells M (W as an example in the figure) constitutes a word of CAM (also called data item, data table item, table item, etc.), W is "word width or bit width", CAM array The number of all words (K in the figure as an example) is called "depth", and the capacity of CAM is represented by (K words×W bits). During the search operation, the search data (Search Key) is loaded into the search line SL through the search line driver SL drivers, the data stored in the memory cell M is matched with the SL, and the matching result is reflected in the match line in the form of level changes On (Match Line, ML), the voltage change on ML is amplified by the sensitive method SA, and finally output to the priority encoder (encoder), and the address with the highest priority of the data item that matches the search data is encoded and output.

It can be seen that when CAM searches for content, it uses the comparison circuit in each memory cell M to compare the search data with the data stored in all memory cells at the same time, so that all data items in the entire CAM array can be as fast as one clock cycle It is queried to achieve fast matching, high parallelism, and the search speed is not affected by the CAM capacity. Compared with ordinary memory which can only be controlled by software, the data in the memory can be read one by one in the order of address for comparison. CAM realizes the function of high-speed search through hardware circuit, which greatly improves the search efficiency and performance of the search system. It is widely used in network communication, pattern recognition and other fields.

However, due to the characteristics of CAM using dedicated circuits for parallel comparison, it inevitably has the problems of large chip area, high power consumption, poor portability and low flexibility, which reduces the performance of CAM chips. And reliability.

Application content

The embodiments of the present application provide a content addressable storage device, method, and related equipment, which can realize the content addressable function while ensuring the low power consumption and flexibility of the content addressable storage device.

In the first aspect, an embodiment of the present application provides a content-addressable storage device, which may include: a memory for storing data to be matched; a comparator including N comparison units, and the N comparison units are respectively coupled to In the memory, N is an integer greater than 1; a scheduler is used to obtain K search data, and schedule the K search data to K target comparison units among the N comparison units, and the target The comparison unit is a comparison unit in an idle state, K is an integer greater than or equal to 1 and less than or equal to N; the controller is used to control the memory to read out the data to be matched and send them to the K targets respectively Comparison unit; each of the K target comparison units is used to compare the corresponding search data with the data to be matched, and output a corresponding matching result according to the comparison result.

In the embodiment of the present application, multiple comparison units in the comparator are used as dynamic, flexible and callable comparison resources in the content addressable storage device. When there is input search data that needs to be searched, the above multiple comparisons are called The idle comparison unit in the unit sequentially compares the search data with the data to be matched in the memory. Among them, since the comparator includes N comparison units, a maximum of N search data can be simultaneously searched in parallel. Different from the prior art CAM, each memory cell of the CAM array has a comparison circuit. Although the search data can be compared with all the stored data in the memory array at the same time, it can be obtained in less or even one clock cycle. The comparison results, however, because each memory cell has the characteristics of a dedicated comparison circuit, it has caused problems such as large chip area, high power consumption, and high cost. Moreover, once the CAM leaves the factory, its physical structure and related parameters are fixed, so portability and flexibility are poor. However, in the embodiment of the present application, the comparison unit of the comparator in the content addressable storage device is shared, and the parallel search function of search data can be realized according to actual search requirements, which doubles the processing capacity of the device and meets the network transient In scenarios with lower throughput and higher throughput, the use of high-cost and high-power CAM structures is avoided, which ensures performance and reduces costs and power consumption. Furthermore, since the memory in the device does not need a dedicated CAM structure, a relatively general memory structure can be used, and other functional structures in the device (scheduler, controller, etc.) can be implemented based on general description languages such as hardware description language verilog , Thus making its portability and flexibility strong, thereby greatly ensuring the high availability, low cost and low power consumption of the content addressable storage device.

In a possible implementation manner, the device further includes a result output register, and the N comparison units are respectively coupled to the result output register; the data to be matched includes multiple data items; the K targets Each target comparison unit in the comparison unit is further configured to send a corresponding matching result to the result output register, and the matching result includes matching indication information, matching data items of the corresponding search data, and matching data items of the matching data items. One or more of the addresses, wherein the matching indication information is used to indicate whether there is a matching data item; the result output register is used to receive and store the matching results respectively sent by the K target comparison units. The N comparison units in the embodiment of the present application are respectively coupled to the result output register in the content addressable storage device. When any one of the N comparison units completes the matching of the search data, the matching result can be sent to The result output register, where the matching result can be one or more of whether the matching is successful, the specific matching data, or the address of the matching data.

In a possible implementation manner, the data to be matched includes M data items. M is an integer greater than 1; the controller is specifically configured to control the memory to sequentially read the M data items and send them to the K target comparison units according to the address traversal mode; the K targets Each target comparison unit in the comparison unit is specifically configured to sequentially compare the corresponding search data with the M data items to determine matching data items of the corresponding search data. In the embodiment of the present application, the M data items stored in the memory are serially read out through address traversal, and are gradually sent to the corresponding target comparison unit for comparison, so as to obtain the corresponding matching result.

In a possible implementation manner, the data to be matched includes M data items; the controller is specifically configured to control the memory to read out L data items in an address polling manner in each clock cycle , And broadcast the read L data items to the N comparison units, where L is a positive integer less than or equal to M; each comparison unit in the K comparison units is used to compare the received data each time The L data items are compared with the corresponding search data. In the embodiment of the present application, when there are multiple search data for searching, there are corresponding multiple comparison units performing the search operation at the same time. Specifically, it may be that the controller reads out L data items in the memory and sends them in parallel. To the comparison unit currently performing the search operation, and the comparison unit currently performing the search operation compares the L pieces of data received each time with the stored search data to obtain the corresponding matching result. For example, the comparator includes 8 comparison units, and currently 4 comparison units are performing data comparison. The controller reads out 2 data items from the 64 data items to be matched every clock cycle and sends them to the above 4 in parallel. Among the comparison units, each comparison unit compares the two data items received each time with the search data stored in itself. For each comparison unit, it obtains the matching result (with all the data items to be matched). All or part of the 64 data items have been compared), the search operation of the comparison unit can be stopped. At this time, the controller controls no longer sending the data items read from the memory to the comparison unit that has completed the search operation.

In a possible implementation manner, the bit width of each of the N comparison units is L times the bit width of each of the M data items. In the embodiment of the present application, the bit width of each comparison unit in the comparator may be L times the bit width of each data item in the data to be matched stored in the memory. In this case, the comparison unit may L data items are compared in clock cycles. For example, if the bit width of each data item is W and the comparison unit comparison bit width is L*W, then the comparison unit can complete the comparison of L*W bit/bit data in one clock cycle.

In a possible implementation manner, the controller is further configured to control the memory to write the data to be matched in a preset manner. In the embodiment of the present application, the controller can complete the initial configuration control of the data to be matched in a preset manner under the control of the external or internal processor of the device in the initial stage, for example, enumerate the addresses of all the data to be matched, and The data to be matched corresponding to the address is correspondingly written into the memory, and the content of the data to be matched depends on the specific business requirements.

In a possible implementation manner, the scheduler is also used to control the preset time when the search data received within the preset time period exceeds a preset number, or when there is no free comparison unit currently After the interval, the target comparison unit is determined from the N comparison units. In the embodiment of the present application, when the throughput in the network is high, such as when the maximum pps of the instantaneous burst is large, or when there is no idle comparison unit currently, the comparison can be performed after a certain period of time through traffic shaping processing. To improve the adaptability of the content addressable storage device in the embodiments of the present application to reduce the requirement for instantaneous comparison of resources.

In a possible implementation manner, the controller is further configured to control the memory to write new data to be matched or modify the data to be matched during the process of controlling the memory to read the data to be matched. The data to be matched. In the embodiment of the present application, the controller can write the data to be matched into the memory by reading and writing. For example, for a system that requires online refreshing of the data to be matched, the controller can select the independent read/write Two-port memory is used to read and update or modify the data to be matched; if a single-port memory is selected, the controller needs to insert some additional refresh time to complete the data to be matched when reading the data to be matched. Refreshing of matching data may reduce the query speed at this time. The refresh time means that when refreshing (writing table entry/data item), the address sequence of suspending query (reading table entry/data item) increases (while the write enable is invalid), after the writing is completed, the query is re-enabled ( Read enable, read address sequence increases).

In a possible implementation, the data to be matched includes M data items, where each data item includes content to be matched, query control information, and output results; each of the K target comparison units A target comparison unit is specifically configured to compare the corresponding search data with the content to be matched in each data item according to the query control information of the M data items, and to output the result in the matched data item Output as the matching result of the corresponding search data. In this embodiment of the application, the query control information and the corresponding output result are carried in the data items contained in the data to be matched (for example, the output result is the address corresponding to the content to be matched), thereby controlling the comparison unit to search for data The query method and related parameters when querying to meet the business needs in multiple scenarios.

In the second aspect, the embodiments of the present application provide a content addressable storage method, which can be applied to a content addressable storage device. The device includes a comparator and a memory. The comparator includes N comparison units. The N comparison units are respectively coupled to the memory, and N is an integer greater than 1. The method includes: storing the data to be matched in the memory; obtaining K search data, and separately Scheduling to K target comparison units among the N comparison units, the target comparison unit is a comparison unit in an idle state, and K is an integer greater than or equal to 1 and less than or equal to N; controlling the memory readout The data to be matched are sent to the K target comparison units respectively; through each target comparison unit of the K target comparison units, the corresponding search data is compared with the data to be matched, and according to The comparison result outputs the corresponding matching result.

In a possible implementation manner, the device further includes a result output register, and the N comparison units are respectively coupled to the result output register; the data to be matched includes multiple data items; the method further includes : Send the matching result corresponding to each target comparing unit of the K target comparing units to the result output register, where the matching result includes matching indication information, matching data items of the corresponding search data, and matching data One or more of the address of the item, wherein the matching indication information is used to indicate whether there is a matching data item; the matching result sent by the K target comparison units is received and stored through the result output register.

In a possible implementation manner, the data to be matched includes M data items, and M is an integer greater than 1, and the control memory reads the data to be matched and sends them to the K data items respectively. The target comparing unit includes: controlling the memory to sequentially read the M data items and sending them to the K target comparing units according to the address traversal mode; the comparing by each of the K target comparing units Unit, which compares the corresponding search data with the data to be matched, and outputs the corresponding matching result according to the comparison result, including: the corresponding search data is compared by each of the K target comparison units Compare with the M data items in sequence to determine matching data items of the corresponding search data.

In a possible implementation manner, the data to be matched includes M data items, and M is an integer greater than 1, and the control memory reads the data to be matched and sends them to the K data items respectively. The target comparison unit includes: controlling the memory to read out L data items in each clock cycle by address polling, and broadcasting the read L data items to the N comparison units, where L is less than or A positive integer equal to M; compare the corresponding search data with the data to be matched through each of the K target comparison units, including: through each of the K comparison units , Compare the L data items received each time with the corresponding search data.

In a possible implementation, the bit width of each of the N comparison units is L times the bit width of each of the M data items.

In a possible implementation, the method further includes: controlling the memory to write the data to be matched in a preset manner.

In a possible implementation manner, the method further includes: when the search data received within the preset time period exceeds the preset number, or when there is no free comparison unit currently, controlling after the preset time interval , And then determine the target comparison unit from the N comparison units.

In a possible implementation manner, the method further includes: in the process of controlling the memory to read the data to be matched, controlling the memory to write new data to be matched or modify the data to be matched The data.

In a possible implementation, the data to be matched includes multiple data items, wherein each data item includes content to be matched, query control information, and output results; Each target comparison unit compares the corresponding search data with the data to be matched, and outputs the corresponding matching result according to the comparison result, including: through each of the K target comparison units, respectively According to the query control information of the M data items, the corresponding search data is compared with the content to be matched in each data item, and the output result in the matched data item is used as the matching result of the corresponding search data. Output.

In the third aspect, this application provides a semiconductor chip, which may include:

The foregoing first aspect and a content addressable storage device provided in combination with any one of the foregoing first aspects.

In a fourth aspect, this application provides a semiconductor chip, which may include:

The foregoing first aspect and the content addressable storage device provided in combination with any one of the foregoing first aspect implementation manners, a processor coupled to the content addressable storage device, and the content addressable storage device External storage.

In a fifth aspect, the present application provides a system-on-chip SoC chip. The SoC chip includes the above-mentioned first aspect and the content-addressable storage device provided in combination with any one of the above-mentioned first aspects, coupled to the The processor of the content addressable storage device and the external memory of the content addressable storage device. The chip system can be composed of chips, or include chips and other discrete devices.

In a sixth aspect, the present application provides a chip system, which includes: a content addressable storage device including the first aspect described above and any one of the implementations provided in combination with the first aspect described above, and including: The processor of the content addressable storage device and the chip of the external memory of the content addressable storage device. The chip system can be composed of chips, or include chips and other discrete devices.

In a seventh aspect, the present application provides an electronic device that includes the foregoing first aspect and the content addressable storage device provided in combination with any one of the foregoing first aspect implementations, and the content addressable An external memory of the storage device, and a processor coupled to the content addressable storage device. The external memory is used to store necessary program instructions and data, the processor is used to run the necessary general operating system of the electronic device, and is used to couple with the content addressable storage device to complete the content addressable storage device Related processing functions. The electronic device may also include a communication interface for the electronic device to communicate with other devices or a communication network.

In an eighth aspect, the present application provides a computer storage medium that stores a computer program, and when the computer program is executed by a processor, it can implement any one of the above second aspect and in combination with the above second aspect The flow in the content addressable storage method provided by the implementation method.

In a ninth aspect, an embodiment of the present application provides a computer program, the computer program includes instructions, when the computer program is executed by a computer, the computer can execute the above-mentioned second aspect and any combination of the above-mentioned second aspect. The process in the content addressable storage method provided by the method.

Description of the drawings

FIG. 1A is a schematic diagram of the functional difference between RAM and CAM in the prior art;

FIG. 1B is a schematic diagram of a typical CAM structure in the prior art;

2 is a schematic diagram of processing a simulated CAM based on Memory address traversal provided by an embodiment of the application;

3 is a schematic diagram of an extended bit-width analog CAM processing based on Memory address traversal provided by an embodiment of the application;

4 is a schematic structural diagram of a content addressable storage device provided by an embodiment of the present application;

5 is a schematic structural diagram of another content addressable storage device provided by an embodiment of the application;

FIG. 6 is a schematic structural diagram of another content addressable device provided by an embodiment of this application;

FIG. 7 is a sequence diagram of comparison of a comparison unit provided by an embodiment of the application;

FIG. 8 is a schematic flowchart of a content addressable storage method provided by an embodiment of the present application.

Detailed ways

The embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

The terms "first", "second", "third" and "fourth" in the description and claims of the application and the drawings are used to distinguish different objects, rather than describing a specific order . In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes unlisted steps or units, or optionally also includes Other steps or units inherent to these processes, methods, products or equipment.

Reference to "embodiments" herein means that a specific feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art clearly and implicitly understand that the embodiments described herein can be combined with other embodiments.

The terms "component", "module", "system", etc. used in this specification are used to denote computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, the component may be, but is not limited to, a process, a processor, an object, an executable file, an execution thread, a program, and/or a computer running on a processor. Through the illustration, both the application running on the computing device and the computing device can be components. One or more components may reside in processes and/or threads of execution, and components may be located on one computer and/or distributed among two or more computers. In addition, these components can be executed from various computer readable media having various data structures stored thereon. The component may be based on, for example, a signal having one or more data packets (such as data from two components interacting with another component in a local system, a distributed system, and/or a network, such as the Internet that interacts with other systems through signals) Communicate through local and/or remote processes.

First, some terms in this application are explained to facilitate the understanding of those skilled in the art.

(1) System-on-Chip (SoC), SoC is called system-on-chip, also called system-on-chip, which means that it is a product, an integrated circuit with a dedicated target, which contains a complete system and has embedded software The entire contents of. At the same time, it is a kind of technology to realize the whole process from determining system functions to software/hardware division and completing the design.

(2) Random Access Memory (RAM), used to store and save data. It can be read and written at any time. RAM is usually used as a temporary storage medium for operating systems or other running programs (which can be called system memory). RAM cannot retain data when the power is turned off. If you need to save data, you must write them into a long-term storage (such as a hard disk).

(3) Random access memory RAM can be further divided into two categories: Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM). The basic principles of the two have the same place, they both store the charge inside the memory. Among them, the structure of SRAM is more complicated, the capacity per unit area is small, and the access speed is fast; DRAM has a simple structure and stores per unit area. The capacity is relatively large, and the access time is slower than that of SRAM. At the same time, DRAM has a relatively simple structure, and the stored charge will gradually disappear over time, so it needs to be recharged regularly (Refresh) to maintain the data stored in the capacitor.

(4) Double Data Rate Synchronous Dynamic Random Access Memory (Dynamic Random Access Memory, DDR SDRAM), abbreviated as DDR, DDR memory is developed on the basis of SDRAM memory, and still uses the SDRAM production system. As far as memory manufacturers are concerned, they only need to slightly improve the equipment for manufacturing ordinary SDRAM to realize the production of DDR memory, which can effectively reduce costs. Compared with the traditional single data rate, DDR technology implements two read/write operations in one clock cycle, that is, one read/write operation is performed on the rising and falling edges of the clock.

(5) Read Only Memory (ROM) is a solid-state semiconductor memory that can only read data stored in advance. Its characteristic is that once the data is stored, it cannot be changed or deleted. It is usually used in electronic or computer systems that do not need to change data frequently, and the data will not disappear because the power is turned off.

(6) Field Programmable Gate Array (Field Programmable Gate Array, FPGA) is further developed on the basis of programmable array logic (PAL), general array logic (GAL), complex programmable logic device (CPLD) and other programmable devices The product. It emerged as a semi-custom circuit in the field of application-specific integrated circuits (ASIC), which not only solves the deficiencies of custom circuits, but also overcomes the shortcomings of the limited number of gate circuits of the original programmable devices.

(7) Emulator (Emu) refers to a device or program that can simulate almost 100% of all the characteristics and behaviors of a hardware or software system. Its purpose is to completely simulate the simulated hardware receiving various external information. Time reaction.

(8) The Round Robin Scheduling algorithm is to sequentially request scheduling/processing ready task queues or processes in a cyclic manner.

(9) Lookup Table (LUT) is essentially a RAM. At present, 4-input LUTs are mostly used in FPGA, so each LUT can be regarded as a RAM with 4-bit address lines. When the user describes a logic circuit through schematic diagram or HDL language, the PLD/FPGA development software will automatically calculate the logic in the future All possible results of the circuit, and the truth table (ie results) is written into RAM in advance, so that each input of a signal for logic operation is equivalent to inputting an address to look up the table, find out the content of the address, and then output it.

(10) Packets per second (pps) is a commonly used unit of network throughput (that is, how many packet data packets are sent per second). The performance of the network is usually measured by throughput. The packet forwarding rate indicates the ability of the switch to forward data packets. Generally, the packet forwarding rate of a switch ranges from tens of Kpps to hundreds of Mpps. The packet forwarding rate refers to how many millions of data packets (Mpps) the switch can forward per second, that is, the number of data packets that the switch can forward at the same time. The packet forwarding rate reflects the switching capability of the switch in units of data packets.

(11) Throughput. Throughput refers to the amount of data (measured in bits, bytes, etc.) that are successfully transmitted to a network, device, port or other facility in a unit of time. In case of loss, the maximum data rate that the device can receive and forward. The throughput is mainly determined by the internal and external network port hardware of the network equipment, and the efficiency of the program algorithm, especially the program algorithm. For devices that require a lot of calculations, the low efficiency of the algorithm will reduce the communication volume.

In order to facilitate the understanding of the embodiments of the present application, the following further analyzes the specific technical problems to be solved by the application embodiments and the corresponding actual application scenarios. Because CAM is performing content search, its highly parallel search feature is based on the comparison circuit in each memory cell in the CAM array. That is to say, the CAM array structure in CAM is different from ordinary memory (such as Memory, RAM, etc.) in the data storage array structure, that is, CAM cannot use the general Memory structure to implement content-based addressing functions. The following provides two solutions that can utilize the general Memory structure to realize the content addressable storage function:

Solution 1: Simulation CAM based on Memory address traversal:

The solution can be simply described as: initially store the item data to be matched in the Memory, and after each subsequent single query is started, read all the item data of the memory depth according to the address traversal method. During the reading process , And compare the target matching data (ie the search input data in this application) and read the table entry data (ie the data items in this application) one by one at the same time. When the address traversal is over, complete a simulated CAM process; Wait for the end of the last query, and then repeat the above complete address traversal process. As shown in FIG. 2, FIG. 2 is a schematic diagram of processing a simulated CAM based on Memory address traversal provided by an embodiment of the application. It is assumed that the addresses corresponding to all entry data in the Memory are 0, 1, 2, 3, 4, and 5. , 6, 7, T ₀ represents the start time of the first query, T ₁ represents the start time of the second query, and T ₃ represents the start time of the third query. Among them, it can be seen that the second query can only be started after the first query is completed at the earliest. There is no overlap between the time slices of each single query, and only one query request is processed at the same time. The above scheme is a serial comparison method, and uses a general memory structure, with relatively low cost and power consumption, low back-end risk (that is, the feasibility risk of converting the logical design into a physical circuit is low), and the flexibility is high.

The shortcomings of the above-mentioned processing structure: due to the processing delay of the address traversal for a single query, the throughput is small and the performance is low.

Scheme two, analog CAM with extended bit width based on Memory address traversal:

This scheme can be simply described as increasing the memory word width of Memroy on the basis of scheme one above, for example, widening to the word width of 2 entry data, and comparing 2 entry data at a time, the memory depth can be reduced At the same time, the processing delay is reduced accordingly. Among them, the single query time is reduced to half of the original, and two entries are compared in one clock cycle. As shown in FIG. 3, FIG. 3 is a schematic diagram of an extended bit-width analog CAM processing based on Memory address traversal provided by an embodiment of the application. 4, 5, 6, 7, T ₀ represents the start time of the first query, T ₁ represents the start time of the second query, and T ₃ represents the start time of the third query. Among them, it can be seen that the data of two entries can be compared in each clock cycle, and the single query time is reduced to half of the original. However, the second query can only be started after the first query is completed at the earliest. There is still no overlap between single query time slices, and only one query request is processed at the same time. That is to say, the above scheme can also be understood as a serial comparison method, and a general memory structure can also be used, with relatively low cost and power consumption, low back-end risk, and high flexibility.

The shortcomings of the above processing structure: make the memory word width significantly wider and the depth significantly smaller, but the actual resource optimized memory shape generally has certain constraints, the above changes may lead to the deterioration of the memory selection, and extreme scenarios may lose the high integration of the memory The advantage of high-speed storage is ultimately reflected in the increase in chip area and power consumption.

By analyzing the application scenarios of general network systems, it is found that there is usually no need to meet the extreme performance requirements of a query request that needs to be initiated every system clock cycle. Typically, such as Ethernet packet processing, query by packet is generally sufficient. Query by byte, and the packet rate is much smaller than the byte rate of the packet, so there will usually not be a large number of query requests in a short time; but in the short packet burst scenario, if the table entry depth is long (the data item to be matched) If the number is large), the pps performance of the above scheme 1 may not meet the performance requirements, because the table entry depth is long, resulting in a long single query time, and there is no time overlap between single queries, resulting in short packets In a sudden scenario, the network throughput rate cannot be guaranteed; however, the CAM in the prior art and the above-mentioned solution 2 will optimize the network throughput rate compared to the above-mentioned solution 1, but there are problems of resource, power consumption degradation or matching flexibility.

In summary, the existing content-based addressing scheme cannot meet the performance of the network. Therefore, a flexible CAM with low power consumption, small area, strong portability, and strong scalability provided in this application is used to solve the above technical problems.

Based on the foregoing, the content addressable storage device and related equipment provided in the embodiments of the present application are described below. Please refer to FIG. 4, which is a schematic structural diagram of a content addressable storage device provided by an embodiment of the present application. The content addressable storage device 40 may include a scheduler 401, a comparator 402, a memory 403, and a memory 404. , Where the comparator 402 includes N comparison units 4021, and the N comparison units are respectively coupled to the memory 403, where N is an integer greater than 1; optionally, the aforementioned scheduler 401, comparator 402, memory 403, and memory 404 Can be located on an integrated circuit substrate. among them,

The memory 404 is used to store data to be matched. The data to be matched are multiple data items that need to be matched for the K search data acquired by the scheduler 401, that is, each search data needs to be matched with the data to be matched , So as to get the corresponding matching result. The data to be matched can be obtained in various ways, such as static configuration, dynamic learning, and so on. Before any target comparison unit 4021 starts to compare search data, the controller 404 controls the memory 404 to write the data to be matched. Optionally, the controller 403 may also control the memory 404 to write new data to be matched or modify the data to be matched when the control memory 404 reads the data to be matched. That is, the controller 403 can control the memory 404 to write the data to be matched into the memory 403 in a read-and-write manner. For example, for a system that requires online refreshing of the data to be matched, you can select an independent read/write Two-port memory is used to read and update or modify the data to be matched; if a single-port memory is selected, the controller 403 can insert some additional refresh time when the memory 404 is controlled to read the data to be matched To complete the refresh of the data to be matched, some query speed may be reduced at this time. The refresh time refers to the increase of the address sequence of the pause query (read table item/data item) during refresh (write table entry/data item) ( At the same time, the write enable is invalid). After the write is completed, the query is re-enabled (read enable, read address sequence increases).

In a possible implementation, the storage structure of the memory 404 may be in the form of a storage array. The storage array is composed of many basic storage units. Each basic storage unit stores a binary number (1 or 0), called bit (bit ), and a row of storage units constitutes a word of the memory 403 (also called data items, data table items, table items, etc.), W is the "word width or bit width", the number of all words in the memory array K Called "depth", the capacity of the memory 403 is characterized by (K words×W bits). Unlike the CAM in the prior art, the memory 403 has no data comparison function, that is, it does not include a comparison circuit. Therefore, a general memory structure can be adopted. For example, the memory 403 can be a general random access memory (Random Access Memory, RAM) or volatile storage devices under power failure, such as static random access memory (Static Random Access Memory, SRAM), dynamic random access memory (Dynamic Random Access Memory, DRAM) or synchronous dynamic random access memory (Synchronous DRAM, SDRAM) , Double Data Rate SDRAM (Dual Data Rate SDRAM, DDR SDRAM), etc.; the memory 403 can also be a general read only memory (Read Only Memory, ROM) or non-power-down volatile memory, such as programmable ROM (Programmable ROM, PROM), Erasable Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), Flash ROM (FLASH ROM), etc.; the memory 403 can also be a processor General-purpose registers, flash memory, or any other suitable type of memory on the computer. It is understandable that if the memory 403 is a RAM, the data to be matched can be changed. If the memory 403 is a ROM, the data to be matched is the data solidified in the memory 403. It should be noted that this application does not specifically limit the specific form in which the memory 404 stores the data to be matched, and relevant changes can be made according to actual needs or business conditions.

The scheduler 401 is configured to obtain K search data and respectively schedule the K search data to K target comparison units among the N comparison units, where the target comparison unit is a comparison unit in an idle state, K is an integer greater than or equal to 1 and less than or equal to N. For example, when the scheduler 401 receives a query request, and the query request includes search data, search type, etc., it indicates that the content addressable storage device 40 needs to perform a search data search operation. At this time, the scheduler 401 needs to allocate a corresponding comparison unit for the search data to search for matching results. When there are multiple query requests, the scheduler 401 needs to allocate different target comparison units for different query requests; According to the dynamically received query request, and combined with the current status of the N comparison units 4021 in the comparator 402, 401 dynamically selects an available target comparison unit (which can be any comparison unit 4021 in FIG. 4), and starts or The query function of the target comparison unit is enabled, and the search data is sent to the target comparison unit 4021, thereby completing the allocation and scheduling of query requests to query resources. Among them, the K search data acquired by the scheduler 401 may be acquired at the same time or at different times, that is, the K search data may be scheduled to K target comparison units at the same time, and It may be scheduled to K target comparison units first, and may depend on the order in which the K search data reaches the scheduler, or it may depend on the scheduler 401 preset or flexible scheduling rules. The application embodiment does not specifically limit this. For example, the scheduler 401 can schedule a certain search data to a certain target comparison unit immediately after receiving it, or it can schedule the scheduler 401 to the corresponding target comparison unit after receiving a certain amount of search data. The target comparison unit. It should be noted that the scheduler 401 may receive a large number of query requests at a certain moment or time period, that is, a large amount of search data. At this time, due to the limited number of comparison units in the comparator 402, the scheduler The device 401 can be based on certain traffic shaping control, that is, currently only obtain K search data among them for query, and after there are free comparison units in the future, other search data scheduling can be performed to avoid search data congestion or throw away.

The controller 403 is configured to control the memory 404 to read the data to be matched and send them to the K target comparison units respectively. When a comparison unit in the comparator 402 is selected as the target comparison unit, that is, when one or more comparison units need to perform a search operation, the comparator 402 can notify the status information (idle state or use state) of the target comparison unit to The controller 403 completes the read-write enable combined control of the controller 403 by the comparator 402, and finally controls the output of the memory 404. In other words, when at least one comparison unit in the comparator 402 is selected as the target comparison unit, then the controller 403 needs to control the memory 404 to continuously read the data items to be matched, because the memory 404 needs to be controlled. The port remains in a readable state, and the read operation is realized. Optionally, the scheduler 401 may also notify the controller 403 of the status information of the target comparison unit to complete the read-write enable combination control of the controller 403 by the comparator 402, which is not specifically limited in this embodiment of the application. The structure in FIG. 4 is based on the example notified by the comparator 402 to the controller 403. It can be understood that if the controller 403 is notified by the scheduler 401, a communication connection is required between the scheduler 401 and the controller 403. I will not repeat them here. Under the control of the controller 403, the memory 403 sends the read data to be matched to the K target comparison units respectively, which may be broadcast to N comparison units (including the K target comparison units), optionally Yes, it may also be sent only to the K target comparison units. For example, when the controller 403 learns through the scheduler 401 or the comparator 402 that there is currently a comparison unit 4021-2 and a comparison unit 4021-4 as target comparison units to perform a comparison operation of search data, the controller 403 controls the memory 404 to read The output data to be matched is broadcast to the N comparison units, or only sent to the comparison unit 4021-2 and the comparison unit 4021-4. It should be noted that if the memory 404 only sends the read data to be matched to the K target comparison units, then the memory 404 needs to know which comparison units are currently the target comparison units. The status information of each comparison unit (notified by the scheduler 401 or notified by the comparator 402) learned by the controller 403 controls the output of the memory 404.

Further, before the search operation starts, the controller 403 is further configured to control the memory 404 to write the data to be matched in a preset manner. The controller 403 may complete the initial configuration control of the data to be matched in a preset manner under the control of the external or internal processor of the device in the initial stage. For example, after the content addressable storage device 40 is powered on, before entering the data search operation, the controller 403, under the control of the external processor, first completes the initialization process of the memory 404, such as defining the matching word width and output result bit width , Select the read/write mode of the data table item (data to be matched), enumerate the addresses of all the data to be matched, and write the data to be matched corresponding to the address to the memory 404, etc., and the to be matched The content of the data depends on the specific business requirements.

The comparator 402 includes N comparison units 4021 for searching data, that is, a collection of comparison units 4021-1, 4021-2, ... 4021 -N in FIG. 4. Since the N comparison units in the comparator 402 are respectively coupled to the memory 404, as shown in FIG. 4, there is a physical connection between each comparison unit 4021 and the memory 404, that is, the comparison between the N comparison units 4021 is parallel. The structure and the search process do not interfere with each other, and there can be no correlation between the start time of the search and the search data. When an idle comparison unit 4021 is selected as the target comparison unit, the target comparison unit compares the search data sent by the scheduler 401 with the data to be matched sent from the memory 404, and determines the search data according to the comparison result The matching result. The matching result includes one or more of matching indication information, a matching data item of the corresponding search data, and an address of the matching data item, wherein the matching indication information is used to indicate whether there is a matching data item. For example, in practical applications, it may not be necessary to completely traverse all data items, such as only taking the result of the first match or only judging whether there is a match. In this case, it is not necessary to traverse all the data items completely to speed up the response or reduce Turnover power consumption; the corresponding matching result can be maintained with a fixed delay or output immediately, which can be determined according to the requirements of other components of the system. That is, in some cases, it is only necessary to find whether there is a matching item, and in some cases, it is necessary to find a specific match or the address corresponding to the match. It is understandable that, in addition to logical resources such as a comparison circuit, each comparison unit 4021 may also include maintenance control of necessary information such as its own comparison status, and a register for storing search data sent by the scheduler 401.

In a possible implementation manner, when the search data received by the scheduler 401 within the preset time period exceeds the preset number, or when there is no idle comparison unit currently, the scheduler 401 also controls the preset time interval After that, an idle target comparison unit is determined from the N comparison units. That is, when the throughput in the network is high, such as when the maximum pps of the instantaneous burst is large, or when there is no idle comparison unit, it can be improved by the traffic shaping processing method, that is, the comparison is controlled after a certain period of time. The adaptability of the content addressable storage device in the embodiment of the present application reduces the demand for instantaneous comparison of resources.

In Figure 4 above, the scheduler 401 selects an idle target comparison unit from N comparison units 4021, or before the controller 403 determines which comparison unit to send the currently read data to be matched, it can be compared Each comparison unit 4021 in the device 402 sends its own status information (idle or use status) directly to the scheduler 401 and/or the controller 403, or each comparison unit 4021 sends the status information uniformly to some of the comparators 402. A state merging module collects, and then the state merging module sends all the summarized state information to the scheduler 401 and/or the controller 403, which is not specifically limited in the embodiment of the present application.

As shown in FIG. 5, FIG. 5 is a schematic structural diagram of another content addressable storage device provided by an embodiment of the application, in which the scheduler 401 and the N comparison units 4021 are connected in parallel through N physical connections 001 The idle state or use state of the N comparison units 4021 can be reflected on the physical connection 001 in the form of level changes, and the scheduler 401 can perceive each comparison unit 4021 according to the voltage change on the physical connection 001 The current idle or use status. For example, when the comparison unit 4021 is in an idle state, the scheduler 401 keeps the physical connection 001 between it at low level, and when the comparison unit 4021 is in use, the scheduler 401 pulls the physical connection 001 between it high Level. When the idle comparison unit 4021 is selected as the target comparison unit, the target comparison unit (such as the target comparison units 4021-2, 4021-4, and 4021-5 in FIG. 5) can receive the scheduler 401 through the corresponding Search data (search data a, search data b, search data c) sent by physical connections (001a, 001b, 001c in Figure 5), and store the corresponding search data.

Further, each comparison unit 4021 in the comparator 402 can feed back its current state information (idle state or use state) to the controller 403 through the physical connection 002, and the controller 403 learns and counts the current status through the physical connection 002. Which comparison units are performing the search operation, and control the data to be matched in the memory 404 to be gradually sent to the corresponding target comparison unit through the physical connection 003 in parallel.

Suppose there are currently three search data: search data a, search data b, and search data c. The comparison units selected by the scheduler 401 for it are target comparison unit 4021-2, target comparison unit 4021-4, and target comparison unit 4021- 5. After the search operation functions of 4021-2, 4021-4 and 4021-5 are turned on, the comparator 402 notifies the controller 403 of the enabled state of the target comparison unit (it can also be notified by the scheduler 401) After the controller 403 obtains the state information of the comparison unit, it combines the states of the N comparison units, that is, 4021-2, 4021-4, and 4021-5 are all enabled states, and other comparison units are in the non-enabled state. The controller 403 combines the state of the comparison unit and the initialization control of the memory 404 to send the combined control information to the memory 404, thereby controlling the stepwise reading of data items and sending them to the target comparison unit 4021-2 in the enabled state in parallel. , 4021-4 and 4021-5. For example, according to the address polling method, each clock cycle sends a data item (or multiple data items) to the target comparison units 4021-2, 4021-4, and 4021-5 in parallel, depending on the comparison unit 4021 and the memory The bit width relationship between 404). Finally, the target comparison units 4021-2, 4021-4, and 4021-5 will gradually read the stored search data and the controller 403 control from the memory 404 and pass them through the corresponding physical connections (003a, 003b, 003c in Figure 5). ) The sent data items are gradually compared until the final matching result of the search data is obtained. It can be understood that the time when each comparing unit 4021 starts to search may be at the same time or at different times, that is, searching data between different comparing units 4021 does not affect each other and does not interfere with each other.

In a possible implementation manner, the data to be matched includes M data items; the controller 403 is specifically configured to control the memory to read out the M data items in sequence according to the address traversal mode and send them to each The K target comparison units can be sent only to K target comparison units (comparison units 4021-2, 4021-4, 4021-5 in Figure 5), or broadcast to N comparison units (as shown in Figure 5). 5 in the comparison unit 4021-1, 4021-2, ... 4021-N); each of the K target comparison units is specifically configured to sequentially compare the corresponding search data with the M pieces of data The items are compared to determine the matching data items of the corresponding search data. In the embodiment of the present application, the M data items stored in the memory are serially read out through address traversal, and are gradually sent to the corresponding target comparison unit for comparison, so as to obtain the corresponding matching result. Optionally, it can be read one by one, that is, one data item is one data item, or two two data items, that is, two data items, two data items, or multiple data items. Reading multiple data items.

As shown in FIG. 6, FIG. 6 is a schematic structural diagram of another content addressable device provided by an embodiment of the application. The content addressable device 40 in FIG. 6 further includes a result output register 405, and N comparison units 4021, respectively Coupled to the result output register 405; the target comparison unit also sends the matching result to the result output register 405, and the result output register 405 receives and stores the matching result. Since the N comparison units 4021 are respectively coupled to the result output register 405 in the content addressable storage device 40 through the physical connection 004, when any one of the N comparison units 4021 completes the matching of the search data , The matching result can be sent to the result output register 405 through the corresponding physical connection 004 in parallel. Optionally, the memory 404 reads data in an address polling manner under the control of the controller 403, so that the read data can participate in independent queries of multiple comparison units at the same time. In a possible implementation manner, the comparator 402 of the content addressable device 40 in FIG. 6 further includes a state combining module 4022, and each comparing unit 4021 sends the state information to the state combining module 4022 in the comparator 402 in a unified manner. After summarizing, the state merging module 4022 sends all the summarized state information to the controller 403. Optionally, the number of comparison units N is greater than or equal to (instantaneous burst maximum pps)*(static table lookup period), where the instantaneous burst maximum pps can be determined by the minimum period of the actual query request, and the static table lookup period is Refers to the time to traverse the lookup table address (the address of the data to be matched). In practical applications, it can be combined with the existing traffic shaping module of the system to reduce peak pps.

For example, as shown in FIG. 7, FIG. 7 is a sequence diagram for comparison of the comparison unit provided by the embodiment of the application. In FIG. 7, they are marked as T0, T1, T2, T3, T4, T5 in chronological order, corresponding to The first query, the second query, the third query, the fourth query, the fifth query, and the sixth query, where the first query and the fourth query (T0 and T3) are made by the comparison unit 402-2, the second query and the fifth query (T1 and T4) are executed by the comparison unit 402-4, the third query and the sixth query (T2 and T5) are executed by the comparison unit 402- 5 executed. That is to say, each comparison unit can perform the search data query in parallel, and each comparison unit returns to the idle state after a single query is completed, and the next round of search data query can be performed, for example, the comparison unit 402 -2 Start the query of search data a at time T0, after completing the query of search data a, you can start a new query of search data d, and in the process of comparing search data a, the comparison unit 402-2 compares The unit 402-4 starts the search for the search data b, and then starts the search for the search data e. It should be noted that all the data to be matched in the memory 404 is read out in the form of address polling. From the timing point of view, it is the address of the data to be matched in FIG. , As long as there is a comparison unit currently inquiring about the corresponding search data, the controller 403 will control the data in the memory 404 to keep cyclically reading, and each comparison unit does not start the comparison from the lowest or highest address Data items are compared. For example, at T1, the comparison starts from address 6, and at T3, the comparison starts from address 2. That is, the data items that all target comparison units start to compare depend on the data currently read from the memory 404. The time period corresponding to address 5 (hold) in Figure 7 is currently because no comparison unit is executing the query task. At this time, if the data to be matched is output, resources will be wasted, and if the comparison unit passes the high and bottom levels Instruct the controller 403, and at this time the N comparison units are all in the low state, the controller 403 will control the reading and matching of the pause data. When the search data is sent to the comparison unit 402-5 at time T5, the controller 403 continues to read the suspended data item and sends it to the comparison unit 402-5 for comparison.

In a possible implementation manner, among the N comparison units, K comparison units are currently performing search data comparison, and different comparison units correspond to different search data, where K is less than or equal to M A positive integer; the data to be matched includes M data items; the controller 403 is specifically used to control the memory 404 to read out L data items in each clock cycle through address polling, and to read the L data items The data item is broadcast to the N comparison units, and L is a positive integer less than or equal to M; each comparison unit in the K comparison units is used to compare the L data items received each time with the corresponding search Compare the data. That is, when there are multiple search data for searching, there are corresponding multiple comparison units performing the search operation at the same time. It can be specifically that the controller 403 controls the memory 404 to read out L data items in each clock cycle and broadcast Among the N comparison units, optionally, it can also be sent in parallel only to the target comparison unit currently performing the search operation, and each target comparison unit currently performing the search operation compares the L pieces of data received each time with The search data stored by itself is compared to obtain the corresponding matching result. For example, assuming that M=64, N=8, L=2, and K=4, the comparator 402 includes 8 comparison units, and currently 4 target comparison units are performing data comparisons. The controller 403 starts data comparison every clock cycle. Among the 64 data items to be matched, 2 data items are read out and sent to the above 4 target comparison units in parallel (or broadcast to the above 8 comparison units), and each target comparison unit will receive the data each time 2 data items are compared with the search data stored by itself, among which, for each target comparison unit, it can get a matching result (compared with all or part of all 64 data items to be matched). The search operation of the comparison unit is stopped. At this time, the controller 403 can control the data item read from the memory to no longer be sent to the comparison unit that has completed the search operation task.

In a possible implementation, the bit width of each of the N comparison units is L times the bit width of each of the M data items. That is, the bit width of each comparison unit in the comparator 402 can be L times the bit width of each data item in the data to be matched stored in the memory 404. At this time, the comparison unit can perform L in each clock cycle. Comparison of data items. For example, if the bit width of each data item is W and the comparison unit comparison bit width is L*W, then the comparison unit can complete the comparison of L*W bit/bit data in one clock cycle. The embodiments of this application can further balance the performance and cost by expanding the word width within the range that the model selection allows and the evaluation of the back-end impact is reasonable. Within the range of relatively low cost and power consumption, multiple comparisons can be performed simultaneously through one clock cycle To speed up the query speed.

In a possible implementation, when multiple matching results appear, a priority encoder (priority) may be added to the content addressable device 40, which is located between the comparison unit 4021 and the result output register 40, and the priority encoder The matching result with the highest priority (for example, the data item at the lowest position of the address) is encoded and output.

In a possible implementation manner, a matching address history register can be added to the content addressable device 40. When a match occurs for the first time, the address where the match occurred is recorded. When a subsequent match occurs, the recorded address is compared. The relative size of the new matching address is used to determine whether to update the matching result and the matching address history register. For example, in the low address priority strategy, the new small matching address and result can always be used to refresh the old large matching address and result.

In a possible implementation, the data to be matched includes M data items, where each data item includes content to be matched, query control information, and output results; each of the K target comparison units A target comparison unit is specifically configured to compare the corresponding search data with the content to be matched in each data item according to the query control information of the M data items, and to output the result in the matched data item Output as the matching result of the corresponding search data. That is, in the above search, the query control information and the corresponding output result (for example, the output result is the address corresponding to the content to be matched) can be carried in the data item contained in the data to be matched, where the query control information may include : The min max range or bit mask used in the specific comparison or combined with other logical operations can be determined based on system requirements. For example, the data items stored in the memory can be defined as a ternary data set of {content to be matched, query control information, output result}, such as one or more data items = {min, max, mask, item_en, The multivariate data group of result} means that when the search data to be queried meets min=<(d0&mask)<=max and item__en is equal to 1, then the data item is the matching data item of the search data, and the result can be output at this time , Which is the matching result in this application.

It should be noted that the scheduler 401 of the content addressable storage device 40 in the foregoing FIGS. 4 to 6 may be a hardware circuit module or a functional device that runs software. Similarly, the controller 403 may also be a hardware circuit module or a functional device running software. It is understandable that under normal circumstances, the use of hardware circuit modules is faster than the use of software to implement corresponding functions. The above scheduler 401 can be deployed inside the controller 403, that is, it is considered to be a part of the controller 403 in physical form or integrated with the controller 403; alternatively, the scheduler 401 can also be deployed outside the controller 403 Of course, it can also be partially deployed inside the controller 403 and the other part deployed outside the controller 403, which is not specifically limited in the embodiment of the present application.

It should be noted that the content addressable storage device in this application can have three operating modes: read mode, write mode and matching mode. In the read and write mode, the way of data access and operation in the memory is the same as in the ordinary memory. The matching mode can realize the content-based search function implemented by the content-addressable storage device in Figures 4-6.

The data search function of the content addressable storage device in this application can be used in various application scenarios such as virtual memory, data compression, pattern recognition, image processing, high-speed caching, and table lookup applications. For example, when performing Media Access Control Address (MAC) address retrieval, the switch (the switch may include any of the content addressable storage devices described in this application) first uses the MAC address as the key ( Search data) retrieve the corresponding index value through the MAC-CAM table (that is, the data to be matched in this application). Among them, on the Ethernet, the MAC-CAM table maintains a piece of data for layer 2 switching for the switch Address table (usually called "CAM table"), which maintains the correspondence between MAC addresses and outbound interfaces. In this way, whenever the switch receives an Ethernet data frame, the switch will make a judgment. Extract the destination MAC address of the data frame, if the data frame is not sent to yourself, query the CAM table according to the destination MAC address of the data frame; if it can be hit (the so-called hit, it is to find the corresponding MAC address in the CAM table The forwarding item), the forwarding is performed according to the result of the query (usually an outbound interface list); if it cannot be hit, the data frame is broadcast to all ports. This CAM table of the switch can be obtained in many ways, such as static configuration and dynamic learning.

When the content addressable storage device in this application only needs to simulate a general CAM operation, it can only use a set of table item storage resources (data to be matched), and by adding a small amount of control logic, the throughput can be linearly doubled ( pps) performance, without the need to significantly change the memory shape (relative to the original look-up table matching requirements), while ensuring throughput and realizability, without losing cost and power consumption advantages. If you need more flexible dynamic table lookup requirements, you can conveniently store some operation information about table items in the memory at the same time, which can more conveniently support implementations such as table item enable, bit mask, value range mask, and disorder Additional features such as table item priority greatly improve the flexibility of table look-up matching processing. At the same time, in combination with specific scenarios, word width expansion can also be combined to further balance performance and area power consumption, and further improve energy efficiency ratio. In general, the content addressable storage device provided by this application includes at least the following advantages:

1. Low cost and power consumption, matching application scenarios are relatively low pps peak scenarios, avoiding the use of high-cost and high-power CAM structures, reducing cost (area) and power consumption (including average and peak values); at the same time, because the circuit is simpler, It can also reduce the risk of back-end engineering process;

2. Strong portability, because the general memory (such as Memory) structure can be used, the logic scheme is highly portable, Emu, FPGA and other scenarios can be directly integrated and realized, and the logic resources such as lut are low, which greatly reduces the inhibition Or verification cost;

3. Strong scalability, TCAM can be easily realized through a small amount of control and modification of table item content, and other complicated methods of fuzzy CAM processing, such as table item enable, such as fuzzy methods with min, max, etc. It is planned to perform dynamic matching processing in the contents of the Memory table; it is easier to achieve a fixed processing delay, and it is easy to form a pipeline structure in the overall processing of the system; it is easier to combine the expanded word width dimension to further improve the cost performance balance; it is easier to expand and realize online The dynamic entry update operation satisfies business scenarios with high online requirements; in some applications, other non-coexisting scenario memory (such as Memory) resources can be reused to further reduce costs.

Please refer to FIG. 8. FIG. 8 is a schematic flowchart of a content addressable storage method provided by an embodiment of the present application. The content addressable storage method is applicable to any of the above-mentioned figures 4-7. An address storage device and a device including the content addressable storage device, the content addressable storage device includes a comparator and a memory, the comparator includes N comparison units, and the N comparison units are respectively coupled to In the memory, N is an integer greater than 1; the method may include the following steps S801 to S804.

S801: Store data to be matched in the memory.

S802: Obtain K search data, and schedule the K search data to K target comparison units in the N comparison units, where the target comparison unit is a comparison unit in an idle state, and K is greater than or An integer equal to 1 and less than or equal to N.

S803: Read the data to be matched from the memory and send it to the target comparison unit.

S804: Compare the corresponding search data with the data to be matched through each of the K target comparison units, and output a corresponding matching result according to the comparison result.

In a possible implementation manner, the data to be matched includes M data items, and M is an integer greater than 1, and the control memory reads the data to be matched and sends them to the K data items respectively. Target comparison unit, including:

According to the address traversal mode, the memory is controlled to sequentially read the M data items and send them to the K target comparison units respectively; the corresponding search is performed by each of the K target comparison units. The data is compared with the data to be matched, and the corresponding matching result is output according to the comparison result, including: the corresponding search data is sequentially compared with the M pieces of search data through each of the K target comparing units. The data items are compared to determine the matching data items of the corresponding search data.

By means of address polling, the memory is controlled to read out L data items in each clock cycle, and the read L data items are broadcast to the N comparison units, where L is a positive integer less than or equal to M; Comparing the corresponding search data with the to-be-matched data through each of the K target comparison units includes: through each of the K comparison units, each comparison unit receives Compare the L data items with the corresponding search data.

It should be noted that, for the specific process in the content addressable storage method described in the embodiment of the present application, please refer to the related description in the application embodiment described in the foregoing FIG. 4 to FIG. 7, and will not be repeated here.

An embodiment of the present application further provides a computer storage medium, wherein the computer storage medium may store a program, and the program includes part or all of the steps of any one of the above method embodiments when executed.

The embodiments of the present application also provide a computer program, which includes instructions, when the computer program is executed by a computer, the computer can execute part or all of the steps of any content addressable storage method. In the above-mentioned embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in an embodiment, reference may be made to related descriptions of other embodiments.

It should be noted that for the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations, but those skilled in the art should know that this application is not limited by the described sequence of actions. Because according to this application, some steps may be performed in other order or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by this application.

In the several embodiments provided in this application, it should be understood that the disclosed device may be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the above-mentioned units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or integrated. To another system, or some features can be ignored, or not implemented. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical or other forms.

The units described above as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.

In addition, the functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or software functional unit.

If the above integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, the technical solution of this application essentially or the part that contributes to the existing technology or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , Including several instructions to make a computer device (which may be a personal computer, a server, or a network device, etc., specifically a processor in a computer device) execute all or part of the steps of the foregoing methods of the various embodiments of the present application. Among them, the aforementioned storage medium may include: U disk, mobile hard disk, magnetic disk, optical disk, read-only memory (Read-Only Memory, abbreviation: ROM) or Random Access Memory (Random Access Memory, abbreviation: RAM), etc. A medium that can store program codes.

Claims

A content addressable storage device, characterized in that it comprises:

Memory, used to store the data to be matched;

The comparator includes N comparison units, the N comparison units are respectively coupled to the memory, and N is an integer greater than 1;

The scheduler is used to obtain K search data and respectively schedule the K search data to K target comparison units among the N comparison units, where the target comparison unit is a comparison unit in an idle state, and K Is an integer greater than or equal to 1 and less than or equal to N;

A controller, configured to control the memory to read the data to be matched and send them to the K target comparison units respectively;

Each of the K target comparison units is used to compare the corresponding search data with the data to be matched, and output a corresponding matching result according to the comparison result.
8. The device according to claim 1, wherein the device further comprises a result output register, and the N comparison units are respectively coupled to the result output register; the data to be matched includes multiple data items;

Each of the K target comparison units is further configured to send a corresponding matching result to the result output register, and the matching result includes matching indication information, matching data items of corresponding search data, and One or more of the addresses of the matching data items, wherein the matching indication information is used to indicate whether there are matching data items;

The result output register is used to receive and store the matching results respectively sent by the K target comparison units.
The device according to claim 1 or 2, wherein the data to be matched includes M data items, and M is an integer greater than 1;

The controller is specifically configured to control the memory to sequentially read the M data items and send them to the K target comparison units according to the address traversal mode;

Each target comparison unit of the K target comparison units is specifically configured to sequentially compare the corresponding search data with the M data items to determine matching data items of the corresponding search data.
The device according to claim 1 or 2, wherein the data to be matched includes M data items;

The controller is specifically configured to control the memory to read out L data items in each clock cycle through address polling, and broadcast the read L data items to the N comparison units, where L is A positive integer less than or equal to M;

Each of the K comparison units is used to compare the L data items received each time with the corresponding search data.
The device according to claim 4, wherein the bit width of each of the N comparison units is L times the bit width of each of the M data items.
5. The device according to any one of claims 1-5, wherein the controller is further configured to control the memory to write the data to be matched in a preset manner.
The device according to any one of claims 1-6, wherein:

The scheduler is further configured to control the number of search data received within the preset time period to exceed the preset number, or when there is no free comparison unit currently Determine the target comparison unit in the comparison unit.
The device according to any one of claims 1-7, wherein the controller is further configured to control the memory to write new data in the process of controlling the memory to read the data to be matched. The data to be matched or modify the data to be matched.
The device according to claim 1, wherein the data to be matched includes M data items, wherein each data item includes content to be matched, query control information and output results;

Each of the K target comparison units is specifically configured to compare the corresponding search data with the content to be matched in each data item according to the query control information of the M data items, respectively, And output the output result in the matched data item as the matching result of the corresponding search data.
A content addressable storage method, characterized in that it is applied to a content addressable storage device, the device includes: a comparator and a memory, the comparator includes N comparison units, and the N comparison units are respectively coupled In the memory, N is an integer greater than 1. The method includes:

Storing data to be matched in the memory;

Acquire K search data, and dispatch the K search data to K target comparison units among the N comparison units, where the target comparison unit is a comparison unit in an idle state, and K is greater than or equal to 1. And an integer less than or equal to N;

Controlling the memory to read the data to be matched and send them to the K target comparison units respectively;

Through each of the K target comparison units, the corresponding search data is compared with the data to be matched, and the corresponding matching result is output according to the comparison result.
The method according to claim 10, wherein the device further comprises a result output register, and the N comparison units are respectively coupled to the result output register; the data to be matched includes multiple data items; The method also includes:

The matching result corresponding to each target comparing unit of the K target comparing units is sent to the result output register, and the matching result includes matching indication information, matching data items of corresponding search data, and matching data items One or more of the addresses in, wherein the matching indication information is used to indicate whether there is a matching data item;

The matching results respectively sent by the K target comparison units are received and stored through the result output register.
The method according to claim 10 or 11, wherein the data to be matched includes M data items, and M is an integer greater than 1; and the memory is controlled to read the data to be matched and respectively Sent to the K target comparison units, including:

According to the address traversal mode, control the memory to sequentially read the M data items and send them to the K target comparison units respectively;

The comparing the corresponding search data with the data to be matched by each of the K target comparing units and outputting the corresponding matching result according to the comparison result includes:

The corresponding search data is sequentially compared with the M data items by each of the K target comparison units to determine matching data items of the corresponding search data.
The method according to claim 10 or 11, wherein the data to be matched includes M data items, and M is an integer greater than 1; and the memory is controlled to read the data to be matched and respectively Sent to the K target comparison units, including:

By means of address polling, the memory is controlled to read out L data items in each clock cycle, and the read L data items are broadcast to the N comparison units, where L is a positive integer less than or equal to M;

Comparing the corresponding search data with the to-be-matched data through each of the K target comparison units includes:

Through each of the K comparison units, the L data items received each time are compared with the corresponding search data.
The method according to claim 13, wherein the bit width of each of the N comparison units is L times the bit width of each of the M data items.
The method according to any one of claims 10-14, wherein the method further comprises:

Controlling the memory to write the data to be matched in a preset manner.
The method according to any one of claims 10-15, wherein the method further comprises:

When the search data received within the preset time period exceeds the preset number, or there is no free comparison unit currently, control is controlled to determine the target comparison unit from the N comparison units after the preset time interval.
The method according to any one of claims 10-16, wherein the method further comprises:

In the process of controlling the memory to read the data to be matched, the memory is controlled to write new data to be matched or modify the data to be matched.
The method according to claim 10, wherein the data to be matched includes multiple data items, wherein each data item includes the content to be matched, query control information, and output results;

The comparing the corresponding search data with the data to be matched by each of the K target comparing units and outputting the corresponding matching result according to the comparison result includes:

Through each of the K target comparison units, according to the query control information of the M data items, the corresponding search data is compared with the content to be matched in each data item, and The output result in the matched data item is output as the matching result of the corresponding search data.
A semiconductor chip, characterized in that it comprises:

The content addressable storage device according to any one of claims 1 to 9, a processor coupled to the content addressable storage device, and a memory external to the content addressable storage device.
An electronic device, characterized in that it comprises:

The content addressable storage device according to any one of claims 1 to 9, and a discrete device coupled to the content addressable storage device.