WO2020232815A1

WO2020232815A1 - Array substrate structure of thin film transistor liquid crystal display

Info

Publication number: WO2020232815A1
Application number: PCT/CN2019/096118
Authority: WO
Inventors: 严雅静; 邹恭华
Original assignee: 武汉华星光电技术有限公司
Priority date: 2019-05-21
Filing date: 2019-07-16
Publication date: 2020-11-26
Also published as: CN110232896A

Abstract

Disclosed is an array substrate structure of a thin film transistor liquid crystal display. The array substrate structure of a thin film transistor liquid crystal display comprises a plurality of pixel blocks, wherein each pixel block is connected to a low operation compensation unit or a high operation compensation unit, and each pixel block outputs a signal through the low operation compensation unit or the high operation compensation unit. The pixel blocks are connected to the low operation compensation unit or the high operation compensation unit, such that the influence of a cancellation voltage on a display signal is reduced, the defect of charging states of the pixel blocks being inconsistent is overcome, and a regular compensation effect is formed in space.

Description

Thin film transistor liquid crystal display array substrate structure

Technical field

The present disclosure relates to the field of display technology, in particular to the structure of a thin film transistor liquid crystal display array substrate.

Background technique

In a liquid crystal display, each pixel has a thin film transistor whose gate is connected to the horizontal scan line, and the drain is connected to the vertical data line. If a forward voltage is applied to a certain horizontal scan line, the thin film transistor switch on the scan line is turned on. At this time, the pixel electrode on the scan line is connected to the data line in the vertical direction, and the data on the data line The signal is input to the pixel to control different liquid crystal transmittance and display effect.

Because in the gate drive circuit substrate (Gate on Array, GOA) circuit manufacturing process, each thin film transistor switch will inevitably have some differences, when reflected on the operational amplifier, a slight offset voltage will be formed. As a result, the opening degree of the thin film transistor switch on the scan line is different, thereby affecting the display effect of the display.

Therefore, there is a need to provide a thin film transistor liquid crystal display array substrate structure to solve the problems in the prior art.

technical problem

During the manufacturing process of the gate drive circuit substrate (Gate on Array, GOA) circuit, there will inevitably be some differences in each thin film transistor switch, and when reflected on the operational amplifier, a slight offset voltage will be formed. As a result, the opening degree of the thin film transistor switch on the scan line is different, thereby affecting the display effect of the display.

Technical solutions

In order to solve the above-mentioned problems, the present disclosure proposes a thin film transistor liquid crystal display array substrate structure to compensate for the inconsistency of the charging state of each pixel block, and form a regular compensation effect in space.

To achieve the above objective, the present disclosure provides a thin film transistor liquid crystal display array substrate structure. The thin film transistor liquid crystal display array substrate structure includes a plurality of pixel blocks, and each pixel block is connected to a low-compensation unit or a high-compensation unit. Wherein, each pixel block outputs a display signal through the low operation compensation unit or the high operation compensation unit.

In one of the embodiments of the present disclosure, the plurality of pixel blocks connected to the low operation compensation unit and the plurality of pixel blocks connected to the high operation compensation unit are arranged in parallel.

In one embodiment of the present disclosure, the plurality of pixel blocks connected to the low-operation compensation unit and the plurality of pixel blocks connected to the high-operation compensation unit are arranged in a staggered manner.

In an embodiment of the present disclosure, the low operation compensation unit includes an operational amplifier, and the operational amplifier includes a first input terminal, a second input terminal, and an output terminal. The first input terminal receives an input voltage signal, and the second input terminal is connected to the output terminal.

In an embodiment of the present disclosure, the high-operation compensation unit includes an operational amplifier, and the operational amplifier includes a first input terminal, a second input terminal, and an output terminal. The second input terminal receives an input voltage signal, and the first input terminal is connected to the output terminal.

In an embodiment of the present disclosure, the operational amplifier is composed of thin film transistors.

In order to achieve the above objective, the present disclosure further provides a thin film transistor liquid crystal display array substrate structure, including: a plurality of pixel blocks, each of the pixel blocks is connected to a low operation compensation unit or a high operation compensation unit, the low operation compensation unit The compensation unit and the high operation compensation unit respectively include an operational amplifier. The operational amplifier includes a first input terminal, a second input terminal, and an output terminal. Each pixel block passes through the low operation compensation unit or the high operation The compensation unit outputs the display signal.

In one embodiment of the present disclosure, in the low arithmetic compensation unit, the first input terminal receives an input voltage signal, and the second input terminal is connected to the output terminal.

In an embodiment of the present disclosure, in the high-arithmetic compensation unit, the second input terminal receives an input voltage signal, and the first input terminal is connected to the output terminal.

In an embodiment of the present disclosure, the plurality of pixel blocks connected to the low-operation compensation unit and the plurality of pixel blocks connected to the high-operation compensation unit are arranged in parallel.

In order to achieve the above object, the present disclosure also provides a thin film transistor liquid crystal display array substrate structure, including a plurality of pixel blocks, each of the pixel blocks is connected to a low operation compensation unit or a high operation compensation unit, and the low operation compensation unit The unit and the high operation compensation unit respectively include an operational amplifier, the operational amplifier includes a first input terminal, a second input terminal, and an output terminal; in the low operation compensation unit, the first input terminal receives an input voltage signal , The second input terminal is connected to the output terminal; in the high arithmetic compensation unit, the second input terminal receives an input voltage signal, and the first input terminal is connected to the output terminal; wherein each The pixel block outputs a display signal through the low operation compensation unit or the high operation compensation unit.

Beneficial effect

Due to the structure of the thin film transistor liquid crystal display array substrate provided by the present disclosure. The thin film transistor liquid crystal display array substrate structure includes a plurality of pixel blocks. Each of the pixel blocks is connected to a low operation compensation unit or a high operation compensation unit, wherein each pixel block outputs a signal through the low operation compensation unit or the high operation compensation unit. The pixel block is connected to the low calculation compensation unit or the high calculation compensation unit to reduce the influence of the offset voltage on the display signal, compensate for the inconsistency of the charging states of each pixel block, and form a regular compensation effect in space.

Description of the drawings

In order to make the above-mentioned content of the present disclosure more obvious and understandable, the following is a detailed description of preferred embodiments in conjunction with the accompanying drawings:

FIG. 1 shows a schematic diagram of the structure of an array substrate according to an embodiment of the present disclosure. The array substrate has a plurality of pixel blocks connected to a low operation compensation unit and a plurality of pixel blocks connected to a high operation compensation unit;

FIG. 2 shows a schematic diagram of the structure of an array substrate according to another embodiment of the present disclosure. The array substrate has a plurality of pixel blocks connected to a low operation compensation unit and a plurality of pixel blocks connected to a high operation compensation unit;

FIG. 3 shows a schematic diagram of the structure of an array substrate according to still another embodiment of the present disclosure. The array substrate has a plurality of pixel blocks connected to a low operation compensation unit and a plurality of pixel blocks connected to a high operation compensation unit;

FIG. 4 shows a schematic diagram of the layout of a low operation compensation unit according to an embodiment of the present disclosure; and

FIG. 5 shows a schematic layout diagram of a high-compensation unit according to an embodiment of the present disclosure.

The best mode of the invention

The description of the following embodiments refers to the attached drawings to illustrate specific embodiments that the present disclosure can be implemented. The directional terms mentioned in this disclosure, such as [top], [bottom], [front], [back], [left], [right], [inside], [outside], [side], etc., are for reference only The direction of the additional schema. Therefore, the directional terms used are used to illustrate and understand the present disclosure, rather than to limit the present disclosure.

In the figure, units with similar structures are indicated by the same reference numerals.

The present disclosure provides a thin film transistor liquid crystal display array substrate structure. The thin film transistor liquid crystal display array substrate structure includes a plurality of pixel blocks, and each pixel block is connected to a low-compensation unit or a high-compensation unit. Wherein, each pixel block outputs a display signal through the low operation compensation unit or the high operation compensation unit. In other words, the pixel block provided with the low calculation compensation circuit operates in the low calculation state, and the pixel block provided with the high calculation compensation circuit operates in the high calculation state. The signal output by the pixel block is adjusted by the low operation compensation unit or the high operation compensation unit to form a regular compensation effect in space.

Please refer to FIG. 1, which is a schematic structural diagram of an array substrate 10 according to an embodiment of the disclosure. The array substrate 10 has a plurality of pixel blocks connected to a low-compensation unit and a plurality of pixel blocks connected to a high-compensation unit. Among them, column 1, column 2, column 3, column N-1, and column N respectively represent the number of columns of the pixel block. Row 1, row 2, row 3, row N-1, and row N respectively represent the number of rows of pixel blocks. In FIG. 1, each square represents a pixel block, + represents that the pixel block is operating in a high computing state, and-represents that the pixel block is operating in a low computing state. For example, -Vos21 means that the pixel block in the first row of the second column is operating in a low computing state, + Vos33 represents that the pixel block in the third row and third row is operating in a high computing state.

Please further refer to FIG. 1. In the embodiment disclosed in FIG. 1, each pixel block located in column 1, column 3, and column N-1 is operating in a high computing state; each pixel block located in column 2, column N The blocks all operate in a low computing state. In other words, each pixel block located in column 1, column 3, and column N-1 is connected to the high calculation compensation unit, and each pixel block located in column 2, column N is connected to the low calculation compensation unit.

In the embodiment disclosed in FIG. 1, the plurality of pixel blocks connected to the low operation compensation unit and the plurality of pixel blocks connected to the high operation compensation unit are arranged side by side, forming a regular pattern in space Compensation effect.

Please refer to FIG. 2, which is a schematic structural diagram of an array substrate 20 according to another embodiment of the present disclosure. The array substrate 20 has a plurality of pixel blocks connected to a low operation compensation unit and a plurality of pixel blocks connected to a high operation compensation unit. The difference from FIG. 1 is that, in the embodiment disclosed in FIG. 2, the plurality of pixel blocks connected to the low operation compensation unit are parallel to the plurality of pixel blocks connected to the high operation compensation unit Arranged to form a regular compensation effect in space.

Please refer to FIG. 3, which is a schematic structural diagram of an array substrate 30 according to still another embodiment of the disclosure. The array substrate 30 has a plurality of pixel blocks connected to a low operation compensation unit and a plurality of pixel blocks connected to a high operation compensation unit. The difference from FIG. 1 is that in the embodiment disclosed in FIG. 3, the plurality of pixel blocks connected to the low operation compensation unit are interleaved with the plurality of pixel blocks connected to the high operation compensation unit Arranged to form a regular compensation effect in space.

Please refer to FIG. 4. FIG. 4 shows a schematic diagram of the layout of the low arithmetic compensation unit 40 according to an embodiment of the present disclosure. In the embodiment disclosed in FIG. 4, the low operation compensation unit 40 includes an operational amplifier OP, and the operational amplifier OP includes a first input terminal 1, a second input terminal 2 and an output terminal O. The first input terminal 1 receives the input voltage signal VIN, and the second input terminal 2 is connected to the output terminal O. Wherein, the offset voltage VOS formed due to the difference of each thin film transistor switch is shown in the figure as being connected between the first input terminal 1 and the input voltage signal VIN.

Furthermore, the output voltage VOUT of the low arithmetic compensation unit 40 is equivalent to VIN-VOS.

Please refer to FIG. 5, which shows a schematic layout diagram of the high-compensation unit 50 according to an embodiment of the present disclosure. In the embodiment disclosed in FIG. 5, the high operation compensation unit 50 includes an operational amplifier OP, and the operational amplifier OP includes a first input terminal 1, a second input terminal 2, and an output terminal O. The second input terminal 2 receives the input voltage signal VIN, and the first input terminal 1 is connected to the output terminal O. Wherein, the offset voltage VOS formed due to the difference of each thin film transistor switch is shown in the figure as being connected between the first input terminal 1 and the output terminal O.

Furthermore, the output voltage VOUT of the high arithmetic compensation unit 50 is equivalent to VIN+VOS.

Please refer to FIGS. 4 and 5 together, by setting the low arithmetic compensation unit 40 and the high arithmetic compensation unit 50, the signal output from the adjusted original pixel block is adjusted to VIN-VOS through the low arithmetic compensation unit; The signal output by the original pixel block is adjusted to VIN+VOS by the high-compensation unit. Balance the different charging states of each pixel block caused by the offset voltage VOS, forming a regular compensation effect in space.

In an embodiment of the present disclosure, the operational amplifier OP is made of thin film transistors.

In summary, due to the structure of the thin film transistor liquid crystal display array substrate provided by the present disclosure. The thin film transistor liquid crystal display array substrate structure includes a plurality of pixel blocks. Each of the pixel blocks is connected to a low operation compensation unit or a high operation compensation unit, wherein each pixel block outputs a signal through the low operation compensation unit or the high operation compensation unit. The pixel block is connected to the low calculation compensation unit or the high calculation compensation unit to reduce the influence of the offset voltage on the display signal, compensate for the inconsistency of the charging states of each pixel block, and form a regular compensation effect in space.

The above are only the preferred embodiments of the present disclosure. It should be pointed out that for those of ordinary skill in the art, without departing from the principles of the present disclosure, several improvements and modifications can be made, and these improvements and modifications should also be regarded as the present disclosure. protected range.

Claims

A thin film transistor liquid crystal display array substrate structure, which includes:

A plurality of pixel blocks, each of which is connected to a low-operation compensation unit or a high-operation compensation unit;

Wherein, each pixel block outputs a display signal through the low operation compensation unit or the high operation compensation unit.
8. The thin film transistor liquid crystal display array structure of claim 1, wherein the plurality of pixel blocks connected to the low-operation compensation unit and the plurality of pixel blocks connected to the high-operation compensation unit are arranged in parallel.
3. The thin film transistor liquid crystal display array structure of claim 1, wherein the plurality of pixel blocks connected to the low-operation compensation unit and the plurality of pixel blocks connected to the high-operation compensation unit are arranged in parallel.
3. The thin film transistor liquid crystal display array structure of claim 1, wherein the plurality of pixel blocks connected to the low-operation compensation unit and the plurality of pixel blocks connected to the high-operation compensation unit are arranged alternately.
8. The thin film transistor liquid crystal display array structure of claim 1, wherein the low operation compensation unit comprises:

Operational amplifier. The operational amplifier includes a first input terminal, a second input terminal and an output terminal, wherein the first input terminal receives an input voltage signal, and the second input terminal is connected to the output terminal.
8. The thin film transistor liquid crystal display array structure of claim 5, wherein the operational amplifier is composed of thin film transistors.
8. The thin film transistor liquid crystal display array structure of claim 1, wherein the high operation compensation unit comprises:

An operational amplifier, the operational amplifier includes a first input terminal, a second input terminal, and an output terminal, wherein the second input terminal receives an input voltage signal, and the first input terminal is connected to the output terminal.
8. The thin film transistor liquid crystal display array structure of claim 7, wherein the operational amplifier is composed of thin film transistors.
A thin film transistor liquid crystal display array substrate structure, which includes:

A plurality of pixel blocks, each of the pixel blocks is connected to a low operation compensation unit or a high operation compensation unit, the low operation compensation unit and the high operation compensation unit respectively include an operational amplifier, and the operational amplifier includes a first input Terminal, second input terminal and output terminal;

Wherein, each pixel block outputs a display signal through the low operation compensation unit or the high operation compensation unit.
9. The thin film transistor liquid crystal display array structure of claim 9, wherein in the low arithmetic compensation unit, the first input terminal receives an input voltage signal, and the second input terminal is connected to the output terminal.
9. The thin film transistor liquid crystal display array structure of claim 9, wherein in the high arithmetic compensation unit, the second input terminal receives an input voltage signal, and the first input terminal is connected to the output terminal.
9. The thin film transistor liquid crystal display array structure according to claim 9, wherein the plurality of pixel blocks connected to the low operation compensation unit and the plurality of pixel blocks connected to the high operation compensation unit are arranged in parallel.
9. The thin film transistor liquid crystal display array structure according to claim 9, wherein the plurality of pixel blocks connected to the low operation compensation unit and the plurality of pixel blocks connected to the high operation compensation unit are arranged in parallel.
9. The thin film transistor liquid crystal display array structure as claimed in claim 9, wherein the plurality of pixel blocks connected to the low operation compensation unit and the plurality of pixel blocks connected to the high operation compensation unit are arranged alternately.
9. The thin film transistor liquid crystal display array structure of claim 9, wherein the operational amplifier is composed of thin film transistors.
A thin film transistor liquid crystal display array substrate structure, which includes:

A plurality of pixel blocks, each of the pixel blocks is connected to a low operation compensation unit or a high operation compensation unit, the low operation compensation unit and the high operation compensation unit respectively include an operational amplifier, and the operational amplifier includes a first input Terminal, second input terminal and output terminal;

In the low arithmetic compensation unit, the first input terminal receives an input voltage signal, and the second input terminal is connected to the output terminal;

In the high arithmetic compensation unit, the second input terminal receives an input voltage signal, and the first input terminal is connected to the output terminal;

Wherein, each pixel block outputs a display signal through the low operation compensation unit or the high operation compensation unit.
16. The thin film transistor liquid crystal display array structure of claim 16, wherein the plurality of pixel blocks connected to the low operation compensation unit and the plurality of pixel blocks connected to the high operation compensation unit are arranged in parallel.
16. The thin film transistor liquid crystal display array structure of claim 16, wherein the plurality of pixel blocks connected to the low-operation compensation unit and the plurality of pixel blocks connected to the high-operation compensation unit are arranged in parallel.
16. The thin film transistor liquid crystal display array structure of claim 16, wherein the plurality of pixel blocks connected to the low-operation compensation unit and the plurality of pixel blocks connected to the high-operation compensation unit are arranged alternately.
16. The thin film transistor liquid crystal display array structure of claim 16, wherein the operational amplifier is composed of thin film transistors.