WO2020232620A1 - 模拟前端电路、信号采集装置 - Google Patents

模拟前端电路、信号采集装置 Download PDF

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Publication number
WO2020232620A1
WO2020232620A1 PCT/CN2019/087730 CN2019087730W WO2020232620A1 WO 2020232620 A1 WO2020232620 A1 WO 2020232620A1 CN 2019087730 W CN2019087730 W CN 2019087730W WO 2020232620 A1 WO2020232620 A1 WO 2020232620A1
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Prior art keywords
resistor
operational amplifier
common mode
signal
circuit
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PCT/CN2019/087730
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English (en)
French (fr)
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夏荣俊
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深圳市汇顶科技股份有限公司
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Priority to PCT/CN2019/087730 priority Critical patent/WO2020232620A1/zh
Priority to CN201990000077.5U priority patent/CN211321301U/zh
Publication of WO2020232620A1 publication Critical patent/WO2020232620A1/zh

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    • A—HUMAN NECESSITIES
    • A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61B—DIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B5/00—Measuring for diagnostic purposes; Identification of persons
    • A61B5/24—Detecting, measuring or recording bioelectric or biomagnetic signals of the body or parts thereof
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/34—Negative-feedback-circuit arrangements with or without positive feedback
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers

Definitions

  • This application relates to the technical field of analog circuits, in particular to an analog front-end circuit and a signal acquisition device.
  • CMRR Common Mode Rejection Ratio
  • ECG electrocardiogram
  • the embodiments of the present application provide an analog front-end circuit and a signal acquisition device to solve the technical problem that the CMRR effect of the acquired signal in the prior art is not ideal.
  • an embodiment of the present application provides an analog front-end circuit, including a differential amplifier circuit, a common-mode feedforward unit, a coupling unit, and a common-mode negative feedback unit; wherein the common-mode feedforward unit receives the first The input signal and the second input signal obtain a common mode component; the coupling unit divides the common mode component to obtain an output common mode component, and DC couples the output common mode component to the input of the differential amplifier circuit The coupling unit also AC-couples the differential mode component of the first input signal and the second input signal to the input terminal of the differential amplifier circuit; the common-mode negative feedback unit receives the differential amplifier circuit And adjust the feedback signal according to the preset negative feedback gain, so that the adjusted feedback signal suppresses the common mode component.
  • the common-mode feedforward unit includes a first operational amplifier, a first resistor, and a second resistor; wherein the first resistor and the second resistor have the same resistance; one end of the first resistor One end of the second resistor is connected to the non-inverting input end of the first operational amplifier, the other end of the first resistor is connected to one input end of the common mode feedforward unit, and the second resistor The other end is connected to the other input end of the common-mode feedforward unit; the non-inverting input end of the first operational amplifier is connected to the voltage divider point between the first resistor and the second resistor, the first The inverting input terminal of an operational amplifier is connected to the output terminal of the first operational amplifier; the output terminal of the first operational amplifier outputs the common mode component of the first input signal and the second input signal.
  • the coupling unit includes: a first capacitor and a second capacitor, a third resistor and a fourth resistor, a fifth resistor and a sixth resistor, and a seventh resistor and an eighth resistor; wherein, the first capacitor and the The capacitance of the second capacitor is the same, the resistance of the third resistor and the fourth resistor are the same, the resistance of the fifth resistor and the sixth resistor are the same, and the seventh resistor and the first resistor have the same resistance.
  • the resistance of the eight resistors is the same; the differential mode component of the first input signal passes through the first capacitor and the fifth resistor, and communicates through the voltage divider point between the fifth resistor and the seventh resistor Coupled to the first input terminal of the differential amplifier circuit, the differential mode component of the second input signal passes through the second capacitor and the sixth resistor, and passes through one of the sixth resistor and the eighth resistor.
  • the voltage dividing point between is AC coupled to the second input terminal of the differential amplifier circuit;
  • the output terminal of the first operational amplifier is connected to the voltage dividing point between the third resistor and the fourth resistor; the common mode component of the first input signal and the second input signal passes through the third resistor , The fifth resistor and the seventh resistor are divided to obtain an output common mode component, and the output common mode component is DC-coupled to all through the voltage division point between the fifth resistor and the seventh resistor.
  • the first input terminal of the differential amplifier circuit; the common mode component of the first input signal and the second input signal is divided by the fourth resistor, the sixth resistor, and the eighth resistor to obtain an output
  • the common mode component, and the output common mode component is DC coupled to the second input terminal of the differential amplifier circuit through the voltage divider point between the sixth resistor and the eighth resistor.
  • the coupling unit includes a first high-pass filter for filtering the differential mode component of the first input signal; and the first high-pass filter is composed of the fifth resistor and the seventh resistor.
  • the resistor is connected in series, and then connected in parallel with the third resistor, and then connected in series with the first capacitor;
  • the coupling unit further includes a second high-pass filter for filtering the differential mode component of the second input signal
  • the second high-pass filter is formed by the sixth resistor and the eighth resistor in series, then in parallel with the fourth resistor, and then in series with the second capacitor.
  • the common-mode negative feedback unit includes a second operational amplifier, a third operational amplifier, a first feedback control resistor, and a second feedback control resistor; wherein the non-inverting input terminal of the second operational amplifier inputs the differential For the feedback signal of the amplifying circuit, the inverting input terminal of the second operational amplifier is connected with the output terminal of the second operational amplifier; one end of the first feedback control resistor is connected with the output terminal of the second operational amplifier , The other end of the first feedback control resistor is connected to the inverting input terminal of the third operational amplifier; one end of the second feedback control resistor is connected to the inverting input terminal of the third operational amplifier, the The other end of the second feedback control resistor is connected to the output end of the third operational amplifier; the non-inverting input end of the third operational amplifier is connected to the reference voltage, and the output end of the third operational amplifier outputs the adjusted feedback signal.
  • the preset negative feedback gain is determined according to the ratio of the resistance of the second feedback control resistor to the resistance of the first feedback control resistor.
  • the differential amplifier circuit includes: a fourth operational amplifier, a fifth operational amplifier, a sixth operational amplifier, a ninth resistor and a tenth resistor, an eleventh resistor and a twelfth resistor, a thirteenth resistor and a Fourteenth, fifteenth and sixteenth resistors; among them, the ninth and tenth resistors have the same resistance value, the eleventh and twelfth resistors have the same resistance, the thirteenth and the fourteenth The resistance values of the resistors are the same, and the resistance values of the fifteenth resistor and the sixteenth resistor are the same; the non-inverting input terminal of the fourth operational amplifier is the first input terminal of the differential amplifier circuit and the non-inverting input terminal of the fifth operational amplifier The input terminal is the second input terminal of the differential amplifier circuit;
  • One end of the ninth resistor and one end of the tenth resistor are respectively connected to the non-inverting input end of the second operational amplifier, and the other end of the ninth resistor is connected to the inverting input end of the fourth operational amplifier The other end of the tenth resistor is connected to the inverting input end of the fifth operational amplifier; the feedback signal of the differential amplifier circuit is the divided voltage between the ninth resistor and the tenth resistor ;
  • One end of the eleventh resistor is connected to the inverting input end of the fourth operational amplifier, and the other end of the eleventh resistor is connected to the output end of the fourth operational amplifier;
  • One end is connected to the inverting input end of the fifth operational amplifier, and the other end of the twelfth resistor is connected to the output end of the fifth operational amplifier;
  • One end of the thirteenth resistor is connected to the output end of the fourth operational amplifier, and the other end of the thirteenth resistor is connected to the inverting input end of the sixth operational amplifier;
  • One end is connected to the output end of the fifth operational amplifier, and the other end of the fourteenth resistor is connected to the non-inverting input end of the sixth operational amplifier;
  • One end of the fifteenth resistor is connected to the inverting input end of the sixth operational amplifier, and the other end of the fifteenth resistor is connected to the output end of the sixth operational amplifier; One end is connected to the non-inverting input end of the sixth operational amplifier, and the other end of the sixteenth resistor is connected to a reference voltage.
  • the analog front-end circuit further includes a pre-buffer unit; the pre-buffer unit respectively follows the received first analog signal from the first signal source and the second analog signal from the second signal source after voltage Obtain the first input signal and the second input signal, and transfer the first input signal and the second input signal to the common mode feedforward unit.
  • the pre-buffer unit includes: a seventh operational amplifier, an eighth operational amplifier, a seventeenth resistor, and an eighteenth resistor; wherein the seventeenth resistor and the eighteenth resistor have the same resistance value;
  • the non-inverting input end of the seventh operational amplifier is connected to one end of the seventeenth resistor, the inverting input end of the seventh operational amplifier is connected to the output end of the seventh operational amplifier; the other of the seventeenth resistor One end is connected to the first analog signal;
  • the non-inverting input end of the eighth operational amplifier is connected to one end of the eighteenth resistor, and the inverting input end of the eighth operational amplifier is connected to the output of the eighth operational amplifier
  • the other end of the eighteenth resistor is connected to the second analog signal;
  • the output of the seventh operational amplifier outputs the first input signal to the common-mode feedforward unit and the eighth operational amplifier
  • the output terminal outputs the second input signal to the common mode feedforward unit.
  • an embodiment of the present application also provides a signal acquisition device, including the above-mentioned analog front-end circuit.
  • the common mode component is obtained from the first input signal and the second input signal through the common mode feedforward unit, and the common mode component is divided by the coupling unit to obtain the output common mode component , And DC-couple the output common mode component to the input end of the differential amplifier circuit.
  • the coupling unit also AC-couples the differential mode components of the first input signal and the second input signal to the input terminal of the differential amplifier circuit.
  • the analog front-end circuit of the present application has the high-pass filter characteristics of ordinary AC coupling circuits, and at the same time avoids the conversion of common mode deviation into differential Modal signal, leading to the disadvantage that the differential mode gain cannot be too high.
  • the feedback signal of the differential amplifier circuit is received by the common mode negative feedback unit, and the feedback signal is adjusted according to the preset negative feedback gain, so that the adjusted feedback signal suppresses the common mode component.
  • FIG. 1 is a schematic diagram of a circuit module structure of an analog front-end circuit of the present application
  • FIG. 2 is a schematic diagram of a specific circuit structure of an analog front-end circuit in an embodiment of the present application
  • 3 is an effect comparison diagram of the differential mode amplitude-frequency response curve of an analog front-end circuit and an ordinary circuit in an embodiment of the present application;
  • Fig. 5 is a comparison effect diagram of the input voltage and the output voltage Vout of the analog front-end circuit and the ordinary circuit in an embodiment of the present application.
  • FIG. 1 is a schematic diagram of the circuit module structure of an analog front-end circuit of the present application.
  • the analog front-end circuit 1 includes: a pre-buffer unit 11, a common-mode feedforward unit 12, a coupling unit 13, a common-mode negative feedback unit 14 and a differential amplifier circuit 15.
  • the pre-buffer unit 11 respectively receives the first analog signal sent by the first signal source (not shown in FIG. 1) and the second analog signal sent by the second signal source (not shown in FIG. 1). After the signal is followed by voltage, a first input signal and a second input signal are obtained, and the first input signal and the second input signal are transferred to the common mode feedforward unit 12.
  • the common mode feedforward unit 12 obtains common mode components from the received first input signal and second input signal.
  • the coupling unit 13 divides the common mode component to obtain an output common mode component, and directly couples the output common mode component to the input terminal of the differential amplifier circuit 15.
  • the coupling unit 13 also AC-couples the differential mode component of the first input signal and the second input signal to the input terminal of the differential amplifier circuit 15.
  • the common mode negative feedback unit 14 receives the feedback signal of the differential amplifier circuit 15 and adjusts the feedback signal according to a preset negative feedback gain, so that the adjusted feedback signal suppresses the common mode component.
  • the analog front-end circuit 1 described in this embodiment can be applied to signal acquisition equipment (for example, electrocardiogram equipment).
  • signal acquisition equipment for example, electrocardiogram equipment
  • the signal amplitude collected by this type of signal acquisition equipment is small (for example, 0.1mV to 5mV), and the frequency is low (for example, 0.05 Hz). ⁇ 100Hz), it is a kind of low-frequency weak analog signal, which has large common mode interference. Therefore, the differential mode component in the received analog signal is amplified by the analog front-end circuit and the common mode component is suppressed to improve the accuracy of the collected signal degree.
  • AC coupling refers to removing the DC component through DC blocking capacitor coupling
  • DC coupling refers to retaining the DC component and AC component without removing the AC component.
  • common mode rejection ratio of the differential amplifier circuit in the ordinary circuit is not good, and the common mode component cannot be suppressed well.
  • a pre-buffer unit 11 a common mode feedforward unit 12, a coupling unit 13 and a common mode negative feedback unit 14 are added to the analog front end circuit 1.
  • the pre-buffer unit 11 has high impedance characteristics, so even if the first analog signal sent by the first signal source (not shown in FIG. 1) and the second signal source (not shown in FIG. 1) are sent.
  • the second analog signal of is very weak and can drive the pre-buffer unit 11, and the stable first input signal and the second input signal are obtained after voltage following.
  • the common mode feedforward unit 12 obtains a common mode component from the first input signal and the second input signal, and then divides the common mode component through the coupling unit 13 to obtain an output common mode component , And DC-couple the output common mode component to the input end of the differential amplifier circuit 15.
  • the coupling unit 13 also AC-couples the differential mode component of the first input signal and the second input signal to the input terminal of the differential amplifier circuit 15.
  • the first input signal is V 1
  • the second input signal is V 2
  • the common mode component of the first input signal and the second input signal is V Com
  • the differential mode component is V Diff .
  • the coupling unit 13 transmits the common mode component of the first input signal and the second input signal to the input terminal of the differential amplifier circuit 15
  • the common mode component will be
  • the output common mode component of the coupling unit 13 is obtained after the resistance voltage division, and then the output common mode component is transmitted to the differential amplifier circuit 15. Therefore, the output common-mode component is not completely equal to the common-mode component of the first input signal and the second input signal.
  • the specific circuit structure of the coupling unit 13 will be described. The relationship between the output common mode component and the common mode components of the first input signal and the second input signal.
  • the coupling unit 13 uses capacitors and resistors to form a first-order high-pass filter that is only effective for differential mode components, thereby reducing the out-of-band noise at the output of the analog front-end circuit.
  • the feedback signal is obtained from the differential amplifier circuit 15 through the common mode negative feedback unit 14.
  • the feedback signal obtained by the common mode negative feedback unit 14 is equal to the output common mode component.
  • the common mode negative feedback unit 14 adjusts the feedback signal by setting the preset negative feedback gain of the operational amplifier, so that the adjusted feedback signal is as close as possible to the difference between the first input signal and the second input signal. Common mode component, thereby achieving the effect of suppressing the common mode component.
  • FIG. 2 is a schematic diagram of a specific circuit structure of an analog front-end circuit in an embodiment of the present application.
  • the analog front-end circuit 2 includes: a pre-buffer unit 21, a common-mode feedforward unit 22, a coupling unit 23, a common-mode negative feedback unit 24 and a differential amplifier circuit 25.
  • the analog front-end circuit 2 receives the first analog signal Vi 1 sent by the first signal source 26 and the second analog signal Vi 2 sent by the second signal source 27, and passes through the pre-buffer unit 21 and the common mode feedforward
  • the unit 22, the coupling unit 23, the common-mode negative feedback unit 24, and the differential amplifier circuit 25 output a signal V out through the output terminal of the differential amplifier circuit 25 after processing.
  • the pre-buffer unit 21 includes: a seventh operational amplifier 211, an eighth operational amplifier 212, a seventeenth resistor R 1 and an eighteenth resistor R 2 ; wherein, the seventeenth resistor R 1 and the tenth resistor R 2 The resistance values of the eight resistors R 2 are the same.
  • Seventh inverting input terminal of the operational amplifier 211 is connected to one end of resistors R 1 of the seventeenth, the inverting input terminal of the seventh operational amplifier 211 is connected to the seventh output terminal of the operational amplifier 211; and the The other end of the seventeenth resistor R 1 is connected to the first analog signal Vi 1 .
  • Inverting input terminal of the eighth operational amplifier 212 is connected to one end of the eighteenth resistor R 2, the inverting input terminal of the eighth operational amplifier 212 is connected to the eighth output terminal of the operational amplifier 212; the The other end of the eighteenth resistor R 2 is connected to the second analog signal Vi 2 .
  • a nineteenth resistor R 3 is also connected between the inverting input terminal of the seventh operational amplifier 211 and the output terminal of the seventh operational amplifier 211.
  • a twentieth resistor R 4 is also connected between the inverting input terminal of the eighth operational amplifier 212 and the output terminal of the eighth operational amplifier 212, and the nineteenth resistor R 3 and the twentieth resistor R 4 The resistance of the resistor R 4 is the same.
  • the output terminal of the seventh operational amplifier 211 outputs the first input signal U 1 to the common mode feedforward unit 22, and the output terminal of the eighth operational amplifier 212 outputs the second input signal U 2 to the common mode feedforward unit 22.
  • the common mode feedforward unit 22 The common mode feedforward unit 22.
  • Prior to said common mode feed unit 22 includes a first operational amplifier 221, a first resistor and a second resistor R 5 R 6; wherein said first resistance of the resistor R 5 and R 6 is the same as the second resistor.
  • One end of the first resistor R 5 and the second end of the resistor R 6 is connected to the inverting input terminal of the first operational amplifier 221, the other end of said first resistor R 5 is connected to the seventh The output terminal of the operational amplifier 211 (that is, one input terminal of the common mode feedforward unit 22), and the other terminal of the second resistor R 6 is connected to the output terminal of the eighth operational amplifier 212 (that is, the common mode The other input terminal of the feedforward unit 22).
  • Inverting input terminal of the first operational amplifier 221 is connected to the dividing point between the first resistor 6 and the second resistor R 5 R, the inverting input terminal of the first operational amplifier 221 is connected to the The output terminal of the first operational amplifier 221 is described.
  • a resistor R 7 is also connected between the inverting input terminal of the first operational amplifier 221 and the output terminal of the first operational amplifier 221.
  • the voltage input to the non-inverting input terminal of the first operational amplifier 221 is (U 1 +U 2 )/2. According to the virtual short nature of the operational amplifier, the voltage output by the output terminal of the first operational amplifier 221 is also (U 1 +U 2 )/2. Therefore, the output terminal of the first operational amplifier 221 outputs the common mode component of the first input signal U 1 and the second input signal U 2 .
  • the coupling unit 23 includes: a first capacitor C 1 and a second capacitor C 2 , a third resistor R 8 and a fourth resistor R 9 , a fifth resistor R 10 and a sixth resistor R 11, and a seventh resistor R 12 and a Eight resistors R 13 ; wherein the capacitances of the first capacitor C 1 and the second capacitor C 2 are the same, the resistance values of the third resistor R 8 and the fourth resistor R 9 are the same, and the fifth resistor R 10 and the same as the sixth resistor 11 of resistance R, the same as the seventh resistor R 12 and the eighth resistor 13 of resistance R.
  • the differential mode component of the first input signal U 1 passes through the first capacitor C 1 and the fifth resistor R 10 , and passes through the division between the fifth resistor R 10 and the seventh resistor R 12
  • the voltage point VP1 is AC coupled to the first input terminal of the differential amplifier circuit 25.
  • the differential mode component of the second input signal U 2 passes through the second capacitor C 2 and the sixth resistor R 11 , and passes through the division between the sixth resistor R 11 and the eighth resistor R 13
  • the voltage point VP2 is AC coupled to the second input terminal of the differential amplifier circuit 25.
  • the coupling unit 23 AC couples the differential mode components of the first input signal U 1 and the second input signal U 2 through the first capacitor C 1 and the second capacitor C 2 respectively.
  • the first capacitor C 1 and the second capacitor C 2 are used as DC blocking capacitors to remove the DC components in the first input signal U 1 and the second input signal U 2 .
  • the fifth resistor R 10 and the seventh resistor R 12 in series and then in parallel with the third resistor R 8, and then form the capacitors C 1 and the first series
  • the first high-pass filter of the differential mode component of the first input signal U 1 ie, C 1 and R 8 //(R 10 +R 12 )
  • the sixth resistor and the eighth resistor R 11 R 13 in series and then in parallel with the fourth resistor R 9, and then forming the second capacitor C 2 connected in series to the second differential input signal U 2
  • the second high-pass filter of the component ie C 2 and R 9 //(R 11 +R 13 )).
  • the high-pass filter can filter out low-frequency signals, thereby reducing the out-of-band noise at the output of the analog front-end circuit.
  • the output terminal of the first operational amplifier 221 is connected to the voltage dividing point VFW between the third resistor R 8 and the fourth resistor R 9 .
  • the voltage dividing point between the third resistor R 8 and the fifth resistor R 10 is VC1
  • the voltage dividing point between the fourth resistor R 9 and the sixth resistor R 11 is VC2.
  • the common mode components of the first input signal U 1 and the second input signal U 2 are divided by the third resistor R 8 , the fifth resistor R 10 and the seventh resistor R 12 to obtain an output common mode component, and the output common-mode components by the fifth resistor R 10 is coupled to the DC voltage dividing point between VP1 said seventh resistor R 12 to a first input of the differential amplifier circuit 25.
  • the common mode components of the first input signal U 1 and the second input signal U 2 are divided by the fourth resistor R 9 , the sixth resistor R 11 and the eighth resistor R 13 to obtain an output
  • the common mode component, and the output common mode component is DC coupled to the second input terminal of the differential amplifier circuit 25 through the voltage dividing point VP2 between the sixth resistor R 11 and the eighth resistor R 13 .
  • the voltage division point between the third resistor R 8 and the fifth resistor R 10 is the voltage of VC1 and the voltage between the fourth resistor R 9 and the sixth resistor R 11
  • the voltage divider point is the same as the voltage of VC2.
  • the fifth resistor R 10 and the voltage dividing point between the seventh resistor R 12 VP1 voltage and the sixth resistor R 11 the same as the voltage dividing point between the eighth resistor 13 VP2 R .
  • the common mode negative feedback unit 24 includes a second operational amplifier 242, a third operational amplifier 241, a first feedback control resistor R 15 and a second feedback control resistor R 14 .
  • the non-inverting input terminal of the second operational amplifier 242 inputs the feedback signal of the differential amplifier circuit 25, and the inverting input terminal of the second operational amplifier 242 is connected to the output terminal of the second operational amplifier 242.
  • a resistor R 16 is also connected between the inverting input terminal of the second operational amplifier 242 and the output terminal of the second operational amplifier 242.
  • One end of the first feedback control resistor R 15 is connected to the output end of the second operational amplifier 242, and the other end of the first feedback control resistor R 15 is connected to the inverting input end of the third operational amplifier 241 .
  • the second feedback control end of resistor R 14 and the inverting input of the third operational amplifier 241 is connected to the second feedback control to the other end of resistor R 14 to the output terminal of the third operational amplifier 241 connection.
  • the non-inverting input terminal of the third operational amplifier 241 is connected to the reference voltage VREF.
  • the second operational amplifier 242 performs a voltage follower function on the feedback signal of the differential amplifier circuit 25 input from the non-inverting input terminal, so the signal voltage output by the output terminal of the second operational amplifier 242 is Feedback signal.
  • the non-inverting input terminal of the third operational amplifier 241 is connected to the reference voltage VREF, and the inverting input terminal of the third operational amplifier 241 receives the feedback signal output by the output terminal of the second operational amplifier 242, according to a preset negative feedback After the feedback signal is adjusted by the gain, the adjusted feedback signal is output through the output terminal of the third operational amplifier 241.
  • the differential amplifier circuit 25 comprises: a fourth operational amplifier 251, a fifth operational amplifier 252, a sixth operational amplifier 253, a ninth resistor and tenth resistor R 17 R 18, an eleventh resistor and a twelfth resistor R 19 R 20.
  • a resistor R 19 and the twelfth resistor R 20 have the same resistance value
  • the thirteenth resistor R 21 and the fourteenth resistor R 22 have the same resistance value
  • the fifteenth resistor R 23 and the sixteenth resistor R 24 have the same resistance value the same.
  • the non-inverting input terminal of the fourth operational amplifier 251 is the first input terminal of the differential amplifier circuit 25, and the non-inverting input terminal of the fifth operational amplifier 252 is the second input terminal of the differential amplifier circuit 25.
  • One end of the ninth resistor R 17 and one end of the tenth resistor R 18 are connected to the inverting input terminal of the second operational amplifier 242, and the other end of the ninth resistor R 17 is connected to the second The inverting input terminal of the fourth operational amplifier 251 and the other end of the tenth resistor R 18 are connected to the inverting input terminal of the fifth operational amplifier 252.
  • One end of the eleventh resistor R 19 is connected to the inverting input end of the fourth operational amplifier 251, and the other end of the eleventh resistor R 19 is connected to the output end of the fourth operational amplifier 251.
  • One end of the twelfth resistor R 20 is connected to the inverting input end of the fifth operational amplifier 252, and the other end of the twelfth resistor R 20 is connected to the output end of the fifth operational amplifier 252.
  • One end of the thirteenth resistor R 21 is connected to the output end of the fourth operational amplifier 251, and the other end of the thirteenth resistor R 21 is connected to the inverting input end of the sixth operational amplifier 253;
  • One end of the fourteenth resistor R 22 is connected to the output end of the fifth operational amplifier 252, and the other end of the fourteenth resistor R 22 is connected to the non-inverting input end of the sixth operational amplifier 253.
  • One end of the fifteenth resistor R 23 is connected to the inverting input end of the sixth operational amplifier 253, and the other end of the fifteenth resistor R 23 is connected to the output end of the sixth operational amplifier 253.
  • One end of the sixteenth resistor R 24 is connected to the non-inverting input end of the sixth operational amplifier 253, and the other end of the sixteenth resistor R 24 is connected to the reference voltage VREF.
  • the feedback signal of the differential amplifying circuit 25 is the ninth resistor R 17 and the divided voltage 18 between the tenth resistor R.
  • the input voltage of the non-inverting input terminal of the fourth operational amplifier 251 is VP1
  • the input voltage of the non-inverting input terminal of the fifth operational amplifier 252 is VP2.
  • the voltage at the inverting input terminal of the fourth operational amplifier 251 is also VP1
  • the voltage at the inverting input terminal of the fifth operational amplifier 252 is also VP2.
  • FIG. 3 is an effect comparison diagram of the differential mode amplitude-frequency response curve of the analog front-end circuit and the ordinary circuit in an embodiment of the present application.
  • the analog front-end circuit of this application is no different from the ordinary circuit.
  • the ordinary circuit amplitude-frequency curve is in the main amplifier.
  • the analog front-end circuit of this application provides an additional pole to make the amplitude-frequency curve of the high frequency band roll off at a slope of -40dB/Dec, so that the analog front-end circuit The noise at the output is lower.
  • FIG. 4 is an effect comparison diagram of the common mode amplitude-frequency response curve of the analog front-end circuit and the common circuit in an embodiment of the present application.
  • the common mode gain amplitude-frequency curve in the figure is in the entire passband range.
  • the common mode component gain of the analog front-end circuit of this application is 21.6dB lower than that of the ordinary circuit. Because the differential mode component has the same gain, it is equivalent to this
  • the CMRR of the applied analog front-end circuit is 21.6dB higher than that of the ordinary circuit.
  • the analog front-end circuit of the present application passes the common-mode component through the common-mode feedforward unit to the differential amplifier circuit after voltage division, so that even if the analog front-end circuit's two input signal sources are analog
  • the signal (that is, the first analog signal Vi1 output by the first signal source and the second analog signal Vi2 output by the second signal source) has a DC deviation, and the differential amplifier circuit can't see it, while the ordinary circuit of DC coupling will cause this DC deviation.
  • the deviation is directly regarded as a differential mode signal, which will result in the inability to set too large differential mode gain and the output is very easy to saturate.
  • the analog front-end circuit of this application does not have this problem.
  • An embodiment of the present application also provides a signal acquisition device, and the signal acquisition device includes the analog front-end circuit described in the foregoing embodiment.
  • the signal acquisition device may be an ECG, various sensors, or other signal acquisition devices that contain small signal amplification circuits that require a higher CMRR.

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Abstract

本申请涉及模拟电路技术领域，提供了一种模拟前端电路及信号采集设备。模拟前端电路包括差分放大电路、共模前馈单元、耦合单元以及共模负反馈单元；共模前馈单元从接收到的第一输入信号与第二输入信号获取共模分量；耦合单元将共模分量经分后得到输出共模分量，并将输出共模分量直流耦合至差分放大电路的输入端；耦合单元还将第一输入信号与第二输入信号的差模分量交流耦合至差分放大电路的输入端；共模负反馈单元接收差分放大电路的反馈信号，并根据预设负反馈增益对反馈信号进行调节，以使调节后的反馈信号抑制共模分量。本技术方案解决了现有的普通电路中CMRR效果不理想的技术问题。

Description

模拟前端电路、信号采集装置 技术领域
本申请涉及模拟电路技术领域，尤其涉及一种模拟前端电路、信号采集装置。
背景技术
在某些采集信号的应用场景中，对模拟前端电路的共模抑制比(Common Mode Rejection Ratio，以下简称CMRR)要求极高，例如心电图(Electrocardiogram，以下简称ECG)设备。其中，CMRR的定义为：差分放大电路对差模信号的电压放大倍数Aud与对共模信号的电压放大倍数Auc之比，CMRR越大表明差分放大电路抑制共模信号的能力越强，放大器的性能越好。
无论是交流耦合还是直流耦合的普通电路，其CMRR都取决于仪表放大器单元，但现有的普通电路中仪表放大器单元的CMRR效果不理想。普通电路在运算放大器的增益带宽积的限制下，当频率高到一定程度时，幅频响应曲线将不再保持平直，而是在放大器的主极点作用下按一定的斜率滚降。
申请内容
有鉴于此，本申请实施例提供了一种模拟前端电路、信号采集装置，用以解决现有技术中采集信号的CMRR效果不理想的技术问题。
一方面，本申请实施例提供了一种模拟前端电路，包括差分放大电路、共模前馈单元、耦合单元以及共模负反馈单元；其中，所述共模前馈单元从接收到的第一输入信号与第二输入信号获取共模分量；所述耦合单元将所述共模分量经分压后得到输出共模分量，并将所述输出共模分量直流耦合至所述差分放大电路的输入端；所述耦合单元还将所述第一输入信号与所述第二输入信号的差模分量交流耦合至所述差分放大电路的输入端；所述共模负反馈单元接收 所述差分放大电路的反馈信号，并根据预设负反馈增益对所述反馈信号进行调节，以使调节后的反馈信号抑制所述共模分量。
可选的，所述共模前馈单元包括第一运算放大器，第一电阻和第二电阻；其中，所述第一电阻与所述第二电阻的阻值相同；所述第一电阻的一端与所述第二电阻的一端分别连接至所述第一运算放大器的同相输入端，所述第一电阻的另一端连接至所述共模前馈单元的一个输入端，所述第二电阻的另一端连接至所述共模前馈单元的另一个输入端；所述第一运算放大器的同相输入端连接至所述第一电阻与所述第二电阻之间的分压点、所述第一运算放大器的反相输入端连接至所述第一运算放大器的输出端；所述第一运算放大器的输出端输出所述第一输入信号与所述第二输入信号的共模分量。
可选的，所述耦合单元包括：第一电容器和第二电容器、第三电阻和第四电阻、第五电阻和第六电阻以及第七电阻和第八电阻；其中，所述第一电容器和所述第二电容器的电容相同、所述第三电阻和所述第四电阻的阻值相同、所述第五电阻和所述第六电阻的阻值相同、所述第七电阻和所述第八电阻的阻值相同；所述第一输入信号的差模分量经由所述第一电容器和所述第五电阻，并通过所述第五电阻与所述第七电阻之间的分压点交流耦合至所述差分放大电路的第一输入端、所述第二输入信号的差模分量经由所述第二电容器和所述第六电阻，并通过所述第六电阻与所述第八电阻之间的分压点交流耦合至所述差分放大电路的第二输入端；
所述第一运算放大器的输出端连接至所述第三电阻与第四电阻之间的分压点；所述第一输入信号与所述第二输入信号的共模分量经所述第三电阻、所述第五电阻和所述第七电阻分压后得到输出共模分量，且所述输出共模分量通过所述第五电阻与所述第七电阻之间的分压点直流耦合至所述差分放大电路的第一输入端；所述第一输入信号与所述第二输入信号的共模分量经所述第四电阻、所述第六电阻和所述第八电阻分压后得到输出共模分量，且所述输出共模分量通过所述第六电阻与所述第八电阻之间的分压点直流耦合至所述差分放大电路的第二输入端。
可选的，所述耦合单元包括用于对所述第一输入信号的差模分量进行滤波的第一高通滤波器；，所述第一高通滤波器由所述第五电阻和所述第七电阻串联，再与所述第三电阻并联，再与所述第一电容器串联所形成；所述耦合单元还包括用于对所述第二输入信号的差模分量进行滤波的第二高通滤波器；所述第二高通滤波器由所述第六电阻和所述第八电阻串联，再与所述第四电阻并联，再与所述第二电容器串联所形成。。
可选的，所述共模负反馈单元包括第二运算放大器、第三运算放大器、第一反馈控制电阻和第二反馈控制电阻；其中，所述第二运算放大器的同相输入端输入所述差分放大电路的反馈信号，所述第二运算放大器的反相输入端与所述第二运算放大器的输出端相连接；所述第一反馈控制电阻的一端与所述第二运算放大器的输出端连接，所述第一反馈控制电阻的另一端与所述第三运算放大器的反相输入端连接；所述第二反馈控制电阻的一端与所述第三运算放大器的反相输入端连接，所述第二反馈控制电阻的另一端与所述第三运算放大器的输出端相连接；所述第三运算放大器的同相输入端连接至参考电压，所述第三运算放大器的输出端输出调节后的反馈信号。
可选的，所述预设负反馈增益根据所述第二反馈控制电阻与所述第一反馈控制电阻的阻值的比值来确定。
可选的，所述差分放大电路包括：第四运算放大器、第五运算放大器、第六运算放大器、第九电阻和第十电阻、第十一电阻和第十二电阻、第十三电阻和第十四电阻、第十五电阻和第十六电阻；其中，第九电阻和第十电阻的阻值相同、第十一电阻和第十二电阻的阻值相同、第十三电阻和第十四电阻的阻值相同、第十五电阻和第十六电阻的阻值相同；所述第四运算放大器的同相输入端为所述差分放大电路的第一输入端、所述第五运算放大器的同相输入端为所述差分放大电路的第二输入端；
所述第九电阻的一端与所述第十电阻的一端分别连接至所述第二运算放大器的同相输入端，且所述第九电阻的另一端连接至所述第四运算 放大器的反相输入端、所述第十电阻的另一端连接至所述第五运算放大器的反相输入端；所述差分放大电路的反馈信号为所述第九电阻与所述第十电阻之间的分压电压；
所述第十一电阻的一端连接至所述第四运算放大器的反相输入端、所述第十一电阻的另一端连接至所述第四运算放大器的输出端；所述第十二电阻的一端连接至所述第五运算放大器的反相输入端、所述第十二电阻的另一端连接至所述第五运算放大器的输出端；
所述第十三电阻的一端连接至所述第四运算放大器的输出端、所述第十三电阻的另一端连接至所述第六运算放大器的反相输入端；所述第十四电阻的一端连接至所述第五运算放大器的输出端、所述第十四电阻的另一端连接至所述第六运算放大器的同相输入端；
所述第十五电阻的一端连接至所述第六运算放大器的反相输入端、所述第十五电阻的另一端连接至所述第六运算放大器的输出端；所述第十六电阻的一端连接至所述第六运算放大器的同相输入端、所述第十六电阻的另一端连接至参考电压。
可选的，模拟前端电路还包括前置缓冲单元；所述前置缓冲单元分别将接收到的第一信号源发出的第一模拟信号和第二信号源发出的第二模拟信号经电压跟随后得到所述第一输入信号和所述第二输入信号，并将所述第一输入信号和所述第二输入信号传递至所述共模前馈单元。
可选的，所述前置缓冲单元包括：第七运算放大器、第八运算放大器、第十七电阻和第十八电阻；其中，第十七电阻和第十八电阻的阻值相同；所述第七运算放大器的同相输入端连接至所述第十七电阻的一端、所述第七运算放大器的反相输入端连接至所述第七运算放大器的输出端；所述第十七电阻的另一端连接至第一模拟信号；所述第八运算放大器的同相输入端连接至所述第十八电阻的一端、所述第八运算放大器的反相输入端连接至所述第八运算放大器的输出端；所述第十八电阻的另一端连接至第二模拟信号；所述第七运算放大器的输出端输出所述第一输入信号至所述共模前馈单元、所述第八运算放大器的输出端输出所述第二输入信号至所述共模前馈单元。
另一方面，本申请实施例还提供了一种信号采集设备，包括上述模拟前端电路。
与现有技术相比，本技术方案至少具有如下有益效果：
根据本申请实施例提供的模拟前端电路，通过共模前馈单元从第一输入信号与第二输入信号中获取共模分量，再经由耦合单元将共模分量经分压后得到输出共模分量，并将输出共模分量直流耦合至差分放大电路的输入端。耦合单元还将所述第一输入信号与所述第二输入信号的差模分量交流耦合至所述差分放大电路的输入端。通过“差模分量交流耦合，共模分量直流耦合”的设计，使本申请的模拟前端电路具有了普通交流耦合电路的高通滤波器特性，同时避免了普通直流耦合电路“共模偏差转化为差模信号，导致差模增益不能太高”的缺点。
通过共模负反馈单元接收差分放大电路的反馈信号，并根据预设负反馈增益对反馈信号进行调节，以使调节后的反馈信号抑制共模分量。通过“共模前馈结合共模负反馈”的方式，自动实现了共模分量直接相减，从而极大的提升了模拟前端电路的CMRR。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1是本申请的一种模拟前端电路的电路模块结构示意图；
图2是本申请的一实施例中模拟前端电路的具体电路结构示意图；
图3是本申请的一实施例中模拟前端电路与普通电路的差模幅频响应曲线效果对比图；
图4是本申请的一实施例中模拟前端电路与普通电路的共模幅频响应曲线效果对比图；
图5是本申请的一实施例中模拟前端电路与普通电路的输入电 压与输出电压Vout对比效果图。
具体实施方式
为了更好的理解本申请的技术方案，下面结合附图对本申请实施例进行详细描述。
应当明确，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本申请保护的范围。
图1是本申请的一种模拟前端电路的电路模块结构示意图。
参考图1，所述模拟前端电路1包括：前置缓冲单元11、共模前馈单元12、耦合单元13、共模负反馈单元14以及差分放大电路15。其中，所述前置缓冲单元11分别将接收到的第一信号源(图1中未示出)发出的第一模拟信号和第二信号源(图1中未示出)发出的第二模拟信号经电压跟随后得到第一输入信号和第二输入信号，并将所述第一输入信号和所述第二输入信号传递至所述共模前馈单元12。所述共模前馈单元12从接收到的第一输入信号与第二输入信号获取共模分量。所述耦合单元13将所述共模分量经分压后得到输出共模分量，并将所述输出共模分量直流耦合至所述差分放大电路15的输入端。所述耦合单元13还将所述第一输入信号与所述第二输入信号的差模分量交流耦合至所述差分放大电路15的输入端。所述共模负反馈单元14接收所述差分放大电路15的反馈信号，并根据预设负反馈增益对所述反馈信号进行调节，以使调节后的反馈信号抑制所述共模分量。
本实施例所述的模拟前端电路1可以应用于信号采集设备(例如心电图设备)，通常这类信号采集设备所采集的信号幅度较小(例如0.1mV～5mV)、频率较低(例如0.05Hz～100Hz)，是一种低频率的微弱模拟信号，存在较大的共模干扰，因此通过模拟前端电路对接收到模拟信号中的差模分量放大并抑制共模分量，以提高采集信号的精确度。
如背景技术中所述，无论是直流耦合还是交流耦合的普通电路，其抑制共模分量的效果主要取决于普通电路中差分放大电路的共模抑制比。其中，交流耦合(AC Coupling)是指通过隔直电容耦合去掉直流分量；直流耦合(DC Coupling)是指保留直流分量和交流分量，并不去掉交流分量。但是普通电路中差分放大电路的共模抑制比效果不佳，不能很好地抑制共模分量。
因此，发明人经过研究，对现有的普通电路进行改进。如图1所示，在模拟前端电路1中增加了前置缓冲单元11、共模前馈单元12、耦合单元13以及共模负反馈单元14。
具体来说，所述前置缓冲单元11具有高阻抗特性，因此即使第一信号源(图1中未示出)发出的第一模拟信号和第二信号源(图1中未示出)发出的第二模拟信号很微弱也能驱动所述前置缓冲单元11，并经过电压跟随后得到稳定的所述第一输入信号和所述第二输入信号。
通过所述共模前馈单元12从所述第一输入信号和所述第二输入信号获取共模分量，再经由所述耦合单元13将所述共模分量经分压后得到输出共模分量，并将所述输出共模分量直流耦合至所述差分放大电路15的输入端。所述耦合单元13还将所述第一输入信号与所述第二输入信号的差模分量交流耦合至所述差分放大电路15的输入端。
例如，所述第一输入信号为V 1、所述第二输入信号为V 2，所述第一输入信号和所述第二输入信号的共模分量为V Com，差模分量为V Diff。本领域技术人员理解，无论第一输入信号还是第二输入信号都可以表示为差模分量和共模分量之和，其中共模分量就是两个信号共同拥有的部分，即所述第一输入信号和所述第二输入信号的共模分量V Com＝(V 1+V 2)/2。对于所述第一输入信号，其差模分量为：V 1-(V 1+V 2)/2＝(V 1-V 2)/2；对于所述第二输入信号，其差模分量为：V 2-(V 1+V 2)/2＝-(V 1-V 2)/2。
在实际电路实现时，所述耦合单元13在将所述第一输入信号和所述第二输入信号的共模分量传递至所述差分放大电路15的输入端过程中，所述共模分量会经过电阻分压后得到所述耦合单元13的输出共模分量， 然后将所述输出共模分量传递至所述差分放大电路15。因此，所述输出共模分量并不完全等于所述第一输入信号和所述第二输入信号的共模分量，在下文的实施例中将结合所述耦合单元13的具体电路结构描述所述输出共模分量与所述第一输入信号和所述第二输入信号的共模分量之间的关系。
进一步，在实际电路实现时，所述耦合单元13中通过电容和电阻组成一个仅对差模分量有效的1阶高通滤波器，从而可以降低模拟前端电路输出端的带外噪声。
通过所述共模负反馈单元14从所述差分放大电路15获取反馈信号。在实际电路实现时，所述共模负反馈单元14获取到的所述反馈信号等于所述输出共模分量。然后，所述共模负反馈单元14通过设置运算放大器的预设负反馈增益对所述反馈信号进行调节，使得调节后的反馈信号尽量逼近所述第一输入信号和所述第二输入信号的共模分量，从而达到抑制所述共模分量的效果。
下面结合具体的电路结构示意图对本申请实施例提供的模拟前端电路的工作原理进行描述。
图2是本申请的一实施例中模拟前端电路的具体电路结构示意图。
参考图2，所述模拟前端电路2包括：前置缓冲单元21、共模前馈单元22、耦合单元23、共模负反馈单元24以及差分放大电路25。
所述模拟前端电路2接收第一信号源26发出的第一模拟信号Vi 1和第二信号源27发出的第二模拟信号Vi 2，经由所述前置缓冲单元21、所述共模前馈单元22、所述耦合单元23、所述共模负反馈单元24以及所述差分放大电路25处理后，通过所述差分放大电路25的输出端输出信号V out。
具体来说，所述前置缓冲单元21包括：第七运算放大器211、第八运算放大器212、第十七电阻R 1和第十八电阻R 2；其中，第 十七电阻R 1和第十八电阻R 2的阻值相同。
所述第七运算放大器211的同相输入端连接至所述第十七电阻R 1的一端、所述第七运算放大器211的反相输入端连接至所述第七运算放大器211的输出端；所述第十七电阻R 1的另一端连接至第一模拟信号Vi 1。
所述第八运算212放大器的同相输入端连接至所述第十八电阻R 2的一端、所述第八运算放大器212的反相输入端连接至所述第八运算放大器212的输出端；所述第十八电阻R 2的另一端连接至第二模拟信号Vi 2。
在本实施例中，所述第七运算放大器211的反相输入端与所述第七运算放大器211的输出端之间还连接有第十九电阻R 3。所述第八运算放大器212的反相输入端与所述第八运算放大器212的输出端之间还连接有第二十电阻R 4，且所述第十九电阻R 3和所述第二十电阻R 4的阻值相同。
所述第七运算放大器211的输出端输出所述第一输入信号U 1至所述共模前馈单元22、所述第八运算放大器212的输出端输出所述第二输入信号U 2至所述共模前馈单元22。
所述第七运算放大器211和所述第八运算放大器212是电压跟随器。本领域技术人员知晓，电压跟随器的作用是输出电压随着输入电压的变化而变化(即输出电压＝输入电压)。具体到本实施例中，所述第一信号源26发出的第一模拟信号Vi 1通过所述第七运算放大器211经电压跟随后输出的所述第一输入信号U 1与第一模拟信号Vi 1相同、所述第二信号源27发出的第二模拟信号Vi 2通过所述第八运算放大器212经电压跟随后输出的所述第二输入信号U 2与第二模拟信号Vi 2相同。由于第一模拟信号Vi 1和第二模拟信号Vi 2较微弱，经过电压跟随后可以得到较为稳定的所述第一输入信号U 1和所述第二输入信号U 2。
所述共模前馈单元22包括第一运算放大器221，第一电阻R 5和第二电阻R 6；其中，所述第一电阻R 5与所述第二电阻R 6的阻值相同。
所述第一电阻R 5的一端与所述第二电阻R 6的一端分别连接至所述第一运算放大器221的同相输入端，所述第一电阻R 5的另一端连接至所述第七运算放大器211的输出端(即所述共模前馈单元22的一个输入端)，所述第二电阻R 6的另一端连接至所述第八运算放大器212的输出端(即所述共模前馈单元22的另一个输入端)。
所述第一运算放大器221的同相输入端连接至所述第一电阻R 5与所述第二电阻R 6之间的分压点、所述第一运算放大器221的反相输入端连接至所述第一运算放大器221的输出端。在本实施例中，所述第一运算放大器221的反相输入端与所述第一运算放大器221的输出端之间还连接有电阻R 7。
由于所述第一电阻R 5与所述第二电阻R 6的阻值相同，因此，所述第一运算放大器221的同相输入端输入的电压为(U 1+U 2)/2。根据运算放大器的虚短性质可知，所述第一运算放大器221的输出端输出的电压也为(U 1+U 2)/2。因此，所述第一运算放大器221的输出端输出的是所述第一输入信号U 1与所述第二输入信号U 2的共模分量。
所述耦合单元23包括：第一电容器C 1和第二电容器C 2、第三电阻R 8和第四电阻R 9、第五电阻R 10和第六电阻R 11以及第七电阻R 12和第八电阻R 13；其中，所述第一电容器C 1和所述第二电容器C 2的电容相同、所述第三电阻R 8和所述第四电阻R 9的阻值相同、所述第五电阻R 10和所述第六电阻R 11的阻值相同、所述第七电阻R 12和所述第八电阻R 13的阻值相同。
所述第一输入信号U 1的差模分量经由所述第一电容器C 1和所述第五电阻R 10，并通过所述第五电阻R 10与所述第七电阻R 12之间的分压点VP1交流耦合至所述差分放大电路25的第一输入端。所述第二输入信号U 2的差模分量经由所述第二电容器C 2和所述第六电阻R 11，并通过所述第六电阻R 11与所述第八电阻R 13之间的分压点VP2交流耦合至所述差分放大电路25的第二输入端。
可以看出，所述耦合单元23分别通过所述第一电容器C 1和所述第二电容器C 2将所述第一输入信号U 1与所述第二输入信号U 2的差模分量 交流耦合至所述差分放大电路25的输入端。其中，所述第一电容器C 1和所述第二电容器C 2作为隔直电容，去除第一输入信号U 1与所述第二输入信号U 2中的直流分量。
进一步，在所述耦合单元23中，所述第五电阻R 10和所述第七电阻R 12串联，再与所述第三电阻R 8并联，再与所述第一电容器C 1串联形成所述第一输入信号U 1的差模分量的第一高通滤波器(即C 1和R 8//(R 10+R 12))。
所述第六电阻R 11和所述第八电阻R 13串联，再与所述第四电阻R 9并联，再与所述第二电容器C 2串联形成所述第二输入信号U 2的差模分量的第二高通滤波器(即C 2和R 9//(R 11+R 13))。
通过高通滤波器可以滤除低频信号，从而降低模拟前端电路输出端的带外噪声。其中，所述第一高通滤波器的高通截止频率为：fc 1＝1/(2×π×C 1×[R 8//(R 10+R 12)])；所述第一高通滤波器的高通截止频率为：fc 2＝1/(2×π×C 2×[R 9//(R 11+R 13)])。
所述第一运算放大器221的输出端连接至所述第三电阻R 8与第四电阻R 9之间的分压点VFW。所述第三电阻R 8和所述第五电阻R 10之间的分压点为VC1、所述第四电阻R 9和所述第六电阻R 11之间的分压点为VC2。
所述第一输入信号U 1与所述第二输入信号U 2的共模分量经所述第三电阻R 8、所述第五电阻R 10和所述第七电阻R 12分压后得到输出共模分量，且所述输出共模分量通过所述第五电阻R 10与所述第七电阻R 12之间的分压点VP1直流耦合至所述差分放大电路25的第一输入端。
所述第一输入信号U 1与所述第二输入信号U 2的共模分量经所述第四电阻R 9、所述第六电阻R 11和所述第八电阻R 13分压后得到输出共模分量，且所述输出共模分量通过所述第六电阻R 11与所述第八电阻R 13之间的分压点VP2直流耦合至所述差分放大电路25的第二输入端。
根据电路对称性可知，所述第三电阻R 8和所述第五电阻R 10之间的分压点为VC1的电压与所述第四电阻R 9和所述第六电阻R 11之间的分压点为VC2的电压相同。所述第五电阻R 10与所述第七电阻R 12之间 的分压点VP1的电压与所述第六电阻R 11与所述第八电阻R 13之间的分压点VP2的电压相同。
所述共模负反馈单元24包括第二运算放大器242、第三运算放大器241、第一反馈控制电阻R 15和第二反馈控制电阻R 14。其中，所述第二运算放大器242的同相输入端输入所述差分放大电路25的反馈信号，所述第二运算放大器242的反相输入端与所述第二运算放大器242的输出端相连接。本实施例中，所述第二运算放大器242的反相输入端与所述第二运算放大器242的输出端之间还连接有电阻R 16。
所述第一反馈控制电阻R 15的一端与所述第二运算放大器242的输出端连接，所述第一反馈控制电阻R 15的另一端与所述第三运算放大器241的反相输入端连接。
所述第二反馈控制电阻R 14的一端与所述第三运算放大器241的反相输入端连接，所述第二反馈控制电阻R 14的另一端与所述第三运算放大器241的输出端相连接。所述第三运算放大器241的同相输入端连接至参考电压VREF。其中，所述预设负反馈增益根据所述第二反馈控制电阻R 14与所述第一反馈控制电阻R 15的阻值的比值来确定，即所述预设负反馈增益G＝-R 14/R 15。
具体来说，所述第二运算放大器242对同相输入端输入的所述差分放大电路25的反馈信号起到电压跟随作用，因此所述第二运算放大器242的输出端输出的信号电压为所述反馈信号。
所述第三运算放大器241的同相输入端连接至参考电压VREF，所述第三运算放大器241的反相输入端接收所述第二运算放大器242的输出端输出的反馈信号，根据预设负反馈增益对反馈信号进行调节后，通过所述第三运算放大器241的输出端输出调节后的反馈信号。所述调节后的反馈信号的极性与所述第三运算放大器241的反相输入端接收到的反馈信号的极性相反，即预设负反馈增益G＝-R 14/R 15。
所述差分放大电路25包括：第四运算放大器251、第五运算放大器252、第六运算放大器253、第九电阻R 17和第十电阻R 18、第十一电阻R 19和第十二电阻R 20、第十三电阻R 21和第十四电阻 R 22、第十五电阻R 23和第十六电阻R 24；其中，第九电阻R 17和第十电阻R 18的阻值相同、第十一电阻R 19和第十二电阻R 20的阻值相同、第十三电阻R 21和第十四电阻R 22的阻值相同、第十五电阻R 23和第十六电阻R 24的阻值相同。
所述第四运算放大器251的同相输入端为所述差分放大电路25的第一输入端、所述第五运算放大器252的同相输入端为所述差分放大电路25的第二输入端。
所述第九电阻R 17的一端与所述第十电阻R 18的一端分别连接至所述第二运算放大器242的同相输入端，且所述第九电阻R 17的另一端连接至所述第四运算放大器251的反相输入端、所述第十电阻R 18的另一端连接至所述第五运算放大器252的反相输入端。
所述第十一电阻R 19的一端连接至所述第四运算放大器251的反相输入端、所述第十一电阻R 19的另一端连接至所述第四运算放大器251的输出端。所述第十二电阻R 20的一端连接至所述第五运算放大器252的反相输入端、所述第十二电阻R 20的另一端连接至所述第五运算放大器252的输出端。
所述第十三电阻R 21的一端连接至所述第四运算放大器251的输出端、所述第十三电阻R 21的另一端连接至所述第六运算放大器253的反相输入端；所述第十四电阻R 22的一端连接至所述第五运算放大器252的输出端、所述第十四电阻R 22的另一端连接至所述第六运算放大器253的同相输入端。
所述第十五电阻R 23的一端连接至所述第六运算放大器253的反相输入端、所述第十五电阻R 23的另一端连接至所述第六运算放大器253的输出端。所述第十六电阻R 24的一端连接至所述第六运算放大器253的同相输入端、所述第十六电阻R 24的另一端连接至参考电压VREF。
在本实施例中，所述差分放大电路25的反馈信号为所述第九电阻R 17与所述第十电阻R 18之间的分压电压。
具体来说，所述第四运算放大器251的同相输入端的输入电压为 VP1，所述第五运算放大器252的同相输入端的输入电压为VP2。根据运算放大器虚短性质，所述第四运算放大器251的反相输入端的电压也为VP1、所述第五运算放大器252的反相输入端的电压也为VP2。由于所述第九电阻R 17与所述第十电阻R 18的阻值相同，因此所述第九电阻R 17与所述第十电阻R 18之间的分压电压为(VP2-VP1)/2+VP1或者(VP1-VP2)/2+VP2，两种计算方式得到的结果均为(VP2+VP1)/2。根据电路对称性得到VP1＝VP2，因此所述差分放大电路25的反馈信号为VP1(或者VP2)。
因此，以VC1和VP1为例，根据电阻分压以及欧姆定律可以得到如下表达式：
(1)VC1＝(VFW-VFB)×β1，其中β1＝(R 10+R 12)/(R 8+R 10+R 12)；
(2)VP1＝(VC1-VFB)×β2，其中β2＝R 12/(R 10+R 12)；
又因为，(3)VFB＝G×VP1，其中反馈增益G＝-R 14/R 15；
因此，综合上述(1)、(2)和(3)，可以得到：
Figure PCTCN2019087730-appb-000001
因此，要减少输出共模分量VP1(以及VP2)，可以通过减小β1、β2，或者增大G来实现。由于在信号采集设备(例如心电图设备)中高通截止频率fc 1和fc 2的频率极低，因此不可将R 8、R 10、R 12(R 9、R 11、R 13)设计得太小，因此实际应用中，只需调整G值即可调节输出共模分量的抵消效果。
发明人采用本申请的模拟前端电路进行仿真实验得到差模幅频响应曲线和共模幅频响应曲线。其中，预设负反馈增益G＝-10。
图3是本申请的一实施例中模拟前端电路与普通电路的差模幅频响应曲线效果对比图。
参考图3，仿真发现，图中差模增益幅频曲线在400Hz以内，本申请的模拟前端电路和普通电路并无二致，当频率高到一定程度时，普通电路幅频曲线在放大器的主极点作用下按-20dB/Dec的斜 率滚降，而本申请的模拟前端电路会提供一个额外的极点，使高频段的幅频曲线按-40dB/Dec的斜率滚降，从而使模拟前端电路的输出端的噪声更低。
图4是本申请的一实施例中模拟前端电路与普通电路的共模幅频响应曲线效果对比图。
参考图4，图中共模增益幅频曲线在整个通带范围内，本申请的模拟前端电路的共模分量的增益都比普通电路低21.6dB，因为差模分量的增益相同，所以相当于本申请的模拟前端电路的CMRR比普通电路提升了21.6dB。
在实际应用中，若进一步提高预设负反馈增益G值，CMRR的提升量将会更大。
进一步，相比于直流耦合的普通电路，本申请的模拟前端电路通过共模前馈单元将共模分量经过分压后传递至差分放大电路，这样即使模拟前端电路的两个输入信号源的模拟信号(即第一信号源输出的第一模拟信号Vi1和第二信号源输出的第二模拟信号Vi2)存在直流偏差，差分放大电路也看不到，而直流耦合的普通电路却会将此直流偏差直接看成了差模信号，这将导致无法设置太大的差模增益且输出极易饱和，而本申请的模拟前端电路则不存在这个问题，如图5所示的是本申请的一实施例中模拟前端电路与普通电路的输入电压与输出电压V out对比效果图。
本申请实施例还提供了一种信号采集装置，所述信号采集装置包括上述实施例所述的模拟前端电路。在实际应用中，所述信号采集装置可以是ECG、各类传感器或者其他包含需要较高CMRR的小信号放大电路的信号采集装置。
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本申请保护的范围之内。

Claims (10)

  1. 一种模拟前端电路，包括差分放大电路，其特征在于，所述模拟前端电路还包括：共模前馈单元、耦合单元以及共模负反馈单元；其中，
    所述共模前馈单元从接收到的第一输入信号与第二输入信号获取共模分量；
    所述耦合单元将所述共模分量经分压后得到输出共模分量，并将所述输出共模分量直流耦合至所述差分放大电路的输入端；所述耦合单元还分别将所述第一输入信号的差模分量与所述第二输入信号的差模分量交流耦合至所述差分放大电路的输入端；
    所述共模负反馈单元接收所述差分放大电路的反馈信号，并根据预设负反馈增益对所述反馈信号进行调节，以使调节后的反馈信号抑制所述共模分量。
  2. 如权利要求1所述的模拟前端电路，其特征在于，所述共模前馈单元包括第一运算放大器，第一电阻和第二电阻；其中，所述第一电阻与所述第二电阻的阻值相同；
    所述第一电阻的一端与所述第二电阻的一端分别连接至所述第一运算放大器的同相输入端，所述第一电阻的另一端连接至所述共模前馈单元的一个输入端，所述第二电阻的另一端连接至所述共模前馈单元的另一个输入端；
    所述第一运算放大器的同相输入端连接至所述第一电阻与所述第二电阻之间的分压点、所述第一运算放大器的反相输入端连接至所述第一运算放大器的输出端；所述第一运算放大器的输出端输出所述第一输入信号与所述第二输入信号的共模分量。
  3. 如权利要求2所述的模拟前端电路，其特征在于，所述耦合单元包括：第一电容器和第二电容器、第三电阻和第四电阻、第五电阻和第六电阻以及第七电阻和第八电阻；
    其中，所述第一电容器和所述第二电容器的电容相同、所述第三电阻和所述第四电阻的阻值相同、所述第五电阻和所述第六电阻的阻值相同、 所述第七电阻和所述第八电阻的阻值相同；
    所述第一输入信号的差模分量经由所述第一电容器和所述第五电阻，并通过所述第五电阻与所述第七电阻之间的分压点交流耦合至所述差分放大电路的第一输入端；
    所述第二输入信号的差模分量经由所述第二电容器和所述第六电阻，并通过所述第六电阻与所述第八电阻之间的分压点交流耦合至所述差分放大电路的第二输入端；
    所述第一运算放大器的输出端连接至所述第三电阻与第四电阻之间的分压点；
    所述第一输入信号与所述第二输入信号的共模分量经所述第三电阻、所述第五电阻和所述第七电阻分压后得到输出共模分量，且所述输出共模分量通过所述第五电阻与所述第七电阻之间的分压点直流耦合至所述差分放大电路的第一输入端；
    所述第一输入信号与所述第二输入信号的共模分量经所述第四电阻、所述第六电阻和所述第八电阻分压后得到输出共模分量，且所述输出共模分量通过所述第六电阻与所述第八电阻之间的分压点直流耦合至所述差分放大电路的第二输入端。
  4. 如权利要求3所述的模拟前端电路，其特征在于，所述耦合单元包括用于对所述第一输入信号的差模分量进行滤波的第一高通滤波器；所述第一高通滤波器由所述第五电阻和所述第七电阻串联，再与所述第三电阻并联，再与所述第一电容器串联所形成；
    所述耦合单元还包括用于对所述第二输入信号的差模分量进行滤波的第二高通滤波器；所述第二高通滤波器由所述第六电阻和所述第八电阻串联，再与所述第四电阻并联，再与所述第二电容器串联所形成。
  5. 如权利要求3所述的模拟前端电路，其特征在于，所述共模负反馈单元包括第二运算放大器、第三运算放大器、第一反馈控制电阻和第二反馈控制电阻；其中，
    所述第二运算放大器的同相输入端连接所述差分放大电路的反馈信 号，所述第二运算放大器的反相输入端与所述第二运算放大器的输出端相连接；
    所述第一反馈控制电阻的一端与所述第二运算放大器的输出端连接，所述第一反馈控制电阻的另一端与所述第三运算放大器的反相输入端连接；
    所述第二反馈控制电阻的一端与所述第三运算放大器的反相输入端连接，所述第二反馈控制电阻的另一端与所述第三运算放大器的输出端相连接；
    所述第三运算放大器的同相输入端连接至参考电压，所述第三运算放大器的输出端输出调节后的反馈信号。
  6. 如权利要求5所述的模拟前端电路，其特征在于，所述预设负反馈增益根据所述第二反馈控制电阻与所述第一反馈控制电阻的阻值的比值来确定。
  7. 如权利要求5所述的模拟前端电路，其特征在于，所述差分放大电路包括：第四运算放大器、第五运算放大器、第六运算放大器、第九电阻和第十电阻、第十一电阻和第十二电阻、第十三电阻和第十四电阻、第十五电阻和第十六电阻；
    其中，第九电阻和第十电阻的阻值相同、第十一电阻和第十二电阻的阻值相同、第十三电阻和第十四电阻的阻值相同、第十五电阻和第十六电阻的阻值相同；
    所述第四运算放大器的同相输入端为所述差分放大电路的第一输入端、所述第五运算放大器的同相输入端为所述差分放大电路的第二输入端；
    所述第九电阻的一端与所述第十电阻的一端分别连接至所述第二运算放大器的同相输入端，且所述第九电阻的另一端连接至所述第四运算放大器的反相输入端，所述第十电阻的另一端连接至所述第五运算放大器的反相输入端；所述差分放大电路的反馈信号为所述第九电阻与所述第十电阻之间的分压电压；
    所述第十一电阻的一端连接至所述第四运算放大器的反相输入端， 所述第十一电阻的另一端连接至所述第四运算放大器的输出端；所述第十二电阻的一端连接至所述第五运算放大器的反相输入端，所述第十二电阻的另一端连接至所述第五运算放大器的输出端；
    所述第十三电阻的一端连接至所述第四运算放大器的输出端，所述第十三电阻的另一端连接至所述第六运算放大器的反相输入端；所述第十四电阻的一端连接至所述第五运算放大器的输出端，所述第十四电阻的另一端连接至所述第六运算放大器的同相输入端；
    所述第十五电阻的一端连接至所述第六运算放大器的反相输入端，所述第十五电阻的另一端连接至所述第六运算放大器的输出端；所述第十六电阻的一端连接至所述第六运算放大器的同相输入端，所述第十六电阻的另一端连接至参考电压。
  8. 如权利要求1所述的模拟前端电路，其特征在于，还包括前置缓冲单元；所述前置缓冲单元分别将接收到的第一信号源发出的第一模拟信号和第二信号源发出的第二模拟信号经电压跟随后得到所述第一输入信号和所述第二输入信号，并将所述第一输入信号和所述第二输入信号传递至所述共模前馈单元。
  9. 如权利要求8所述的模拟前端电路，其特征在于，所述前置缓冲单元包括：第七运算放大器、第八运算放大器、第十七电阻和第十八电阻；其中，第十七电阻和第十八电阻的阻值相同；
    所述第七运算放大器的同相输入端连接至所述第十七电阻的一端，所述第七运算放大器的反相输入端连接至所述第七运算放大器的输出端；所述第十七电阻的另一端连接至第一模拟信号；
    所述第八运算放大器的同相输入端连接至所述第十八电阻的一端，所述第八运算放大器的反相输入端连接至所述第八运算放大器的输出端；所述第十八电阻的另一端连接至第二模拟信号；
    所述第七运算放大器的输出端输出所述第一输入信号至所述共模前馈单元，所述第八运算放大器的输出端输出所述第二输入信号至所述共模前馈单元。
  10. 一种信号采集装置，其特征在于，包括权利要求1～9中任一项所述 的模拟前端电路。
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114184856A (zh) * 2021-12-06 2022-03-15 中国计量科学研究院 一种基于全差分结构的热噪声检测装置及噪声温度计
CN115276797A (zh) * 2022-06-27 2022-11-01 深圳麦科信科技有限公司 激光传输电路、激光传输组件和电子测量仪器
GB2606825A (en) * 2021-03-08 2022-11-23 Cirrus Logic Int Semiconductor Ltd Frequency-selective common-mode control and output stage biasing in an operational amplifier for a class-D amplifier loop filter
CN115426000A (zh) * 2022-08-31 2022-12-02 集益威半导体(上海)有限公司 模拟接收前端电路
CN115951105A (zh) * 2023-03-09 2023-04-11 苏州联讯仪器股份有限公司 一种电信号采样通道装置及采样示波器
CN116818795A (zh) * 2023-08-31 2023-09-29 中国地质大学（武汉） 一种管道光电无损检测系统
CN116991304A (zh) * 2023-08-01 2023-11-03 北京交通大学 一种力信号采集与监测电路

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113253027A (zh) * 2021-05-13 2021-08-13 宁波水表(集团)股份有限公司 电磁水表的转换器测量电路
CN114640349A (zh) * 2022-05-12 2022-06-17 苏州联讯仪器有限公司 一种差分信号采样电路、差分信号的采样方法及装置
CN115296631B (zh) * 2022-07-15 2023-05-12 广州致远仪器有限公司 一种差分电路、电路板及电子设备

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120095361A1 (en) * 2010-10-15 2012-04-19 Stichting Imec Nederland Multi-channel biopotential signal acquisition systems
CN104757964A (zh) * 2015-04-13 2015-07-08 深圳市飞马与星月科技研究有限公司 心电信号采集的超高共模抑制电路及心电采集设备
CN205144555U (zh) * 2015-11-26 2016-04-13 江苏盖睿健康科技有限公司 一种两电极单导心电前端采集电路
CN106419894A (zh) * 2016-10-11 2017-02-22 江苏南大五维电子科技有限公司 一种用于生理电信号采集前端处理电路
CN109512419A (zh) * 2018-11-30 2019-03-26 湖南大学 信号处理电路

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120095361A1 (en) * 2010-10-15 2012-04-19 Stichting Imec Nederland Multi-channel biopotential signal acquisition systems
CN104757964A (zh) * 2015-04-13 2015-07-08 深圳市飞马与星月科技研究有限公司 心电信号采集的超高共模抑制电路及心电采集设备
CN205144555U (zh) * 2015-11-26 2016-04-13 江苏盖睿健康科技有限公司 一种两电极单导心电前端采集电路
CN106419894A (zh) * 2016-10-11 2017-02-22 江苏南大五维电子科技有限公司 一种用于生理电信号采集前端处理电路
CN109512419A (zh) * 2018-11-30 2019-03-26 湖南大学 信号处理电路

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2606825A (en) * 2021-03-08 2022-11-23 Cirrus Logic Int Semiconductor Ltd Frequency-selective common-mode control and output stage biasing in an operational amplifier for a class-D amplifier loop filter
US11522509B2 (en) 2021-03-08 2022-12-06 Cirrus Logic, Inc. Frequency-selective common-mode control and output stage biasing in an operational amplifier for a class-D amplifier loop filter
GB2606825B (en) * 2021-03-08 2023-07-05 Cirrus Logic Int Semiconductor Ltd Frequency-selective common-mode control and output stage biasing in an operational amplifier for a class-D amplifier loop filter
CN114184856A (zh) * 2021-12-06 2022-03-15 中国计量科学研究院 一种基于全差分结构的热噪声检测装置及噪声温度计
CN115276797A (zh) * 2022-06-27 2022-11-01 深圳麦科信科技有限公司 激光传输电路、激光传输组件和电子测量仪器
CN115276797B (zh) * 2022-06-27 2023-08-25 深圳麦科信科技有限公司 激光传输电路、激光传输组件和电子测量仪器
CN115426000B (zh) * 2022-08-31 2023-07-04 集益威半导体(上海)有限公司 模拟接收前端电路
CN115426000A (zh) * 2022-08-31 2022-12-02 集益威半导体(上海)有限公司 模拟接收前端电路
CN115951105A (zh) * 2023-03-09 2023-04-11 苏州联讯仪器股份有限公司 一种电信号采样通道装置及采样示波器
CN116991304A (zh) * 2023-08-01 2023-11-03 北京交通大学 一种力信号采集与监测电路
CN116991304B (zh) * 2023-08-01 2024-05-14 北京交通大学 一种力信号采集与监测电路
CN116818795A (zh) * 2023-08-31 2023-09-29 中国地质大学（武汉） 一种管道光电无损检测系统
CN116818795B (zh) * 2023-08-31 2023-12-19 中国地质大学（武汉） 一种管道光电无损检测系统

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