WO2020230456A1

WO2020230456A1 - Insulated gate bipolar transistor

Info

Publication number: WO2020230456A1
Application number: PCT/JP2020/013177
Authority: WO
Inventors: Yuki Yakushigawa; Masaru Senoo; Masanori Miyata; Shuji Yoneda
Original assignee: Denso Corporation
Priority date: 2019-05-15
Filing date: 2020-03-24
Publication date: 2020-11-19
Also published as: JP2020188168A

Abstract

An insulated gate bipolar transistor may include a semiconductor substrate, an emitter electrode, a collector electrode, a gate electrode, and a gate insulating film. The semiconductor substrate may include: a p-type collector region disposed at a lower surface of the semiconductor substrate and being in contact with the collector electrode; an n-type region disposed above the collector region; a p-type body region separated from the collector region by the n-type region; and an emitter region disposed at an upper surface of the semiconductor substrate, separated from the n-type region by the body region, and being in contact with the emitter electrode. The gate electrode may be opposed to a portion of the body region that separates the emitter region and the n-type region via the gate insulating film. An n-type impurity concentration at an interface between the n-type region and the collector region may be 100 times or more a minimum value of an n-type impurity concentration of the n-type region.

Description

INSULATED GATE BIPOLAR TRANSISTOR

Cross-Reference to Related Application

This application claims priority to Japanese Patent Application No. 2019-092437 filed on May 15, 2019, the contents of which are hereby incorporated by reference into the present application.

A technique disclosed herein relates to an insulated gate bipolar transistor.

Patent Literature 1 describes an insulated gate bipolar transistor (IGBT) including a semiconductor substrate provided with a collector region, an n-type region, a body region, and an emitter region. An emitter electrode is disposed on an upper surface of the semiconductor substrate, and a collector electrode is disposed on a lower surface of the semiconductor substrate. The collector region is of p-type, is disposed at the lower surface of the semiconductor substrate, and is in contact with the collector electrode. The n-type region is disposed above the collector region. In this IGBT, a peak concentration of p-type impurities in the collector region is 10 to 100 times a peak concentration of n-type impurities in the n-type region.

The IGBT of Patent Literature 1 suppresses holes from flowing into the n-type region from the collector region by controlling the peak concentration of p-type impurities in the collector region within the abovementioned range relative to the peak concentration of n-type impurities in the n-type region. According to Patent Literature 1, this mitigates an electric field applied to a p-n junction between the collector region and the n-type region, by which the IGBT’s tolerability against short circuit is improved.

[Patent Literature 1] Japanese Patent Application Publication No. 2007-243212

As a result of study by the inventors of the present disclosure, it has been found that IGBT’s tolerability against short circuit may be decreased even when a peak concentration of p-type impurities in a collector region is controlled as described in Patent Literature 1. The disclosure herein provides a technique that ensures tolerability of an IGBT.

The disclosure herein discloses an insulated gate bipolar transistor. The insulated gate bipolar transistor may comprise a semiconductor substrate, an emitter electrode disposed on an upper surface of the semiconductor substrate, a collector electrode disposed on a lower surface of the semiconductor substrate, a gate electrode, and a gate insulating film. The semiconductor substrate may comprise a p-type collector region disposed at the lower surface of the semiconductor substrate and being in contact with the collector electrode, an n-type region disposed above the collector region, a p-type body region separated from the collector region by the n-type region, and an emitter region disposed at the upper surface of the semiconductor substrate, separated from the n-type region by the body region, and being in contact with the emitter electrode. The gate electrode may be opposed to a portion of the body region that separates the emitter region and the n-type region via the gate insulating film. An n-type impurity concentration at an interface between the n-type region and the collector region may be 100 times or more a minimum value of an n-type impurity concentration of the n-type region.

FIG. 4 shows distributions of impurity concentrations in the collector region and the n-type region. In FIG. 4, reference sign 234 indicates a distribution of n-type impurity concentration, and reference sign 238 indicates distributions of p-type impurity concentration. FIG. 4 shows three different distributions of p-type impurity concentration indicated by reference signs 238a to 238c, respectively. In FIG. 4, an area where the p-type impurity concentration is higher than the n-type impurity concentration corresponds to the p-type collector region, and an area where the n-type impurity concentration is higher than the p-type impurity concentration corresponds to the n-type region. Further, positions of intersections X, Y, Z between the line 234 and each of the lines 238a to 238c correspond to an interface (i.e., p-n junction) between the collector region and the n-type region. Varying the p-type impurity concentration as indicated by the lines 238a to 238c varies the impurity concentration at the p-n junction. FIG. 5 shows simulation results on how an electric field applied to the semiconductor substrate varies when the p-type impurity concentration is varied as shown in FIG. 4. Here, it should be noted that FIGS. 4 and 5 merely show examples for explanatory purpose, and the technique disclosed herein is not limited to the examples shown in FIGS. 4 and 5. Reference sign A in FIG. 5 indicates a line corresponding to the impurity concentration distribution of reference sign 238a in FIG. 4, reference sign B in FIG. 5 indicates a line corresponding to the impurity concentration distribution of reference sign 238b in FIG. 4, and reference sign C in FIG. 5 indicates a line corresponding to the impurity concentration distribution of reference sign 238c in FIG. 4. As exemplified in FIGS. 4 and 5, in the distribution indicated by reference sign 238a, a value of the n-type impurity concentration (point X) at the interface between the n-type region and the collector region is less than 100 times a minimum value of the n-type impurity concentration in the n-type region (point m). In this case, it was found that the electric field applied to the semiconductor substrate is high as indicated by reference A in FIG. 5. In the distributions indicated by

reference signs

238b and 238c, values of the n-type impurity concentration (points Y and Z) at the interface between the n-type region and the collector region are 100 times or more the minimum value of the n-type impurity concentration in the n-type region. In these cases, it was found that the electric field applied to the semiconductor substrate is significantly decreased as indicated by reference signs B and C in FIG. 5.

As described above, in the insulated gate bipolar transistor disclosed herein, the n-type impurity concentration at the interface between the n-type region and the collector region is 100 times or more the minimum value of the n-type impurity concentration in the n-type region. Thus, an electric field applied to the semiconductor substrate can be significantly decreased. Due to this, this insulated gate bipolar transistor can have high tolerability against short circuit.

FIG. 1 is a cross-sectional view of an IGBT 10 according to a first embodiment. FIG. 2 is a graph showing distributions of impurity concentrations along a line II-II in FIG. 1. FIG. 3 is a graph showing distributions of impurity concentrations at a cross section of an IGBT according to a second embodiment, where the cross section corresponds to the one in FIG. 2. FIG. 4 is a diagram showing distributions of impurity concentrations in IGBTs of embodiments and an IGBT of a comparative example. FIG. 5 is a diagram showing simulation results on electric fields applied to a semiconductor substrate in the respective distributions of impurity concentrations shown in FIG. 4.

(First Embodiment)
FIG. 1 shows an insulated gate bipolar transistor 10 (called IGBT, hereinbelow) of a first embodiment. The IGBT 10 includes a semiconductor substrate 12, electrodes, insulating layers, and the like. The semiconductor substrate 12 is constituted of a semiconductor material such as silicon (Si) or silicon carbide (SiC). A plurality of trenches 22 is disposed in an upper surface 12a of the semiconductor substrate 12. The trenches 22 extend in parallel to each other along a perpendicular direction to the sheet surface of FIG. 1.

An inner surface of each trench 22 is covered with a gate insulating film 24. A gate electrode 26 is disposed in each trench 22. The gate electrodes 26 cover surfaces of their corresponding gate insulating films 24. The gate electrodes 26 are insulated from the semiconductor substrate 12 by the gate insulating films 24. An upper surface of each gate electrode 26 is covered with an interlayer insulating film 28.

An emitter electrode 70 is disposed on the upper surface 12a of the semiconductor substrate 12. The emitter electrode 70 is in contact with portions of the upper surface 12a of the semiconductor substrate 12 where the interlayer insulating films 28 are not disposed. The emitter electrode 70 is insulated from the gate electrodes 26 by the interlayer insulating films 28. A collector electrode 72 is disposed on a lower surface 12b of the semiconductor substrate 12. The collector electrode 72 is in contact with the lower surface 12b of the semiconductor substrate 12.

The semiconductor substrate 12 includes a plurality of emitter regions 30, a body region 32, a drift region 34, a buffer region 36, and a collector region 38.

Each emitter region 30 is an n-type region. The emitter regions 30 are disposed at positions that are disposed at the upper surface 12a of the semiconductor substrate 12. The emitter regions 30 are in contact with the emitter electrode 70. Each emitter region 30 is in contact with its corresponding gate insulating film 24 at a side surface of the trench 22. Each emitter region 30 is in contact with its corresponding gate insulating film 24 at an upper end portion of the trench 22.

The body region 32 is a p-type region. The body region 32 is in contact with the emitter regions 30. The body region 32 extends from areas interposed between two adjacent emitter regions 30 to below the emitter regions 30. The body region 32 includes contact regions 32a and a main body region 32b. The contact regions 32a has a higher p-type impurity concentration than the main body region 32b. Each contact region 32a is disposed between two adjacent emitter regions 30. The contact regions 32a are in contact with the emitter electrode 70. The main body region 32b is in contact with the gate insulating films 24 at the side surfaces of the trenches 22. The main body region 32b is in contact with the gate insulating films 24 below the emitter regions 30. The main body region 32b is opposed to the gate electrodes 26 via the gate insulating films 24.

The drift region 34 is an n-type region. The drift region 34 is disposed below the body region 32 and is separated from the emitter regions 30 by the body region 32. Below the body region 32, the drift region 34 is in contact with the gate insulating films 24 near lower end portions of the trenches 22. The drift region 34 has a lower n-type impurity concentration than the emitter regions 30 and the buffer region 36. The n-type impurity concentration of the drift region 34 is substantially constant. Specifically, the n-type impurity concentration of the drift region 34 is in a range of ±10% relative to an average value of the n-type impurity concentration.

The buffer region 36 is an n-type region and has a higher n-type impurity concentration than the drift region 34. The buffer region 36 is disposed below the drift region 34. The buffer region 36 and the drift region 34 configure a continuous n-type region.

The collector region 38 is a p-type region. The collector region 38 is disposed below the buffer region 36. The collector region 38 is disposed at the lower surface 12b of the semiconductor substrate 12. The collector region 38 is in contact with the collector electrode 72.

FIG. 2 is a graph showing distributions of impurity concentrations along a line II-II in FIG. 1. That is, FIG. 2 shows distributions of impurity concentrations on the lower surface 12b side of the semiconductor substrate 12. As shown in FIG. 2, an n-type impurity concentration at an interface 37 (i.e., p-n junction) between the buffer region 36 and the collector region 38 (approximately 4.0×10¹⁶ cm^-3) is 100 times or more (approximately 500 times) a minimum value of the n-type impurity concentration in the drift region 34 (n-type impurity concentration at a position indicated by reference sign m in FIG. 2 (approximately 8.0×1013 cm^-3)). The n-type impurity concentration in the buffer region 36 is distributed to have a peak P1 on an upper surface 12a side relative to the interface 37 between the buffer region 36 and the collector region 38.

Next, an operation of the IGBT 10 will be described. When a potential (i.e., gate-emitter voltage) that is equal to or greater than a gate threshold is applied to the gate electrodes 26, channels are formed in portions of the main body region 32b that are adjacent to the gate insulating films 24. When the channels are formed while a potential that makes the collector electrode 72 have a higher potential than the emitter electrode 70 is being applied, electrons flow from the emitter electrode 70 to the collector electrode 72 through the emitter regions 30, the channels in the main body region 32b, the drift region 34, the buffer region 36, and the collector region 38. At this time, holes flow from the collector electrode 72 to the emitter electrode 70 through the collector region 38, the buffer region 36, the drift region 34, the main body region 32b, and the contact regions 32a. That is, the IGBT 10 is turned on. In the IGBT 10 of the present embodiment, the n-type impurity concentration at the interface 37 between the buffer region 36 and the collector region 38 is relatively high (100 times or more the minimum value of the n-type impurity concentration in the drift region 34), thus the junction capacitance of the p-n junction at the interface 37 is relatively high. Since a high junction capacitance allows a current to easily flow through a p-n junction, the electrons that have flowed into the buffer region 36 from the emitter regions 30 are easily discharged to the collector electrode 72. Thus, accumulation of the electrons in the buffer region 36 is less likely to occur and an electric field generated in the buffer region 36 is decreased. Due to this, the IGBT 10 has high tolerability against short circuit.

When the potential on the gate electrodes 26 is decreased, the channels disappear, by which the IGBT is turned off. At this time, the holes that existed in the drift region 34 while the IGBT 10 was on are discharged to the emitter electrode 70 through the contact regions 32a. Flow of a current caused by such holes generates a loss when the IGBT 10 is turned off. However, the IGBT 10 of the first embodiment can suppress the loss generated when it is turned off, as follows. The IGBT 10 has high tolerability against short circuit because the n-type impurity concentration at the interface 37 between the collector region 38 and the buffer region 36 is high, as described above. In other words, high tolerability against short circuit can be ensured even when a peak concentration of p-type impurities in the collector region 38 is low, as long as the n-type impurity concentration at the interface 37 is high. For this reason, the peak concentration of p-type impurities in the collector region 38 is set to a relatively low value in the IGBT 10. Such a low peak concentration of p-type impurities in the collector region 38 suppresses holes from flowing into the drift region 34 from the collector region 38 while the IGBT 10 is on. As a result, the current caused by the holes discharged when the IGBT 10 is turned off (so-called tail current) flows only for a short time. Thus, in the IGBT 10 of the present embodiment, the loss generated when it is turned off is small.

In the above-described first embodiment, the n-type impurity concentration in the buffer region 36 is distributed to have the peak P1 on the upper surface 12a side relative to the interface 37 between the buffer region 36 and the collector region 38. However, the peak P1 may be located on the lower surface 12b side relative to the interface 37.

(Second Embodiment)
Next, an IGBT of a second embodiment will be described. In the IGBT of the second embodiment, a distribution of n-type impurity concentration in a buffer region 136 is different from that in the buffer region 36 in the first embodiment. FIG. 3 shows distributions of impurity concentrations at the same cross section as that in FIG. 2. As shown in FIG. 3, in the IGBT of the second embodiment, the n-type impurity concentration in the buffer region 136 further has a peak P2 and a peak P3, in addition to the peak P1 described in the first embodiment. The peak P2 is located on the upper surface 12a side of the semiconductor substrate 12 relative to the peak P1, and the peak P3 is located on the upper surface 12a side of the semiconductor substrate 12 relative to the peak P2. The n-type impurity concentration at the peak P2 is lower than the n-type impurity concentration at the peak P1, and the n-type impurity concentration at the peak P3 is lower than the n-type impurity concentration at the peak P2.

In a thickness direction of the semiconductor substrate 12, a distance D1 from a position of the peak P1 to a position of the peak P2 is greater than a distance D2 from the position of the peak P2 to a position of the peak P3. Further, a difference C1 between the n-type impurity concentrations at the peak P1 and the peak P2 is larger than a difference C2 between the n-type impurity concentrations at the peak P2 and the peak P3.

In the IGBT of the second embodiment, the n-type impurity concentration at an interface 137 between the buffer region 136 and the collector region 38 is 100 times or more a minimum value of the n-type impurity concentration in a drift region 134, as in the first embodiment. Thus, the IGBT of the second embodiment can bring the same effects as those of the first embodiment.

In the present embodiment, the n-type impurity concentration in the buffer region 136 has the three peaks P1, P2, and P3. The relatively long distance D1 from the peak P1 to the peak P2 allows a thickness of the buffer region 136 to be greater than a thickness of the buffer region 36 of the first embodiment. For example, when the lower surface 12b side of the semiconductor substrate 12 is damaged, the IGBT of the present embodiment that includes the buffer region 136 with the greater thickness can suppress the drift region 34 from being affected by the damage. Thus, the IGBT of the present embodiment can suppress variation in its characteristics such as pressure resistance.

In the present embodiment, the difference C1 between the n-type impurity concentrations at the peaks P1 and P2 is larger than the difference C2 between the n-type impurity concentrations at the peaks P2 and P3. That is, the n-type impurity concentrations at the peaks P2 and P3 are relatively low. This enables an amount of donors for an entirety of the buffer region 136 to be relatively small, while the thickness of the buffer region 136 is ensured. Therefore, in this IGBT, an electric field applied to the p-n junction at the interface 137 does not become so high, and tolerability of the IGBT against short circuit can be ensured.

In the second embodiment, the n-type impurity concentration in the buffer region 136 is distributed to have the peaks P1, P2, and P3. However, the peak P3 may be omitted in other embodiments.

Relationships between the constituent elements in the above-described embodiments and constituent elements in the claims will be described. The

drift regions

34, 134 and the

buffer regions

36, 136 in the embodiments are an example of “n-type region” in the claims. The peak P1, the peak P2, and the peak P3 in the embodiments are examples of “first peak”, “second peak”, and “third peak” in the claims, respectively.

Some of the technical features disclosed herein will be listed below. It should be noted that the respective technical elements are independent of one another, and are useful solely or in combinations.

In an aspect of IGBT disclosed herein, the n-type region may comprise: a buffer region disposed above the collector region; and a drift region disposed above the buffer region and having a substantially constant n-type impurity concentration lower than an n-type impurity concentration of the buffer region. The n-type impurity concentration of the buffer region may be distributed so as to have a first peak on an upper surface side of the semiconductor substrate relative to an interface between the buffer region and the collector region. It should be noted that “substantially constant” herein means that the n-type impurity concentration may distribute in a range of ±10% relative to its average value.

In an aspect of IGBT disclosed herein, the n-type impurity concentration of the buffer region may be distributed so as to have a second peak on the upper surface side relative to the first peak. The n-type impurity concentration at the first peak may be higher than the n-type impurity concentration at the second peak.

Such a configuration can ensure the thickness of the buffer region. For example, when the lower surface of the semiconductor substrate is damaged, such a configuration can suppress the drift region from being affected by the damage.

In an aspect of IGBT disclosed herein, the n-type impurity concentration of the buffer region may be distributed so as to have a third peak on the upper surface side relative to the second peak. The n-type impurity concentration at the second peak may be higher than the n-type impurity concentration at the third peak. In a thickness direction of the semiconductor substrate, a distance from the first peak to the second peak may be greater than a distance from the second peak to the third peak.

Such a configuration can ensure a larger thickness of the buffer region. For example, when the lower surface of the semiconductor substrate is damaged, such a configuration can suppress the drift region from being affected by the damage.

In an aspect of IGBT disclosed herein, a difference between the n-type impurity concentrations at the first peak and the second peak may be larger than a difference between the n-type impurity concentrations at the second peak and the third peak.

Such a configuration can ensure the thickness of the buffer region and can make an amount of electrons for the entirety of the buffer region relatively small. Thus, in such a configuration, an electric field applied to the interface between the collector region and the buffer region does not become so high, and thus tolerability against short circuit can be ensured.

While specific examples of the present disclosure have been described above in detail, these examples are merely illustrative and place no limitation on the scope of the claims. The technology described in the claims also encompasses various changes and modifications to the specific examples described above. The technical elements explained in the present description or drawings provide technical utility either independently or through various combinations. The present disclosure is not limited to the combinations described at the time the claims are filed. Further, the purpose of the examples illustrated by the present description or drawings is to satisfy multiple objectives simultaneously, and satisfying any one of those objectives gives technical utility to the present disclosure.

10: IGBT, 12: Semiconductor Substrate, 12a: Upper Surface, 12b: Lower Surface, 22: Trenches, 24: Gate Insulating Films, 26: Gate Electrodes, 28: Interlayer Insulating Films, 30: Emitter Regions, 32: Body Region, 32a: Contact Regions, 32b: Main Body Region, 34: Drift Region, 36: Buffer Region, 37: Interface, 38: Collector Region, 70: Emitter Electrode, 72: Collector Electrode

Claims

An insulated gate bipolar transistor comprising:
a semiconductor substrate;
an emitter electrode disposed on an upper surface of the semiconductor substrate;
a collector electrode disposed on a lower surface of the semiconductor substrate;
a gate electrode; and
a gate insulating film,
wherein
the semiconductor substrate comprises:
a p-type collector region disposed at the lower surface of the semiconductor substrate and being in contact with the collector electrode;
an n-type region disposed above the collector region;
a p-type body region separated from the collector region by the n-type region; and
an emitter region disposed at the upper surface of the semiconductor substrate, separated from the n-type region by the body region, and being in contact with the emitter electrode,
the gate electrode is opposed to a portion of the body region that separates the emitter region and the n-type region via the gate insulating film, and
an n-type impurity concentration at an interface between the n-type region and the collector region is 100 times or more a minimum value of an n-type impurity concentration of the n-type region.
The insulated gate bipolar transistor according to claim 1, wherein
the n-type region comprises:
a buffer region disposed above the collector region; and
a drift region disposed above the buffer region and having a substantially constant n-type impurity concentration lower than an n-type impurity concentration of the buffer region, and
the n-type impurity concentration of the buffer region is distributed so as to have a first peak on an upper surface side of the semiconductor substrate relative to an interface between the buffer region and the collector region.
The insulated gate bipolar transistor according to claim 2, wherein
the n-type impurity concentration of the buffer region is distributed so as to have a second peak on the upper surface side relative to the first peak, and
the n-type impurity concentration at the first peak is higher than the n-type impurity concentration at the second peak.
The insulated gate bipolar transistor according to claim 3, wherein
the n-type impurity concentration of the buffer region is distributed so as to have a third peak on the upper surface side relative to the second peak,
the n-type impurity concentration at the second peak is higher than the n-type impurity concentration at the third peak, and
in a thickness direction of the semiconductor substrate, a distance from the first peak to the second peak is greater than a distance from the second peak to the third peak.
The insulated gate bipolar transistor according to claim 4, wherein
a difference between the n-type impurity concentrations at the first peak and the second peak is larger than a difference between the n-type impurity concentrations at the second peak and the third peak.