WO2020227883A1

WO2020227883A1 - Data processing method, device, and system

Info

Publication number: WO2020227883A1
Application number: PCT/CN2019/086594
Authority: WO
Inventors: 王嘉兴; 李升林; 陈元丰
Original assignee: 云图有限公司
Priority date: 2019-05-13
Filing date: 2019-05-13
Publication date: 2020-11-19

Abstract

A data processing method, device, and system, the method comprising: on the basis of an LLVM compiler, compiling cryptographic protocol algorithm source code data to be processed, and acquiring initial LLVM intermediate code data (S202); performing no-jump static single assignment processing on the initial LLVM intermediate code data, and acquiring processed intermediate code data (S204); and converting the processed intermediate code data to acquire R1CS data (S206). Thus, the compiling processing of cryptographic algorithm source code data to R1CS data may be achieved more simply and efficiently.

Description

Data processing method, device and system

Technical field

The present invention relates to the field of computer data processing technology, in particular, to a data processing method, device and system.

Background technique

With the development of blockchain technology in recent years, zero-knowledge proofs and verifiable calculations have received widespread attention and use. The current mainstream zero-knowledge algorithms are usually not directly used to solve computational problems. The computational problems must be converted into the correct "form" for processing. This form is called QAP (quadratic arithmetic problem). In specific implementation, it is generally necessary to convert calculations into logic circuits first, and then into R1CS (rank-1 constraint system), and then use R1CS to generate QAP.

At present, circuit compilers are usually used to convert calculations into logic circuits, but circuit compilers generally correspond to a specific source code writing language. If you need to support other high-level languages, you can only redevelop a new compiler. In addition, current circuit compilers can only implement common grammars and lack operations such as error checking and compilation optimization. However, advanced cryptographic protocol algorithms are usually very complex, and grammatical restrictions, error checking, and lack of compilation and optimization will make the overall system's operating accuracy and efficiency not guaranteed. Therefore, the technical field urgently needs a simpler and more efficient method for processing cryptographic data.

Summary of the invention

The purpose of the embodiments of this specification is to provide a data processing method, device, and system, which can more simply and efficiently compile the source code data of a cryptographic algorithm into R1CS data.

This specification provides a data processing method, device and system which are implemented in the following ways:

A data processing method, including:

Compile the source code data of the cryptographic protocol algorithm to be processed based on the LLVM compiler to obtain the initial LLVM intermediate code data;

Performing static single assignment processing without jump on the initial LLVM intermediate code data to obtain processed intermediate code data;

Perform conversion processing on the processed intermediate code data to obtain R1CS data.

In another embodiment of the method provided in this specification, the performing static single assignment processing without jump to the initial LLVM intermediate code data includes:

Performing function inlining and static single assignment processing on the initial LLVM intermediate code data to obtain the first intermediate code data;

Performing elimination control flow processing on the first intermediate code data to obtain processed intermediate code data.

In another embodiment of the method provided in this specification, the performing control flow elimination processing on the first intermediate code data includes:

Converting the Phi instruction in the first intermediate code data into a selection instruction to obtain the second intermediate code data;

The jump sentence in the second intermediate code data is removed to obtain processed intermediate code data.

In another embodiment of the method provided in this specification, the performing function inlining and static single assignment processing on the initial LLVM intermediate code data includes:

Inlining the sub-functions of the initial LLVM intermediate code data into the main function, and putting global variables into the main function;

Performing loop expansion and constant folding elimination on the main function, and replacing and eliminating class and structure variables in the main function with scalar;

Convert the Switch jump statement in the main function into a jump statement, and merge multiple return statements into one return statement;

Converting multiple assignments of the same variable in the main function into single assignments of multiple variables.

In another embodiment of the method provided in this specification, the conversion processing on the processed intermediate code data includes:

Based on the constraint generation algorithm, the processed intermediate code data is converted to obtain R1CS data.

On the other hand, an embodiment of this specification also provides a data processing device, which includes:

The data compilation module is used to compile the source code data of the cryptographic protocol algorithm to be processed based on the LLVM compiler to obtain the initial LLVM intermediate code data;

The single assignment processing module is used to perform static single assignment processing without jumping on the initial LLVM intermediate code data to obtain processed intermediate code data;

The data conversion module is used to perform conversion processing on the processed intermediate code data to obtain R1CS data.

In another embodiment of the device provided in this specification, the single assignment processing module includes:

The single assignment processing unit is configured to perform function inlining and static single assignment processing on the initial LLVM intermediate code data to obtain the first intermediate code data;

The control flow elimination unit is configured to perform control flow elimination processing on the first intermediate code data to obtain processed intermediate code data.

In another embodiment of the device provided in this specification, the conversion module includes:

The conversion unit is used to convert the processed intermediate code data based on the constraint generation algorithm to obtain R1CS data.

On the other hand, the embodiments of the present specification also provide a data processing device, including a processor and a memory for storing executable instructions of the processor, the instructions being executed by the processor include the following steps:

On the other hand, the embodiments of this specification also provide a data processing system. The data compilation system includes at least one processor and a memory storing computer-executable instructions. When the processor executes the instructions, any one of the above embodiments is implemented. The steps of the method.

The data processing method, device and system provided by one or more embodiments of this specification can compile the source code data of the cryptographic protocol algorithm to be processed by using the LLVM compiler, and then further optimize the intermediate code data obtained by the compilation, and then The R1CS data is obtained based on the optimized intermediate code data. The LLVM compiler can support algorithm compilation in any language, and can implement error checking and code optimization, which can greatly improve the ease of writing algorithm source code data and the efficiency of compilation processing. At the same time, the embodiment of this specification further optimizes the intermediate code data compiled by the LLVM compiler, so that the optimized intermediate code data can adapt to the R1CS form required by the cryptographic algorithm, so as to implement complex complex data more simply and efficiently. Conversion of logic calculations to R1CS.

Description of the drawings

In order to more clearly explain the technical solutions in the embodiments of this specification or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only These are some embodiments described in this specification. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative labor. In the attached picture:

FIG. 1 is a schematic flowchart of an embodiment of a data processing method provided in this specification;

2 is a schematic diagram of the control flow of LLVM intermediate code data in an embodiment provided in this specification;

3 is a schematic diagram of a data processing flow in another embodiment provided in this specification;

4 is a schematic diagram of the module structure of an embodiment of a data processing device provided in this specification;

Fig. 5 is a schematic structural diagram of a server according to an exemplary embodiment of the present specification.

Detailed ways

In order to enable those skilled in the art to better understand the technical solutions in this specification, the following will make clear and complete the technical solutions in one or more embodiments of this specification in conjunction with the drawings in one or more embodiments of this specification. It is obvious that the described embodiments are only a part of the embodiments in the specification, rather than all the embodiments. Based on one or more embodiments of the specification, all other embodiments obtained by a person of ordinary skill in the art without creative work shall fall within the protection scope of the embodiment scheme of this specification.

With the development of blockchain technology in recent years, zero-knowledge proofs and verifiable calculations have received widespread attention and use. The current mainstream zero-knowledge algorithms are usually not directly used to solve computational problems. The computational problems must be converted into the correct "form" for processing. This form is called QAP (quadratic arithmetic problem). In specific implementation, it is generally necessary to convert the calculation into a logic circuit first, and then into an R1CS (rank-1 constraint system, first-order constraint system), and further use R1CS to generate QAP. R1CS is a sequence composed of three vector groups (a, b, c), R1CS has a solution vector s, s must satisfy s·a*s·bs·c=0, and the symbol "·" represents the inner product operation of the vector .

Currently, a circuit compiler is usually used to convert calculations into logic circuits. However, the algorithm source code writing language corresponding to the circuit compiler is relatively simple, the supported language syntax is limited, it cannot meet the complex logic calculation, and the conversion efficiency is low.

Correspondingly, the embodiment of this specification provides a data processing method, which can compile the source code data of the cryptographic protocol algorithm to be processed by using the LLVM compiler, and then further optimize the intermediate code data obtained by the compilation, and then optimize the processing based on The following intermediate code data obtains R1CS data. The LLVM compiler can support algorithm compilation in any language, and can implement error checking and code optimization, which can greatly improve the ease of writing algorithm source code data and the efficiency of compilation processing. At the same time, the embodiment of this specification further optimizes the intermediate code data compiled by the LLVM compiler, so that the optimized intermediate code data can adapt to the logic circuit or R1CS form required by the cryptographic algorithm, so as to achieve simple and efficient implementation Conversion of complex logic calculations to logic circuits or R1CS.

Fig. 1 is a schematic flowchart of an embodiment of the data processing method provided in this specification. Although this specification provides method operation steps or device structures as shown in the following embodiments or drawings, the method or device may include more or fewer operation steps after partial combination based on conventional or no creative labor. Or modular unit. In steps or structures where there is no necessary causal relationship logically, the execution order of these steps or the module structure of the device is not limited to the execution order or module structure shown in the embodiments of this specification or the drawings. When the described method or module structure is applied to an actual device, server or terminal product, it can be executed sequentially or in parallel according to the method or module structure shown in the embodiments or drawings (for example, parallel processor or multi-threaded processing). Environment, even including distributed processing, server cluster implementation environment).

A specific embodiment is shown in Fig. 1. In an embodiment of the data processing method provided in this specification, the method may include:

S202: Compile the algorithm source code data to be processed based on the LLVM compiler to obtain LLVM intermediate code data.

The source code data of the cryptographic protocol algorithm to be processed can be obtained. The cryptographic protocol algorithm source code data may include cryptographic algorithm source code data in any form, such as corresponding algorithm source code data based on zero-knowledge proof, verifiable calculation, and the like. Figure 2 shows a schematic diagram of the process of conversion from calculation to final zero-knowledge proof in zk-SNARK. Computation in Figure 2 means calculation, Algebraic Circuit means logic circuit, R1CS means first-order constraint system, and QAP means secondary algorithm problem.

The generation language of the source code data of the cryptographic protocol algorithm in the embodiment of this specification is not limited, and the language type of the source code can be selected according to actual needs. For example, a variety of mainstream high-level languages C, C++, Java, etc. can be used.

Then, the algorithm source code data can be compiled based on the LLVM (Low Level Virtual Machine) compiler. The LLVM compiler can perform operations such as lexical analysis, syntax analysis, semantic analysis, and optimization of the algorithm source code data to generate initial LLVM intermediate code (LLVM IR) data.

S204: Perform static single assignment processing without jump on the initial LLVM intermediate code data to obtain processed intermediate code data.

The initial LLVM intermediate code data can be further subjected to static single assignment processing without jump, so that the processed intermediate code data format meets the requirements of the cryptographic form. The static single assignment processing without jump may include eliminating multiple assignments, function calls, statement jumps and other operations in the initial LLVM intermediate code data to obtain intermediate code data in the form of static single assignment without jump.

Although part of the algorithm source code data can be converted into static single assignment form during LLVM compilation, it only converts the static single assignment form of some simple algorithm source code data. The converted intermediate code data still contains multiple assignments and function calls for the same variable. , Sentence jump and other operations, and these operations are difficult to convert to the circuit or R1CS form required by cryptographic algorithms. In the embodiment of this specification, by further eliminating multiple assignments, function calls, statement jumps and other operations of the same variable in the initial LLVM intermediate code data, the processed intermediate code data format can be made more consistent with the requirements of cryptographic forms, and The efficiency of subsequent processing.

In an embodiment of this specification, the initial LLVM intermediate code data may be subjected to function inlining and static single assignment processing to obtain the first intermediate code data; the first intermediate code data may be eliminated control flow processing to obtain processing After the intermediate code data.

You can inline the initial LLVM intermediate code data first, and inline all the sub-functions into the main function to eliminate function calls. Then, static single assignment processing can be performed on the intermediate code data after the function inline processing, and multiple assignments of the same variable can be converted into a single assignment to obtain the first intermediate code data.

By first inlining all the sub-functions into the main function, the intermediate code data containing only the main function is obtained, and then, on this basis, multiple assignments of the same variable in the main function are converted into a single assignment, which can be more efficient Accurately eliminate all multiple assignments in the intermediate code data.

In one or more embodiments of this specification, the performing function inlining and static single assignment processing on the initial LLVM intermediate code data may include:

The sub-functions of the initial LLVM intermediate code data can be inlined into the main function first to eliminate function calls in the intermediate code data. Then, you can further put all global variables into the main function, and convert multiple assignments of global variables into single assignments of multiple variables.

Further, the loop can be expanded, and constant folding can be eliminated, and jumps can be eliminated initially. The constant folding elimination is to evaluate the constant calculation, replace the expression with the value, and put it into the constant table. You can use scalar substitution to eliminate class and structure variables. The switch statement can be further converted into a jump statement (Br statement), and multiple return statements (Return statements) can be combined into one Return statement. After that, you can further convert the memory read and write instructions into a static single assignment form.

Through the above processing, the static single assignment processing of the intermediate code data can be realized more accurately and completely. At the same time, jump processing can be eliminated initially. Further, by preliminarily converting the switch statement that controls the flow of the node into the Br jump statement, the subsequent jump elimination processing can be further facilitated.

After completing the above processing, the intermediate code data can be converted into the following form: there is only one main function, and there are multiple basic blocks in the main function. Correspondingly, the final instruction of the last basic block is a Return statement, and the final instruction of other basic blocks is a Br jump instruction. Correspondingly, the Br jump instruction can be a conditional jump instruction or an unconditional jump instruction. The other instructions in the basic block are only arithmetic operations, bitwise operations, comparison operations, select instructions (Select instructions) and Phi instructions.

The Br instruction may include a conditional jump instruction or an unconditional jump instruction. The conditional jump instruction may refer to an instruction to jump from a current node to a preset node under certain preset conditions. The transfer instruction refers to an instruction to jump from the current node to the preset node without any conditions.

The Phi instruction is an instruction used to determine the node executed before the current node in the data for the static single assignment form, so as to use the value of the previously executed node to process the current node. After multiple assignments of the same variable are converted into a single assignment form of multiple variables, a node may correspond to multiple nodes before. The Phi instruction can be used to determine the previous node corresponding to the current node in the control flow to use this The value of the previous node is processed by the current node.

Then, the first intermediate code data can be further processed to eliminate control flow, eliminate Phi statements and jump statements in the first intermediate code data, and convert to a static single assignment form without jumps, so that the processed intermediate code The data can be directly used in the circuit or R1CS format required by the cryptographic protocol.

In an embodiment of this specification, the Phi instruction in the first intermediate code data may be further converted into a selection instruction to obtain the second intermediate code data;

For any Phi instruction in the first intermediate code data, it can be converted into several Select instructions to eliminate the Phi instruction. After the Phi instruction is eliminated, the execution order and mode between the nodes can be directly connected through the Select instruction. Correspondingly, during the entire intermediate code data execution process, it is no longer necessary to determine the execution sequence and method through jump instructions, and just remove the jump instructions between nodes. Therefore, by using the solution of the foregoing embodiment, the elimination processing of the jump instruction in the intermediate code data is simply and efficiently realized, and the intermediate code data in the form of static single assignment without jump is obtained.

This manual provides an example of an application scenario. The initial LLVM intermediate code data can be processed through the following steps to obtain intermediate code data in the form of static single assignment without jump:

1) Function call: inline all functions into the main function;

2) Global variables: After all functions are inlined, put all global variables into the main function;

3) Loop: use loop expansion and constant folding to eliminate;

4) Class and structure variables: use scalar replacement to eliminate;

5) Switch jump statement: degraded into Br jump statement;

6) Multiple Return statements: merge into one Return statement;

7) Memory read and write: converted to SSA format;

8) Control flow: Combine all basic blocks into one basic block.

Steps 1)-7) can be implemented with reference to the above-mentioned scheme, which will not be repeated here. Fig. 2 shows a schematic diagram of the control flow corresponding to the intermediate code data processed through the above steps 1)-7). With reference to Fig. 2, the control flow elimination processing is further explained. Suppose that the first intermediate code data obtained through steps 1)-7) is:

It can be seen from Figure 2 that taking the basic block bb4 as an example, the basic blocks before bb4 can have bb2 and bb3. Correspondingly, the control flow data corresponding to bb4 contains the Phi instruction: %r4=phi i32[42,%bb2] ,[43,%bb3]. If the control flow jumps from the basic block bb2 to bb4, %r4 is assigned the value 42, and if the control flow jumps from bb3 to bb4, the %r4 is assigned bit 43. Therefore, the value of bb4 to be executed can be determined through the Phi instruction. If the value of %r4 is 42, then bb4 performs subsequent processing based on the data of the basic block bb2, and if the value of %r4 is 43, then bb4 is performed based on the data of the basic block bb3 Follow-up processing.

Similarly, the basic block before the basic block bb6 also contains multiple basic blocks, which also correspond to the Phi instruction. The %r6 in the Phi instruction can be assigned a value of 1, 2, %r4, or 5 according to the previous basic block.

For the above control flow, the Br instruction and Phi instruction can be eliminated in the following ways:

Step 1: Convert each Phi instruction into several Select instructions.

Take the basic block bb4 containing the Phi instruction as an example:

First, find the basic block bb4 containing the Phi instruction, and find the control node of bb4 (the node must be passed before) bb0, and traverse backward from bb4 to find all the basic blocks bb0, bb1, bb2, and bb3 that can reach bb4.

Perform the following operations to convert the Phi instruction corresponding to bb4 into a Select instruction:

During the above operation:

InsertSelect(bb3,phi) returns the corresponding value 43 of bb3 in the phi statement,

InsertSelect(bb2,phi) returns 42,

InsertSelect(bb1,phi) calls InsertSelect(bb2,phi), returns 42,

InsertSelect(bb0,phi) calls InsertSelect(bb1,phi) to get 42, call InsertSelect(bb3,phi) to get 43, create Select statement Select(%cond0,42,43), and replace phi statement.

After the processing is completed, the phi sentence "%r4=phi i32[42,%bb2],[43,%bb3]" corresponding to bb4 is replaced with the Select sentence "%r4.bb0=select i1%cond0,i32 42,i32 43 ".

The basic block bb6 is also processed in the above manner. After the execution is completed, the corresponding intermediate code data is:

Finally, remove all Br statements and move other statements to a basic block to complete the control flow elimination process. Correspondingly, the intermediate code data after completing the control flow elimination processing becomes the following form:

In the above-mentioned embodiments of this specification, by further optimizing the LLVM intermediate code data, the finally obtained intermediate code data can be more adapted to the needs of cryptographic protocol data processing. At the same time, through the above optimization processing, the subsequent processing can be further improved. The simplicity and efficiency.

S206: Perform conversion processing on the processed intermediate code data to obtain R1CS data.

The logic circuit data or data in the form of R1CS can be further obtained based on the above-mentioned processed intermediate code data conversion. In some embodiments, the processed intermediate code data may be converted into logic circuit data first, and then further converted into data in the form of R1CS.

FIG. 3 shows a flowchart of the conversion of cryptographic calculation algorithm source code data into R1CS data based on the LLVM compiler in the solutions provided by the foregoing embodiments. As shown in FIG. 3, preferably, in an embodiment of this specification, the processed intermediate code data may be converted based on a constraint generation algorithm to obtain R1CS data.

The conversion processing of the processed intermediate code data based on the constraint generation algorithm may include: processing each arithmetic instruction in the intermediate code data by adding constraints, so as to be configured to be represented by only addition and multiplication form. By directly constructing the instructions in the intermediate code data into a form that only uses addition and multiplication to obtain R1CS data, the cumbersome steps of obtaining R1CS data using logic circuit data can be avoided, and the efficiency and simplicity of data processing can be improved.

The following takes some basic LLVM instructions as examples to illustrate how to convert LLVM IR to R1CS that only uses addition and multiplication:

1. Packing constraints

In order to deal with bitwise operations, you need to expand a multi-bit variable into multiple one-bit variables, or combine multiple one-bit variables into a multi-bit variable. Using Packing constraints can ensure that multiple variables are a variable Bit expansion, namely:

2 ⁱ can be expressed by multiplication or directly by addition. In addition, by restricting each c _{i to} be 1 or 0, the relationship between c and each c _i can be guaranteed.

Wherein, the packing constraint is a constraint processing method of splitting an n-digit number into n 1-digit numbers, or combining n 1-digit arrays into an n-digit number.

2. Greater than comparison

％C=icmp sgt i32％a,％b

Calculate b-a and use Packing to get the sign bit (the highest bit) of the difference;

When a is greater than b, the sign bit is equal to 1;

When a is not greater than b, the sign bit is equal to 0.

3. Greater than or equal to comparison

％C=icmp sge i32%a,%b

Use greater than comparison and store the result in gt;

Use equal comparison and store the result in eq;

Plus constraints.

4.Add instruction

％C=add i32％a,i32％b

It can be expressed as the following constraints:

c=(a+b)×1.

5.Mul instruction

％C=mul i32％a,i32％b

It can be expressed as the following constraints:

c=a×b.

6.Sub instruction

％C=sub i32％a,i32％b

It can be expressed as the following constraints:

c=(a-b)×1.

7.Div instruction

％C=div i32％a,i32％b

It can be expressed as the following constraints:

Among them, d is the remainder, c is the quotient, and the greater than and greater than or equal constraints refer to the subsequent content.

8.Rem instruction

％D=rem i32％a,i32％b

It can be expressed as the following constraints:

9. Equal comparison

％C=icmp eq i32％a,％b

It can be expressed as the following constraints:

When a=b, according to the first constraint, c can be any number, so the second constraint is needed, aux is set to any value, and c must be 1;

When a≠b, according to the first constraint, c must be equal to 0, and aux is set to the multiplicative inverse of a-b, so that the second constraint also holds.

10. Not equal to comparison

％C=icmp ne i32%a,%b

Add constraints:

When a=b, according to the first constraint, c can be any number, according to the second constraint, aux can be set to any value, and c must be 0;

When a≠b, according to the first constraint, c must be equal to 1, and aux is set to the multiplicative inverse of a-b, so that the second constraint is also valid.

11.Select instruction

％C=select i1％cond,i32％a,i32％b

Among them, %cond has only 1 digit, and only has two values of 0 or 1;

The Select command can be converted into the following constraint form:

c=cond×a+(1+(-1×cond))×b.

12.And instruction

％C=and i32％a,％b

and a bitwise AND, needed to Packing 32 bits a and b are split into 32 variables for each of the operational variables, constraints and a _{_{_i,}} b _i, c _i, and then the 32 Packing _Ci merge into c variable;

The constraints of each variable are:

c _i =a _i +b _i .

13.Or instruction

％C＝or i32％a,％b

or is the bitwise OR operation, need to 32 Packing of a and b are split into 32 variables for each of the operational variables, constraints and a _{_{_i,}} b _i, c _i, and then the 32 Packing _Ci merge into c variable;

The constraints of each variable are:

a _i ×b _i =a _i +b _i -c _i .

14.xor instruction

％C=xor i32％a,％b

xor is a bitwise exclusive OR operation. Packing is used to separate the 32-bit a and b into 32 variables, and each pair of variables is ANDed, and the relationship between a _i , b _i and c _i is restricted, and then Packing is used to 32 c _{i are} merged into c variable;

The constraints of each variable are implemented using unequal constraints.

In each of the above-mentioned embodiments of this specification, by compiling the source code of cryptographic calculation algorithms based on the LLVM compiler, the language type when writing the algorithm source code is no longer limited, and developers can choose a variety of mainstream development languages according to their own needs. The writing of algorithms improves the simplicity of algorithm writing.

At the same time, due to the complexity of the cryptographic algorithm, the intermediate code data directly compiled by the LLVM compiler may not be directly converted into a logic circuit or R1CS data. In the embodiment of this specification, the intermediate code data is further optimized. . Therefore, by using the solutions provided by the various embodiments of this specification, the compilation processing of the source code data of the cryptographic algorithm into the R1CS data can be realized simply and efficiently.

The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. For details, reference may be made to the description of the foregoing related processing related embodiments, which will not be repeated here.

The foregoing describes specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims may be performed in a different order than in the embodiments and still achieve desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or sequential order shown to achieve the desired result. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

The data processing method provided by one or more embodiments of this specification can compile the source code data of the cryptographic protocol algorithm to be processed by using the LLVM compiler, and then further optimize the intermediate code data obtained by the compilation, and then based on the optimized processing R1CS data is obtained from the intermediate code data. The LLVM compiler can support algorithm compilation in any language, and can implement error checking and code optimization, which can greatly improve the ease of writing algorithm source code data and the efficiency of compilation processing. At the same time, the embodiment of this specification further further optimizes the intermediate code data obtained by the LLVM compiler, so that the optimized intermediate code data can adapt to the R1CS form required by the cryptographic algorithm, so as to implement complex logic simply and efficiently. Calculate the conversion process to R1CS.

Based on the data processing method described above, one or more embodiments of this specification also provide a data processing device. The described devices may include systems, software (applications), modules, components, servers, etc. that use the methods described in the embodiments of this specification, combined with necessary implementation hardware devices. Based on the same innovative concept, the devices in one or more embodiments provided in the embodiments of this specification are as described in the following embodiments. Since the implementation scheme of the device to solve the problem is similar to the method, the implementation of the specific device in the embodiment of this specification can refer to the implementation of the foregoing method, and the repetition will not be repeated. As used below, the term "unit" or "module" can be a combination of software and/or hardware that implements predetermined functions. Although the devices described in the following embodiments are preferably implemented by software, hardware or a combination of software and hardware is also possible and conceived. Specifically, FIG. 4 shows a schematic diagram of the module structure of an embodiment of a data processing device provided in the specification. As shown in FIG. 4, the device may include:

The data compiling module 102 can be used to compile the cryptographic protocol algorithm source code data to be processed based on the LLVM compiler to obtain initial LLVM intermediate code data;

The single assignment processing module 104 may be used to perform static single assignment processing without jumps on the initial LLVM intermediate code data to obtain processed intermediate code data;

The data conversion module 106 may be used to perform conversion processing on the processed intermediate code data to obtain R1CS data.

In an embodiment of this specification, the single assignment processing module 104 may include:

The single assignment processing unit may be used to perform function inlining and static single assignment processing on the initial LLVM intermediate code data to obtain the first intermediate code data;

The control flow elimination unit may be used to perform control flow elimination processing on the first intermediate code data to obtain processed intermediate code data.

In an embodiment of this specification, the control flow elimination unit may include:

The instruction conversion subunit can be used to convert the Phi instruction in the first intermediate code data into a selection instruction to obtain the second intermediate code data;

The sentence merging subunit can be used to remove the jump sentence in the second intermediate code data to obtain processed intermediate code data.

In an embodiment of this specification, the conversion module 106 may include:

The conversion unit may be used to perform conversion processing on the processed intermediate code data based on the constraint generation algorithm to obtain R1CS data.

It should be noted that the above-mentioned device may also include other implementation manners according to the description of the method embodiment. For specific implementation manners, reference may be made to the description of the related method embodiments, which will not be repeated here.

The data processing device provided by one or more embodiments of this specification can compile the source code data of the cryptographic protocol algorithm to be processed by using the LLVM compiler, and then further optimize the intermediate code data obtained by the compilation, and then based on the optimized processing R1CS data is obtained from the intermediate code data. The LLVM compiler can support algorithm compilation in any language, and can implement error checking and code optimization, which can greatly improve the ease of writing algorithm source code data and the efficiency of compilation processing. At the same time, the embodiment of this specification further further optimizes the intermediate code data obtained by the LLVM compiler, so that the optimized intermediate code data can adapt to the R1CS form required by the cryptographic algorithm, so as to implement complex logic simply and efficiently. Calculate the conversion to R1CS.

The method or device described in the foregoing embodiment provided in this specification can implement business logic through a computer program and record it on a storage medium, and the storage medium can be read and executed by a computer to achieve the effects of the solution described in the embodiment of this specification. Therefore, this specification also provides a data processing device including a processor and a memory storing executable instructions of the processor. When the instructions are executed by the processor, the implementation includes the following steps:

The storage medium may include a physical device for storing information, and the information is usually digitized and then stored in an electric, magnetic, or optical medium. The storage medium may include: devices that use electrical energy to store information, such as various types of memory, such as RAM, ROM, etc.; devices that use magnetic energy to store information, such as hard disks, floppy disks, magnetic tapes, magnetic core memory, bubble memory, U disk; a device that uses optical means to store information, such as CD or DVD. Of course, there are other ways of readable storage media, such as quantum memory, graphene memory, and so on.

The method embodiments provided in the embodiments of this specification can be executed in a mobile terminal, a computer terminal, a server or a similar computing device. Taking running on a server as an example, FIG. 5 is a hardware structure block diagram of a data processing server to which the embodiment of this specification is applied. As shown in FIG. 5, the server 10 may include one or more (only one is shown in the figure) processor 20 (the processor 20 may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA), The memory 30 for storing data, and the transmission module 40 for communication functions. Those of ordinary skill in the neighborhood can understand that the structure shown in FIG. 5 is only for illustration, and does not limit the structure of the above electronic device. For example, the server 10 may also include more or fewer components than shown in FIG. 5, for example, may also include other processing hardware, such as a database or multi-level cache, GPU, or have a configuration different from that shown in FIG.

The memory 30 may be used to store software programs and modules of application software, such as program instructions/modules corresponding to the search method in the embodiment of the present invention. The processor 20 executes various functions by running the software programs and modules stored in the memory 30 Application and data processing. The memory 30 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 30 may further include a memory remotely provided with respect to the processor 20, and these remote memories may be connected to the computer terminal through a network. Examples of the aforementioned networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

The transmission module 40 is used to receive or send data via a network. The above-mentioned specific examples of the network may include a wireless network provided by a communication provider of a computer terminal. In an example, the transmission module 40 includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices through a base station to communicate with the Internet. In an example, the transmission module 40 may be a radio frequency (RF) module, which is used to communicate with the Internet in a wireless manner.

The data processing device described in the above embodiment can compile the source code data of the cryptographic protocol algorithm to be processed by using the LLVM compiler, and then further optimize the intermediate code data obtained by the compilation, and then based on the optimized intermediate code data Obtain R1CS data. The LLVM compiler can support algorithm compilation in any language, and can implement error checking and code optimization, which can greatly improve the ease of writing algorithm source code data and the efficiency of compilation processing. At the same time, the embodiment of this specification further further optimizes the intermediate code data obtained by the LLVM compiler, so that the optimized intermediate code data can adapt to the R1CS form required by the cryptographic algorithm, so as to implement complex logic simply and efficiently. Calculate the conversion process to R1CS.

This specification also provides a data processing system, which can be a separate data processing system or can be applied to multiple computer data processing systems. The system can be a single server, or it can include server clusters, systems (including distributed systems), software (applications), and one or more of the methods described in this specification or one or more embodiments of the device. The actual operation device, logic gate circuit device, quantum computer, etc., combined with the terminal device necessary to implement the hardware. The data processing system may include at least one processor and a memory storing computer-executable instructions. The processor implements the steps of the method in any one or more of the foregoing embodiments when the processor executes the instructions.

It should be noted that the above-mentioned system may also include other implementation manners based on the description of the method or device embodiment. For the specific implementation manner, reference may be made to the description of the relevant method embodiment, which will not be repeated here.

The data processing system described in the above embodiment can compile the source code data of the cryptographic protocol algorithm to be processed by using the LLVM compiler, and then further optimize the intermediate code data obtained by the compilation, and then based on the optimized intermediate code data Obtain R1CS data. The LLVM compiler can support algorithm compilation in any language, and can implement error checking and code optimization, which can greatly improve the ease of writing algorithm source code data and the efficiency of compilation processing. At the same time, the embodiment of this specification further further optimizes the intermediate code data obtained by the LLVM compiler, so that the optimized intermediate code data can adapt to the R1CS form required by the cryptographic algorithm, so as to implement complex logic simply and efficiently. Calculate the conversion process to R1CS.

It should be noted that the device or system described above in this specification may also include other implementation manners based on the description of the related method embodiments. For specific implementation manners, refer to the description of the method embodiments, which will not be repeated here. The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, as for the hardware+program and storage medium+program embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and for related parts, please refer to the part of the description of the method embodiments.

Although the acquisition, definition, interaction, calculation, judgment and other operations and data descriptions mentioned in the content of the embodiment of this specification, such as loop expansion and constant folding elimination, etc., the embodiment of this specification is not limited to the standard data model/template. Or the situation described in the embodiment of this specification. Certain industry standards or implementations described in custom methods or examples with slight modifications can also achieve the same, equivalent or similar implementation effects of the foregoing examples, or predictable implementation effects after modification. The examples obtained by applying these modified or deformed data acquisition, storage, judgment, processing methods, etc., may still fall within the scope of the optional implementation solutions of this specification.

The systems, devices, modules, or units illustrated in the above embodiments may be specifically implemented by computer chips or entities, or implemented by products with certain functions. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a vehicle-mounted human-computer interaction device, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, and a tablet. Computers, wearable devices, or any combination of these devices.

For the convenience of description, when describing the above device, the functions are divided into various modules and described separately. Of course, when implementing one or more of this specification, the function of each module can be realized in the same one or more software and/or hardware, or the module that realizes the same function can be realized by a combination of multiple sub-modules or sub-units, etc. . The device embodiments described above are merely illustrative, for example, the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or integrated To another system, or some features can be ignored, or not implemented. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.

Those skilled in the art also know that in addition to implementing the controller in a purely computer-readable program code manner, it is entirely possible to program the method steps to make the controller use logic gates, switches, application specific integrated circuits, programmable logic controllers and embedded The same function can be realized in the form of a microcontroller, etc. Therefore, such a controller can be regarded as a hardware component, and the devices included in the controller for realizing various functions can also be regarded as a structure within the hardware component. Or even, the device for realizing various functions can be regarded as both a software module for realizing the method and a structure within a hardware component.

The present invention is described with reference to flowcharts and/or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and/or block in the flowchart and/or block diagram, and the combination of processes and/or blocks in the flowchart and/or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing equipment to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing equipment are generated It is a device that realizes the functions specified in one process or multiple processes in the flowchart and/or one block or multiple blocks in the block diagram.

These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing equipment to work in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including the instruction device. The device implements the functions specified in one process or multiple processes in the flowchart and/or one block or multiple blocks in the block diagram.

These computer program instructions can also be loaded on a computer or other programmable data processing equipment, so that a series of operation steps are executed on the computer or other programmable equipment to produce computer-implemented processing, so as to execute on the computer or other programmable equipment. The instructions provide steps for implementing functions specified in a flow or multiple flows in the flowchart and/or a block or multiple blocks in the block diagram.

In a typical configuration, the computing device includes one or more processors (CPU), input/output interfaces, network interfaces, and memory.

It should also be noted that the terms "include", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, product or equipment including a series of elements not only includes those elements, but also includes Other elements that are not explicitly listed, or include elements inherent to this process, method, commodity, or equipment. If there are no more restrictions, the element defined by the sentence "including a..." does not exclude the existence of other same elements in the process, method, or device that includes the element.

Those skilled in the art should understand that one or more embodiments of this specification can be provided as a method, a system, or a computer program product. Therefore, one or more embodiments of this specification may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, one or more embodiments of this specification may adopt a computer program implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes. The form of the product.

One or more embodiments of this specification may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. One or more embodiments of this specification can also be practiced in distributed computing environments. In these distributed computing environments, tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules can be located in local and remote computer storage media including storage devices.

The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, as for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for related parts, please refer to the part of the description of the method embodiment. In the description of this specification, descriptions with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" etc. mean specific features described in conjunction with the embodiment or example , Structure, materials or features are included in at least one embodiment or example in this specification. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the described specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples and the characteristics of the different embodiments or examples described in this specification without contradicting each other.

The above descriptions are only examples of this specification and are not intended to limit this specification. For those skilled in the art, this specification can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this specification shall be included in the scope of the claims of this specification.

Claims

A data processing method, characterized by comprising:

Compile the source code data of the cryptographic protocol algorithm to be processed based on the LLVM compiler to obtain the initial LLVM intermediate code data;

Performing static single assignment processing without jump on the initial LLVM intermediate code data to obtain processed intermediate code data;

Perform conversion processing on the processed intermediate code data to obtain R1CS data.
The method according to claim 1, wherein the performing static single assignment processing without jump to the initial LLVM intermediate code data comprises:

Performing function inlining and static single assignment processing on the initial LLVM intermediate code data to obtain the first intermediate code data;

Performing elimination control flow processing on the first intermediate code data to obtain processed intermediate code data.
The method according to claim 2, wherein the performing control flow elimination processing on the first intermediate code data comprises:

Converting the Phi instruction in the first intermediate code data into a selection instruction to obtain the second intermediate code data;

The jump sentence in the second intermediate code data is removed to obtain processed intermediate code data.
The method according to claim 2, wherein the performing function inlining and static single assignment processing on the initial LLVM intermediate code data comprises:

Inlining the sub-functions of the initial LLVM intermediate code data into the main function, and putting global variables into the main function;

Performing loop expansion and constant folding elimination on the main function, and replacing and eliminating class and structure variables in the main function with scalar;

Convert the Switch jump statement in the main function into a jump statement, and merge multiple return statements into one return statement;

Converting multiple assignments of the same variable in the main function into single assignments of multiple variables.
The method according to any one of claims 1 to 4, wherein the conversion processing on the processed intermediate code data comprises:

Based on the constraint generation algorithm, the processed intermediate code data is converted to obtain R1CS data.
A data processing device, characterized in that the device includes:

The data compilation module is used to compile the source code data of the cryptographic protocol algorithm to be processed based on the LLVM compiler to obtain the initial LLVM intermediate code data;

The single assignment processing module is used to perform static single assignment processing without jumping on the initial LLVM intermediate code data to obtain processed intermediate code data;

The data conversion module is used to perform conversion processing on the processed intermediate code data to obtain R1CS data.
The device according to claim 6, wherein the single assignment processing module comprises:

The single assignment processing unit is configured to perform function inlining and static single assignment processing on the initial LLVM intermediate code data to obtain the first intermediate code data;

The control flow elimination unit is configured to perform control flow elimination processing on the first intermediate code data to obtain processed intermediate code data.
The device according to claim 6, wherein the conversion module comprises:

The conversion unit is used to convert the processed intermediate code data based on the constraint generation algorithm to obtain R1CS data.
A data processing device is characterized in that it comprises a processor and a memory for storing executable instructions of the processor, and the implementation of the instructions when executed by the processor includes the following steps:

Compile the source code data of the cryptographic protocol algorithm to be processed based on the LLVM compiler to obtain the initial LLVM intermediate code data;

Performing static single assignment processing without jump on the initial LLVM intermediate code data to obtain processed intermediate code data;

Perform conversion processing on the processed intermediate code data to obtain R1CS data.
A data processing system, characterized in that the data compilation system includes at least one processor and a memory storing computer executable instructions, and when the processor executes the instructions, the instructions described in any of claims 1-5 The steps of the method.