WO2020224425A1 - 一种确定预测窗口期的方法及装置 - Google Patents

一种确定预测窗口期的方法及装置 Download PDF

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WO2020224425A1
WO2020224425A1 PCT/CN2020/085789 CN2020085789W WO2020224425A1 WO 2020224425 A1 WO2020224425 A1 WO 2020224425A1 CN 2020085789 W CN2020085789 W CN 2020085789W WO 2020224425 A1 WO2020224425 A1 WO 2020224425A1
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period
prediction window
window period
cycle
processor
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PCT/CN2020/085789
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English (en)
French (fr)
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李卫军
王岩
李文江
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深圳大普微电子科技有限公司
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Publication of WO2020224425A1 publication Critical patent/WO2020224425A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/22—Employing cache memory using specific memory technology
    • G06F2212/222—Non-volatile memory

Definitions

  • This application relates to the technical field of solid state hard disk data processing, and in particular to a method and device for determining a prediction window period.
  • Flash Translation Layer is the core of SSD software, and its importance lies in determining the service life, performance and reliability of an SSD.
  • FTL Flash Translation Layer
  • the I/O information in the SSD disk in the first time period in the future can be predicted, then there can be more active mechanisms, such as active buffer scheduling or active GC, and perform the first time period in the future
  • active buffer scheduling or active GC active buffer scheduling
  • how to choose the forecast window period will greatly affect the accuracy of the forecast. If the forecast window period is too short, it does not make much sense for FTL; on the contrary, if it is too long, even if the computing power can be achieved, the result will not be too accurate.
  • the embodiments of the present application provide a method and device for determining a prediction window period, which are used to determine the prediction window period in a solid state hard disk, so as to improve the accuracy of prediction.
  • the first aspect of the embodiments of the present application provides a method for determining a prediction window period, including:
  • the prediction window period is determined according to the first cycle and the I/O throughput.
  • the determining the prediction window period according to the first period and the I/O throughput includes:
  • the first data amount is greater than the buffer capacity, it is determined that the first period is the prediction window period.
  • the method further includes:
  • the first data amount is not greater than the cache capacity, calculating a second cycle for completing a full-speed read and write to the cache capacity according to the I/O throughput and the cache capacity;
  • the second period is the prediction window period.
  • the method further includes:
  • the determining the number of sliding steps in the prediction window period according to the third period and the prediction window period includes:
  • prediction window period is the first period, determine the number of sliding steps in the prediction window period according to the third period and the first period;
  • the number of sliding steps of the prediction window period is determined according to the third period and the second period.
  • the method further includes:
  • the solid-state hard disk processor is made to predict the I/O information of the first time period in the future.
  • a second aspect of the embodiments of the present application provides an apparatus for determining a prediction window period, including:
  • the first obtaining unit is used to obtain the read and write bandwidth and cache capacity of the solid state drive
  • a calculation unit configured to calculate the first cycle for completing a full-speed read and write to the cache capacity according to the read and write bandwidth and the cache capacity;
  • the second obtaining unit is used to obtain the I/O throughput of the solid-state hard disk processor
  • the determining unit is configured to determine the prediction window period according to the first cycle and the I/O throughput.
  • the determining unit is configured to:
  • the first data amount is greater than the buffer capacity, it is determined that the first period is the prediction window period.
  • the determining unit is further used for:
  • the first data amount is not greater than the cache capacity, calculating a second cycle for completing a full-speed read and write to the cache capacity according to the I/O throughput and the cache capacity;
  • the second period is the prediction window period.
  • the first obtaining unit is further configured to:
  • the first obtaining unit is further configured to:
  • prediction window period is the first period, determine the number of sliding steps in the prediction window period according to the third period and the first period;
  • the number of sliding steps of the prediction window period is determined according to the third period and the second period.
  • the device further includes:
  • the prediction unit is configured to make the solid-state hard disk processor predict the I/O information of the first time period in the future according to the prediction window period and the number of sliding steps.
  • the third aspect of the embodiments of the present application provides a solid state drive, which includes the device for determining the prediction window period provided in the second aspect of the embodiments of the present application, or calls the device for determining the prediction window period provided by the second aspect of the embodiments of the present application to Realize the prediction of I/O information for the first time period in the future.
  • An embodiment of the present application also provides a computer device, including a processor, which is used to implement the method for determining a prediction window provided in the first aspect of the application embodiment when the processor executes a computer program stored on the memory.
  • This embodiment of the application also provides a computer-readable storage medium on which a computer program is stored.
  • the computer program When the computer program is executed by a processor, it is used to implement the method for determining the prediction window provided in the first aspect of the embodiment of the application.
  • the read and write bandwidth and cache capacity of the solid state drive are obtained, and the first cycle of completing a full-speed read and write to the cache capacity is calculated according to the read and write bandwidth and the cache capacity, and the solid state drive processor is obtained
  • the prediction window period is determined according to the first cycle and the I/O throughput.
  • the prediction window is determined according to the capacity of the cache and the I/O throughput of the SSD The period is determined so that the prediction window period not only meets the cycle of completing a full-speed read and write to the cache, but also meets the load capacity of the solid-state hard disk processor, thereby improving the accuracy of the prediction.
  • FIG. 1 is a schematic diagram of an embodiment of a method for determining a prediction window period in an embodiment of the application
  • FIG. 2 is a detailed step of step 104 in the embodiment of FIG. 1 in the embodiment of this application;
  • FIG. 3 is a schematic diagram of another embodiment of a method for determining a prediction window period in an embodiment of the application
  • FIG. 4 is a schematic diagram of an embodiment of an apparatus for determining a prediction window period in an embodiment of the application.
  • the embodiments of the present application provide a method and device for determining a prediction window period, which are used to determine the prediction window period in a solid state hard disk, so as to improve the accuracy of prediction.
  • an embodiment of the present application proposes a method for determining the prediction window period The method used to improve the accuracy of prediction.
  • An embodiment of the method for determining the prediction window period in this application includes:
  • the processing strategy of the solid state drive processor is meaningless. If the prediction window is too long, even if the load capacity of the SSD processor (that is, the computing power of the SSD processor) can be reached, the accuracy of the prediction will not be too high.
  • this application proposes a method for determining the prediction window period. Specifically, it is necessary to obtain the read and write bandwidth and cache capacity of the SSD before calculating the prediction window.
  • the read and write bandwidth of the SSD is determined by the SSD processor. The amount of data that can be read or written in a unit time can be determined according to the SSD interface protocol. If the read and write bandwidth of the SSD is 14GB/s and 10GB/s, then the SSD processor can read within 1S The amount of data output is 14GB, and the amount of data that can be written in 1S is 10GB.
  • a certain cache area is generally set in the SSD to realize the fast reading and writing of the data requested by the host.
  • the setting of the cache area will be different for each manufacturer.
  • the settings will be marked on the solid state drive.
  • the cache capacity can be calculated for the first cycle of a full-speed read and write.
  • step 104 After the first cycle is obtained, it is necessary to further obtain the I/O throughput of the solid state drive, so as to perform step 104 according to the first cycle and I/O throughput.
  • the I/O throughput of the solid state drive is the IOPS of the solid state drive, which refers to the number of I/Os that the solid state drive can process in a unit time.
  • the length of the prediction window period can be determined according to the first cycle and the I/O throughput.
  • the read and write bandwidth and cache capacity of the solid state drive are obtained, and the first cycle of completing a full-speed read and write to the cache capacity is calculated according to the read and write bandwidth and the cache capacity, and the solid state drive processor is obtained
  • the prediction window period is determined according to the first cycle and the I/O throughput.
  • the prediction window is determined according to the capacity of the cache and the I/O throughput of the SSD The period is determined so that the prediction window period not only meets the cycle of completing a full-speed read and write to the cache, but also meets the load capacity of the solid-state hard disk processor, thereby improving the accuracy of the prediction.
  • step 104 in the embodiment in FIG. 1 will be described in detail below. Please refer to FIG. 2 for details.
  • FIG. 1 is a detailed step of step 104 in the embodiment in FIG. 1 in the embodiment of this application:
  • the process of determining the prediction window period according to the I/O throughput and the first cycle is as follows:
  • the device that determines the prediction window period obtains the I/O throughput of the SSD processor, it calculates the first data volume according to the I/O throughput and the first cycle. Specifically, assume the I/O throughput of the SSD processor The volume is 15GB/S, the first cycle is 70ms, the first data volume that the solid-state drive can process in the first cycle is 1.05G.
  • the solid-state hard disk processor in this embodiment can not only realize the function of the main control unit in the ordinary solid-state hard disk, but also can further realize the data processing function, which can be regarded as a combination of the solid-state hard disk main control unit and the data processing unit. set.
  • step 204 Obtain the first data volume, and determine whether the first data volume is greater than the cache capacity of the solid state drive. If it is greater, it means that the I/O calculation amount for the forecast window period is within the load capacity of the solid state drive processor, then execute the steps 203. If it is not greater than, it indicates that the I/O calculation amount for the prediction window period exceeds the load capacity of the solid-state hard disk processor, and step 204 is executed.
  • the first data volume is greater than the cache capacity of the solid state drive, it means that the I/O calculation amount for the forecast window period is within the load capacity of the solid state drive processor, and the first period is set as the prediction of the I/O information prediction window period.
  • the first data volume is not greater than the cache capacity of the solid state drive, it means that the number of I/Os that occurred during the prediction window exceeds the I/O throughput of the solid state drive processor, and then the I/O throughput of the solid state drive processor And the cache capacity of the solid state drive, calculate the second cycle of completing a full-speed read and write to the cache capacity.
  • the I/O read and write throughput of the solid state drive is 7GB/s and 5GB/s
  • the cache capacity is 1GB
  • the second cycle is determined as the prediction window period, which specifically corresponds to step 204, which is to set 140ms and 200ms respectively Determined as the corresponding read-write prediction window period.
  • the number of sliding steps in the prediction window period can also be calculated according to specific application scenarios, which can be used to perform I/O information for a longer period of time in the future. Prediction. Specifically, this application can also determine the third cycle for completing a full-speed read and write for the smallest erase unit, and use the prediction window period as the sliding window to calculate the prediction of I/O information in the third cycle. For the required number of sliding steps, please refer to FIG. 3 for details.
  • Another embodiment for determining the prediction window period in the embodiment of the present application includes:
  • the storage capacity of the minimum erasing unit of the solid state drive can also be obtained.
  • the storage capacity of the minimum erasing unit is larger than the cache of the solid state drive.
  • the minimum erasing unit It is super block, and the capacity of super block is 4G.
  • the storage capacity of the smallest erasing unit is marked when the solid state drive leaves the factory.
  • the third cycle for completing a full-speed reading and writing to the minimum erasing unit can also be calculated according to the read and write bandwidth and the capacity of the minimum erasing unit.
  • the minimum erasing unit is a super block
  • the capacity of the super block is 4G
  • the read and write bandwidths are 14GB/s and 10GB/s, respectively
  • the third cycle for completing a full-speed read and write of the super block is respectively 280ms and 400ms.
  • the number of sliding steps required to complete the prediction of the I/O information in the third cycle can be calculated.
  • the calculated third cycle for completing a full-speed read and write to the super block is 280 ms and 400 ms, respectively, and after the prediction window period is determined, the number of sliding steps can be determined.
  • the third cycle for completing a full-speed read and write to the superblock is 280ms and 400ms, respectively, corresponding to the embodiment in FIG. 2, the first cycle is 70ms and 100ms, and the number of sliding steps is 4 steps.
  • the third cycle for completing a full-speed read and write to the superblock is 280ms and 400ms, respectively, corresponding to the embodiment in FIG. 2, the second cycle is 140ms and 200ms, and the number of sliding steps is 2 steps.
  • the solid-state hard disk processor is allowed to predict the I/O information of the first time period in the future.
  • the solid-state hard disk processor can predict the I/O information for the first time period in the future based on the prediction window period and the number of sliding steps.
  • the I/O information in the third cycle when the minimum erasing unit completes a full-speed read and write can be predicted, so that the solid-state hard disk processor performs active cache scheduling according to the prediction result to improve host-side data Response time.
  • the first obtaining unit 401 is configured to obtain the read and write bandwidth and cache capacity of the solid state drive
  • the calculation unit 402 is configured to calculate the first cycle for completing a full-speed read and write to the cache capacity according to the read and write bandwidth and the cache capacity;
  • the second obtaining unit 403 is configured to obtain the I/O throughput of the solid state disk processor
  • the determining unit 404 is configured to determine the prediction window period according to the first cycle and the I/O throughput.
  • the determining unit 404 is configured to:
  • the first data amount is greater than the buffer capacity, it is determined that the first period is the prediction window period.
  • the determining unit 404 is further configured to:
  • the first data amount is not greater than the cache capacity, calculating a second cycle for completing a full-speed read and write to the cache capacity according to the I/O throughput and the cache capacity;
  • the second period is the prediction window period.
  • the first obtaining unit 401 is further configured to:
  • the first obtaining unit 401 is specifically further configured to:
  • prediction window period is the first period, determine the number of sliding steps in the prediction window period according to the third period and the first period;
  • the number of sliding steps of the prediction window period is determined according to the third period and the second period.
  • the device further includes:
  • the prediction unit 405 is configured to make the solid-state hard disk processor predict the I/O information of the first time period in the future according to the prediction window period and the number of sliding steps.
  • each unit in the embodiment of the present application is similar to the function of the device for determining the prediction window period in the embodiment of FIG. 1 to FIG. 3, and will not be repeated here.
  • the read and write bandwidth and cache capacity of the solid state drive are obtained by the first obtaining unit 401, and the calculation unit 402 calculates the completion of a full-speed read and write to the cache capacity according to the read and write bandwidth and the cache capacity Then, the I/O throughput of the solid-state disk processor is obtained, and the prediction window period is determined by the determining unit 404 according to the first cycle and the I/O throughput.
  • the prediction window period is determined so that the forecast window period meets the cycle of completing a full-speed read and write to the cache and also meets the load capacity of the SSD processor, thereby improving the forecast The accuracy rate.
  • the embodiment of the present application also provides a solid state hard disk, which may include the device for determining the prediction window period described in FIG. 4, or may call a third-party device for determining the prediction window period through a calling interface (such as an API interface) for use Determine a suitable prediction window period to predict the I/O information of the first time period in the future to improve the accuracy of the prediction.
  • a calling interface such as an API interface
  • the working principle of the device for determining the prediction window period can be referred to as described in FIGS. 1 to 3 The embodiments are not repeated here.
  • the computer device is used to implement the function of the device for measuring the window period.
  • An embodiment of the computer device in the embodiment of the present application includes:
  • the memory is used to store computer programs, and when the processor is used to execute the computer programs stored in the memory, the following steps can be implemented:
  • the prediction window period is determined according to the first cycle and the I/O throughput.
  • the processor may also be used to implement the following steps:
  • the first data amount is greater than the buffer capacity, it is determined that the first period is the prediction window period.
  • the processor may also be used to implement the following steps:
  • the first data amount is not greater than the cache capacity, calculating a second cycle for completing a full-speed read and write to the cache capacity according to the I/O throughput and the cache capacity;
  • the second period is the prediction window period.
  • the processor may also be used to implement the following steps:
  • the processor may also be used to implement the following steps:
  • prediction window period is the first period, determine the number of sliding steps in the prediction window period according to the third period and the first period;
  • the number of sliding steps of the prediction window period is determined according to the third period and the second period.
  • the processor may also be used to implement the following steps:
  • the solid-state hard disk processor is made to predict the I/O information of the first time period in the future.
  • the processor in the computer device described above executes the computer program, it can also implement the functions of the units in the corresponding device embodiments described above, which will not be repeated here.
  • the computer program may be divided into one or more modules/units, and the one or more modules/units are stored in the memory and executed by the processor to complete the application.
  • the one or more modules/units may be a series of computer program instruction segments capable of completing specific functions, and the instruction segments are used to describe the execution process of the computer program in the device in the prediction window period.
  • the computer program may be divided into units in the aforementioned predictive window period device, and each unit can implement specific functions as described in the aforementioned corresponding predictive window period device.
  • the computer device may be a computing device such as a desktop computer, a notebook, a palmtop computer, and a cloud server.
  • the computer device may include, but is not limited to, a processor and a memory.
  • the processor and the memory are only examples of the computer device and do not constitute a limitation on the computer device. They may include more or fewer components, or combine certain components, or different components, such as
  • the computer device may also include input and output devices, network access devices, buses, and the like.
  • the processor may be a central processing unit (Central Processing Unit, CPU), or other general-purpose processors, digital signal processors (Digital Signal Processor, DSP), and application specific integrated circuits (Applicat I/On Specific Integrated Circuit, ASIC) , Ready-made programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • the general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.
  • the processor is the control center of the computer device, and various interfaces and lines are used to connect various parts of the entire computer device.
  • the memory may be used to store the computer program and/or module, and the processor implements the computer by running or executing the computer program and/or module stored in the memory, and calling data stored in the memory.
  • the memory may mainly include a program storage area and a data storage area.
  • the program storage area may store an operating system, an application program required by at least one function, etc.; the data storage area may store data created according to the use of the terminal, etc.
  • the memory may include high-speed random access memory, and may also include non-volatile memory, such as hard disks, memory, plug-in hard disks, Smart Media Card (SMC), Secure Digital (SD) cards , Flash Card, at least one magnetic disk storage device, flash memory device, or other volatile solid-state storage device.
  • SMC Smart Media Card
  • SD Secure Digital
  • This application also provides a computer-readable storage medium for realizing the function of the device for predicting the window period.
  • a computer program is stored thereon.
  • the processor can use To perform the following steps:
  • the prediction window period is determined according to the first cycle and the I/O throughput.
  • the processor when a computer program stored in a computer-readable storage medium is executed by a processor, the processor may be specifically configured to execute the following steps:
  • the first data amount is greater than the buffer capacity, it is determined that the first period is the prediction window period.
  • the processor when a computer program stored in a computer-readable storage medium is executed by a processor, the processor may be specifically configured to execute the following steps:
  • the first data amount is not greater than the cache capacity, calculating a second cycle for completing a full-speed read and write to the cache capacity according to the I/O throughput and the cache capacity;
  • the second period is the prediction window period.
  • the processor when a computer program stored in a computer-readable storage medium is executed by a processor, the processor may be specifically configured to execute the following steps:
  • the processor when a computer program stored in a computer-readable storage medium is executed by a processor, the processor may be specifically configured to execute the following steps:
  • prediction window period is the first period, determine the number of sliding steps in the prediction window period according to the third period and the first period;
  • the number of sliding steps of the prediction window period is determined according to the third period and the second period.
  • the processor when a computer program stored in a computer-readable storage medium is executed by a processor, the processor may be specifically configured to execute the following steps:
  • the solid-state hard disk processor is made to predict the I/O information of the first time period in the future.
  • the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a corresponding computer readable storage medium.
  • this application implements all or part of the processes in the above-mentioned corresponding embodiments and methods, and can also be completed by instructing relevant hardware through a computer program.
  • the computer program can be stored in a computer-readable storage medium.
  • the computer program is executed by the processor, it can implement the steps of the foregoing method embodiments.
  • the computer program includes computer program code, and the computer program code may be in the form of source code, object code, executable file, or some intermediate forms.
  • the computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory) , Random Access Memory (RAM, Random Access Memory), electrical carrier signal, telecommunications signal, and software distribution media.
  • ROM Read-Only Memory
  • RAM Random Access Memory
  • electrical carrier signal telecommunications signal
  • software distribution media any entity or device capable of carrying the computer program code
  • recording medium U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory) , Random Access Memory (RAM, Random Access Memory), electrical carrier signal, telecommunications signal, and software distribution media.
  • the disclosed system, device, and method can be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or It can be integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • each unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated unit can be implemented in the form of hardware or software functional unit.

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Abstract

一种确定预测窗口期的方法及装置，用于确定固态硬盘中的预测窗口期，以提高预测的准确率。本申请实施例方法包括：获取固态硬盘的读写带宽及缓存容量；根据所述读写带宽及所述缓存容量，计算对所述缓存容量完成一次全速读写的第一周期；获取固态硬盘处理器的I/O吞吐量；根据所述第一周期及所述I/O吞吐量确定所述预测窗口期。

Description

一种确定预测窗口期的方法及装置
本申请要求于2019年5月9日提交中国专利局、申请号为201910385554.0、发明名称为“一种确定预测窗口期的方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及固态硬盘数据处理技术领域，尤其涉及一种确定预测窗口期的方法及装置。
背景技术
Flash Translation Layer(FTL)是SSD的软件核心，其重要程度在于决定了一个SSD的使用寿命、性能和可靠性。在学术界，这十年来有很多文章在讨论如何实现一个高效的FTL，例如，在有限硬件资源的环境下如何优化mapping table？如何实现buffer的管理？如何实现高效的垃圾回收(GC)？如何实现磨损均衡？但是，这些方法或是策略大多是后知后觉的、被动的。
而如果可以对未来第一时间段的SSD盘中的I/O信息进行预测，那么就可以有更多主动的机制，如主动地buffer调度或主动地GC，而在对未来第一时间段执行预测时，如何选择预测窗口期，将会很大程度的影响预测的准确性。如果，预测窗口期太短，对于FTL没有太大意义；反之，如果太长，即使计算力可以达到，结果也不会太准确。
发明内容
本申请实施例提供了一种确定预测窗口期的方法及装置，用于确定固态硬盘中的预测窗口期，以提高预测的准确率。
本申请实施例第一方面提供了一种确定预测窗口期的方法，包括：
获取固态硬盘的读写带宽及缓存容量；
根据所述读写带宽及所述缓存容量，计算对所述缓存容量完成一次全速读写的第一周期；
获取固态硬盘处理器的I/O吞吐量；
根据所述第一周期及所述I/O吞吐量确定所述预测窗口期。
优选的，所述根据所述第一周期及所述I/O吞吐量确定所述预测窗口期，包括：
根据所述I/O吞吐量，计算所述固态硬盘处理器在所述第一周期内处理的第一数据量；
判断所述第一数据量是否大于所述缓存容量；
若所述第一数据量大于所述缓存容量，则确定所述第一周期为所述预测窗口期。
优选的，所述方法还包括：
若所述第一数据量不大于所述缓存容量，则根据所述I/O吞吐量及所述缓存容量，计算对所述缓存容量完成一次全速读写的第二周期；
确定所述第二周期为所述预测窗口期。
优选的，所述方法还包括：
获取所述固态硬盘最小擦除单元的存储容量；
根据所述读写带宽及所述最小擦除单元的存储容量，计算对所述最小擦除单元完成一次全速读写的第三周期；
根据所述第三周期及所述预测窗口期，确定所述预测窗口期的滑动步数。
优选的，所述根据所述第三周期及所述预测窗口期，确定所述预测窗口期的滑动步数，包括：
若所述预测窗口期为所述第一周期时，则根据所述第三周期和所述第一周期，确定所述预测窗口期的滑动步数；
若所述预测窗口期为所述第二周期时，则根据所述第三周期和所述第二周期，确定所述预测窗口期的滑动步数。
优选的，所述方法还包括：
根据所述预测窗口期及所述滑动步数，使得固态硬盘处理器对未来第一时间段的I/O信息进行预测。
本申请实施例第二方面提供了一种确定预测窗口期的装置，包括：
第一获取单元，用于获取固态硬盘的读写带宽及缓存容量；
计算单元，用于根据所述读写带宽及所述缓存容量，计算对所述缓存容量完成一次全速读写的第一周期；
第二获取单元，用于获取固态硬盘处理器的I/O吞吐量；
确定单元，用于根据所述第一周期及所述I/O吞吐量确定所述预测窗口期。
优选的，所述确定单元，具有用于：
根据所述I/O吞吐量，计算所述固态硬盘处理器在所述第一周期内处理的第一数据量；
判断所述第一数据量是否大于所述缓存容量；
若所述第一数据量大于所述缓存容量，则确定所述第一周期为所述预测窗口期。
优选的，所述确定单元，还用于：
若所述第一数据量不大于所述缓存容量，则根据所述I/O吞吐量及所述缓存容量，计算对所述缓存容量完成一次全速读写的第二周期；
确定所述第二周期为所述预测窗口期。
优选的，所述第一获取单元，还用于：
获取所述固态硬盘最小擦除单元的存储容量；
根据所述读写带宽及所述最小擦除单元的存储容量，计算对所述最小擦除单元完成一次全速读写的第三周期；
根据所述第三周期及所述预测窗口期，确定所述预测窗口期的滑动步数。
优选的，所述第一获取单元，还用于：
若所述预测窗口期为所述第一周期时，则根据所述第三周期和所述第一周期，确定所述预测窗口期的滑动步数；
若所述预测窗口期为所述第二周期时，则根据所述第三周期和所述第二周期，确定所述预测窗口期的滑动步数。
优选的，所述装置还包括：
预测单元，用于根据所述预测窗口期及所述滑动步数，使得固态硬盘 处理器对未来第一时间段的I/O信息进行预测。
本申请实施例第三方面提供了一种固态硬盘，包括本申请实施例第二方面提供的确定预测窗口期的装置，或调用本申请实施例第二方面提供的确定预测窗口期的装置，以实现对未来第一时间段I/O信息的预测。
本申请实施例还提供了一种计算机装置，包括处理器，该处理器在执行存储于存储器上的计算机程序时，用于实现申请实施例第一方面提供的确定预测窗口期的方法。
本申实施例还提供了一种计算机可读存储介质，其上存储有计算机程序，该计算机程序被处理器执行时，用于实现申请实施例第一方面提供的确定预测窗口期的方法。
从以上技术方案可以看出，本申请实施例具有以下优点：
本申请实施例中，获取固态硬盘的读写带宽及缓存容量，根据所述读写带宽及所述缓存容量，计算对所述缓存容量完成一次全速读写的第一周期，获取固态硬盘处理器的I/O吞吐量，根据所述第一周期及所述I/O吞吐量确定所述预测窗口期，本实施例中，根据缓存的容量和固态硬盘的I/O吞吐量，对预测窗口期进行确定，使得该预测窗口期既符合对缓存完成一次全速读写的周期，也满足固态硬盘处理器的负载能力，从而提高了预测的准确率。
附图说明
图1为本申请实施例中一种确定预测窗口期的方法的一个实施例示意图；
图2为本申请实施例中图1实施例步骤104的细化步骤；
图3为本申请实施例中一种确定预测窗口期的方法的另一个实施例示意图；
图4为本申请实施例中一种确定预测窗口期的装置的一个实施例示意图。
具体实施方式
本申请实施例提供了一种确定预测窗口期的方法及装置，用于确定固态硬盘中的预测窗口期，以提高预测的准确率。
为了使本技术领域的人员更好地理解本申请方案，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分的实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本申请保护的范围。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的实施例能够以除了在这里图示或描述的内容以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
基于在对固态硬盘中的未来第一时间段内的I/O信息进行预测时，如何确定一个合适的预测窗口期，以提高预测的准确率，本申请实施例提出了一种确定预测窗口期的方法，用于提高预测的准确率。
为方便理解，下面对本申请中的确定预测窗口期的方法进行详细描述，具体请参阅图1，本申请中一种确定预测窗口期的方法的一个实施例，包括：
101、获取固态硬盘的读写带宽及缓存容量；
在对固态硬盘中未来第一时间段内的I/O信息进行预测时，需要选择一个合适的预测窗口期，若该预测窗口期太短，则对固态硬盘处理器的处理策略没有意义，而若预测窗口期太长，即使固态硬盘处理器的负载能力(即固态硬盘处理器的算力)可以达到，但预测的准确率也不会太高。
故本申请提出了一种确定预测窗口期的方法，具体的，需要在计算预测窗口期前，获取固态硬盘的读写带宽及缓存容量，一般，固态硬盘的读写带宽为固态硬盘处理器在单位时间内可以读出或写入的数据量，可以根 据固态硬盘接口协议确定，假如固态硬盘的读写带宽分别为14GB/s与10GB/s，则为该固态硬盘处理器在1S内可以读出的数据量为14GB，而在1S内可以写入的数据量为10GB。
而为了提高固态硬盘的数据处理速度，一般都会在固态硬盘内设置一定的缓存区，以用于实现对主机请求数据的快速读出及写入，而缓存区的设置每个生产厂家都会有不同的设置，且都会在固态硬盘上进行标注。
102、根据所述读写带宽及所述缓存容量，计算对所述缓存容量完成一次全速读写的第一周期；
获取到固态硬盘的读写带宽及缓存容量后，即可对缓存容量完成一次全速读写的第一周期进行计算。
具体的，假设固态硬盘的读写带宽分别为14GB/s与10GB/s，而该固态硬盘的缓存为1GB，则对该缓存完成一次全速读的第一周期为：1GB/14GB/s＝70ms，对该缓存完成一次全速写的第一周期为：1GB/10GB/s＝100ms。
需要说明的是，上述举例只是对第一周期的示例性说明，并不对第一周期的大小构成具体限制。
103、获取固态硬盘处理器的I/O吞吐量；
得到第一周期后，还需要进一步获取固态硬盘的I/O吞吐量，以便于根据第一周期和I/O吞吐量，执行步骤104.
具体的，固态硬盘的I/O吞吐量，即为固态硬盘的IOPS，是指固态硬盘在单位时间内可以处理的I/O次数。
104、根据所述第一周期及所述I/O吞吐量确定所述预测窗口期。
得到第一周期和固态硬盘的I/O吞吐量后，即可根据第一周期和I/O吞吐量，确定预测窗口期的时长。
具体的，对于预测窗口期的确定过程，将在下面的实施例中进行描述，此处不再赘述。
本申请实施例中，获取固态硬盘的读写带宽及缓存容量，根据所述读写带宽及所述缓存容量，计算对所述缓存容量完成一次全速读写的第一周期，获取固态硬盘处理器的I/O吞吐量，根据所述第一周期及所述I/O吞吐 量确定所述预测窗口期，本实施例中，根据缓存的容量和固态硬盘的I/O吞吐量，对预测窗口期进行确定，使得该预测窗口期既符合对缓存完成一次全速读写的周期，也满足固态硬盘处理器的负载能力，从而提高了预测的准确率。
基于图1所述的实施例，下面对图1实施例中的步骤104进行详细描述，具体请参阅图2，图1为本申请实施例中图1实施例中步骤104的细化步骤：
201、根据所述I/O吞吐量，计算所述固态硬盘处理器在所述第一周期内处理的第一数据量；
具体的，在根据I/O吞吐量和第一周期确定预测窗口期的过程如下：
确定预测窗口期的装置在获取到固态硬盘处理器的I/O吞吐量时，根据I/O吞吐量和第一周期计算第一数据量，具体的，假设固态硬盘处理器的I/O吞吐量为15GB/S,第一周期为70ms,则固态硬盘在第一周期能够处理的第一数据量为1.05G。
需要说明的是，本实施例中的固态硬盘处理器不仅可以实现普通固态硬盘中主控单元的功能，还可以进一步实现对数据的处理功能，可以视为固态硬盘主控单元和数据处理单元的集合。
202、判断所述第一数据量是否大于所述缓存容量，若是，则执行步骤203，若否，则执行步骤204；
获取到第一数据量，判断第一数据量是否大于该固态硬盘的缓存容量，若大于，则说明对预测窗口期的I/O计算量在固态硬盘处理器的负载能力范围内，则执行步骤203，若不大于，则说明对预测窗口期的I/O计算量超出固态硬盘处理器的负载能力，则执行步骤204。
203、确定所述第一周期为所述预测窗口期；
若第一数据量大于固态硬盘的缓存容量，则说明对预测窗口期的I/O计算量在固态硬盘处理器的负载能力范围内，则将该第一周期设置为I/O信息预测的预测窗口期。
204、根据所述I/O吞吐量及所述缓存容量，计算对所述缓存容量完成一次全速读写的第二周期；
若第一数据量不大于固态硬盘的缓存容量，则说明发生在预测窗口期 内的I/O次数超出固态硬盘处理器的I/O吞吐量，则根据固态硬盘处理器的I/O吞吐量和固态硬盘的缓存容量，计算对所述缓存容量完成一次全速读写的第二周期，具体的，假设固态硬盘的I/O读写吞吐量分别为7GB/s和5GB/s，缓存容量为1GB,则对缓存容量完成一次全速读写的第二周期分别为1GB/7GB/S＝140ms和1GB/5GB/S＝200ms。
205、确定所述第二周期为所述预测窗口期。
在根据固态硬盘处理器的I/O吞吐量和固态硬盘的缓存容量，确定了第二周期后，则将第二周期确定为预测窗口期,具体对应于步骤204，即为将140ms和200ms分别确定为对应的读写预测窗口期。
本申请实施例中，对如何根据固态硬盘处理器的I/O吞吐量和第一周期，确定预测窗口期的过程做了详细描述，提升了本申请实施例的可实施性。
基于图2所述的实施例，在确定了预测窗口期后，还可以根据具体的应用场景，计算预测窗口期的滑动步数，以用于对未来更长时间段内的I/O信息进行预测，具体的，本申请还可以确定对最小擦除单元完成一次全速读写的第三周期，并以预测窗口期为滑动窗口，来计算完成对第三周期内I/O信息的预测，所需要的滑动步数，具体请参阅图3，本申请实施例中确定预测窗口期的另一个实施例，包括：
301、获取所述固态硬盘最小擦除单元的存储容量；
进一步的，在确定了预测窗口期后，还可以获取固态硬盘的最小擦除单元的存储容量，一般最小擦除单元的存储容量都大于固态硬盘的缓存，本申请实施例中假设最小擦除单元为super block,而super block的容量为4G。
具体的，固态硬盘在出厂时，都会对最小擦除单元的存储容量进行标注。
302、根据所述读写带宽及所述最小擦除单元的存储容量，计算对所述最小擦除单元完成一次全速读写的第三周期；
得到固态硬盘的最小擦除单元后，还可以根据读写带宽和最小擦除单元的容量，计算对该最小擦除单元完成一次全速读写的第三周期。
具体的，假设最小擦除单元为super block，而super block的容量为4G，读写带宽分别为14GB/s与10GB/s，则对该super block完成一次全速读写的第三周期为分别为280ms和400ms。
303、根据所述第三周期及所述预测窗口期，确定所述预测窗口期的滑动步数；
在确定了对最小擦除单元完成一次全速读写的第三周期后，结合预测窗口期，即可计算出完成对第三周期内的I/O信息预测，所需要的滑动步数。
具体的，对应于步骤302，计算的对super block完成一次全速读写的第三周期为分别为280ms和400ms，而在确定了预测窗口期后，即可确定滑动步数。
进一步的，根据预测窗口期的不同，滑动步数的计算也有所不同，具体的计算过程如下；
①、假设预测窗口期为第一周期，则根据第三周期和第一周期，计算滑动步数；
因为对super block完成一次全速读写的第三周期为分别为280ms和400ms，对应于图2的实施例，第一周期分别为70ms和100ms，则滑动步数为4步。
②、假设预测窗口期为第二周期，则根据第三周期和第二周期，计算滑动步数；
因为对super block完成一次全速读写的第三周期为分别为280ms和400ms，对应于图2的实施例，第二周期分别为140ms和200ms，则滑动步数为2步。
304、根据所述预测窗口期及所述滑动步数，使得固态硬盘处理器对未来第一时间段的I/O信息进行预测。
确定了预测窗口期和滑动步数后，即可根据预测窗口期和滑动步数，使得固态硬盘处理器对未来第一时间段的I/O信息进行预测。
在本申请实施例中，可以对最小擦除单元完成一次全速读写的第三周期内的I/O信息进行预测，以便于固态硬盘处理器根据预测结果执行主动缓存调度，以提高主机端数据的响应时间。
本申请实施例中，对在具体应用场景中，对滑动步数的计算方法做了详细描述，提升了本申请实施例的可实施性。
上面对本申请中确定预测窗口期的方法做了详细描述，下面接着对本申请中确定预测窗口期的装置进行描述，具体请参阅图4，本申请实施例中确定预测窗口期的装置的一个实施例，包括：
第一获取单元401，用于获取固态硬盘的读写带宽及缓存容量；
计算单元402，用于根据所述读写带宽及所述缓存容量，计算对所述缓存容量完成一次全速读写的第一周期；
第二获取单元403，用于获取固态硬盘处理器的I/O吞吐量；
确定单元404，用于根据所述第一周期及所述I/O吞吐量确定所述预测窗口期。
优选的，所述确定单元404，具有用于：
根据所述I/O吞吐量，计算所述固态硬盘处理器在所述第一周期内处理的第一数据量；
判断所述第一数据量是否大于所述缓存容量；
若所述第一数据量大于所述缓存容量，则确定所述第一周期为所述预测窗口期。
优选的，所述确定单元404，还用于：
若所述第一数据量不大于所述缓存容量，则根据所述I/O吞吐量及所述缓存容量，计算对所述缓存容量完成一次全速读写的第二周期；
确定所述第二周期为所述预测窗口期。
优选的，所述第一获取单元401，还用于：
获取所述固态硬盘最小擦除单元的存储容量；
根据所述读写带宽及所述最小擦除单元的存储容量，计算对所述最小擦除单元完成一次全速读写的第三周期；
根据所述第三周期及所述预测窗口期，确定所述预测窗口期的滑动步数。
优选的，所述第一获取单元401，具体还用于：
若所述预测窗口期为所述第一周期时，则根据所述第三周期和所述第 一周期，确定所述预测窗口期的滑动步数；
若所述预测窗口期为所述第二周期时，则根据所述第三周期和所述第二周期，确定所述预测窗口期的滑动步数。
优选的，所述装置还包括：
预测单元405，用于根据所述预测窗口期及所述滑动步数，使得固态硬盘处理器对未来第一时间段的I/O信息进行预测。
需要说明的是，本申请实施例中各单元的作用与图1至图3实施例中确定预测窗口期的装置的作用类似，此处不再赘述。
本申请实施例中，通过第一获取单元401获取固态硬盘的读写带宽及缓存容量，通过计算单元402根据所述读写带宽及所述缓存容量，计算对所述缓存容量完成一次全速读写的第一周期，然后获取固态硬盘处理器的I/O吞吐量，通过确定单元404根据所述第一周期及所述I/O吞吐量确定所述预测窗口期，本实施例中，根据缓存的容量和固态硬盘的I/O吞吐量，对预测窗口期进行确定，使得该预测窗口期既符合对缓存完成一次全速读写的周期，也满足固态硬盘处理器的负载能力，从而提高了预测的准确率。
本申请实施例还提供了一种固态硬盘，可以包括图4所述的确定预测窗口期的装置，或可以通过调用接口(如API接口)调用第三方的确定预测窗口期的装置，以用于确定合适的预测窗口期，以对未来第一时间段的I/O信息进行预测，以提升预测的准确率，其中，确定预测窗口期的装置的作用原理可以参照图1至图3所述的实施例，此处不再赘述。
上面从模块化功能实体的角度对本申请实施例中确定预测窗口期的装置进行了描述，下面从硬件处理的角度对本申请实施例中的计算机装置进行描述：
该计算机装置用于实现测窗口期的装置的功能，本申请实施例中计算机装置一个实施例包括：
处理器以及存储器；
存储器用于存储计算机程序，处理器用于执行存储器中存储的计算机程序时，可以实现如下步骤：
获取固态硬盘的读写带宽及缓存容量；
根据所述读写带宽及所述缓存容量，计算对所述缓存容量完成一次全速读写的第一周期；
获取固态硬盘处理器的I/O吞吐量；
根据所述第一周期及所述I/O吞吐量确定所述预测窗口期。
在本申请的一些实施例中，处理器，还可以用于实现如下步骤：
根据所述I/O吞吐量，计算所述固态硬盘处理器在所述第一周期内处理的第一数据量；
判断所述第一数据量是否大于所述缓存容量；
若所述第一数据量大于所述缓存容量，则确定所述第一周期为所述预测窗口期。
在本申请的一些实施例中，处理器，还可以用于实现如下步骤：
若所述第一数据量不大于所述缓存容量，则根据所述I/O吞吐量及所述缓存容量，计算对所述缓存容量完成一次全速读写的第二周期；
确定所述第二周期为所述预测窗口期。
在本申请的一些实施例中，处理器，还可以用于实现如下步骤：
获取所述固态硬盘最小擦除单元的存储容量；
根据所述读写带宽及所述最小擦除单元的存储容量，计算对所述最小擦除单元完成一次全速读写的第三周期；
根据所述第三周期及所述预测窗口期，确定所述预测窗口期的滑动步数。
在本申请的一些实施例中，处理器，还可以用于实现如下步骤：
若所述预测窗口期为所述第一周期时，则根据所述第三周期和所述第一周期，确定所述预测窗口期的滑动步数；
若所述预测窗口期为所述第二周期时，则根据所述第三周期和所述第二周期，确定所述预测窗口期的滑动步数。
在本申请的一些实施例中，处理器，还可以用于实现如下步骤：
根据所述预测窗口期及所述滑动步数，使得固态硬盘处理器对未来第一时间段的I/O信息进行预测。
可以理解的是，上述说明的计算机装置中的处理器执行所述计算机程 序时，也可以实现上述对应的各装置实施例中各单元的功能，此处不再赘述。示例性的，所述计算机程序可以被分割成一个或多个模块/单元，所述一个或者多个模块/单元被存储在所述存储器中，并由所述处理器执行，以完成本申请。所述一个或多个模块/单元可以是能够完成特定功能的一系列计算机程序指令段，该指令段用于描述所述计算机程序在所述预测窗口期的装置中的执行过程。例如，所述计算机程序可以被分割成上述预测窗口期的装置中的各单元，各单元可以实现如上述相应预测窗口期的装置说明的具体功能。
所述计算机装置可以是桌上型计算机、笔记本、掌上电脑及云端服务器等计算设备。所述计算机装置可包括但不仅限于处理器、存储器。本领域技术人员可以理解，处理器、存储器仅仅是计算机装置的示例，并不构成对计算机装置的限定，可以包括更多或更少的部件，或者组合某些部件，或者不同的部件，例如所述计算机装置还可以包括输入输出设备、网络接入设备、总线等。
所述处理器可以是中央处理单元(Central Processing Unit，CPU)，还可以是其他通用处理器、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(ApplicatI/On Specific Integrated Circuit，ASIC)、现成可编程门阵列(Field-Programmable Gate Array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等，所述处理器是所述计算机装置的控制中心，利用各种接口和线路连接整个计算机装置的各个部分。
所述存储器可用于存储所述计算机程序和/或模块，所述处理器通过运行或执行存储在所述存储器内的计算机程序和/或模块，以及调用存储在存储器内的数据，实现所述计算机装置的各种功能。所述存储器可主要包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需的应用程序等；存储数据区可存储根据终端的使用所创建的数据等。此外，存储器可以包括高速随机存取存储器，还可以包括非易失性存储器，例如硬盘、内存、插接式硬盘，智能存储卡(Smart Media Card,SMC)， 安全数字(Secure Digital,SD)卡，闪存卡(Flash Card)、至少一个磁盘存储器件、闪存器件、或其他易失性固态存储器件。
本申请还提供了一种计算机可读存储介质，该计算机可读存储介质用于实现预测窗口期的装置的功能，其上存储有计算机程序，计算机程序被处理器执行时，处理器，可以用于执行如下步骤：
获取固态硬盘的读写带宽及缓存容量；
根据所述读写带宽及所述缓存容量，计算对所述缓存容量完成一次全速读写的第一周期；
获取固态硬盘处理器的I/O吞吐量；
根据所述第一周期及所述I/O吞吐量确定所述预测窗口期。
在本申请的一些实施例中，计算机可读存储介质存储的计算机程序被处理器执行时，处理器，可以具体用于执行如下步骤：
根据所述I/O吞吐量，计算所述固态硬盘处理器在所述第一周期内处理的第一数据量；
判断所述第一数据量是否大于所述缓存容量；
若所述第一数据量大于所述缓存容量，则确定所述第一周期为所述预测窗口期。
在本申请的一些实施例中，计算机可读存储介质存储的计算机程序被处理器执行时，处理器，可以具体用于执行如下步骤：
若所述第一数据量不大于所述缓存容量，则根据所述I/O吞吐量及所述缓存容量，计算对所述缓存容量完成一次全速读写的第二周期；
确定所述第二周期为所述预测窗口期。
在本申请的一些实施例中，计算机可读存储介质存储的计算机程序被处理器执行时，处理器，可以具体用于执行如下步骤：
获取所述固态硬盘最小擦除单元的存储容量；
根据所述读写带宽及所述最小擦除单元的存储容量，计算对所述最小擦除单元完成一次全速读写的第三周期；
根据所述第三周期及所述预测窗口期，确定所述预测窗口期的滑动步数。
在本申请的一些实施例中，计算机可读存储介质存储的计算机程序被处理器执行时，处理器，可以具体用于执行如下步骤：
若所述预测窗口期为所述第一周期时，则根据所述第三周期和所述第一周期，确定所述预测窗口期的滑动步数；
若所述预测窗口期为所述第二周期时，则根据所述第三周期和所述第二周期，确定所述预测窗口期的滑动步数。
在本申请的一些实施例中，计算机可读存储介质存储的计算机程序被处理器执行时，处理器，可以具体用于执行如下步骤：
根据所述预测窗口期及所述滑动步数，使得固态硬盘处理器对未来第一时间段的I/O信息进行预测。
可以理解的是，所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在相应的一个计算机可读取存储介质中。基于这样的理解，本申请实现上述相应的实施例方法中的全部或部分流程，也可以通过计算机程序来指令相关的硬件来完成，所述的计算机程序可存储于一计算机可读存储介质中，该计算机程序在被处理器执行时，可实现上述各个方法实施例的步骤。其中，所述计算机程序包括计算机程序代码，所述计算机程序代码可以为源代码形式、对象代码形式、可执行文件或某些中间形式等。所述计算机可读介质可以包括：能够携带所述计算机程序代码的任何实体或装置、记录介质、U盘、移动硬盘、磁碟、光盘、计算机存储器、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、电载波信号、电信信号以及软件分发介质等。需要说明的是，所述计算机可读介质包含的内容可以根据司法管辖区内立法和专利实践的要求进行适当的增减，例如在某些司法管辖区，根据立法和专利实践，计算机可读介质不包括电载波信号和电信信号。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统，装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，装置 和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
以上所述，以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (10)

  1. 一种确定预测窗口期的方法，其特征在于，包括：
    获取固态硬盘的读写带宽及缓存容量；
    根据所述读写带宽及所述缓存容量，计算对所述缓存容量完成一次全速读写的第一周期；
    获取固态硬盘处理器的I/O吞吐量；
    根据所述第一周期及所述I/O吞吐量确定所述预测窗口期。
  2. 根据权利要求1所述的方法，其特征在于，所述根据所述第一周期及所述I/O吞吐量确定所述预测窗口期，包括：
    根据所述I/O吞吐量，计算所述固态硬盘处理器在所述第一周期内处理的第一数据量；
    判断所述第一数据量是否大于所述缓存容量；
    若所述第一数据量大于所述缓存容量，则确定所述第一周期为所述预测窗口期。
  3. 根据权利要求2所述的方法，其特征在于，所述方法还包括：
    若所述第一数据量不大于所述缓存容量，则根据所述I/O吞吐量及所述缓存容量，计算对所述缓存容量完成一次全速读写的第二周期；
    确定所述第二周期为所述预测窗口期。
  4. 根据权利要求3所述的方法，其特征在于，所述方法还包括：
    获取所述固态硬盘最小擦除单元的存储容量；
    根据所述读写带宽及所述最小擦除单元的存储容量，计算对所述最小擦除单元完成一次全速读写的第三周期；
    根据所述第三周期及所述预测窗口期，确定所述预测窗口期的滑动步数。
  5. 根据权利要求4所述的方法，其特征在于，所述根据所述第三周期及所述预测窗口期，确定所述预测窗口期的滑动步数，包括：
    若所述预测窗口期为所述第一周期时，则根据所述第三周期和所述第一周期，确定所述预测窗口期的滑动步数；
    若所述预测窗口期为所述第二周期时，则根据所述第三周期和所述第 二周期，确定所述预测窗口期的滑动步数。
  6. 根据权利要求1至5中任一项所述的方法，其特征在于，所述方法还包括：
    根据所述预测窗口期及所述滑动步数，使得固态硬盘处理器对未来第一时间段的I/O信息进行预测。
  7. 一种确定预测窗口期的装置，其特征在于，包括：
    第一获取单元，用于获取固态硬盘的读写带宽及缓存容量；
    计算单元，用于根据所述读写带宽及所述缓存容量，计算对所述缓存容量完成一次全速读写的第一周期；
    第二获取单元，用于获取固态硬盘处理器的I/O吞吐量；
    确定单元，用于根据所述第一周期及所述I/O吞吐量确定所述预测窗口期。
  8. 一种固态硬盘，其特征在于，所述固态硬盘包括如权利要求7所述的确定预测窗口期的装置，或调用如权利要求7所述的确定预测窗口期的装置，以实现对未来第一时间段I/O信息的预测。
  9. 一种计算机装置，包括处理器，其特征在于，所述处理器在执行存储于存储器上的计算机程序时，用于实现如权利要求1至7中任一项所述的确定预测窗口期的方法。
  10. 一种计算机可读存储介质，其上存储有计算机程序，其特征在于，所述计算机程序被处理器执行时，用于实现如权利要求1至7中任一项所述的确定预测窗口期的方法。
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