WO2020224240A1 - Goa circuit, display panel and display device - Google Patents

Goa circuit, display panel and display device Download PDF

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Publication number
WO2020224240A1
WO2020224240A1 PCT/CN2019/121003 CN2019121003W WO2020224240A1 WO 2020224240 A1 WO2020224240 A1 WO 2020224240A1 CN 2019121003 W CN2019121003 W CN 2019121003W WO 2020224240 A1 WO2020224240 A1 WO 2020224240A1
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Prior art keywords
film transistor
thin film
pull
node
drain
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PCT/CN2019/121003
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French (fr)
Chinese (zh)
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薛炎
韩佰祥
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2020224240A1 publication Critical patent/WO2020224240A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits

Definitions

  • the invention relates to the field of display, in particular to a liquid crystal display panel and a driving method thereof.
  • the scan lines of display panels are driven by external integrated circuits, which can control the scan lines at all levels.
  • the line scan driver circuit can be integrated on the display panel substrate, which can reduce the number of external ICs, thereby reducing the production cost of the display panel, and can realize the display device Narrow bezel.
  • IGZO Indium Gallium Zinc Oxide
  • the current method to reduce GOA power consumption is to use the DC-AC signal input method.
  • the thin film transistor (TFT) in the pull-up module is the thin film transistor with the largest aspect ratio in the GOA circuit, the dynamic power consumption caused by the parasitic capacitance is relatively large.
  • the DC-AC method can eliminate the dynamic power consumption of the TFT, it will cause the TFT to be subjected to the stress of Vds all the time, making the threshold voltage (Vth) of the TFT prone to forward bias, resulting in output signal distortion serious.
  • the purpose of the present invention is to provide a GOA circuit, a display panel and a display device, which can avoid output signal distortion.
  • the present invention provides a GOA circuit, wherein the GOA circuit includes m cascaded GOA units, and the nth level GOA unit includes:
  • Pull up control module for pulling up the potential of the first node
  • the first pull-up module is used to pull up the potential of the n-th level transmission signal
  • the second pull-up module is used to pull up the potential of the first output terminal, which includes:
  • the pull-up unit includes a pull-up thin film transistor; the gate of the pull-up thin film transistor is connected to the second node, the source of the pull-up thin film transistor is connected to the drain of the fifth thin film transistor, and the The drain of the pull-up thin film transistor is connected to the first output terminal;
  • a voltage stabilizing unit for eliminating the influence of the threshold voltage of the pull-up thin film transistor on the potential of the first output terminal; the voltage stabilizing unit is respectively connected to the pull-up thin film transistor and the first output terminal;
  • a pull-down module for pulling down the potentials of the first node, the second node and the first output terminal
  • the pull-down maintenance module is used to maintain the potential of the first node when the first node is at a low potential, where m ⁇ n ⁇ 1.
  • the present invention provides a display panel including the GOA circuit described above.
  • the present invention provides a display device including the above-mentioned display panel.
  • the potential of the first output terminal is independent of the threshold voltage of the pull-up thin film transistor, and the deviation of the threshold voltage is prevented from affecting the output
  • the signal affects, so as to avoid distortion of the output signal.
  • Figure 1 is a schematic diagram of the structure of an existing GOA circuit
  • Figure 2 is a waveform diagram of the output signal of the existing GOA circuit
  • FIG. 3 is a schematic diagram of the structure of the GOA circuit of the present invention.
  • Fig. 6 is a waveform comparison diagram between M point and the first output terminal of the present invention.
  • the existing GOA circuit includes m cascaded GOA units, and the n-th level GOA unit includes: a pull-up control module 100, a first pull-up module 200, a second pull-up module 300', a pull-down module 400.
  • the pull-down maintenance module 500 further includes a storage capacitor C. Where m ⁇ n ⁇ 1.
  • the pull-up control module 100 is used to pull up the potential of the first node Q; that is, to charge the Q point.
  • the first pull-up module 200 is used to pull up the potential of the n-th stage transmission signal Cout(n), that is, to raise the potential of the n-th stage transmission signal Cout(n), and the second pull-up module 300' is used for When the potential of the first output terminal is pulled up, even if the potential of the output signal Out(n) rises, the first output terminal is connected to the scan line.
  • the function of the pull-down module 400 is to pull down the potential of the first node Q point, the second node M point and the first output terminal, that is, pull down the potential of the M point and the output signal Out(n).
  • the pull-down sustaining module 500 is used to maintain the potential of the Q point when the potential of the Q point is at a low potential, where the potential of the Q point and the QB point are opposite.
  • the storage capacitor C is used to store the potential input by the pull-up control module 100 in the storage capacitor.
  • the disadvantage of the traditional GOA circuit is that the thin film transistor T21 is affected by the DC stress of Vds, and the Vth is prone to forward bias, which will cause serious distortion of the output signal.
  • the Vth of T21 does not shift, Out(n)
  • the high level of the signal is 18V (the highest level), as shown in the waveform 101
  • the Vth of T21 is positively biased by 10V
  • the high level of the Out(n) signal is 8V (the highest level), as shown in the waveform 102, That is, the level of the Out(n) signal drops, and the visible signal is distorted.
  • the GOA circuit of the present invention includes m cascaded GOA units, and the n-th level GOA unit includes: a pull-up control module 100, a first pull-up module 200, a second pull-up module 300, and a pull-down module 400 , Pull-down maintenance module 500 and storage capacitor C1.
  • the second pull-up module 300 is used to pull up the potential of the first output terminal.
  • the second pull-up module 300 includes: a pull-up unit 31 and a voltage stabilizing unit; the pull-up unit 31 includes a pull-up thin film transistor T21; the pull-up thin film transistor The gate of T21 is connected to the second node M, the source of the pull-up thin film transistor T21 is connected to the drain of the fifth thin film transistor T65, and the drain of the pull-up thin film transistor T21 is connected to the The first output terminal is connected.
  • the voltage stabilizing unit is used to eliminate the influence of the threshold voltage of the pull-up thin film transistor T21 on the potential of the first output terminal.
  • the voltage stabilizing unit is respectively connected to the pull-up thin film transistor and the first output terminal.
  • the voltage stabilizing unit includes a first thin film transistor T61, a second thin film transistor T62, a third thin film transistor T63, a fourth thin film transistor T64, and a fifth thin film transistor T65.
  • the gate of the first thin film transistor T61 is connected to the n-1th level transmission signal Cout(n-1); the drain of the first thin film transistor T61 is connected to the second node M;
  • the gate of the second thin film transistor T62 is connected to the n-2th level transmission signal Cout(n-2), the source of the second thin film transistor T62 is connected to the high potential signal VDD, and the second thin film transistor The drain of T62 is connected to the second node M;
  • the gate of the third thin film transistor T63 is connected to the n-2th level transmission signal Cout(n-2), and the drain of the third thin film transistor T63 is connected to the second node M through the first capacitor C3 , The source of the third thin film transistor T63 is connected to the low potential signal VGL.
  • the gate of the fourth thin film transistor T64 is connected to the n-1th level transmission signal Cout(n-1), the drain of the fourth thin film transistor T64 and the first output terminal (for outputting Out(n) Signal) connection, the source of the fourth thin film transistor T64 is connected to the low potential signal VGL.
  • the gate of the fifth thin film transistor T65 is connected to the high potential signal VDD, and the source of the fifth thin film transistor T65 is connected to the n-1th stage reverse signal QB(n-1); the fifth thin film transistor The drain of T65 is connected to the source of the first thin film transistor T61.
  • the voltage stabilizing unit further includes a second capacitor C2, one end of the second capacitor C2 is connected to the drain of the second thin film transistor T62, and the other end of the second capacitor C2 is connected to the second output terminal, The second output terminal is used to output a Cout(n) signal.
  • the pull-down module 400 further includes a seventh thin film transistor T51, an eighth thin film transistor T52, a ninth thin film transistor T53, and a tenth thin film transistor T54;
  • the gate of the seventh thin film transistor T51, the gate of the eighth thin film transistor T52, the gate of the ninth thin film transistor T53, and the gate of the tenth thin film transistor T54 are all connected to the n+1th stage Transmission signal Cout(n+1), the source of the seventh thin film transistor T51, the source of the eighth thin film transistor T52, the source of the ninth thin film transistor T53, and the source of the tenth thin film transistor T54 Both are connected to the low potential signal VGL.
  • the drain of the seventh thin film transistor T51 is connected to the first output terminal, the drain of the eighth thin film transistor T52 is electrically connected to the second node M, and the drain of the ninth thin film transistor T53 is connected to the second node M.
  • the output terminal is connected, and the drain of the tenth thin film transistor T54 is connected to the first node Q point.
  • the first pull-up module 200 includes an eleventh thin film transistor T22, the gate of the eleventh thin film transistor T22 is connected to the first node Q, and the source of the eleventh thin film transistor T22 is connected to the second Clock signal CK2; the drain of the eleventh thin film transistor T22 is connected to the second output terminal.
  • the second output terminal is used to output a Cout(n) signal.
  • the pull-down sustain module 500 includes a twelfth thin film transistor T31 and a thirteenth thin film transistor T32.
  • the gate and source of the twelfth thin film transistor T31 are both connected to a high-level signal VDD, and the drain of the twelfth thin film transistor T31 and the drain of the thirteenth thin film transistor T32 are both connected to the third
  • the node (used to output the nth stage reverse signal QR(n)) is connected, the gate of the thirteenth thin film transistor T32 is connected to the first node Q, and the source of the thirteenth thin film transistor T32 is connected to Low level signal VGL.
  • the pull-down maintenance module 500 further includes a fourteenth thin film transistor T4, the gate of the fourteenth thin film transistor T4 is connected to the third node, and the source of the fourteenth thin film transistor T4 is connected to a low level Signal VGL, the drain of the fourteenth thin film transistor T4 is connected to the first node Q point.
  • the pull-up control module 100 includes a fifteenth thin film transistor T1, the gate of the fifteenth thin film transistor T1 is connected to the first clock signal CK1, and the source of the fifteenth thin film transistor T1 is connected to the n-th The first-level transmission signal Cout(n-1), the drain of the fifteenth thin film transistor T1 is connected to the first node Q point.
  • One end of the storage capacitor C1 is connected to the first node Q, and the other end of the storage capacitor C1 is connected to the second output terminal.
  • Q(n) is the signal of the nth level Q point
  • Q(n-1) is the signal of the n-1th level Q point
  • Cout(n-1), Cout(n-2) The maximum voltage of Cout(n+2), CK1, CK2, CK3, CK4 is 20V, the minimum voltage is -10V, VDD is for example 20V, and VGL is for example -10v.
  • CK1 and CK2 are a set of clock signals
  • Cout(n-2) is the Cout(n) signal connected to the previous two stages
  • Cout(n-1) is the Cout(n) signal connected to the previous stage
  • Cout(n+1) Connect the Cout(n) output signal of the next stage, where Cout(n-2) and Cout(n-1) of the GOA circuit of the first stage of the GOA circuit are connected to the STV1 and STV2 signals respectively.
  • the STV signal is the start of the GOA circuit
  • the signals, STV1 and STV2 correspond to the left STV and the right STV respectively.
  • the GOA circuit circulates with 2 basic units as the minimum repeating unit.
  • the nth level GOA unit and the n+2 level GOA unit can jointly form a GOA repeating unit.
  • the display panel can also use the 8CK architecture, and the GOA circuit circulates with 4 basic units as the minimum repeating unit.
  • QB(n-1) is the n-1 level reverse signal, that is, the signal of the QB point of the n-1 level GOA unit
  • M(n) is the M point of the nth level GOA unit signal.
  • Period t1 Cout(n-1), CK1, and CK2 are all low potentials, and point Q is low, that is, Q(n) is low, so T22 and T32 are turned off.
  • QB(n) is high and T4 is open.
  • CK2 is also low, the level transfer signal Cout(n) is low and Cout(n-2) is high, making T62 open and the potential at point M reset to 20V, and T63 is turned on at the same time, pulling down the potential at point M, that is, M(n) is a low potential, T21 is turned on, and QB(n-1) is a low potential, and T65 is turned off.
  • Cout(n-2) is high, T63 is turned on, and the output signal Out(n) is low.
  • Time period t2 Cout(n-1) and CK1 are high, T1 is open, Q(n) is raised to high, T22 and T32 are open, QB(n) is pulled down to low, making T4 closed. Since CK2 is low potential, the level transmission signal Cout(n) is low potential, Cout(n-1) is high potential, T61 is open, point M is connected to point N, T21 forms a diode connection, T64 is open, Out(n) The low potential VGL is output, and the potential at point M is VGL+Vth.
  • Phase t3 CK1 and Cout(n-1) fall to low potential, T1 is closed, and CK2 rises to high potential. Due to the existence of storage capacitor C1, the potential of point Q is coupled to a higher potential, and T22 is turned on.
  • the level-by-level transmission signal Cout(n) output potential rises from VGL to VGH. Therefore, the potential increase value of Cout(n) is (VGH-VGL). At this time, the n-th stage transmission signal Cout(n) is high.
  • V1 (VGH-VGL)+(VGL+Vth)+ ⁇ V;
  • V2 has nothing to do with Vth, that is, the potential of the first output terminal has nothing to do with the threshold voltage of T21.
  • point M that is, M(n) is high, so T21 is turned on and Cout(n-1) is low.
  • T61 is closed, QB(n-1) is high, and T65 is open, therefore, the output signal Out(n) is high
  • 201 represents the waveform diagram at point M when the potential is negatively biased by 10V
  • 202 represents the waveform diagram at point M when the potential is not biased
  • 203 represents the waveform diagram at point M when the potential is positively biased by 10V
  • 301 represents the waveform of Out(n) when the potential is negatively biased by 10V
  • 302 represents the waveform of Out(n) when the potential is not biased
  • 303 represents the waveform of Out(n) when the potential is positively biased by 10V.
  • the present invention also provides a display panel, which includes any of the aforementioned GOA circuits.
  • the present invention also provides a display device, which includes any of the above-mentioned display panels.
  • the potential of the first output terminal is independent of the threshold voltage of the pull-up thin film transistor, and the deviation of the threshold voltage is prevented from affecting the output
  • the signal affects, so as to avoid distortion of the output signal.

Abstract

A GOA circuit, a display panel and a display device. The GOA circuit comprises m cascaded GOA units, wherein an Nth stage GOA unit comprises: a pull-up control module (100) for pulling up the potential of a first node (Q); a first pull-up module (200) for pulling up the potential of an nth stage stage-transfer signal (Cout(n)); a second pull-up module (300) for pulling up the potential of a first output end (Out(n)), the second pull-up module comprising: a pull-up unit (31) comprising a pull-up thin-film transistor (T21), and a voltage stabilizing unit for eliminating the influence of the threshold voltage of the pull-up thin-film transistor (T21) on the potential of the first output end (Out(n)), wherein the voltage stabilizing unit is connected to the pull-up thin-film transistor (T21) and the first output end (Out(n)) respectively; a pull-down module (400) for pulling down the potential of the first node (Q), a second node (M) and the first output end (Out(n)); and a pull-down holding module (500) for holding the potential of the first node (Q) when the first node (Q) is at a low potential. According to the GOA circuit, the display panel and the display device, the distortion of an output signal can be avoided.

Description

一种GOA电路、显示面板及显示装置A GOA circuit, display panel and display device 技术领域Technical field
本发明涉及显示领域，特别是涉及一种液晶显示面板及其驱动方法。The invention relates to the field of display, in particular to a liquid crystal display panel and a driving method thereof.
背景技术Background technique
目前显示面板(比如有源矩阵有机发光二极体面板(AMOLED，Active-matrix organic light-emitting diode)的扫描线的驱动是由外接集成电路来实现的，外接集成电路可以控制各级行扫描线的逐级开启，而采用GOA(Gate Driver on Array)方法，可以将行扫描驱动电路集成在显示面板基板上，能够减少外接IC的数量，从而降低了显示面板的生产成本，并且能够实现显示装置的窄边框化。At present, the scan lines of display panels (such as active-matrix organic light-emitting diodes (AMOLED)) are driven by external integrated circuits, which can control the scan lines at all levels. With the GOA (Gate Driver on Array) method, the line scan driver circuit can be integrated on the display panel substrate, which can reduce the number of external ICs, thereby reducing the production cost of the display panel, and can realize the display device Narrow bezel.
IGZO(铟镓锌氧化物)的迁移率较高、器件稳定性较好，因此广泛地应用于GOA电路中。由于GOA电路的宽度较窄(mm级)，散热困难，如果GOA电路的功耗较高，GOA电路的发热会特别严重，会影响到电路中TFT的电性，甚至造成电路烧毁，因此低功耗的GOA电路成为研究的热点。IGZO (Indium Gallium Zinc Oxide) has high mobility and good device stability, so it is widely used in GOA circuits. Due to the narrow width of the GOA circuit (mm level), it is difficult to dissipate heat. If the power consumption of the GOA circuit is high, the heat of the GOA circuit will be particularly serious, which will affect the electrical properties of the TFT in the circuit, and even cause the circuit to burn out, so low power The consumption of GOA circuits has become a research focus.
技术问题technical problem
目前降低GOA功耗的方法是采用DC-AC信号输入的方法，由于上拉模块中的薄膜晶体管(TFT)是GOA电路中宽长比最大的薄膜晶体 管，由寄生电容造成的动态功耗较大，虽然DC-AC的方式能够消除该TFT的动态功耗，然而会导致该TFT一直受Vds的应力(stress)作用，使得该TFT的阈值电压(Vth)易发生正偏，从而导致输出信号失真严重。The current method to reduce GOA power consumption is to use the DC-AC signal input method. Because the thin film transistor (TFT) in the pull-up module is the thin film transistor with the largest aspect ratio in the GOA circuit, the dynamic power consumption caused by the parasitic capacitance is relatively large. Although the DC-AC method can eliminate the dynamic power consumption of the TFT, it will cause the TFT to be subjected to the stress of Vds all the time, making the threshold voltage (Vth) of the TFT prone to forward bias, resulting in output signal distortion serious.
因此，有必要提供一种GOA电路、显示面板及显示装置，以解决现有技术所存在的问题。Therefore, it is necessary to provide a GOA circuit, a display panel and a display device to solve the problems existing in the prior art.
技术解决方案Technical solutions
本发明的目的在于提供一种GOA电路、显示面板及显示装置，能够避免输出信号失真。The purpose of the present invention is to provide a GOA circuit, a display panel and a display device, which can avoid output signal distortion.
为解决上述技术问题，本发明提供一种GOA电路，其中GOA电路包括m个级联的GOA单元，第n级GOA单元包括：In order to solve the above technical problems, the present invention provides a GOA circuit, wherein the GOA circuit includes m cascaded GOA units, and the nth level GOA unit includes:
上拉控制模块，用于上拉第一节点的电位；Pull up control module for pulling up the potential of the first node;
第一上拉模块，用于上拉第n级级传信号的电位；The first pull-up module is used to pull up the potential of the n-th level transmission signal;
第二上拉模块，用于上拉第一输出端的电位，其包括：The second pull-up module is used to pull up the potential of the first output terminal, which includes:
上拉单元，包括上拉薄膜晶体管；所述上拉薄膜晶体管的栅极与所述第二节点连接，所述上拉薄膜晶体管的源极与所述第五薄膜晶体管的漏极连接，所述上拉薄膜晶体管的漏极与所述第一输出端连接；The pull-up unit includes a pull-up thin film transistor; the gate of the pull-up thin film transistor is connected to the second node, the source of the pull-up thin film transistor is connected to the drain of the fifth thin film transistor, and the The drain of the pull-up thin film transistor is connected to the first output terminal;
稳压单元，用于消除所述上拉薄膜晶体管的阈值电压对所述第一输出端电位的影响；所述稳压单元分别与所述上拉薄膜晶体管以及所述第一输出端连接；A voltage stabilizing unit for eliminating the influence of the threshold voltage of the pull-up thin film transistor on the potential of the first output terminal; the voltage stabilizing unit is respectively connected to the pull-up thin film transistor and the first output terminal;
下拉模块，用于下拉所述第一节点、第二节点以及所述第一输出 端的电位；A pull-down module for pulling down the potentials of the first node, the second node and the first output terminal;
下拉维持模块，用于当所述第一节点为低电位时，维持第一节点的电位，其中m≥n≥1。The pull-down maintenance module is used to maintain the potential of the first node when the first node is at a low potential, where m≥n≥1.
本发明提供一种显示面板，其包括上述GOA电路。The present invention provides a display panel including the GOA circuit described above.
本发明提供一种显示装置，其包括上述显示面板。The present invention provides a display device including the above-mentioned display panel.
有益效果Beneficial effect
本发明的GOA电路、显示面板及显示装置，通过在现有的上拉模块中增加稳压单元，使得第一输出端的电位与上拉薄膜晶体管的阈值电压无关，避免阈值电压的偏移对输出信号造成影响，从而避免输出信号出现失真。In the GOA circuit, display panel and display device of the present invention, by adding a voltage stabilizing unit to the existing pull-up module, the potential of the first output terminal is independent of the threshold voltage of the pull-up thin film transistor, and the deviation of the threshold voltage is prevented from affecting the output The signal affects, so as to avoid distortion of the output signal.
附图说明Description of the drawings
图1为现有GOA电路的结构示意图；Figure 1 is a schematic diagram of the structure of an existing GOA circuit;
图2为现有GOA电路的输出信号的波形图；Figure 2 is a waveform diagram of the output signal of the existing GOA circuit;
图3为本发明GOA电路的结构示意图；Figure 3 is a schematic diagram of the structure of the GOA circuit of the present invention;
图4为本发明GOA电路输入信号的时序图；4 is a timing diagram of the input signal of the GOA circuit of the present invention;
图5为本发明GOA电路的输出信号的时序图；5 is a timing diagram of the output signal of the GOA circuit of the present invention;
图6为本发明M点和第一输出端的波形对比图。Fig. 6 is a waveform comparison diagram between M point and the first output terminal of the present invention.
本发明的最佳实施方式The best mode of the invention
以下各实施例的说明是参考附加的图式，用以例示本发明可用以 实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。The description of the following embodiments refers to the attached drawings to illustrate specific embodiments in which the present invention can be implemented. The directional terms mentioned in the present invention, such as "up", "down", "front", "rear", "left", "right", "in", "out", "side", etc., are for reference only The direction of the additional schema. Therefore, the directional terms used are used to describe and understand the present invention, rather than to limit the present invention. In the figure, units with similar structures are indicated by the same reference numerals.
如图1所示，现有的GOA电路包括m个级联的GOA单元，第n级GOA单元包括：上拉控制模块100、第一上拉模块200、第二上拉模块300’、下拉模块400、下拉维持模块500，此外还包括存储电容C。其中m≥n≥1。As shown in FIG. 1, the existing GOA circuit includes m cascaded GOA units, and the n-th level GOA unit includes: a pull-up control module 100, a first pull-up module 200, a second pull-up module 300', a pull-down module 400. The pull-down maintenance module 500 further includes a storage capacitor C. Where m≥n≥1.
上拉控制模块100用于上拉第一节点Q的电位；也即给Q点充电。第一上拉模块200用于将第n级级传信号Cout(n)的电位拉高，也即拉高第n级级传信号Cout(n)的电位，第二上拉模块300’用于上拉第一输出端的电位，也即使输出信号Out(n)的电位抬高，第一输出端与扫描线连接。下拉模块400作用是下拉第一节点Q点、第二节点M点以及第一输出端的电位，也即将M点及输出信号Out(n)的电位拉低。下拉维持模块500用于当Q点的电位为低电位时，维持Q点的电位，其中Q点与QB点的电位相反。存储电容C用于将上拉控制模块100输入的电位存储在存储电容中。The pull-up control module 100 is used to pull up the potential of the first node Q; that is, to charge the Q point. The first pull-up module 200 is used to pull up the potential of the n-th stage transmission signal Cout(n), that is, to raise the potential of the n-th stage transmission signal Cout(n), and the second pull-up module 300' is used for When the potential of the first output terminal is pulled up, even if the potential of the output signal Out(n) rises, the first output terminal is connected to the scan line. The function of the pull-down module 400 is to pull down the potential of the first node Q point, the second node M point and the first output terminal, that is, pull down the potential of the M point and the output signal Out(n). The pull-down sustaining module 500 is used to maintain the potential of the Q point when the potential of the Q point is at a low potential, where the potential of the Q point and the QB point are opposite. The storage capacitor C is used to store the potential input by the pull-up control module 100 in the storage capacitor.
传统GOA电路的缺点是薄膜晶体管T21受Vds的直流应力的作用，Vth易发生正偏，这会导致输出信号失真严重，如图2所示，如果T21的Vth未发生偏移，Out(n)信号的高电平为18V(最高电平)，如波形101所示，如果T21的Vth正偏10V，Out(n)信号的高电平为8V(最高电平)，如波形102所示，也即Out(n)信号的电平下降，可见 信号出现失真。The disadvantage of the traditional GOA circuit is that the thin film transistor T21 is affected by the DC stress of Vds, and the Vth is prone to forward bias, which will cause serious distortion of the output signal. As shown in Figure 2, if the Vth of T21 does not shift, Out(n) The high level of the signal is 18V (the highest level), as shown in the waveform 101, if the Vth of T21 is positively biased by 10V, the high level of the Out(n) signal is 8V (the highest level), as shown in the waveform 102, That is, the level of the Out(n) signal drops, and the visible signal is distorted.
如图3所示，本发明的GOA电路包括m个级联的GOA单元，第n级GOA单元包括：上拉控制模块100、第一上拉模块200、第二上拉模块300、下拉模块400、下拉维持模块500以及存储电容C1。As shown in FIG. 3, the GOA circuit of the present invention includes m cascaded GOA units, and the n-th level GOA unit includes: a pull-up control module 100, a first pull-up module 200, a second pull-up module 300, and a pull-down module 400 , Pull-down maintenance module 500 and storage capacitor C1.
第二上拉模块300用于上拉第一输出端的电位，第二上拉模块300包括：上拉单元31和稳压单元；上拉单元31包括上拉薄膜晶体管T21；所述上拉薄膜晶体管T21的栅极与所述第二节点M点连接，所述上拉薄膜晶体管T21的源极与所述第五薄膜晶体管T65的漏极连接，所述上拉薄膜晶体管T21的漏极与所述第一输出端连接。The second pull-up module 300 is used to pull up the potential of the first output terminal. The second pull-up module 300 includes: a pull-up unit 31 and a voltage stabilizing unit; the pull-up unit 31 includes a pull-up thin film transistor T21; the pull-up thin film transistor The gate of T21 is connected to the second node M, the source of the pull-up thin film transistor T21 is connected to the drain of the fifth thin film transistor T65, and the drain of the pull-up thin film transistor T21 is connected to the The first output terminal is connected.
稳压单元用于消除所述上拉薄膜晶体管T21的阈值电压对所述第一输出端电位的影响。所述稳压单元分别与所述上拉薄膜晶体管以及所述第一输出端连接。The voltage stabilizing unit is used to eliminate the influence of the threshold voltage of the pull-up thin film transistor T21 on the potential of the first output terminal. The voltage stabilizing unit is respectively connected to the pull-up thin film transistor and the first output terminal.
其中所述稳压单元包括第一薄膜晶体管T61、第二薄膜晶体管T62、第三薄膜晶体管T63、第四薄膜晶体管T64以及第五薄膜晶体管T65。The voltage stabilizing unit includes a first thin film transistor T61, a second thin film transistor T62, a third thin film transistor T63, a fourth thin film transistor T64, and a fifth thin film transistor T65.
所述第一薄膜晶体管T61的栅极接入第n-1级级传信号Cout(n-1)；所述第一薄膜晶体管T61的漏极与所述第二节点M连接；The gate of the first thin film transistor T61 is connected to the n-1th level transmission signal Cout(n-1); the drain of the first thin film transistor T61 is connected to the second node M;
所述第二薄膜晶体管T62的栅极接入第n-2级级传信号Cout(n-2)，所述第二薄膜晶体管T62的源极接入高电位信号VDD，所述第二薄膜晶体管T62的漏极与所述第二节点M连接；The gate of the second thin film transistor T62 is connected to the n-2th level transmission signal Cout(n-2), the source of the second thin film transistor T62 is connected to the high potential signal VDD, and the second thin film transistor The drain of T62 is connected to the second node M;
所述第三薄膜晶体管T63的栅极接入第n-2级级传信号Cout(n-2)，所述第三薄膜晶体管T63的漏极通过第一电容C3与所述 第二节点M连接，所述第三薄膜晶体管T63的源极接入低电位信号VGL。The gate of the third thin film transistor T63 is connected to the n-2th level transmission signal Cout(n-2), and the drain of the third thin film transistor T63 is connected to the second node M through the first capacitor C3 , The source of the third thin film transistor T63 is connected to the low potential signal VGL.
所述第四薄膜晶体管T64的栅极接入第n-1级级传信号Cout(n-1)，所述第四薄膜晶体管T64的漏极与第一输出端(用于输出Out(n)信号)连接，所述第四薄膜晶体管T64的源极接入低电位信号VGL。The gate of the fourth thin film transistor T64 is connected to the n-1th level transmission signal Cout(n-1), the drain of the fourth thin film transistor T64 and the first output terminal (for outputting Out(n) Signal) connection, the source of the fourth thin film transistor T64 is connected to the low potential signal VGL.
所述第五薄膜晶体管T65的栅极接入高电位信号VDD，所述第五薄膜晶体管T65的源极接入第n-1级反向信号QB(n-1)；所述第五薄膜晶体管T65的漏极与所述第一薄膜晶体管T61的源极连接。The gate of the fifth thin film transistor T65 is connected to the high potential signal VDD, and the source of the fifth thin film transistor T65 is connected to the n-1th stage reverse signal QB(n-1); the fifth thin film transistor The drain of T65 is connected to the source of the first thin film transistor T61.
其中所述稳压单元还包括第二电容C2，所述第二电容C2的一端与所述第二薄膜晶体管T62的漏极连接，所述第二电容C2的另一端与第二输出端连接，其中所述第二输出端用于输出Cout(n)信号。The voltage stabilizing unit further includes a second capacitor C2, one end of the second capacitor C2 is connected to the drain of the second thin film transistor T62, and the other end of the second capacitor C2 is connected to the second output terminal, The second output terminal is used to output a Cout(n) signal.
所述下拉模块400还包括第七薄膜晶体管T51、第八薄膜晶体管T52、第九薄膜晶体管T53以及第十薄膜晶体管T54；The pull-down module 400 further includes a seventh thin film transistor T51, an eighth thin film transistor T52, a ninth thin film transistor T53, and a tenth thin film transistor T54;
所述第七薄膜晶体管T51的栅极、所述第八薄膜晶体管T52的栅极、所述第九薄膜晶体管T53的栅极以及第十薄膜晶体管T54的栅极均接入第n+1级级传信号Cout(n+1)，所述第七薄膜晶体管T51的源极、所述第八薄膜晶体管T52的源极、所述第九薄膜晶体管T53的源极以及第十薄膜晶体管T54的源极均接入低电位信号VGL。The gate of the seventh thin film transistor T51, the gate of the eighth thin film transistor T52, the gate of the ninth thin film transistor T53, and the gate of the tenth thin film transistor T54 are all connected to the n+1th stage Transmission signal Cout(n+1), the source of the seventh thin film transistor T51, the source of the eighth thin film transistor T52, the source of the ninth thin film transistor T53, and the source of the tenth thin film transistor T54 Both are connected to the low potential signal VGL.
所述第七薄膜晶体管T51的漏极与第一输出端连接、所述第八薄膜晶体管T52的漏极与第二节点M点电性连接，所述第九薄膜晶体管T53的漏极与第二输出端连接，所述第十薄膜晶体管T54的漏极与第 一节点Q点连接。The drain of the seventh thin film transistor T51 is connected to the first output terminal, the drain of the eighth thin film transistor T52 is electrically connected to the second node M, and the drain of the ninth thin film transistor T53 is connected to the second node M. The output terminal is connected, and the drain of the tenth thin film transistor T54 is connected to the first node Q point.
所述第一上拉模块200包括第十一薄膜晶体管T22，所述第十一薄膜晶体管T22的栅极与第一节点Q点连接，所述第十一薄膜晶体管T22的源极接入第二时钟信号CK2；所述第十一薄膜晶体管T22的漏极与第二输出端连接。所述第二输出端用于输出Cout(n)信号。The first pull-up module 200 includes an eleventh thin film transistor T22, the gate of the eleventh thin film transistor T22 is connected to the first node Q, and the source of the eleventh thin film transistor T22 is connected to the second Clock signal CK2; the drain of the eleventh thin film transistor T22 is connected to the second output terminal. The second output terminal is used to output a Cout(n) signal.
所述下拉维持模块500包括第十二薄膜晶体管T31和第十三薄膜晶体管T32。The pull-down sustain module 500 includes a twelfth thin film transistor T31 and a thirteenth thin film transistor T32.
所述第十二薄膜晶体管T31的栅极和源极均接入高电平信号VDD，所述第十二薄膜晶体管T31的漏极与所述第十三薄膜晶体管T32的漏极均与第三节点(用于输出第n级反向信号QR(n))连接，所述第十三薄膜晶体管T32的栅极与第一节点Q点连接，所述第十三薄膜晶体管T32的源极接入低电平信号VGL。The gate and source of the twelfth thin film transistor T31 are both connected to a high-level signal VDD, and the drain of the twelfth thin film transistor T31 and the drain of the thirteenth thin film transistor T32 are both connected to the third The node (used to output the nth stage reverse signal QR(n)) is connected, the gate of the thirteenth thin film transistor T32 is connected to the first node Q, and the source of the thirteenth thin film transistor T32 is connected to Low level signal VGL.
所述下拉维持模块500还包括第十四薄膜晶体管T4、所述第十四薄膜晶体管T4的栅极与所述第三节点连接，所述第十四薄膜晶体管T4的源极接入低电平信号VGL，所述第十四薄膜晶体管T4的漏极与所述第一节点Q点连接。The pull-down maintenance module 500 further includes a fourteenth thin film transistor T4, the gate of the fourteenth thin film transistor T4 is connected to the third node, and the source of the fourteenth thin film transistor T4 is connected to a low level Signal VGL, the drain of the fourteenth thin film transistor T4 is connected to the first node Q point.
所述上拉控制模块100包括第十五薄膜晶体管T1，所述第十五薄膜晶体管T1的栅极接入第一时钟信号CK1，所述第十五薄膜晶体管T1的源极接入第n-1级级传信号Cout(n-1)，所述第十五薄膜晶体管T1的漏极与第一节点Q点连接。The pull-up control module 100 includes a fifteenth thin film transistor T1, the gate of the fifteenth thin film transistor T1 is connected to the first clock signal CK1, and the source of the fifteenth thin film transistor T1 is connected to the n-th The first-level transmission signal Cout(n-1), the drain of the fifteenth thin film transistor T1 is connected to the first node Q point.
所述存储电容C1的一端与所述第一节点Q点连接，所述存储电容C1的另一端与所述第二输出端连接。One end of the storage capacitor C1 is connected to the first node Q, and the other end of the storage capacitor C1 is connected to the second output terminal.
如图4所示，Q(n)为第n级Q点的信号，Q(n-1)为第n-1级Q点的信号，Cout(n-1)、Cout(n-2)、Cout(n+2)、CK1、CK2、CK3、CK4的最大电压为20V，最小电压为-10V，VDD比如为20V，VGL比如为-10v。As shown in Figure 4, Q(n) is the signal of the nth level Q point, Q(n-1) is the signal of the n-1th level Q point, Cout(n-1), Cout(n-2), The maximum voltage of Cout(n+2), CK1, CK2, CK3, CK4 is 20V, the minimum voltage is -10V, VDD is for example 20V, and VGL is for example -10v.
CK1、CK2为一组时钟讯号，Cout(n-2)为连接前两级的Cout(n)信号，Cout(n-1)为连接前一级的Cout(n)信号，Cout(n+1)连接下一级的Cout(n)输出信号，其中GOA电路第一级GOA电路的Cout(n-2)与Cout(n-1)分别与STV1与STV2信号相连，STV信号是GOA电路的启动信号，STV1和STV2分别对应左侧STV和右侧STV。CK1 and CK2 are a set of clock signals, Cout(n-2) is the Cout(n) signal connected to the previous two stages, Cout(n-1) is the Cout(n) signal connected to the previous stage, Cout(n+1) ) Connect the Cout(n) output signal of the next stage, where Cout(n-2) and Cout(n-1) of the GOA circuit of the first stage of the GOA circuit are connected to the STV1 and STV2 signals respectively. The STV signal is the start of the GOA circuit The signals, STV1 and STV2 correspond to the left STV and the right STV respectively.
当显示面板为4CK架构时，GOA电路以2个基本单元为最小重复单元进行循环。第n级GOA单元和第n+2级GOA单元可以共同构成一个GOA重复单元。GOA电路中共有4个时钟信号CK：第1时钟信号CK1至第4条时钟信号CK4，第n级GOA单元对应第1时钟信号CK1时和第2时钟信号CK2，当第n+2级GOA单元对应第3时钟信号CK3和第4时钟信号CK4。当然显示面板也可使用8CK架构，GOA电路以4个基本单元为最小重复单元进行循环。When the display panel adopts the 4CK architecture, the GOA circuit circulates with 2 basic units as the minimum repeating unit. The nth level GOA unit and the n+2 level GOA unit can jointly form a GOA repeating unit. There are four clock signals CK in the GOA circuit: the first clock signal CK1 to the fourth clock signal CK4, the nth level GOA unit corresponds to the first clock signal CK1 and the second clock signal CK2, when the n+2 level GOA unit Corresponds to the third clock signal CK3 and the fourth clock signal CK4. Of course, the display panel can also use the 8CK architecture, and the GOA circuit circulates with 4 basic units as the minimum repeating unit.
如图5所示，QB(n-1)为第n-1级反向信号，也即第n-1级GOA单元的QB点的信号，M(n)为第n级GOA单元M点的信号。As shown in Figure 5, QB(n-1) is the n-1 level reverse signal, that is, the signal of the QB point of the n-1 level GOA unit, and M(n) is the M point of the nth level GOA unit signal.
t1时段：Cout(n-1)、CK1以及CK2均为低电位，Q点为低电位，也即Q(n)为低电平，因此T22及T32关闭。QB(n)为高电位，T4打开，由于CK2也为低电位，级传信号Cout(n)为低电位，而Cout(n-2)为高电位，使得T62打开，M点电位被复位至20V，同时T63打开，将M点的电位拉低，也即M(n)为低电位，T21打开，且QB(n-1)为低 电位，T65关闭。当Cout(n-2)为高电位，T63打开，此时输出信号Out(n)为低电位。Period t1: Cout(n-1), CK1, and CK2 are all low potentials, and point Q is low, that is, Q(n) is low, so T22 and T32 are turned off. QB(n) is high and T4 is open. Since CK2 is also low, the level transfer signal Cout(n) is low and Cout(n-2) is high, making T62 open and the potential at point M reset to 20V, and T63 is turned on at the same time, pulling down the potential at point M, that is, M(n) is a low potential, T21 is turned on, and QB(n-1) is a low potential, and T65 is turned off. When Cout(n-2) is high, T63 is turned on, and the output signal Out(n) is low.
t2时段：Cout(n-1)及CK1为高电位，T1打开，Q(n)的电位被抬升至高电位，T22及T32打开，QB(n)被拉低至低电位，使得T4关闭。由于CK2为低电位，因此级传信号Cout(n)为低电位，Cout(n-1)为高电位，T61打开，M点与N点连接，T21构成二极管连接，T64打开，Out(n)输出低电位VGL，M点的电位为VGL+Vth。Time period t2: Cout(n-1) and CK1 are high, T1 is open, Q(n) is raised to high, T22 and T32 are open, QB(n) is pulled down to low, making T4 closed. Since CK2 is low potential, the level transmission signal Cout(n) is low potential, Cout(n-1) is high potential, T61 is open, point M is connected to point N, T21 forms a diode connection, T64 is open, Out(n) The low potential VGL is output, and the potential at point M is VGL+Vth.
t3阶段：CK1及Cout(n-1)降为低电位，T1关闭，CK2升为高电位，由于存储电容C1的存在，Q点电位被耦合至更高电位，T22的打开，此时第n级级传信号Cout(n)输出电位由VGL升至VGH。因此，Cout(n)的电位增加值为(VGH-VGL)。此时第n级级传信号Cout(n)为高电位。Phase t3: CK1 and Cout(n-1) fall to low potential, T1 is closed, and CK2 rises to high potential. Due to the existence of storage capacitor C1, the potential of point Q is coupled to a higher potential, and T22 is turned on. The level-by-level transmission signal Cout(n) output potential rises from VGL to VGH. Therefore, the potential increase value of Cout(n) is (VGH-VGL). At this time, the n-th stage transmission signal Cout(n) is high.
由于电容C2的存在，根据电容耦合原理，M点的电位原理上也相应增加(VGH-VGL)，实际由于M点连接了T61及T62，因此会存在一定漏电路径，而且由于C3的存在，也会分担去部分M点的电位，设定漏电以及电容C3导致的电位变化为ΔV。t2阶段M点初始电位为VGL+Vth，t3开始阶段，M点电位实际上被C2耦合至V1，具体如下式：Due to the existence of capacitor C2, according to the principle of capacitive coupling, the potential of point M also increases in principle (VGH-VGL). Actually, because point M is connected to T61 and T62, there will be a certain leakage path, and because of the existence of C3, It will share the potential of part M, and set the leakage and the potential change caused by the capacitor C3 to ΔV. The initial potential at point M in t2 is VGL+Vth. At the beginning of t3, the potential at point M is actually coupled to V1 by C2, as shown in the following formula:
V1＝(VGH-VGL)+(VGL+Vth)+ΔV；V1=(VGH-VGL)+(VGL+Vth)+ΔV;
由于Out(n)的初始电位是VGL，此时T21的漏极的电位V2如下：Since the initial potential of Out(n) is VGL, the potential V2 of the drain of T21 is as follows:
V2＝Vgs-Vth＝(VGH-VGL)+(VGL+Vth)+ΔV-VGL-Vth＝VGH-VGL+ΔV；V2=Vgs-Vth=(VGH-VGL)+(VGL+Vth)+ΔV-VGL-Vth=VGH-VGL+ΔV;
可见，V2值与Vth无关，也即第一输出端的电位与T21的阈值 电压无关，由于此时M点也即M(n)为高电位，因此T21打开，Cout(n-1)为低电位，T61关闭，QB(n-1)为高电位，T65打开，因此，输出信号Out(n)为高电位It can be seen that the value of V2 has nothing to do with Vth, that is, the potential of the first output terminal has nothing to do with the threshold voltage of T21. At this time, point M, that is, M(n) is high, so T21 is turned on and Cout(n-1) is low. , T61 is closed, QB(n-1) is high, and T65 is open, therefore, the output signal Out(n) is high
t4阶段，Cou(n+1)升为高电位，T51、T52、T53、T54均打开，Q点、Cout(n)、M点以及输出信号Out(n)被拉至低电位。At stage t4, Cou(n+1) rises to high potential, T51, T52, T53, and T54 are all turned on, and point Q, Cout(n), point M and output signal Out(n) are pulled to low potential.
如图6所示，201表示电位负偏10V时M点的波形图，202表示电位未偏时M点的波形图，203表示电位正偏10V时M点的波形图；As shown in Figure 6, 201 represents the waveform diagram at point M when the potential is negatively biased by 10V, 202 represents the waveform diagram at point M when the potential is not biased, and 203 represents the waveform diagram at point M when the potential is positively biased by 10V;
301表示电位负偏10V时Out(n)的波形图，302表示电位未偏时Out(n)的波形图，303表示电位正偏10V时Out(n)的波形图，经过对比发现，当T21的Vth正偏10V时，输出信号的幅值从17V降至16V，也即Out(n)只下降了1V，大幅度降低了输出信号的衰减幅度，从而有效地避免了输出信号出现失真。301 represents the waveform of Out(n) when the potential is negatively biased by 10V, 302 represents the waveform of Out(n) when the potential is not biased, and 303 represents the waveform of Out(n) when the potential is positively biased by 10V. After comparison, it is found that when T21 When the Vth is positively biased by 10V, the amplitude of the output signal is reduced from 17V to 16V, that is, Out(n) only drops by 1V, which greatly reduces the attenuation amplitude of the output signal, thereby effectively avoiding distortion of the output signal.
本发明还提供一种显示面板，其包括上述任意一种GOA电路。The present invention also provides a display panel, which includes any of the aforementioned GOA circuits.
本发明还提供一种显示装置，其包括上述任意一种显示面板。The present invention also provides a display device, which includes any of the above-mentioned display panels.
本发明的GOA电路、显示面板及显示装置，通过在现有的上拉模块上增加稳压单元，使得第一输出端的电位与上拉薄膜晶体管的阈值电压无关，避免阈值电压的偏移对输出信号造成影响，从而避免输出信号出现失真。In the GOA circuit, display panel and display device of the present invention, by adding a voltage stabilizing unit to the existing pull-up module, the potential of the first output terminal is independent of the threshold voltage of the pull-up thin film transistor, and the deviation of the threshold voltage is prevented from affecting the output The signal affects, so as to avoid distortion of the output signal.
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示意性实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中，对上述术语的 示意性表述不一定指的是相同的实施例或示例。而且描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples", "specific examples", or "some examples" etc. means to incorporate the implementation The specific features, structures, materials or characteristics described by the examples or examples are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above-mentioned terms does not necessarily refer to the same embodiment or example. Moreover, the described specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.
尽管已经示出和描述了本发明的实施例，本领域的普通技术人员可以理解：在不脱离本发明的原理和宗旨的情况下可以对这些实施例进行多种变化、修改、替换和变型，本发明的范围由权利要求及其等同物限定。Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions and modifications can be made to these embodiments without departing from the principle and purpose of the present invention. The scope of the present invention is defined by the claims and their equivalents.

Claims (10)

  1. 一种显示面板，其中，包括一种GOA电路，其中GOA电路包括m个级联的GOA单元，第n级GOA单元包括：A display panel, including a GOA circuit, wherein the GOA circuit includes m cascaded GOA units, and the n-th stage GOA unit includes:
    上拉控制模块，用于上拉第一节点的电位；Pull up control module for pulling up the potential of the first node;
    第一上拉模块，用于上拉第n级级传信号的电位；The first pull-up module is used to pull up the potential of the n-th level transmission signal;
    第二上拉模块，用于上拉第一输出端的电位，其包括：The second pull-up module is used to pull up the potential of the first output terminal, which includes:
    上拉单元，包括上拉薄膜晶体管；所述上拉薄膜晶体管的栅极与所述第二节点连接，所述上拉薄膜晶体管的源极与所述第五薄膜晶体管的漏极连接，所述上拉薄膜晶体管的漏极与所述第一输出端连接；The pull-up unit includes a pull-up thin film transistor; the gate of the pull-up thin film transistor is connected to the second node, the source of the pull-up thin film transistor is connected to the drain of the fifth thin film transistor, and the The drain of the pull-up thin film transistor is connected to the first output terminal;
    稳压单元，用于消除所述上拉薄膜晶体管的阈值电压对所述第一输出端电位的影响；所述稳压单元分别与所述上拉薄膜晶体管以及所述第一输出端连接；A voltage stabilizing unit for eliminating the influence of the threshold voltage of the pull-up thin film transistor on the potential of the first output terminal; the voltage stabilizing unit is respectively connected to the pull-up thin film transistor and the first output terminal;
    下拉模块，用于下拉所述第一节点、第二节点以及所述第一输出端的电位；A pull-down module for pulling down the potential of the first node, the second node, and the first output terminal;
    下拉维持模块，用于当所述第一节点为低电位时，维持所述第一节点的电位，其中m≥n≥1；The pull-down maintenance module is used to maintain the potential of the first node when the first node is at a low potential, where m≥n≥1;
    所述稳压单元包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管以及第五薄膜晶体管；The voltage stabilizing unit includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, and a fifth thin film transistor;
    所述第一薄膜晶体管的栅极接入第n-1级级传信号；所述第一薄膜晶体管的漏极与所述第二节点连接；The gate of the first thin film transistor is connected to the n-1th stage signal; the drain of the first thin film transistor is connected to the second node;
    所述第二薄膜晶体管的栅极接入第n-2级级传信号，所述第二薄膜晶体管的源极接入高电位信号，所述第二薄膜晶体管的漏极与所述 第二节点连接；The gate of the second thin film transistor is connected to the n-2th stage signal, the source of the second thin film transistor is connected to a high-potential signal, and the drain of the second thin film transistor is connected to the second node connection;
    所述第三薄膜晶体管的栅极接入第n-2级级传信号，所述第三薄膜晶体管的漏极与所述第二节点连接，所述第三薄膜晶体管的源极接入低电位信号；The gate of the third thin film transistor is connected to the n-2th stage signal, the drain of the third thin film transistor is connected to the second node, and the source of the third thin film transistor is connected to a low potential signal;
    所述第四薄膜晶体管的栅极接入第n-1级级传信号，所述第四薄膜晶体管的漏极与所述第一输出端连接，所述第四薄膜晶体管的源极接入所述低电位信号；The gate of the fourth thin film transistor is connected to the n-1th stage signal, the drain of the fourth thin film transistor is connected to the first output terminal, and the source of the fourth thin film transistor is connected to the Said low potential signal;
    所述第五薄膜晶体管的栅极接入所述高电位信号，所述第五薄膜晶体管的源极接入第n-1级反向信号；所述第五薄膜晶体管的漏极与所述第一薄膜晶体管的源极连接；The gate of the fifth thin film transistor is connected to the high potential signal, and the source of the fifth thin film transistor is connected to the n-1th stage reverse signal; the drain of the fifth thin film transistor is connected to the first A source connection of a thin film transistor;
    所述稳压单元还包括第一电容，所述第三薄膜晶体管的漏极通过所述第一电容与所述第二节点连接，所述第三薄膜晶体管的源极接入所述低电位信号。The voltage stabilizing unit further includes a first capacitor, the drain of the third thin film transistor is connected to the second node through the first capacitor, and the source of the third thin film transistor is connected to the low potential signal .
  2. 一种GOA电路，其中，其中GOA电路包括m个级联的GOA单元，第n级GOA单元包括：A GOA circuit, wherein the GOA circuit includes m cascaded GOA units, and the nth level GOA unit includes:
    上拉控制模块，用于上拉第一节点的电位；Pull up control module for pulling up the potential of the first node;
    第一上拉模块，用于上拉第n级级传信号的电位；The first pull-up module is used to pull up the potential of the n-th level transmission signal;
    第二上拉模块，用于上拉第一输出端的电位，其包括：The second pull-up module is used to pull up the potential of the first output terminal, which includes:
    上拉单元，包括上拉薄膜晶体管；所述上拉薄膜晶体管的栅极与所述第二节点连接，所述上拉薄膜晶体管的源极与所述第五薄膜晶体管的漏极连接，所述上拉薄膜晶体管的漏极与所述第一输出端连接；The pull-up unit includes a pull-up thin film transistor; the gate of the pull-up thin film transistor is connected to the second node, the source of the pull-up thin film transistor is connected to the drain of the fifth thin film transistor, and the The drain of the pull-up thin film transistor is connected to the first output terminal;
    稳压单元，用于消除所述上拉薄膜晶体管的阈值电压对所述第一 输出端电位的影响；所述稳压单元分别与所述上拉薄膜晶体管以及所述第一输出端连接；A voltage stabilizing unit for eliminating the influence of the threshold voltage of the pull-up thin film transistor on the potential of the first output terminal; the voltage stabilizing unit is connected to the pull-up thin film transistor and the first output terminal respectively;
    下拉模块，用于下拉所述第一节点、第二节点以及所述第一输出端的电位；A pull-down module for pulling down the potential of the first node, the second node, and the first output terminal;
    下拉维持模块，用于当所述第一节点为低电位时，维持所述第一节点的电位，其中m≥n≥1。The pull-down maintenance module is used to maintain the potential of the first node when the first node is at a low potential, where m≥n≥1.
  3. 根据权利要求2所述的GOA电路，其中，The GOA circuit according to claim 2, wherein:
    所述稳压单元包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管以及第五薄膜晶体管；The voltage stabilizing unit includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, and a fifth thin film transistor;
    所述第一薄膜晶体管的栅极接入第n-1级级传信号；所述第一薄膜晶体管的漏极与所述第二节点连接；The gate of the first thin film transistor is connected to the n-1th stage signal; the drain of the first thin film transistor is connected to the second node;
    所述第二薄膜晶体管的栅极接入第n-2级级传信号，所述第二薄膜晶体管的源极接入高电位信号，所述第二薄膜晶体管的漏极与所述第二节点连接；The gate of the second thin film transistor is connected to the n-2th stage signal, the source of the second thin film transistor is connected to a high-potential signal, and the drain of the second thin film transistor is connected to the second node connection;
    所述第三薄膜晶体管的栅极接入第n-2级级传信号，所述第三薄膜晶体管的漏极与所述第二节点连接，所述第三薄膜晶体管的源极接入低电位信号；The gate of the third thin film transistor is connected to the n-2th stage signal, the drain of the third thin film transistor is connected to the second node, and the source of the third thin film transistor is connected to a low potential signal;
    所述第四薄膜晶体管的栅极接入第n-1级级传信号，所述第四薄膜晶体管的漏极与所述第一输出端连接，所述第四薄膜晶体管的源极接入所述低电位信号；The gate of the fourth thin film transistor is connected to the n-1th stage signal, the drain of the fourth thin film transistor is connected to the first output terminal, and the source of the fourth thin film transistor is connected to the Said low potential signal;
    所述第五薄膜晶体管的栅极接入所述高电位信号，所述第五薄膜晶体管的源极接入第n-1级反向信号；所述第五薄膜晶体管的漏极与 所述第一薄膜晶体管的源极连接。The gate of the fifth thin film transistor is connected to the high potential signal, and the source of the fifth thin film transistor is connected to the n-1th stage reverse signal; the drain of the fifth thin film transistor is connected to the first The source of a thin film transistor is connected.
  4. 根据权利要求3所述的GOA电路，其中，The GOA circuit according to claim 3, wherein:
    所述稳压单元还包括第一电容，所述第三薄膜晶体管的漏极通过所述第一电容与所述第二节点连接，所述第三薄膜晶体管的源极接入所述低电位信号。The voltage stabilizing unit further includes a first capacitor, the drain of the third thin film transistor is connected to the second node through the first capacitor, and the source of the third thin film transistor is connected to the low potential signal .
  5. 根据权利要求3所述的GOA电路，其中，The GOA circuit according to claim 3, wherein:
    所述稳压单元还包括第二电容，所述第二薄膜晶体管的漏极通过所述第二电容与所述第二输出端连接。The voltage stabilizing unit further includes a second capacitor, and the drain of the second thin film transistor is connected to the second output terminal through the second capacitor.
  6. 根据权利要求2所述的GOA电路，其中，The GOA circuit according to claim 2, wherein:
    所述下拉模块还包括第七薄膜晶体管、第八薄膜晶体管、第九薄膜晶体管以及第十薄膜晶体管；The pull-down module further includes a seventh thin film transistor, an eighth thin film transistor, a ninth thin film transistor, and a tenth thin film transistor;
    所述第七薄膜晶体管的栅极、所述第八薄膜晶体管的栅极、所述第九薄膜晶体管的栅极以及第十薄膜晶体管的栅极均接入第n+1级级传信号，所述第七薄膜晶体管的源极、所述第八薄膜晶体管的源极、所述第九薄膜晶体管的源极以及第十薄膜晶体管的源极均接入低电位信号；The gate of the seventh thin film transistor, the gate of the eighth thin film transistor, the gate of the ninth thin film transistor, and the gate of the tenth thin film transistor are all connected to the n+1 level signal transmission, so The source of the seventh thin film transistor, the source of the eighth thin film transistor, the source of the ninth thin film transistor, and the source of the tenth thin film transistor are all connected to a low potential signal;
    所述第七薄膜晶体管的漏极与所述第一输出端连接、所述第八薄膜晶体管的漏极与所述第二节点连接，所述第九薄膜晶体管的漏极与所述第二输出端连接，所述第十薄膜晶体管的漏极与所述第一节点连接。The drain of the seventh thin film transistor is connected to the first output terminal, the drain of the eighth thin film transistor is connected to the second node, and the drain of the ninth thin film transistor is connected to the second output. The drain of the tenth thin film transistor is connected to the first node.
  7. 根据权利要求2所述的GOA电路，其中，The GOA circuit according to claim 2, wherein:
    所述第一上拉模块包括第十一薄膜晶体管，所述第十一薄膜晶体 管的栅极与所述第一节点连接，所述第十一薄膜晶体管的源极接入第二时钟信号；所述第十一薄膜晶体管的漏极与所述第二输出端连接。The first pull-up module includes an eleventh thin film transistor, the gate of the eleventh thin film transistor is connected to the first node, and the source of the eleventh thin film transistor is connected to a second clock signal; The drain of the eleventh thin film transistor is connected to the second output terminal.
  8. 根据权利要求2所述的GOA电路，其中，The GOA circuit according to claim 2, wherein:
    所述下拉维持模块包括第十二薄膜晶体管、第十三薄膜晶体管以及第十四薄膜晶体管；The pull-down maintenance module includes a twelfth thin film transistor, a thirteenth thin film transistor, and a fourteenth thin film transistor;
    所述第十二薄膜晶体管的栅极和源极均接入高电平信号，所述第十二薄膜晶体管的漏极与所述第十三薄膜晶体管的漏极均与第三节点连接，所述第十三薄膜晶体管的栅极与所述第二节点连接，所述第十三薄膜晶体管的源极接入低电平信号；The gate and source of the twelfth thin film transistor are both connected to a high level signal, the drain of the twelfth thin film transistor and the drain of the thirteenth thin film transistor are both connected to the third node, so The gate of the thirteenth thin film transistor is connected to the second node, and the source of the thirteenth thin film transistor is connected to a low-level signal;
    所述第十四薄膜晶体管的栅极与所述第三节点连接，所述第十四薄膜晶体管的源极接入所述低电平信号，所述第十四薄膜晶体管的漏极与所述第一节点连接。The gate of the fourteenth thin film transistor is connected to the third node, the source of the fourteenth thin film transistor is connected to the low-level signal, and the drain of the fourteenth thin film transistor is connected to the The first node is connected.
  9. 根据权利要求2所述的GOA电路，其中，The GOA circuit according to claim 2, wherein:
    所述上拉控制模块还包括第十五薄膜晶体管，所述第十五薄膜晶体管的栅极接入第一时钟信号，所述第十五薄膜晶体管的源极接入第n-1级级传信号，所述第十五薄膜晶体管的漏极与所述第一节点连接。The pull-up control module further includes a fifteenth thin film transistor, the gate of the fifteenth thin film transistor is connected to the first clock signal, and the source of the fifteenth thin film transistor is connected to the n-1th stage transmission. Signal, the drain of the fifteenth thin film transistor is connected to the first node.
  10. 一种显示装置，其中，包括如权利要求1所述的显示面板。A display device comprising the display panel according to claim 1.
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