WO2020224150A1

WO2020224150A1 - System and method for quantum circuit simulation

Info

Publication number: WO2020224150A1
Application number: PCT/CN2019/105910
Authority: WO
Inventors: Chu GUO; Heliang HUANG; Junhua Liu
Original assignee: Supreme Qi Pte Ltd; Guangdong Supremacy Future Technologies Ltd
Priority date: 2019-05-05
Filing date: 2019-09-16
Publication date: 2020-11-12
Also published as: WO2020223850A1

Abstract

A system and method for quantum circuit simulation is provided. The system comprises: a computer system including a processor and a memory communicably coupled to the processor to store data and instructions, wherein the processor is configured to generate an N-qubit system based on a M-dimensional lattice, and each qubit in the N-qubit system comprises a pair of indexes corresponding to a point on the M-dimensional lattice (101); generate N multi-dimensional tensors, each multi-dimensional tensor corresponding to a qubit and including a dimension which is determined based on the M-dimensional lattice (102); conduct a gate operation on one or more than one qubit based on the multi-dimensional tensor corresponding to each of the one or more than one qubit (103); and conduct a measurement on a qubit based on the multi-dimensional tensor corresponding to the qubit (104).

Description

SYSTEM AND METHOD FOR QUANTUM CIRCUIT SIMULATION

Field of Invention

The invention relates to quantum computing, and more particularly to a system and method for quantum circuit simulation.

Background

In recent years, intensive research on quantum computers has achieved significant improvements due to breakthroughs in superconducting quantum computing. For example, 50-70 qubits scale quantum chips have been realized, which were expected to surpass the capability of a most advanced classical computer. However, the advantage of the quantum computers with 50-70 qubits scale has not been shown mainly due to the high error rate in quantum gate operations or lack of automatic error correction ability.

Quantum circuit is a model for quantum computation performed by a quantum computer. This model includes a sequence of quantum gates. To reduce the error rate in quantum gate operations, accuracy of the quantum computing results need to be verified by using classical computers since scalable and affordable quantum hardware solutions are still not available to facilitate quantum circuit simulation and hardware design of quantum computers. However, in the existing solution for quantum circuit simulation using classical computers, as the number of qubits used in the quantum computing increases, both memory usage and complexity of quantum gate operation increase at an exponential rate, which has substantially limited the simulation ability of classical computers.

Summary of Invention

Embodiments of the invention provide a solution for quantum circuit simulation using a classical computer which can effectively reduce memory usage and complexity of quantum gate operation during the simulation process.

According to one aspect of the invention, a system for quantum circuit simulation is provided. The system comprises a computer system including a processor and a memory communicably coupled to the processor, wherein the memory is configured to store data and instructions to be executed by the processor, and data generated during a simulation process, wherein the processor is configured to generate an N-qubit system based on a M-dimensional lattice, wherein N and M are positive integers, and each qubit in the N-qubit system comprises a position indicator corresponding to a point on the M-dimensional lattice; generate a quantum state for the N-qubit system wherein the quantum state comprises N multi-dimensional tensors, each multi-dimensional tensor corresponds to a qubit in the N-qubit system and includes a dimension which is determined based on the M-dimensional lattice; conduct a gate operation on one or more than one qubit in the N-qubit system based on the multi-dimensional tensor corresponding to each of the one or more than one qubit; and conduct a measurement on a qubit in the N-qubit system based on the multi-dimensional tensor corresponding to the qubit.

According to a second aspect of the invention, a method for quantum circuit simulation is provided. The method comprises: generating, by a processor in a computer system, an N-qubit system based on a M-dimensional lattice, wherein N and M are positive integers, and each qubit in the N-qubit system comprises a position indicator corresponding to a point on the M-dimensional lattice; generating, by the processor, a quantum state for the N-qubit system wherein the quantum state comprises N multi-dimensional tensors, each multi-dimensional tensor corresponds to a qubit in the N-qubit system and includes a dimension which is determined based on the M-dimensional lattice; conducting, by the processor, a gate operation on one or more than one qubit in the N-qubit system based on the multi-dimensional tensor corresponding to each of the one or more than one qubit; and conducting, by the processor, a measurement on a qubit in the N-qubit system based on the multi-dimensional tensor corresponding to the qubit.

According to a third aspect of the invention, a non-transitory computer readable medium is provided, which comprises computer program code for quantum circuit simulation, wherein the computer program code, when executed, is configured to cause a processor in a computer system to perform a method for quantum circuit simulation proposed by any embodiment of the invention.

Brief Description of the Drawings

The invention will be described in detail with reference to the accompanying drawings, in which:

Figure 1 is a flow chart illustrating a method for quantum circuit simulation according to some embodiments of the invention;

Figure 2 (a) shows a rectangular lattice for generating an N-qubit system and a corresponding quantum state according to one embodiment of the invention;

Figure 2 (b) shows a triangular lattice for generating an N-qubit system and a corresponding quantum state according to one embodiment of the invention;

Figure 2 (c) shows a hexagonal lattice for generating an N-qubit system and a corresponding quantum state according to one embodiment of the invention;

Figure 2 (d) shows a one-dimensional lattice for generating a 5-qubit system and a corresponding quantum state according to one embodiment of the invention;

Figure 2 (e) shows a one-dimensional lattice for generating an N-qubit system amd a corresponding quantum state according to one embodiment of the invention;

Figure 3 is a flow chart illustrating a first method for conducting two-qubit gate operation on two nearest-neighbour qubits according to some embodiments of the invention;

Figure 4 is a flow chart illustrating a second method for conducting two-qubit gate operation on two nearest-neighbour qubits according to some embodiments of the invention;

Figure 5 is a flow chart illustrating a method for conducting a two-qubit gate operation on two non-nearest neighbor qubits according to some embodiments of the invention;

Figure 6 is a flow chart illustrating a method for conducting a quantum measurement on a qubit according to some embodiments of the invention;

Figure 7 is a flow chart illustrating a method for quantum circuit simulation according to one embodiment of the invention;

Figure 8 is a flow chart illustrating a first method for conducting a two-qubit nearest-neighbour gate operation according to some embodiments of the invention in which the multi-dimensional tensors are stored in right-canonical form, left-canonical form or mixed-canonical form;

Figures 9A to 9C are flow charts illustrating a second method for conducting a two-qubit nearest-neighbor gate operation according to some embodiments of the invention in which the multi-dimensional tensors are stored in right-canonical form, left-canonical form and mixed-canonical form respectively.

Detailed Description of Embodiments of the Invention

In the following description, numerous specific details are set forth in order to provide a thorough understanding of various illustrative embodiments of the invention. It will be understood, however, to one skilled in the art, that embodiments of the invention may be practiced without some or all of these specific details. It is understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the invention.

Embodiments described in the context of one of the methods or systems are analogously valid for the other methods or systems. Similarly, embodiments described in the context of a method are analogously valid for a system, and vice versa.

Features that are described in the context of an embodiment may correspondingly be applicable to the same or similar features in the other embodiments. Features that are described in the context of an embodiment may correspondingly be applicable to the other embodiments, even if not explicitly described in these other embodiments. Furthermore, additions and/or combinations and/or alternatives as described for a feature in the context of an embodiment may correspondingly be applicable to the same or similar feature in the other embodiments.

As used herein, the articles “a” , “an” and “the” as used with regard to a feature or element include a reference to one or more of the features or elements. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. As used herein, the terms “first, ” “second, ” and “third, ” etc. are used merely as labels, and are not intended to impose numerical requirements on their objects. As used herein, the term “configured to” is interchangeable with “operative” or “adapted to” .

Embodiments of the invention propose a system for quantum circuit simulation. This system comprises a computer system including a processor and a memory communicably coupled to the processor, wherein the memory is configured to store data and instructions to be executed by the processor, and data generated during a simulation process, wherein the processor is configured to generate an N-qubit system based on a M-dimensional lattice, wherein N and M are positive integers, and each qubit in the N-qubit system comprises a position indicator corresponding to a point on the M-dimensional lattice; generate N multi-dimensional tensors, wherein each multi-dimensional tensor corresponds to a qubit in the N-qubit system and includes a dimension which is determined based on the M-dimensional lattice; conduct a gate operation on one or more than one qubit in the N-qubit system based on the multi-dimensional tensor corresponding to each of the one or more than one qubit; and conduct a measurement on a qubit in the N-qubit system based on the multi-dimensional tensor corresponding to the qubit.

In some embodiments, the processor may be further configured to determine the dimension of the multi-dimensional tensor corresponding to each of the qubits in the N-qubit system based on the number of edges of the M-dimensional lattice connecting to the each of the qubits. Thus, the dimension of the multi-dimensional tensor corresponding to each of the qubits may be different.

In some embodiments, the processor may be further configured to determine the dimension of the multi-dimensional tensor corresponding to each of the qubits in the N-qubit system based on the maximum value of the number of edges of the M-dimensional lattice connecting to a qubit. Thus, the dimension of each multi- dimensional tensor is same.

In some embodiments, the processor may be further configured to conduct a single-qubit gate operation on a qubit in the N-qubit by multiplying a two-dimensional tensor corresponding to the single-qubit gate operation by the multi-dimensional tensor corresponding to the qubit.

In some embodiments, the processor may be further configured to conduct a two-qubit gate operation on a first qubit and a second qubit which are two nearest-neighbor qubits according to a first method by decomposing a four-dimensional tensor corresponding to the two-qubit gate operation into a first three-dimensional tensor corresponding to the first qubit and a second three-dimensional tensor corresponding to the second qubit, and multiplying the first three-dimensional tensor by a first multi-dimensional tensor corresponding to the first qubit to obtain a first resulting tensor and multiplying the second three-dimensional tensor by a second multi-dimensional tensor corresponding to the second qubit to obtain a second resulting tensor.

In some embodiments, the processor may be further configured to compress a size of the first resulting tensor and/or the second resulting tensor using singular value decomposition.

In some embodiments, the processor may be further configured to conduct a two-qubit gate operation on a third qubit and a fourth qubit which are two nearest-neighbor qubits according to a second method by determining a combined tensor based on a third multi-dimensional tensor corresponding to the third qubit and a fourth multi-dimensional tensor corresponding to the fourth qubit; determining a product based on the combined tensor and a four-dimensional tensor corresponding to the two-qubit gate operation; and using a decomposition method to decompose the product to obtain a third and a fourth resulting tensors corresponding to the third and the fourth qubits respectively.

In some embodiments, the processor may be further configured to generate the N-qubit system based on a one-dimensional lattice, generate and store a canonical form of each multi-dimensional tensor corresponding to a qubit in the N-qubit system, store a singlular vector corresponding to each pair of nearest-neighbor points in the one-dimensional lattice, and conduct a gate operation on one or more than one qubit based on the canonical form of each corresponding multi-dimensional tensor.

In some embodiments, the processor may be further configured to generate and store a right-canonical form, a left-canonical form or a mixed canonical form of each multi-dimensional tensor corresponding to a qubit in the N-qubit system.

In some embodiments, when the first approach is used for conducting the two-qubit gate operation on the first and the second qubits and the one-dimensional lattice is used to generate the N-qubit system, in a first example example, the processor may be further configured to generate and store a right-canonical form of each multi-dimensional tensor, and conduct a two-qubit gate operation on two nearest-neighbor qubits by multiplying the first resulting tensor by a left singular vector associated with the first and the second qubits; and restoring the the first and the second resulting tensors to a right-canonical form. In a second example, the processor may be further configured togenerate and store a left-canonical form of each multi-dimensional tensor, and conduct a two-qubit gate operation on two nearest-neighbor qubits by multiplying the second resulting tensor by a right singular vector associated with the first and the second qubits; and restoring the first and the second resulting tensors to a left-canonical form. In a third example, the processor may be configured to generate and store a mixed-canonical form of each multi-dimensional tensor, and conduct a two-qubit gate operation on two nearest-neighbor qubits by multiplying each of the first and the second resulting tensors by at least one singular vecor associated with the first and the second qubits; and restoring the first and the second resulting tensors to a mixed-canonical form.

In some embodiments, when the second approach is used for conducting the two-qubit gate operation on the third and the fourth qubits and the one-dimensional lattice is used to generate the N-qubit system, the processor may be configured to conduct a two-qubit gate operation on the third and the fourth qubits by determining the product based on a singular vector associated with the third and the fourth qubits; restoring the third and the fourth resulting tensors to a canonical form and using the canonical form of the third and the fourth resulting tensors to replace the third and the fourth multi-dimensional tensors. In a first example, the canonical form is a right-canonical form, and the singular vector is a left singular vector associated with the two qubits; in a second example, the canonical form is a left-canonical form, and the singular vector is a right singular vector associated with the two qubits; in a third example, the canonical form is a mixed-canonical form and the processor is further configured to determine the combined tensor based on a product of the third and the fourth multi-dimentional tensors and three singular vectors associated with the third and the fourth qubits.

In some embodiments, the processor may be further configured to conduct a two-qubit gate operation on two non-nearest neighbor qubits by applying at least one SWAP gate operation to one of two multi-dimensional tensor corresponding to the two non-nearest neighbor qubits to obtain two nearest-neighbor qubits; conducting the two-qubit gate operation on the obtained two nearest-neighbor qubits to obtain two resulting tensors corresponding to the two nearest-neighbor qubits; and applying at least one SWAP gate operation to one of the two resulting tensors to obtain two final resulting tensors corresponding to the two non-nearest neighbor qubits.

In some embodiments, the processor may be configured to conduct a measurement on a qubit by determining a probability of the qubit in a predetermined quantum state based on the multi-dimensional tensor corresponding to the qubit; using the determined probability to randomly sample between 0 and 1 to obtain a measurement result; and collapsing the qubit into a quantum state depending on the measurement result.

In some embodiments, the processor may be further configured to conduct a measurement on a qubit by applying a projection operator corresponding to a predetermined quantum state to a multi-dimensional tensor corresponding to the qubit; multiplying each multi-dimensional tensor corresponding to a qubit in the N-qubit system by a conjugate tensor thereof to determine a probability of the qubit in the predetermined quantum state; using the determined probability to randomly sample between 0 and 1 to obtain a measurement result; and collapsing the qubit into a quantum state depending on the measurement result.

In some embodiments, the processor may be further configured to determine the dimension of the multi-dimensional tensor corresponding to the qubit in the N-qubit system based on a physical dimension with a size of 2 indicating a quantum state of the corresponding qubit, and a plurality of auxiliary dimensions each corresponding to an edge of the M-dimensional lattice connecting to the qubit, wherein each auxiliary dimension has a size D which is to be changed with quantum gate operations, and wherein each multi-dimensional tensor has a maximum size of

wherein D _max refers to a maximum size of each auxiliary dimension of the multi-dimensional tensor, m refers to a maximum value of the number of edges connecting to the point in the M-dimensional lattice corresponding to the qubit.

In some embodiments, the M-dimensional lattice may be a two-dimensional lattice. In one example, the two-dimensional lattice may be a rectangular lattice, and accordingly the maximum value of the number of edges connecting to the point in the two-dimensional lattice corresponding to the qubit m is 4. In another example, the two-dimensional lattice may be a triangular lattice, and accordingly m is 6. In another example, the two-dimensional lattice may be a hexagonal lattice, and accordingly m is 3. In some embodiments, the M-dimensional lattice may be a one-dimensional lattice, and accordingly m is 2.

In some embodiments, the N-qubit system may be generated based on a one-dimensional lattice. To further improve the efficiency of gate operation and measurement operation, the processor may be further configured to store a single vector corresponding to each pair of the nearest-neighbor points in the one-dimensional lattice, and generate and store a canonical form tensor for each multi-dimensional tensor corresponding to a qubit in the N-qubit system. Accordingly, the corresponding canonical form of each multi-dimensional tensor is to be used in gate and measurement operations.

In some embodiments, the processor may be further configured to set an initial value of D as 1 and the size of each multi-dimensional tensor corresponding to the initial quantum state as 2.

Embodiments of the invention also provide a method 100 for quantum circuit simulation. Figure 1 is a flow chart illustrating the method for quantum circuit simulation according to some embodiments of the invention.

In block 101, a processor in a computer system is configured to generate an N-qubit system based on a M-dimensional lattice, wherein both N and M are positive integers, and each qubit in the N-qubit system comprises a position indicator corresponding to a point on the M-dimensional lattice.

In some embodiments, the M-dimensional lattice is a two-dimensional lattice, and the position indicator of each qubit may include a pair of indexes. In some embodiments, the M-dimensional lattice is a one-dimensional lattice, and the positional indicator of each qubit may include one single index.

In block 102, the processor is configurd to generate N multi-dimensional tensors, and each multi-dimensional tensor corresponds to a qubit in the N-qubit system and includes a dimension which is determined based on the M-dimensional lattice.

In some embodiments, when generating the multi-dimensional tensors, the processor may also determine some values to be used in the simulation process, e.g. a maximum size, initial value and size of each multi-dimensional tensor. The maximum size of each multi-dimensional tensor may be determined based on the M-dimensional lattice used for generating the quantum state.

In block 103, the processor is configured to conduct a gate operation on one or more than one qubit in the N-qubit system based on the multi-dimensional tensor corresponding to each of the one or more than one qubit.

The gate operation conducted by the processor may include a single-qubit gate operation, a two-qubit gate operation on two nearest-neighbor qubits and/or on two non-nearest neighbor qubits.

In block 104, the processor is configured to conduct a measurement on a qubit in the N-qubit system based on the multi-dimensional tensor corresponding to the qubit.

The details of each function of the processor in the system for quantum circuit simulation and each step in the method for quantum circuit simulation disclosed in embodiments of the invention will be described in detail below.

Generation of N-qubit system and a corresponding quantum state

Figure 2 (a) shows a rectangular lattice for generating an N-qubit system and a corresponding quantum state according to one embodiment of the invention. In this embodiment, this rectangular lattice is used to generate a 9-qubit system. Each of the qubits in the 9-qubit system corresponds to a point in the rectangular lattice, and comprises/is represented by a pair of indexes corresponding to the point in the rectangular lattice. For example, the qubit corresponding to the point (0, 0) in the lattice is written as q _(0, 0) , Accordingly, the 9-qubit system generated based on the 3X3 rectangular lattice may be written as |q _(0, 0) , q _(0, 1) , q _(0, 2) , q _(1, 0) , q _(1, 1) , q _(1, 2) , q _(2, 0) , q _(2, 1) , q _(2, 2) >.

In one example, the dimension of the multi-dimensional tensor corresponding to a qubit in the N-qubit system is determined based on the number of edges of the 3X3 rectangular lattice connecting to the point corresponding to the qubit, i.e. the number of other qubits in the 9-qubit system connecting to the qubit. Specifically, the dimension of the multi-dimensional tensor is equal to the number of edges connecting to the point corresponding to the qubit plus 1. Table 1 below sets out the multi-dimensional tensor corresponding to each qubit in the 9-qubit system.

Table 1

Referring to Table 1 and Figure 2 (a) , each multi-dimensional tensor corresponding to a qubit includes a physical index/dimension which indicates a quantum state of the qubit, and a plurality of auxiliary indexes/dimensions which indicate the edges in the lattice connecting to the point corresponding to the qubit. For example, the multi-dimensional tensor

corresponding to the qubit q _(0, 0) has a dimension of 3 including the physical dimension σ ₁ and two auxiliary dimensions a, c since there are two edges a, c of the 3X3 rectangular lattice, as shown in Figure 2 (a) , connecting to the point corresponding to qubitq _(0, 0) . The multi-dimensional tensor

corresponding to the qubit q _(0, 1) has a dimension of 4 including the physical dimension σ ₂ and three auxiliary dimensions a, b, d since there are three edges a, b, d connecting to the point corresponding to q _(0, 1) . The multi-dimensional tensor

corresponding to the qubit q _(1, 1) has a dimension of 5 including the physical dimension σ ₅ and four auxiliary dimensions f, d, g, i since there are four edges f, d, g, i connecting to the point corresponding to q _(1, 1) .

Alternatively, in another example, the multi-dimensional tensor corresponding to each qubit in the 9-qubit system may have the same dimension of 5 including the physical dimension and four auxiliary dimensions since there are at most four edges connecting to a point corresponding to a qubit in this 9-qubit system. For example, the quantum state corresponding to the 9-qubit system may be written as

wherein σ ₁-σ ₉ represent the physical dimensions of the 9 multi-dimensional tensors respectively, and l _n, r _n, u _n, d _n n=1-9, represent the four auxiliary dimensions of the 9 multi-dimensional tensors.

Figure 2 (b) shows a triangular lattice for generating an N-qubit system and a corresponding quantum state according to one embodiment of the invention. In this embodiment, this triangular lattice is used to generate a 9-qubit system. Similar to the 9-qubit generated based on the rectangular lattice, the 9-qubit system generated based on the 3X3 triangular lattice shown in Figure 2 (b) may be written as |q _(0, 0) , q _(0, 1) , q _(0, 2) , q _(1, 0) , q _(1, 1) , q _(1, 2) , q _(2, 0) , q _(2, 1) , q _(2, 2) >.

In one example, the dimension of a multi-dimensional tensor corresponding to a qubit in the N-qubit system is determined based on the number of edges of the 3X3 triangular lattice connecting to the point corresponding to the qubit, i.e. the number of other qubits in the 9-qubit system connecting to the qubit. Specifically, the dimension of the multi-dimensional tensor is equal to the number of edges connecting to the point corresponding to the qubit plus 1.

The multi-dimensional tensor corresponding to each qubit in the 9-qubit system is set out in Table 2 below. Similar to the rectangular lattice, each multi- dimensional tensor corresponding to a qubit includes a physical index/dimension which indicates a quantum state of the qubit, and a plurality of auxiliary indexes/dimensions which indicate the edges in the lattice connecting to the point corresponding to the qubit.

Table 2

Referring to Table 2 and Figure 2 (b) , the multi-dimensional tensor

corresponding to the qubit q _(0, 0) has a dimension of 3 including the physical dimension σ ₁and two auxiliary dimensions a, c since there are two edges a, c of the 3X3 triangular lattice, as shown in Figure 2 (b) , connecting to the point corresponding to qubitq _(0, 0) _. The multi-dimensional tensor

corresponding to the qubit q _(0, 1) has a dimension of 5 including the physical dimension σ ₂ and four auxiliary dimensions a, b, e, d since there are four edges a, b, e, d connecting to the point corresponding to q _(0, 1) . The multi-dimensional tensor

corresponding to the qubit q _(1, 1) has a dimension of 7 including the physical dimension σ ₅ and six auxiliary dimensions h, e, f, i, l, k since there are six edges h, e, f, i, l, k connecting to the point corresponding to q _(1, 1) .

Alternatively, in another example, the multi-dimensional tensor corresponding to each qubit in the 9-qubit system may have the same dimension of 7 including the physical dimension and six auxiliary dimensions since there are at most six edges connecting to a point corresponding to a qubit in this 9-qubit system.

Figure 2 (c) shows a hexagonal lattice for generating an N-qubit system and a corresponding quantum state according to one embodiment of the invention. In this embodiment, this hexagonal lattice is used to generate a 16-qubit system. Each qubit corresponds to a point in the hexagonal lattice and may be represented by a pair of indexes corresponding to a point in the lattice. Accordingly, the 16-qubit system may be represented as |q _(0, 0) , q _(0, 1) , q _(1, 0) , q _(1, 1) , q _(1, 2) , q _(2, 0) , q _(2, 1) , q _(2, 2) , q _(3, 0) , q _(3, 1) , q _(3, 2) , q _(4, 0) , q _(4, 1) , q _(4, 2) , q _(5, 0) , q _(5, 1) > .

In one example, the dimension of a multi-dimensional tensor corresponding to a qubit is determined based on the number of edges of this lattice connecting to the point corresponding to the qubit, i.e. the number of other qubits in the 16-qubit system connecting to the qubit. Specifically, the dimension of the multi-dimensional tensor is equal to the number of edges connecting to the point corresponding to the qubit plus 1.

The multi-dimensional tensor corresponding to each qubit in the 16-qubit system is set out in Table 3 below. Similar to the rectangular lattice, each multi-dimensional tensor corresponding to a qubit includes a physical index/dimension which indicates a quantum state of the qubit, and a plurality of auxiliary indexes/dimensions which indicate the edges in the lattice connecting to the point corresponding to the qubit.

Table 3

Referring to Table 3 and Figure 2 (c) , the multi-dimensional tensor

corresponding to the qubit q _(0, 0) has a dimension of 3 including the physical dimension σ ₁ and two auxiliary dimensions a, b since there are two edges a, b of the lattice, as shown in Figure 2 (c) , connecting to the point corresponding to qubit q _(0, 0) . The multi-dimensional tensor

corresponding to the qubit q _(1, 1) has a dimension of 4 including the physical dimension σ ₄ and three auxiliary dimensions d, b, f since there are three edges d, b, f connecting to the point corresponding to q _(1, 1) .

Alternatively, in another example, the multi-dimensional tensor corresponding to each qubit in the 16-qubit system may have the same dimension of 4 including the physical dimension and three auxiliary dimensions since there are at most three edges connecting to a point corresponding to a qubit in this 16-qubit system.

Figure 2 (d) shows a one-dimensional lattice for generating an N-qubit system and a corresponding quantum state according to one embodiment of the invention. In this embodiment, this one-dimensional lattice is used to generate a 5-qubit system. Each qubit corresponds to a point in the one-dimensional lattice and may be represented by an index corresponding to a point in the lattice. Accordingly, the 5-qubit system may be represented as |q ₀, q ₁, q ₂, q ₃, q ₄>.

In one example, the dimension of a multi-dimensional tensor corresponding to a qubit is determined based on the number of edges of this lattice connecting to the point corresponding to the qubit, i.e. the number of other qubits in the 5-qubit system connecting to the qubit. Specifically, the dimension of the multi-dimensional tensor is equal to the number of edges connecting to the point corresponding to the qubit plus 1.

The multi-dimensional tensor corresponding to each qubit in the 5-qubit system is set out in Table 4 below. Each multi-dimensional tensor corresponding to a qubit includes a physical index/dimension which indicates a quantum state of the qubit, and a plurality of auxiliary indexes/dimensions which indicate the edges in the lattice connecting to the point corresponding to the qubit.

Table 4

Referring to Table 4 and Figure 2 (d) , the multi-dimensional tensor

corresponding to the qubit q ₀ has a dimension of 2 including the physical dimension σ ₁₀ and one auxiliary dimension a since there is only one edge a of the lattice, as shown in Figure 2 (d) , connecting to the point corresponding to qubit q ₀. The multi-dimensional tensor

corresponding to the qubit q ₁ has a dimension of 3 including the physical dimension σ ₁ and two auxiliary dimensions a, b since there are two edges a, b connecting to the point corresponding to the qubit q ₁in the one-dimensional lattice.

Alternatively, in another example, the multi-dimensional tensor corresponding to each qubit in the 5-qubit system may have the same dimension of 3 including the physical dimension and two auxiliary dimensions since there are at most two edges connecting to a point corresponding to a qubit in this 5-qubit system.

Initialization of quantum state and parameters (Size of multi-dimensional tensor corresponding to each qubit)

As mentioned above, a multi-dimensional tensor corresponding to a qubit includes a physical dimension which has a size of 2, and a plurality of auxiliary dimensions each corresponding to an edge of the M-dimensional lattice connecting to the point corresponding to the qubit. Each auxiliary dimension is configured to have a size D which is to be changed with quantum gate operations. A maximum size of the multi-dimensional tensor may be determined as

wherein D _max refers to a maximum size of each auxiliary dimension of the multi-dimensional tensor, m refers to the maximum value of the number of edges in the M-dimensional lattice connecting to the qubit.

For example, if the M-dimensional lattice is a two-dimensional rectangular lattice, the maximum size of the multi-dimensional tensor may be determined as

if the M-dimensional lattice is a two-dimensional triangular lattice, the maximum size of the multi-dimensional tensor may be determined as

if the M-dimensional lattice is a hexagonal lattice, the maximum size of the multi-dimensional tensor may be determined as

If the M-dimensional lattice is a one-dimensional lattice, the maximum size of the multidimensional tensor may be determined as

In some embodiments, the quantum state may be initialized to be in quantum state |0> or |1>. The initial value of the size of each auxiliary dimension D may be set as 1 and the size of each multi-dimensional tensor corresponding to the initial quantum state may be set as 2. The initial value of each multi-dimensional tensor may be set as [1, 0] corresponding to state |0>, or [0, 1] corresponding to state |1>.

Single-qubit quantum gate operation

The single-qubit gate operation may be a two-dimensional tensor representing by a 2×2 matrix. The single-qubit operation on a qubit may be conducted by multiplying the two-dimensional tensor corresponding to the single-qubit gate operation by the multi-dimensional tensor corresponding to the qubit.

In one example, the single-qubit operation is acted on the qubit q _(1, 1) which is generated based on a rectangular lattice shown in Figure 2 (a) . The single-qubit operation may be represented as

and acted on the multi-dimensional tensor corresponding to the qubit q _(1, 1) according to equation (1a) . With this single-qubit operation, the original tensor is changed to the resulting tensor

with the same size as the original tensor.

In another example, the single-qubit operation is acted on the qubit q ₁ which is generated based on a one-dimensional lattice shown in Figure 2 (d) and the multi-dimensional tensor corresponding to this qubit is

Accordingly, the single-qubit operation may be conducted according to equation (1b) . With this single-qubit operation, the original tensor is changed to the resulting tensor

with the same size as the original tensor.

Two-qubit quantum gate operation on two nearest-neighbor qubits

The two-qubit gate operation may be conducted on two nearest-neighbour qubits by applying the two-qubit gate operation to the two multi-dimensional tensors corresponding to the two qubits, compressing at least one of the resulting tensors, and using the resulting tensors to replace the original tensors corresponding to the two qubits. It should be noted that the compression step is optional. In some embodiments, the compression step may not be conducted. In some embodiments, the compression step may be conducted on at least one of the resulting tensors regardless of the size thereof. In some embodiments, the compression step may be only conducted when the size of the resulting tensors exceeds a predetermined maximum size.

In some embodiments, a two-qubit gate operation may be conducted on a first qubit and a second qubit which are two nearest-neighbor qubits by a processor in a computer system according to a first method 300 as shown in Figure 3.

In block 301, the processor is configured to decompose/split the tensor corresponding to the two-qubit gate operation into a first three-dimensional tensor corresponding to the first qubit and a second three-dimensional tensor corresponding to the second qubit using any matrix decomposition, for example, QR decomposition or singular value decomposition.

In a first example, the two-qubit gate operation is conducted on two qubitsq _(1, 0) and q _(1, 1) in an N-qubit system generated based on a two-dimensional lattice. The tensor of the two-qubit gate operation may be represented as

and split into two three-dimensional tensors according to equation (2a) :

wherein the first three-dimensional tensor

corresponds to q _(1, 0) , and the second three-dimensional tensor

corresponds to q _(1, 1) .

In a second example, the two-qubit gate operation is conducted on two qubits q ₁ and q ₂ in an N-qubit system generated based on a one-dimensional lattice. The tensor of the two-qubit gate operation may be represented as

and split into two three-dimensional tensors according to equation (2b) :

wherein the first three-dimensional tensor

corresponds to q ₁, and the second three-dimensional tensor

corresponds to q ₂.

In block 302, the processor is configured to obtain a first resulting tensor by multiplying the first three-dimensional tensor by the first multi-dimensional tensor, and obtain a second resulting tensor by multiplying the second three-dimensional tensor by the second multi-dimensional tensor.

In the first example, the two three-dimensional tensors

and

are conducted on two multi-dimensional tensors corresponding to the two qubits q _(1, 0) and q _(1, 1) respectively. The two multi-dimensional tensors may be

and

which are generated based on the rectangular lattice shown in Figure 2 (a) . The three-dimensional tensor

is multiplied by the tensor

and the three-dimensional tensor

is multiplied by the tensor

according to equation (3a) :

In the second example, the two three-dimensional tensors

and

are conducted on two multi-dimensional tensors corresponding to the two qubits q ₁ and q ₂ respectively. The two multi-dimensional tensors may be

and

which are generated based on the one-dimensional lattice shown in Figure 2 (d) . The three-dimensional tensor

is multiplied by the tensor

and the three-dimensional tensor

is multiplied by the tensor

according to equation (3b) :

In block 303, the processor is configured to combine the dimensions of the first and the second resulting tensors.

In the first example, the dimensions of the two resulting tensors

and

are combined using f′← (f, s) according to equation (4a) :

In the second example, the dimensions of the two resulting tensors

and

are combined using b′← (b, s) according to equation (4b) :

In block 304, the processor is configured to compress the first and the second resulting tensors if the size of the two resulting tensors exceeds a predetermined maximum size and replace the first and the second multi-dimensional tensors with the compressed first and the second resulting tensors respectively.

It should be noted that in this method, if the size of the resulting tensors does not exceed the predetermined maximum size, the original multi-dimensional tensors may be replaced with the two resulting tensors without being compressed. In other embodiments, the compression step may not be conducted or may be conducted regardless of the size of the resulting tensors.

In the two examples mentioned above, as the dimensions of the resulting tensors are combined, the size of the resulting tensors is larger than the original tensors by a factor of the dimension s, namely dim (s) . For a two-qubit control gate operation, dim (s) =2. As a result, after several two-qubit operations, the size of the two resulting tensors may become larger than a predetermined maximum value if no compression is done.

In the first example, the two resulting tensors

and

may be compressed by any compression method described below.

In a first compression method, the resulting tensor

is compressed using singular value decomposition according to equation (5) :

wherein SVD refers to Singular Value Decomposition. As SVD can only applies to a tensor with two dimensions, the dimensions τ ₁, c, h of the resulting tensor

are combined into one single dimension (τ ₁, c, h) , and accordingly the resulting tensor becomes

with only two dimensions. Then, after the SVD is applied to the resulting tensor, the combined dimensions are decomposed again. In this example, the resulting tensors

and

may be decomposed by the following steps:

Step 1: discarding singular values in the singular vector S _s, swhich are less than a given threshold, and/or restricting the size of singular vector S _s, s to less than a given size D _max to ensure the size of each multi-dimensional tensor corresponding to the qubit is bounded by

In this case, several simulations with different values of D _max may be performed to ensure the convergence of the simulation;

Step 2: multiplying S _s, s by V _s, f′ to obtain V′ _s, f′, or calculating V′ _s, f′ according to equation (6) and then calculating

according to equation (7) :

Step 3: multiplying V′ _s, f′ by

to obtain the compressed tensor according to the following the equation (8) :

After the compression step, two compressed resulting tensors

and

are obtained. The size of the dimension s of the compressed resulting tensors is smaller than that of the dimension f′ of the two resulting tensors

and

Then, the two compressed resulting tensors are used to replace the original multi-dimensional tensors

and

A second compression method includes the following steps:

Step 1: conducting SVD on

instead of

Step 2: obtaining V′ _s, f′ and multiplying V′ _s, f′ by

A third compression method includes the following steps:

Step 1: conducting QR decomposition on

Step 2: obtaining V′ _s, f′ and multiplying V′ _s, f′ by

Step 3: conducting SVD on

obtaining V′ _s, f′ again and multiplying V′ _s, f′ by

A fourth compression method is similar to the third one except that the sequence of operations conducted on

and

is swapped. In the third and fourth methods, the additional step of QR decomposition is used to keep the values of the resulting tensors to be balanced, namely not too large or too small.

It is to be appreciated by a person skilled in the art that the method for compressing the size of resulting tensors is similar when different lattice e.g. triangular or hexagonal lattice, is used to generate N-qubit system, except that the dimension of the multi-dimensional tensors may be different.

In the second example, the two resulting tensors

and

may be compressed by any of the following four methods:

A first compression method includes the following steps:

Step 1: conducting SVD on

according to equation (9a) and discarding singular values smaller than a threshold in S.

Step 2: multiplying S _s, s and V _s, b′ by

according to equation (9b) :

Step 3: replacing

and

with

and

respectively.

A second compression method includes the following steps:

Step 1: conducting SVD on

according to equation (10a) and discarding the singular values smaller than a predetermined threshold in S.

Step 2: multiplying S _s, s and U _b′, s by

according to equation (10b) :

Step 3: replacing

and

with

and

respectively.

A third compression method includes the following steps:

Step 1: conducting QR decomposition on

according to equation (11a) :

Step 2: multiplying R _s, b′ by

according to equation (11b) :

Step 3: conducting the second method on

and

A fourth compression method includes the following steps:

Step 1: conducting LQ decomposition on

according to equation (12a) :

Step 2: multiplying L _b′, s by

according to equation (12b) :

Step 3: conducting the first method on

and

In some embodiments, the two-qubit gate operation may be conducted on a third qubit and a fourth qubit which are two nearest-neighbor qubits by a processor in a computer system according to a second method 400 as shown in Figure 4.

In block 401, the processor is configured to determine a combined tensor based on a third and a fourth multi-dimensional tensors corresponding to the third and the fourth qubits respectively.

In a first example, the two-qubit gate operation is conducted on two qubitsq _(1, 0) and q _(1, 1) in an N-qubit system generated based on a two-dimensional lattice. The two multi-dimensional tensors

and

corresponding to q _(1, 0) and q _(1, 1) respectively are multiplied to obtain a combined tensor according to equation (13a) :

In a seond example, the two-qubit gate operation is conducted on two qubits q ₁ and q ₂ in an N-qubit system generated based on a one-dimensional lattice. The two multi-dimensional tensors

and

corresponding to the two qubits respectively are multiplied to obtain a combined tensor according to equation (13b) :

In block 402, the processor is configured to determine a product based on the combined tensor and the two-qubit gate operation.

In the first example, the tensor corresponding to the two-qubit gate operation is

which is multiplied by the combined tensor according to equation (14a) :

In a second example, the tensor corresponding to the two-qubit gate operation is

which is multiplied by the combined tensor according to equation (9b) :

In block 403, the processor is configured to use a decomposition method to decompose the product to obtain a third and a fourth resulting tensors and replace the third and the fourth multi-dimensional tensors with the third and fourth resulting tensors respectively.

In the first example, the product

may be decomposed to obtain the third and the fourth resulting tensors according to equation (15a) by using SVD. After the decomposition, the resulting tensors are compressed by discarding singular values smaller than a predetermined threshold, and/or only keeping the largest singular values if the size of s is larger than D _max.

The two resulting tensors

and

are to be used to replace the third and the fourth multi-dimensional tensors corresponding to the third and the fourth qubits respectively.

In the second example, the product

is decomposed to obtain the third and the fourth resulting tensors according to equation (15b) by using SVD. After the decomposition, the resulting tensors are compressed by discarding singular values smaller than a predetermined threshold, and/or only keeping the largest singular values if the size of b′ is larger than D _max.

The two resulting tensors

and

are to be used to replace the the third and the fourth multi-dimensional tensors corresponding to the third and the fourth qubits respectively.

Two-qubit quantum gate operation on two non-nearest neighbor qubits

To simulate a quantum circuit, the two-qubit gate operation may also be conducted on two non-nearest neighbor qubits. Figure 5 is a flow chart illustrating a method 500 for conducting a two-qubit gate operation on two non-nearest neighbor qubits by a processor in a computer system according to some embodiments of the invention.

In block 501, the processor is configured to conduct at least one SWAP gate operation on one of the two multi-dimensional tensors corresponding to the two non-nearest neighbor qubits to obtain two nearest-neighbor qubits.

For example, in a two-dimensional case, to conduct a two-qubit operation on two qubits q _(0, 1) and q _(1, 2) , a SWAP gate operation may be applied to the qubit q _(1, 2) to move the qubit to q _(0, 2) . In a one-dimensional case, to conduct a two-qubit gate operation on two non-nearest neighbour qubits, e.g. q ₁ and q ₃, a SWAP gate operation may be applied to move the qubit q ₁ to q ₂. In some other examples, more than one SWAP gate operation may be required to move one of the qubits to obtain two nearest neighbour qubits.

In block 502, the processor is configured to conduct the two-qubit gate operation on the obtained two nearest-neighbor qubits according to the first or second method described above to obtain two resulting tensors corresponding to the two nearest-neighbor qubits.

In block 503, the processor is configured to conduct at least one SWAP gate operation on one of the two resulting tensors to obtain two final resulting tensors corresponding to the two non-nearest neighbor qubits.

Quantum Measurements

According to some embodiments of the invention, to conduct a quantum measurement on one qubit, the processor is configured to determine a probability of the qubit in a predetermined quantum state based on the multi-dimensional tensor corresponding to the qubit; use the determined probability to randomly sample between 0 and 1 to obtain a measurement result; and collapse the qubit into a quantum state based on the measurement result.

Figure 6 is a flow chart illustrating a method 600 for conducting a quantum measurement on a qubit by a processor in a computer system according to one embodiment of the invention.

In block 601, the processor is configured to apply a projection operator corresponding to a predetermined quantum state to the multi-dimensional tensor corresponding to the qubit, i.e. multiply the tensor corresponding to the predetermined projection operator by the multi-dimensional tensor corresponding to the qubit.

The projection operator may be

corresponding to the predetermined quantum state |1> or

corresponding to the predetermined quantum state |0>.

In a first example, to conduct a quantum measurement on a qubit of an N- qubit system, a projection operator corresponding to a predetermined quantum state is applied to the multi-dimensional tensor corresponding to this qubit. If the qubit is q _(1, 1) , the corresponding multi-dimensional tensor is

and the predetermined quantum state is |1> . The projection is conducted on the qubit according to equation (16a) :

In a second example, the qubit is q ₁, and the multi-dimensional tensor corresponding to this qubit is

The predetermined quantum state is quantum state |1> , the corresponding projection operator is applied to the qubit according to equation (16b) :

In block 602, the processor is configured to determine a probability of the qubit in the predetermined quantum state by multiplying each multi-dimensional tensor corresponding to a qubit in the N-qubit system by a conjugate tensor thereof.

In the first example, the probability p of the qubit

in the quantum state |1> may be calculated according to equation (17a) :

p= <q _(0, 0) , q _(0, 1) , ...q _(1, 1) ...q _(0, 2) ...|q _(0, 0) , q _(0, 1) , ...q′ _(1, 1) ...q _(0, 2) ...> (17a)

wherein the multi-dimensional tensor corresponding to q′ _(1, 1) is

obtained according to equation (17a) .

In the second example, the probability p of the qubit

may be calculated according to equation (17b) :

p= <q ₀, q ₁, ...|q ₀, q′ ₁, ...> (17b)

wherein the multi-dimensional tensor corresponding to the qubit q′ ₁is

obtained according to equation (17b) .

In block 603, the processor is configured to use the determined probability p to randomly sample between the

quantum state

0 and 1 to obtain a measurement result.

In block 604, the processor is configured to collapse the qubit into a quantum state depending on the measurement result.

In one embodiment, this collapsing step may include: the processor multiplies the multi-dimensional tensor corresponding to the qubit by a projection operator P ¹ or P ⁰ depending on the measurement result to obtain a product, and then rescales the product by the probability obtained in the step as shown in block 603. Specifically, if the measurement result is 0, the processor multiplies the multi-dimensional tensor by the projection operator P ⁰ to obtain the product; if the measurement result is 1, the processor multiplies the multi-dimensional tensor by the projection operator P ¹ to obtain the product.

In a first example, the qubit q _(1, 1) generated based on a two-dimensional rectangular lattice is taken as an example to explain the step in block 605. If the measurement result is 0, the processor first multiplies the multi-dimension

corresponding to the qubit q _(1, 1) by the projection operator P ⁰ according to equation (18a) , next rescales the result tensor according to equation (19a) , and then uses the rescaled result tensor to replace the original tensor.

If the measurement result is 1, the processor first multiplies the multi-dimension

by the projection operator P ¹ according to equation (20a) , next rescales the result tensor according to equation (21a) , and then uses the rescaled result tensor to replace the original tensor.

In a second example, a qubit of an N-qubit system generated based on a one-dimensional lattice, e.g. q ₁ , is taken as an example to explain the step in block 605. If the measurement result is 0, the processor first multiplies the multi-dimensional tensor

corresponding to the qubit q ₁ by the corresponding projection operator according to equation (18b) to produce a resultant tensor, next rescales the resultant tensor according to equation (19b) , and then uses the rescaled resultant tensor to replace the original tensor

and if the measurement result is 1, the processor first multiplies the multi-dimensional tensor

by the corresponding projection operator according to equation (20b) , next rescales the result tensor according to equation (21b) , and then uses the rescaled result tensor to replace the original tensor.

In some embodiments, the N-qubit system may be generated based on a one-dimensional lattice. To further improve the efficiency of gate operation and measurement operation, the method may further include the following steps: the processor generates and stores N multi-dimensional tensors in a canonical form, each multi-dimensional tensor corresponding to a qubit in the N-qubit system; and then stores a singular vector corresponding to each pair of nearest-neighbor points in the one-dimensional lattice. The stored singular vectors are produced during the generation of the canonical form of the multi-dimensional tensors. Accordingly, the canonical form of the multi-dimensional tensors are to be used in gate and measurement operations.

Figure 7 is a flow chart illustrating a method 700 for quantum circuit simulation according to one embodiment of the invention. In this embodiment, a one-dimensional lattice is used to generate an N-qubit system and each multi-dimensional tensor corresponding to a qubit in the N-qubit system is stored in a canonical form. The one-dimensional lattice used for generating the N-qubit system are shown in Figure 2 (e) .

In block 701, a processor in a computer system is configured to generate an N-qubit system based on a one-dimensional lattice, wherein N is a positive integer, and each qubit in the N-qubit system comprises an index corresponding to a point on the one-dimensional lattice.

In block 702, the processor is configured to generate and store N multi-dimensional tensors in a canonical form, and each multi-dimensional tensor corresponds to a qubit in the N-qubit system and includes a dimension of 3.

The canonical form may be a right-canonical form, a left-canonical form or a mixed-canonical form.

To explain the different canonical form, the multi-dimensional tensor

is taken as an example. If the multi-dimensional tensor is stored in a right-canonical form, an identity matrix associated with the position l-1 is to be generated by calculating the product of the multi-dimensional tensor and its conjugate according to equation (22a) :

where I is the identity matrix. If the multi-dimensional tensor

is stored in a left-canonical form, it means that an identity matrix associated with the position l is to be generated by calculating the product of the multi- tensor and its conjugate according to equation (22b) :

If the multi-dimensional tensor

is stored in mixed-canonical form, it means that if it is multiplied by the singular vector between position l and l+1, the result

is in the right-canonical form, and if it is multiplied by the singular vector between position l-1 and l, the result

is in the left-canonical form.

In one embodiment of the invention, each singular vector may be initialized to be a vector of size 1, and the only element thereof is 1; the quantum state may be initialized to be in quantum state |0> or |1>. The initial value of each multi-dimensional tensor may be set as [1, 0] corresponding to state |0>, or [0, 1] corresponding to state |1>.

In block 703, the processor is configured to store N-1 singular vectors, each singular vector corresponding to a pair of nearest-neighbour points in the one-dimensional lattice.

In block 704, the processor is configured to conduct a gate operation on one or more than one qubit in the N-qubit system based on the canonical form of each multi-dimensional tensor corresponding to the one or more than one qubit.

In block 705, the processor is configured to conduct a measurement on a qubit in the N-qubit system based on the canonical form of the multi-dimensional tensor corresponding to the qubit.

Gate Operation in Block 704

For single-qubit gate operation, the processor may conduct the gate operation on one qubit as shown in equation (1b) , the only difference is the multi-dimensional tensor is in a canonical form.

For a two-qubit nearest-neighbor gate operation, the processor may conduct the gate operation on two neareast-neighbor qubits according to a first method 800 similar to the first method 300 or a second method 900 similar to the second method 400 mentioned above.

Figure 8 is a flow chart illustrating the first method 800 for conducting a two-qubit nearest-neighbour gate operation according to some embodiments of the invention in which the multi-dimensional tensors are stored in right-canonical form, left-canonical form or mixed-canonical form. In these embodiments, the two-qubit gate operation is represented as

which is acted on two qubits q ₁ and q ₂. The multi-dimensional tensors corresponding to the two qubits q ₁ and q ₂ are represented as

and

respectively.

In block 801, a processor in a computer system is configured to decompose the two-qubit gate operation

into a first and a seond three-dimensional tensors according to equation (23) ;

In block 802, the processor is configured to determine a first resulting tensor by multiplying the first three-dimensional tensor

by the first multi-dimensional tensor

and determine a second resulting tensor by multiplying the second three-dimensional tensor

by the second multi-dimensional tensor

according to equation (24) .

In block 803, the processor is configured to combine dimensions of the first and the second resulting tensors as b′← (b, s) according to equation (25)

In block 804, the processor is configured to compress and restore the first and the second resulting tensors with the combined dimensions

and

into a canonical form.

When the multi-dimensional tensors are stored in the right-canonical form, the block 804 includes the following steps 1a-7a:

Step 1a: the processor is configured to multiply the first resulting tensor

by a singular vector S _a, a between position 0 and position 1, i.e. a left singular vector associated with the two qubits q ₁ and q ₂ , according to equation (26a) :

Step2a: the processor is configured to conduct QR decomposition on the first resulting tensor

according to equation (27a) :

This step may also be replaced by conducting a SVD on the first resulting tensor

according to equation (28a) :

Step3a: the processor is configured to multiply R _s, b′ by the second resulting tensor

according to equation (29a) :

Step4a: the processor is configured to conduct SVD decomposition on

according to equation (30a) :

Step 5a: the processor is configured to discard singular values in the singular vector S _s′, s′ smaller than a predetermined value.

Step 6a: the processor is configured to multiply U _s, s′, S _s′, s′ by

and divide the product by S _a, a according to equation (31a) :

Step 7a: the processor is configured to replace the first and and the second resulting tensors

and

with the compressed and canonical form resulting tensors

and

respectively and replace a singular vector S _b, b between position 1 and position 2, i.e. a middle singular vector associated with the two qubits q ₁ and q ₂, with S _s′, s′.

When the multi-dimensional tensors are stored in left-canonical form, the block 804 includes the following steps 1b-7b:

Step 1b: the processor is configured to multiply the second resulting tensor

by a singular vector S _c, c between position 2 and position 3, i.e. a right singular vector associated with the two qubits q ₁ and q ₂, according to equation (26b)

Step 2b: the processor is configured to conduct LQ decomposition on the second resulting tensor

according to equation (27b) :

This step may also be replaced by conducting a SVD on the second resulting tensor

according to equation (28b) :

Step 3b: the processor is configured to multiply L _b′, s by the first resulting tensor

according to equation (29b) :

Step 4b: the processor is configured to conduct SVD decomposition on

according to equation (30b) :

Step 5b: the processor is configured to discard singular values in the singular vector S _s′, s′ smaller than a predetermined value.

Step 6b: the processor is configured to multiply S _s′, s′, V _s′, s by

and divide the product by the right singular vector S _c, c according to equation (31b) :

Step 7b: the processor is configured to replace the first and the second resulting tensors

and

with the compressed and canonical form resulting tensors

and

respectively and replace the middle singular vector S _b, b with S _s′, s′.

When the multi-dimensional tensors are stored in a mixed-canonical form, the block 804 may be conducted according to a first approach or a second approach.

In the first approach, the processor is configured to multiply the first resulting tensor

with the left singular vector S _a, a and the middle singular vector S _b, b according to equation (26c) , and multiply the second resulting tensor

with the right singular vector S _c, c according to equation (27c)

Then, the processor is configured to conduct the steps 2a-5a, and the following steps 6c-8c.

Step 6c: the processor is configured to divide a product of U _s, s′ and

by the left singular vector S _a, a according to equation (28c) :

Step 7c: the processor is configured to divide

by the right singular vector S _c, c, according to equation (29c) :

Step 8c: the processor is configured to replace the first and the second resulting tensors

and

with the compressed and canonical form resulting tensors

and

respectively and replace the middle singular vector S _b, b with S _s′, s′.

In the second approach, the processor may be configured to multiply the first resulting tensor

with the left singular vector S _a, a according to equation (26d) , and multiply the second resulting tensor

with the right singular vector S _c, c and the middle singular vector S _b, b according to equation (27d)

Then, the processor is configured to conduct the steps 2b to 5b and the following steps 6d to 8d.

Step 6d: the processor is configured to multiply V _s′, s by

and divide by the right singular vector S _c, c according to equation (28d) :

Step 7d: the processor is configured to divide

by the left singular vector S _a, a according to equation (29d) :

Step 8d: the processor is configured to replace the first and the second resulting tensors

and

with the compressed and canonical form

and

respectively and replace the middle singular vector S _b, b with S _s′, s′.

Figures 9A to 9C are flow charts illustrating a second method 900A to 900C for conducting a two-qubit nearest-neighbor gate operation according to some embodiments of the invention in which the multi-dimensional tensors are stored in the right-canonical form, the left-canonical form or the mixed-canonical form. In these embodiments, the two-qubit nearest-neighbor gate operation is represented as

the two nearest-neighbor qubits are represented as a third qubit q _l and a fourth qubit q _l+1, and the multi-dimensional tensor corresponding to the two qubits are represented as a third multi-dimensional tensor

and a fourth multi-dimensional tensor

respectively.

If the multi-dimensional tensor is stored in the right-canonical form, the gate operation includes the following steps as shown in Figure 9A:

In block 901a, the processor is configured to determine a combined tensor based on the third and the fourth multi-dimensional tensors corresponding to the third and the fourth qubits according to equation (32a) .

In block 902a, the processor is configured to determine a product based on the combined tensor and the two-qubit gate operation according to equation (33a) .

In block 903a, the processor is configured to multiply the product obtained in block 902a with the singular vector

between position l-1 and position l, i.e. the left singular vector associated with the two nearest-neighbor qubits q _l and q _l+1, according to equation (34a) .

In block 904a, the processor is configured to apply SVD to the result

obtained in block 903a to obtain a third and a fourth resulting tensors according to equation (35a) .

wherein

is the singular vector between position l and position l+1.

In block 905a, the processor is configured to restore the third and the fourth resulting tensors

and

obtained in block 904a into the right-canonical form according into equation (36a) .

or

In block 906a, the processor is configured to use the right-canonical form of the third and the fourth resulting tensors

and

to replace the third and the fourth multi-dimensional tensors

and

respectively, and update the singular value

based on the value obtained in block 904a.

If a multi-dimensional tensor is stored in the left-canonical form, the gate operation includes the following steps as shown in Figure 9B:

In block 901b, the processor is configured to determine a combined tensor based on the third and the fourth multi-dimensional tensors corresponding to the third and the fourth qubits according to equation (32b) .

In block 902b, the processor is configured to determine a product based on the combined tensor and the two-qubit gate operation according to equation (33b) .

In block 903b, the processor is configured to multiply the product obtained in block 902b with the singular vector between position l+1 and position l+2 , i.e. the right singular vector associated with the two nearest-neighbor qubits q _l and q _l+1, according to equation (34b) .

In block 904b, the processor is configured to apply SVD to the result

obtained in block 903b to obtain a third and a fourth resulting tensors according to equation (35b) .

In block 905b, the processor is configured to restore the the third and the fourth resulting tensors

and

into the left-canonical form according to equation (36b) .

or

In block 906b, the processor is configured to use the left-canonical form of the third and the fourth resulting tensors

and

to replace the third and the fourth multi-dimensional tensors

and

respectively, and update the singular value

based on the value obtained from equation (35b) in block 904b.

If a multi-dimensional tensor is stored in mixed-canonical form, the gate operation includes the following steps as shown in Figure 9C:

In block 901c, the processor is configured to determine a combined tensor based on a product of the third and the fourth multi-dimensional tensors corresponding to the third and the fourth qubits and three singular vectors associated with the two qubits according to equation (32c) .

In block 902c, the processor is configured to determine a product based on the combined tensor and the two-qubit gate operation according to equation (33c) .

In block 903c, the processor is configured to apply SVD to the result

obtained in block 902c to obtain a third and a fourth resulting tensors according to equation (34c) .

In block 904c, the processor is configured to restore the third and the fourth resulting tensors

and

obtained in block 903c into the mixed-canonical form according to equation (35c) .

In block 905c, the processor is configured to use the mixed-canonical form of the third and the fourth resulting tensors

and

to replace the third and the fourth multi-dimensional tensors

and

respectively, and update the singular vector

based on the value obtained in block 903c from equation (34c) .

Measurement Operation in Block 705

If the multi-dimensional tensors are stored in canonical form, the measurement operation may be performed more efficiently. More specifically, the process for obtaining the probability P ¹ or P ⁰may be performed more efficiently. In the method described in Figure 6, to determine P ¹ or P ⁰, all of the mutli-dimensional tensors need to be contracted with the conjugate thereof. However, in this embodiment, the measurement operation on the position l may be performed according to the following methods. The qubit corresponding to position l is q _l. Only the steps different from the method in Figure 6 are described below.

If the multi-dimensional tensor is stored in a right-canonical form, the measurement operation may include the following steps:

Step1: the processor is configured to multiply the multi-dimensional tensor with the singular vector

between position l-1 and position l, i.e. the left singular vector associated with the qubit, according to equation (37a) :

Step 2: the processor is configured to calculate the probability p ¹according to equation (38) :

where σ _l is replaced with 1 to indicate that only the case where σ _l is in state 1 is calculated.

If the multi-dimensional tensors are stored in left-canonical form, the measurement operation may include the following steps:

between position l and position l+1 , i. e the right singular vector associated with the qubit q _l, according to equation (37b) :

Step 2: the processor is configured to calculate the probability according to equation (38) .

If the multi-dimensional tensors are stored in mixed-canonical form, the measurement operation may include the following steps:

Step 1: the processor is configured to multiply the multi-dimensional tensor with both the singular

and the singular vector

according to equation (37c) .

Compared with the prior art, the system and method for quantum circuit simulation proposed by embodiments of the invention at least have the following advantages: (a) when the solution proposed by embodiments of the invention is used to conduct quantum circuit simulation, the memory usage required for quantum state storage increases with the number of qubits linearly instead of exponentially; (b) with this solution, a quantum gate operation only affects the local tensor (s) , so the computational complexity will not be affected by the total number of the qubits used in the quantum computation, thus, a classical computer may be used to simulate quantum computation with a large number of qubits; (c) in this solution, the quantum computation may be simulated based on different lattice. That is to say, a lattice consistent with the arrangement of the qubits in the hardware of the quantum computers may be selected to perform the simulation to further improve the efficiency of the simulation. For example, when a two-dimensional lattice is used to simulate the quantum computation, as it is consistent with the arrangement of the qubits in the hardware of most existing quantum computers, the solution proposed by embodiments of the invention is more efficient and effective for quantum algorithm with two-dimensional features; (d) In this solution, when a one-dimensional lattice is used to simulate the quantum computation, the efficiency of the gate operation and measurement operation may be greatly improved, especially when the multi-dimensional tensor corresponding to each qubit is stored in canonical form.

It is to be understood that the embodiments and features described above should be considered exemplary and not restrictive. Many other embodiments will be apparent to those skilled in the art from consideration of the specification and practice of the invention. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. Furthermore, certain terminology has been used for the purposes of descriptive clarity, and not to limit the disclosed embodiments of the invention.

Claims

A system for quantum circuit simulation, the system comprising: a computer system including a processor and a memory communicably coupled to the processor, wherein the memory is configured to store data and instructions to be executed by the processor, and data generated during a simulation process, wherein the processor is configured to

generate an N-qubit system based on a M-dimensional lattice, wherein N and M are positive integers, and each qubit in the N-qubit system comprises a position indicator corresponding to a point on the M-dimensional lattice;

generate N multi-dimensional tensors, each multi-dimensional tensor corresponding to a qubit in the N-qubit system and including a dimension which is determined based on the M-dimensional lattice;

conduct a gate operation on one or more than one qubit in the N-qubit system based on the multi-dimensional tensor corresponding to each of the one or more than one qubit; and

conduct a measurement on a qubit in the N-qubit system based on the multi-dimensional tensor corresponding to the qubit.
The system according to claim 1, wherein the processor is further configured to determine the dimension of the multi-dimensional tensor corresponding to each of the qubits in the N-qubit system based on a number of edges of the M-dimensional lattice connecting to the each of the qubits.
The system according to claim 1, wherein the processor is further configured to conduct a single-qubit gate operation on a qubit in the N-qubit by multiplying a two-dimensional tensor corresponding to the single-qubit gate operation by the multi- dimensional tensor corresponding to the qubit.
The system according to any one of claim 1 to claim 3, wherein the processor is further configured to conduct a two-qubit gate operation on a first qubit and a second qubit which are two nearest-neighbor qubits by

decomposing a four-dimensional tensor corresponding to the two-qubit gate operation into a first three-dimensional tensor corresponding to the first qubit and a second three-dimensional tensor corresponding to the second qubit, and

multiplying the first three-dimensional tensor by a first multi-dimensional tensor corresponding to the first qubit to obtain a first resulting tensor and multiplying the second three-dimensional tensor by a second multi-dimensional tensor corresponding to the second qubit to obtain a second resulting tensor.
The system according to claim 4, wherein the processor is further configured to compress a size of the first resulting tensor and/or the second resulting tensor using singular value decomposition.
The system according to any one of claim 1 to claim 3, wherein the processor is further configured to conduct a two-qubit gate operation on a third qubit and a fourth qubit of which are two nearest-neighbor qubits by

determining a combined tensor based on a third multi-dimensional tensor corresponding to the third qubit and a fourth multi-dimensional tensor corresponding to the fourth qubit; determining a product based on the combined tensor and a four-dimensional tensor corresponding to the two-qubit gate operation; and using a decomposition method to decompose the product to obtain a third and a fourth resulting tensors corresponding to the third and the fourth qubits respectively.
The system according to any one of claim 4 to claim 6, wherein the processor is further configured to generate the N-qubit system based on a one-dimensional lattice, generate and store a canonical form of each multi-dimensional tensor corresponding to a qubit in the N-qubit system, store a singlular vector corresponding to each pair of nearest-neighbor points in the one-dimensional lattice, and conduct a gate operation on one or more than one qubit based on the canonical form of each corresponding multi-dimensional tensor.
The system according to claim 7, wherein the processor is further configured to generate and store a right-canonical form, a left-canonical form or a mixed canonical form of each multi-dimensional tensor corresponding to a qubit in the N-qubit system.
The system according to claim 8, wherein the processor is further configured to conduct a two-qubit gate operation on the first and the second qubits by

multiplying at least one of the first and the second resulting tensors by at least one singular vector associated with the first and the second qubits;

compressing and restoring the first and the second resulting tensors to a canonical form; and

using the canonical form of the first and the second resulting tensors to replace the first and the second multi-dimensional tensors.
The system according to claim 9, wherein the processor is further configured to generate and store a right-canonical form of each multi-dimensional tensor, and conduct a two-qubit gate operation on two nearest-neighbor qubits by multiplying the first resulting tensor by a left singular vector associated with the first and the second qubits; and restoring the the first and the second resulting tensors to a right-canonical form.
The system according to claim 9, wherein the processor is further configured to generate and store a left-canonical form of each multi-dimensional tensor, and conduct a two-qubit gate operation on two nearest-neighbor qubits by multiplying the second resulting tensor by a right singular vector associated with the first and the second qubits; and restoring the first and the second resulting tensors to a left-canonical form.
The system according to claim 9, wherein the processor is configured to generate and store a mixed-canonical form of each multi-dimensional tensor, and conduct a two-qubit gate operation on two nearest-neighbor qubits by multiplying each of the first and the second resulting tensors by at least one singular vecor associated with the first and the second qubits; and restoring the first and the second resulting tensors to a mixed-canonical form.
The system according to claim 8, wherein the processor is further configured to conduct a two-qubit gate operation on the third and the fourth qubits by determining the product based on a singular vector associated with the third and the fourth qubits;

restoring the third and fourth resulting tensors to a canonical form; and

using the canonical form of the third and fourth resulting tensors to replace the third and fourth multi-dimensional tensors.
The system according to claim 13, wherein the processor is further configured to generate and store a right-canonical form of each multi-dimensional tensor, and determine the product based on a left singular vector associated with the third and the fourth qubits, and

restore the third and the fourth resulting tensors to a right-canonical form.
The system according to claim 13, wherein the processor is further configured to generate and store a left-canonical form of each multi-dimensional tensor, and determine the product based on a right singular vector associated with the third and the fourth qubits; and

restore the third and the fourth resulting tensors to a left-canonical form.
The system according to claim 13, wherein the processor is further configured to generate and store a mixed-canonical form of each multi-dimensional tensor; determine the combined tensor based on a product of the third and the fourth multi-dimentional tensors and three singular vectors associated with the third and the fourth qubits; and restore the third and the fourth resulting tensors to a mixed-canonical form.
The system according to any one of claim 4 to claim 16, wherein the processor is further configured to conduct a two-qubit gate operation on two non-nearest-neighbor qubits by applying at least one SWAP gate operation to one of two multi-dimensional tensor corresponding to the two non-nearest-neighbor qubits to obtain two nearest-neighbor qubits; conducting the two-qubit gate operation on the obtained two nearest-neighbor qubits to obtain two resulting tensors corresponding to the two nearest-neighbor qubits; and applying at least one SWAP gate operation to one of the two resulting tensors to obtain two final resulting tensors corresponding to the two non-nearest neighbor qubits.
The system according to any preceding claim, wherein the processor is further configured to conduct a measurement on a qubit by

determining a probability of the qubit in a predetermined quantum state based on the multi-dimensional tensor corresponding to the qubit;

using the determined probability to randomly sample between 0 and 1 to obtain a measurement result; and

collapsing the qubit into a quantum state based on the measurement result.
The system according to claim 18, wherein the processor is further configured to determine a probability of the qubit in the predetermined quantum state by

applying a projection operator corresponding to the predetermined quantum state to the multi-dimensional tensor corresponding to the qubit to obtain an operated tensor; and

multiplying each multi-dimensional tensor corresponding to a qubit in the N-qubit system by a conjugate tensor thereof to determine a probability of the qubit in the predetermined quantum state, wherein the multi-dimensional tensor corresponding to the qubit is replaced with the operated tensor.
The system according to claim 18, wherein the processor is further configured to determine a probability of the qubit in the predetermined quantum state by

multiplying the multi-dimensional tensor corresponding to the qubit by a singular vector associated with the qubit; and

multiplying the product of the multi-dimensional tensor and the singular vector, by a conjugate of the product to determine the probability of the qubit in the predetermined quantum state, wherein the N-qubit system is generated based on a one-dimensional lattice and the multi-dimensional tensor corresponding to each qubit is stored in a canonical form.
The system according to claim 20, wherein the processor is further configured to determine a probability of the qubit in the predetermined quantum state by

multiplying the multi-dimensional tensor corresponding to the qubit by a left singular vector associated with the qubit if the multi-dimensional tensor corresponding to the qubit is stored in a right-canonical form.
The system according to claim 20, wherein the processor is further configured to determine a probability of the qubit in the predetermined quantum state by

multiplying the multi-dimensional tensor corresponding to the qubit by a right singular vector associated with the qubit if the multi-dimensional tensor corresponding to the qubit is stored in a left-canonical form.
The system according to claim 20, wherein the processor is further configured to determine a probability of the qubit in the predetermined quantum state by

multiplying the multi-dimensional tensor corresponding to the qubit by both a right singular vector and a left singular vector associated with the qubit if the multi-dimensional tensor corresponding to the qubit is stored in a mixed-canonical form.
The system according to any preceding claim, wherein the processor is further configured to determine the dimension of the multi-dimensional tensor corresponding to the qubit in the N-qubit system based on a physical dimension with a size of 2 indicating a quantum state of the corresponding qubit, and a plurality of auxiliary dimensions each corresponding to an edge of the two-dimensional lattice connecting to the qubit, wherein each auxiliary dimension has a size D which is to be changed with quantum gate operations, and wherein each multi-dimensional tensor has a maximum size of
wherein D _max refers to a maximum size of each auxiliary dimension, and m refers to a maximum value of the number of edges connecting to the point in the M-dimensional lattice corresponding to the qubit.
The system according to claim 24, wherein the processor is further configured to set an initial value of D as 1 and the size of each multi-dimensional tensor corresponding to the initial quantum state as 2.
The system according to claim 24, wherein if the M-dimensional lattice is a two dimensional rectangular lattice, m is 4; if the M-dimensional lattice is a two-dimensional triangular lattice, m is 6 and if the M-dimensional lattice is a two-dimensional hexagonal lattice, m is 3; if the M-dimensional lattice is a one-dimensional lattice, m is 2.
A method for quantum circuit simulation, the method comprising:

generating, by a processor in a computer system, an N-qubit system based on a M-dimensional lattice, wherein N and M are positive integers, and each qubit in the N-qubit system comprises a pair of indexes corresponding to a point on the M-dimensional lattice;

generating, by the processor, N multi-dimensional tensors, each multi-dimensional tensor corresponding to a qubit in the N-qubit system and including a dimension which is determined based on the M-dimensional lattice;

conducting, by the processor, a gate operation on one or more than one qubit in the N-qubit system based on the multi-dimensional tensor corresponding to each of the one or more than one qubit; and

conducting, by the processor, a measurement on a qubit in the N-qubit system based on the multi-dimensional tensor corresponding to the qubit.
The method according to claim 27, further comprising: determining, by the processor, the dimension of the multi-dimensional tensor corresponding to each of the qubits in the N-qubit system based on a number of edges of the M-dimensional lattice connecting to the each of the qubits.
The method according to claim 27, wherein the step of conducting a gate operation on one or more than one qubit comprising:

conducting, by the processor, a single-qubit gate operation on a qubit in the N-qubit system by multiplying a M-dimensional tensor corresponding to the single-qubit gate operation by the multi-dimensional tensor corresponding to the qubit.
The method according to any one of claim 27 to claim 29, wherein the step of conducting a gate operation on one or more than one qubit further comprising:

conducting, by the processor, a two-qubit gate operation on a first qubit and a second qubit which are two nearest-neighbor qubits by decomposing a four-dimensional tensor corresponding to the two-qubit gate operation into a first three-dimensional tensor corresponding to the first qubit and a second three-dimensional tensor corresponding to the second qubit, and

multiplying the first three-dimensional tensor by a first multi-dimensional tensor corresponding to the first qubit to obtain a first resulting tensor and multiplying the second three-dimensional tensor by a second multi-dimensional tensor corresponding to the second qubit to obtain a second resulting tensor.
The method according to claim 30, further comprising:

compressing, by the processor, a size of the first resulting tensor and/or the second resulting tensor using a singular value decomposition.
The method according to any one of claim 27 to claim 29, wherein the step of conducting a gate operation on one or more than one qubit further comprising:

conducting, by the processor, a two-qubit gate operation on a third qubit and a fourth qubit which are two nearest-neighbor qubits by determining a combined tensor based on a third multi-dimensional tensor corresponding to the third qubit and a fourth multi-dimensional tensor corresponding to the fourth qubit; determining a product based on the combined tensor and a four-dimensional tensor corresponding to the two-qubit gate operation, and using a decomposition method to decompose the product to obtain a third and a fourth resulting sensors corresponding to the third and the fourth qubits respectively.
The method according to any one of claim 30 to claim 32, wherein the step of generating an N-qubit system comprises: generating, by the processor, the N-qubit system based on a one-dimensional lattice, wherein the method further comprises:

generating and storing, by the processor, a canonical form of each multi-dimensional tensor corresponding to a qubit in the N-qubit system,

wherein the step of conducting the gate operation and measurement comprises: conducting, by the processor, the gate operation and the measurement based on the canonical form of each corresponding multi-dimensional tensor.
The method according to claim 33, wherein the step of generating and storing a canonical form of each multi-dimensional tensor comprises: generating and storing, by the processor, a right-canonical form, a left-canonical form or a mixed canonical form of each multi-dimensional tensor corresponding to a qubit in the N-qubit system.
The method according to claim 34, wherein the step of conducting a gate operation comprises: conducting a two-qubit operation on the first and the second qubits by multiplying at least one of the first and the second resulting tensors by at least one singular vector associated with the first and the second qubits; compressing and restoring the first and the second resulting tensors to a canonical form; and using the canonical form of the first and the second resulting tensors to replace the first and the second multi-dimensional tensors.
The method according to claim 35, wherein the step of generating and storing a canonical form of each multi-dimensional tensor comprises: generating and storing, by the processor, a right-canonical form of each multi-dimensional tensor;

wherein the step of conducting the two-qubit gate operation on two nearest-neighbor qubits comprises: multiplying the first resulting tensor by a left singular vector associated with the first and the second qubits; and restoring the first and the second resulting tensors to a right-canonical form.
The method according to claim 35, wherein the step of generating and storing a canonical form of each multi-dimensional tensor comprises: generating and storing, by the processor, a left-canonical form of each multi-dimensional tensor;

wherein the step of conducting the two-qubit gate operation on two nearest-neighbor qubits comprises: multiplying the second resulting tensor by a right singular vector associated with the first and the second qubits; and restoring the first and the second resulting tensors to a left-canonical form.
The method according to claim 35, wherein the step of generating and storing a canonical form of each multi-dimensional tensor comprises: generating and storing, by the processor, a mixed-canonical form of each multi-dimensional tensor;

wherein the step of conducting the two-qubit gate operation on two nearest-neighbor qubits comprises: multiplying each of the first and the second resulting tensors by at least one singular vecor associated with the first and the second qubits; and restoring the first and the second resulting tensors to a mixed-canonical form.
The method according to claim 34, wherein the step of conducting a gate operation comprises: conducting a two-qubit gate operation on the third and the fourth qubits by determining the product based on a singular vector associated with the third and the fourth qubits, restoring the third and the fourth resulting tensors to a canonical form, and using the canonical form of the third and the fourth resulting tensors to replace the third and the fourth multi-dimensional tensors.
The method according to claim 39, wherein the step of generating and storing a canonical form of each multi-dimensional tensor comprises: generating and storing, by the processor, a right-canonical form of each multi-dimensional tensor;

wherein the step of conducting the two-qubit gate operation on two nearest- neighbor qubits further comprises: determining the product based on a left singular vector associated with the third and the fourth qubits, and restoring the third and the fourth resulting tensors to a right-canonical form.
The method according to claim 39, wherein the step of generating and storing a canonical form of each multi-dimensional tensor comprises: generating and storing, by the processor, a left-canonical form of each multi-dimensional tensor;

wherein the step of conducting the two-qubit gate operation on two nearest-neighbor qubits comprises: determining the product based on a right singular vector associated with the third and the fourth qubits, and restoring the third and the fourth resulting tensors to a left-canonical form.
The method according to claim 39, wherein the step of generating and storing a canonical form of each multi-dimensional tensor comprises: generating and storing, by the processor, a mixed-canonical form of each multi-dimensional tensor;

wherein the step of conducting the two-qubit gate operation on two nearest-neighbor qubits comprises: determining the combined tensor based on a product of the third and the fourth multi-dimensional tensors and three singular vectors associated with the third and the fourth qubits; and restoring the third and the fourth resulting tensors to a mixed-canonical form.
The method according to any one of claim 30 to claim 42, wherein the step of conducting a gate operation on one or more than one qubit further comprising:

applying at least one SWAP gate operation to one of two multi-dimensional tensor corresponding to the two non-nearest-neighbor qubits to obtain two nearest-neighbor qubits; conducting the two-qubit gate operation on the obtained two nearest-neighbor qubits to obtain two resulting tensors corresponding to the two nearest-neighbor qubits; and applying at least one SWAP gate operation to one of the two resulting tensors to obtain two final resulting tensors corresponding to the two non-nearest neighbor qubits.
The method according to any one of claim 27 to claim 43, wherein the step of conducting a measurement on a qubit comprises:

determining, by the processor, a probability of the qubit in a predetermined quantum state based on the multi-dimensional tensor corresponding to the qubit;

using, by the processor, the determined probability to randomly sample between 0 and 1 to obtain a measurement result; and

collapsing, by the processor, the qubit into a quantum state based on the measurement result.
The method according to claim 44, wherein the step of determining a probability of the qubit in the predetermined quantum state comprises:

applying, by the processor, a projection operator corresponding to the predetermined quantum state to a multi-dimensional tensor corresponding to the qubit; and

multiplying, by the processor, each multi-dimensional tensor corresponding to a qubit in the N-qubit system by a conjugate tensor thereof to determine the probability of the qubit in the predetermined quantum state.
The method according to claim 44, wherein the step of determining a probability of the qubit in the predetermined quantum state comprises:

multiplying, by the processor, the multi-dimensional tensor corresponding to the qubit by a singular vector associated with the qubit; and

multiplying, by the processor, the product of the multi-dimensional tensor and the singular vector, by a conjugate of the product to determine the probability of the qubit in the predetermined quantum state, wherein the N-qubit system is generated based on a one-dimensional lattice and the multi-dimensional tensor corresponding to each qubit is stored in a canonical form.
The method according to claim 46, wherein the step of determining the probability of the qubit in the predetermined quantum state further comprises:

multiplying the multi-dimensional tensor corresponding to the qubit by a left singular vector associated with the qubit if the multi-dimensional tensor corresponding to the qubit is stored in a right-canonical form.
The method according to claim 46, wherein the step of determining the probability of the qubit in the predetermined quantum state further comprises:

multiplying the multi-dimensional tensor corresponding to the qubit by a right singular vector associated with the qubit if the multi-dimensional tensor corresponding to the qubit is stored in a left-canonical form.
The method according to claim 46, wherein the step of determining the probability of the qubit in the predetermined quantum state further comprises:

multiplying the multi-dimensional tensor corresponding to the qubit by both a right singular vector and a left singular vector associated with the qubit if the multi-dimensional tensor corresponding to the qubit is stored in a mixed-canonical form.
The method according to any one of claim 27 to claim 49, wherein each multi-dimensional tensor corresponding to a qubit in the N-qubit system includes a physical dimension with a size of 2 indicating a quantum state of the corresponding qubit, and a plurality of auxiliary dimensions each corresponding to an edge of the two-dimensional lattice connecting to the qubit, wherein each auxiliary dimension has a size D which is to be changed with quantum gate operations, and wherein each multi-dimensional tensor has a maximum size of
wherein D _max refers to a maximum size of each auxiliary dimension, and m refers to a maximum value of the number of edges connecting to the point in the M-dimensional lattice corresponding to the qubit.
The method according to claim 50, further comprising: setting, by the processor, an initial value of D as 1 and the size of each multi-dimensional tensor corresponding to the initial quantum state as 2.
The method according to claim 50 or claim 51, wherein if the M-dimensional lattice is a two-dimensional rectangular lattice, m is 4; if the M-dimensional lattice is a two-dimensional triangular lattice, m is 6 and if the M-dimensional lattice is a two-dimensional hexagonal lattice, m is 3; if the M-dimensional lattice is a one-dimensional lattice, m is 2.
A non-transitory computer readable medium comprising computer program code for simulating a quantum circuit, wherein the computer program code, when executed, is configured to cause a processor in a computer system to perform a method according to any one of claim 27 to claim 52.