WO2020220814A1

WO2020220814A1 - Array substrate and manufacture method therefor, display panel and display device

Info

Publication number: WO2020220814A1
Application number: PCT/CN2020/077136
Authority: WO
Inventors: 李蒙; 李永谦; 孟松
Original assignee: 京东方科技集团股份有限公司; 合肥鑫晟光电科技有限公司
Priority date: 2019-04-29
Filing date: 2020-02-28
Publication date: 2020-11-05
Also published as: CN111863834B; CN111863834A

Abstract

Disclosed are an array substrate and a manufacture method therefor, a display panel and a display device. The array substrate comprises a base substrate, a plurality of sub-pixel groups arranged in array along a row direction and a column direction on the base substrate, and gate lines extending along the row direction. The gate line comprises a first gate line and a second gate line located on the same side of the sub-pixel which is connected to the first gate line group. A part of sub-pixels include a first thin film transistor and a second thin film transistor. The first thin film transistor is connected to the first gate line and the second thin film transistor is connected to the second gate line; and a channel region of the first thin film transistor and a channel region of the second thin film transistor are located on the side of the first gate line group close to the sub-pixels which are connected to the first gate line group. According to the array substrate, the channel region of the first thin film transistor and the channel region of the second thin film transistor are both arranged on the side of the first gate line group close to the sub-pixels which are connected to the first gate line group, thereby reducing the distance between the first gate line and the second gate line and saving the wiring space.

Description

Array substrate and manufacturing method thereof, display panel and display device

Technical field

At least one embodiment of the present disclosure relates to an array substrate and a manufacturing method thereof, a display panel, and a display device.

Background technique

The current mainstream display screen resolutions are 2k (1920*1080) and 4k (3810*2160), but with the continuous increase in display size, even 4k resolution display screens cannot meet people's needs. Therefore, the 8k (7680*4320) resolution display screen will be the future development direction.

Summary of the invention

At least one embodiment of the present disclosure provides an array substrate, a manufacturing method thereof, a display panel, and a display device. The array substrate includes: a base substrate; a plurality of sub-pixel groups arranged in an array along a row direction and a column direction on the base substrate, each of the sub-pixel groups including a plurality of sub-pixels; and a base substrate On the gate line extending along the row direction, the gate line includes a first gate line group, and the first gate line group includes first gate lines on the same side of the sub-pixels connected to the first gate line group. The gate line and the second gate line, wherein at least some of the sub-pixels in the plurality of sub-pixels include a first thin film transistor and a second thin film transistor, which are connected to the sub-pixels of the first gate line group, and the first The thin film transistor is connected to the first gate line, the second thin film transistor is connected to the second gate line, and the channel region of the first thin film transistor and the channel region of the second thin film transistor are both located The side of the first gate line group close to the sub-pixel connected to the first gate line group.

For example, the distance between the first grid line and the second grid line is 3 micrometers to 12 micrometers.

For example, the width of at least one of the first gate line and the second gate line is 3 micrometers to 3.5 micrometers.

For example, the gate line further includes a second gate line group, and the first gate line group and the second gate line group are respectively located on both sides of each row of the sub-pixel group in the column direction to make the The sub-pixel groups in two adjacent rows include the first gate line group and the second gate line group, and the second gate line group includes a third gate line and a fourth gate line; In the sub-pixels of the second gate line group, the first thin film transistor is connected to the third gate line, the second thin film transistor is connected to the fourth gate line, and the first thin film transistor The channel region of and the channel region of the second thin film transistor are both located on the side of the second gate line group close to the sub-pixel connected to the second gate line group.

For example, the distance between the third grid line and the fourth grid line is 3 micrometers to 12 micrometers.

For example, along the column direction, the sequence of the first gate line and the second gate line is the same as the sequence of the third gate line and the fourth gate line.

For example, the sub-pixel group includes two rows of sub-pixels, each of the two rows of sub-pixels includes a first-color sub-pixel, a second-color sub-pixel, and a third-color sub-pixel, and the color of each sub-pixel is different from that in the row. The color of the adjacent sub-pixels in the direction or column direction, and along the row direction, the second row of sub-pixels and the first row of sub-pixels are offset from each other by a pitch of less than one sub-pixel; the array substrate further includes: For the data lines on the base substrate, each column of the sub-pixel group corresponds to three data lines, and each of the three data lines corresponds to the phase of the sub-pixels in different rows of each sub-pixel group. Two adjacent sub-pixels of different colors are connected, and the first electrode of the first thin film transistor of the sub-pixel is connected to the data line.

For example, the width of each of the data lines is 3.5 micrometers to 4 micrometers.

For example, the array substrate further includes: a source-drain metal layer located on the base substrate, the source-drain metal layer including the data line; and a semiconductor layer located on a side of the data line close to the base substrate , Including a conductive first part, wherein the source and drain metal layers are connected to the first part of the semiconductor layer through a first connection hole to form a second electrode of the first thin film transistor, and The first connection hole is located on the side of the first gate line group close to the sub-pixel connected to it, or on the side of the second gate line group close to the sub-pixel connected to it.

For example, the gate of one of the first thin film transistor and the second thin film transistor in the sub-pixel is connected to the gate line through the source-drain metal layer.

For example, the array substrate further includes a sensing line, wherein each column of the sub-pixel group corresponds to two sensing lines, and each of the sensing lines corresponds to each sub-pixel group in a different row of sub-pixels. Three adjacent sub-pixels of different colors are connected, and the first electrode of the second thin film transistor of the sub-pixel is connected to the sensing line.

For example, the semiconductor layer further includes a second portion that is conductive, and the source/drain metal layer is connected to the second portion of the semiconductor layer through a second connection hole to form a second portion of the second thin film transistor. One pole, and the second connection hole is located on the side of the first gate line group close to the sub-pixel connected to the first gate line group, or located close to the second gate line group One side of the sub-pixel connected to the second gate line group.

For example, the array substrate further includes a light-shielding layer located on the side of the sensing line facing the base substrate, wherein each sensing line includes a plurality of sub-sensing lines and connecting two adjacent sub-sensing lines. A connecting line of the sensing line, each of the sub-sensing lines corresponds to one of the sub-pixel groups, the connecting line is located between two adjacent sub-pixel groups arranged along the column direction, the The orthographic projection of the connecting wire on the base substrate overlaps the orthographic projection of the data wire on the base substrate, and a part of the light shielding layer is multiplexed as the connecting wire.

For example, the array substrate further includes a power supply line, wherein each of the sub-pixels further includes a light-emitting element, a driving transistor, and a storage capacitor, and the semiconductor layer further includes a third portion that is conductive; the second thin film transistor The second electrode is connected to the light emitting element; the gate of the driving transistor is connected to the second electrode of the first thin film transistor, the first electrode of the driving transistor is connected to the power line, and the The second electrode is connected to the light-emitting element, wherein the first electrode of the driving transistor of at least one of the sub-pixels is connected to the power supply line through the third portion of the semiconductor layer; The first electrode is connected to the gate of the driving transistor, and the second electrode of the storage capacitor is connected to the second electrode of the driving transistor.

For example, the two sensing lines include a first sensing line and a second sensing line, and the first sensing line is located in the first color sub-pixel in the first row and the second sensing line in the first row. Between the color sub-pixels, and between the third color sub-pixels in the second row and the first color sub-pixels in the second row, the first sensing line and the first color sub-pixels in the first row The color sub-pixels, the second color sub-pixels in the first row, and the third color sub-pixels in the second row are connected; the second sensing line is located between the second color sub-pixels in the first row and the Between the third color sub-pixels in one row and between the first color sub-pixels in the second row and the second color sub-pixels in the second row, the second sensing line is The second color sub-pixels in one row, the third color sub-pixels in the first row, and the first color sub-pixels in the second row are connected.

For example, each of the first sensing line and the second sensing line includes a plurality of sub-sensing lines and a connecting line connecting two adjacent sub-sensing lines, and the first sensing line The sub-sensing lines included in the line are connected to the first-color sub-pixels in the first row and the second-color sub-pixels in the first row through the connecting lines; all the sub-sensing lines included in the second sensing line The sub-sensing line is connected to the first color sub-pixel in the second row and the second color sub-pixel in the second row through the connecting line.

At least one embodiment of the present disclosure provides a display panel including the above-mentioned array substrate.

At least one embodiment of the present disclosure provides a display device including the above-mentioned display panel.

For example, the display device is an organic light emitting diode display device, and the resolution of the display device is 8k.

At least one embodiment of the present disclosure provides a method for manufacturing an array substrate, including: forming a plurality of sub-pixel groups arranged in an array along a row direction and a column direction on a base substrate, each of the sub-pixel groups including a plurality of sub-pixels Forming a gate line extending in the row direction on the base substrate, forming the gate line includes forming a first gate line group, and the first gate line group includes the first gate line group connected to The first gate line and the second gate line on the same side of the sub-pixel. Forming at least one sub-pixel of the plurality of sub-pixels includes forming a first thin film transistor and a second thin film transistor, which are connected to the sub-pixels of the first gate line group, the first thin film transistor and the second thin film transistor. A gate line is connected, the second thin film transistor is connected to the second gate line, and the channel region of the first thin film transistor and the channel region of the second thin film transistor are both formed on the first gate A side of the line group close to the sub-pixel connected to the first gate line group.

For example, forming the gate line further includes: forming a second gate line group, and the first gate line group and the second gate line group are respectively formed on two rows of the sub-pixel group in the column direction. Side, and forming the second gate line group includes forming a third gate line and a fourth gate line. In the sub-pixels connected to the second gate line group, the first thin film transistor is connected to the third gate line, the second thin film transistor is connected to the fourth gate line, and the first thin film transistor is connected to the fourth gate line. The channel region of a thin film transistor and the channel region of the second thin film transistor are both formed on the side of the second gate line group close to the sub-pixel connected to the second gate line group.

For example, the manufacturing method further includes: forming a data line on the base substrate. Forming the first thin film transistor, the second thin film transistor, and the data line includes: forming a semiconductor layer on the base substrate; conducting a conductive process on the first part and the second part of the semiconductor layer to form A first conductive region and a second conductive region; an insulating layer is formed on the side of the semiconductor layer away from the base substrate, and the insulating layer includes a first connection hole and a second connection hole; in the insulating layer A source-drain metal layer is formed on the side away from the semiconductor layer, wherein the source-drain metal layer is connected to the first conductive region through the first connection hole to form the second electrode of the first thin film transistor , And the first connection hole is located on the side of the first gate line group close to the sub-pixels connected to the first gate line group, or located close to the second gate line group and the One side of the sub-pixel connected to the second gate line group; the source and drain metal layers are connected to the second conductive area through the second connection hole to form the first electrode of the second thin film transistor, And the second connection hole is located on the side of the first gate line group close to the sub-pixel connected to the first gate line group, or located close to the second gate line group and the first gate line group. One side of the sub-pixel connected by the two gate line groups; and patterning the source and drain metal layer to form the data line.

At least one embodiment of the present disclosure provides an array substrate, including: a base substrate; a plurality of sub-pixel groups located on the base substrate, at least one sub-pixel group of the plurality of sub-pixel groups includes two rows of sub-pixels , The first row of sub-pixels sequentially includes a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel along the first direction, and the second row of sub-pixels sequentially includes the third color sub-pixel along the first direction , The first color sub-pixels and the second color sub-pixels, and along the first direction, the second row of sub-pixels and the first row of sub-pixels are staggered from each other; located on the base substrate The at least one sub-pixel group corresponds to three data lines in the plurality of data lines, and each of the three data lines is different from a row in the at least one sub-pixel group Two adjacent sub-pixels of different colors in the sub-pixels are connected; the extending direction of the plurality of data lines intersects the first direction; and the plurality of gate lines located on the base substrate, the The plurality of gate lines includes a first gate line group and a second gate line group respectively located on both sides of the sub-pixel group, and both the first gate line group and the second gate line group include at least one gate line; The plurality of gate lines extend along the first direction. At least some of the sub-pixels include a first thin film transistor and a second thin film transistor, and the first thin film transistor and the second thin film transistor of a row of sub pixels adjacent to the first gate line group are both connected to the first gate line group, Both the first thin film transistor and the second thin film transistor of a row of sub-pixels adjacent to the second gate line group are connected to the second gate line group.

For example, the first gate line group includes a first gate line and a second gate line that do not cross each other, and the second gate line group includes a third gate line and a fourth gate line that do not cross each other, and the same sub-pixel It includes that the first thin film transistor and the second thin film transistor are connected to different gate lines in the same gate line group.

For example, the array substrate further includes: a plurality of sensing lines on the base substrate, wherein the at least one sub-pixel group corresponds to two sensing lines, and each of the two sensing lines The survey line is connected to three adjacent sub-pixels of different colors among the sub-pixels of different rows in the at least one sub-pixel group.

For example, the first electrode of the first thin film transistor is connected to one of the three data lines, and the first electrode of the second thin film transistor is connected to one of the two sensing lines .

For example, the two sensing lines include a first sensing line and a second sensing line, and the first sensing line is located in the first color sub-pixel and the first row of the at least one sub-pixel group. Between the second color sub-pixels in the first row and between the third color sub-pixels in the second row and the first color sub-pixels in the second row, and the first sensing line Connected to the first color sub-pixels in the first row, the second color sub-pixels in the first row, and the third color sub-pixels in the second row; the second sensing line is located in the at least one Between the second-color sub-pixels in the first row and the third-color sub-pixels in the first row in the sub-pixel group, and located between the first-color sub-pixels in the second row and the second row Between the second color sub-pixels, and the second sensing line and the third color sub-pixels in the first row, the first color sub-pixels in the second row, and the second color in the second row Sub-pixel connection.

For example, the array substrate further includes a light shielding layer located on the side of the sensing line and the data line facing the base substrate. The first sensing line is connected to the first color sub-pixels in the first row through a first sensing line connecting part, and the orthographic projection of the first sensing line connecting part on the base substrate is consistent with the The orthographic projection of the data line on the base substrate overlaps, and a part of the light shielding layer is multiplexed as the first sensing line connection part; the second sensing line passes through the second sensing line The connecting portion is connected to the second color sub-pixels in the second row, the second sensing line connecting portion and the gate line are provided in the same layer, and the second sensing line connecting portion is on the base substrate The orthographic projection of the data line overlaps the orthographic projection of the data line on the base substrate.

For example, the three data lines corresponding to the at least one sub-pixel group include a first data line, a second data line, and a third data line, and the first data line is located in the first row of the at least one sub-pixel group. Between the first color sub-pixel and the second color sub-pixel in the first row, and the third color sub-pixel in the second row is far from one of the first color sub-pixels in the second row Side; the second data line is located between the second color sub-pixel in the first row and the third color sub-pixel in the first row in the at least one sub-pixel group, and is located in all the second row Between the third color sub-pixels and the first color sub-pixels in the second row; the third data line is located in the at least one sub-pixel group and the third color sub-pixels in the first row are far from the first One side of the second color sub-pixels of the row is located between the first color sub-pixels of the second row and the second color sub-pixels of the second row.

For example, the first data line is connected to the first color sub-pixel in the first row and the third color sub-pixel in the second row; the second data line is connected to the second color in the first row The sub-pixels are connected to the first color sub-pixels in the second row; the third data line is connected to the third color sub-pixels in the first row and the second color sub-pixels in the second row.

For example, the orthographic projection of the second electrode of the first thin film transistor on the base substrate overlaps the orthographic projection of the second gate line on the base substrate.

For example, the array substrate further includes: a plurality of power lines located on the base substrate, wherein the at least one sub-pixel group corresponds to two power lines of the plurality of power lines, and the two power lines Each power supply line in is connected to three adjacent sub-pixels of different colors among the sub-pixels of different rows in the at least one sub-pixel group.

For example, the at least part of the sub-pixels further includes a light-emitting element, and the second electrode of the second thin film transistor is connected to the light-emitting element.

For example, the at least part of the sub-pixels further includes a driving transistor and a storage capacitor, the gate of the driving transistor is connected to the second electrode of the first thin film transistor, and the first electrode of the driving transistor is connected to the two power supplies. One of the lines is connected, the second electrode of the drive transistor is connected to the light emitting element; the first electrode of the storage capacitor is connected to the gate of the drive transistor, and the second electrode of the storage capacitor is connected to the drive The second pole of the transistor is connected.

For example, the array substrate further includes a semiconductor layer, which is located on a side of the data line close to the base substrate and includes a conductive part, wherein the power line passes through the conductive part in the semiconductor layer. Partly connected to the first pole of the driving transistor.

For example, in the at least one sub-pixel group, along the first direction, the second row of sub-pixels and the first row of sub-pixels are offset from each other by less than one sub-pixel pitch, and the first row of sub-pixels The distance between the centers of two adjacent sub-pixels in the pixel is equal to the distance between the centers of two adjacent sub-pixels in the second row of sub-pixels.

For example, in the at least one sub-pixel group, the distance between the center of the third-color sub-pixel in one row and the center of the first-color sub-pixel and the center of the second-color sub-pixel in another row is equal.

For example, the first color subpixel, the second color subpixel, and the third color subpixel include a red subpixel, a green subpixel, and a blue subpixel.

Description of the drawings

In order to explain the technical solutions of the embodiments of the present disclosure more clearly, the following will briefly introduce the drawings of the embodiments. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limit the present disclosure. .

1A is a schematic diagram of a partial structure of an array substrate provided by an embodiment of the present disclosure;

FIG. 1B is a schematic diagram of a pixel circuit structure in a sub-pixel in the array substrate shown in FIG. 1A;

FIG. 1C is a schematic diagram of a sub-pixel group and a signal line connected to the sub-pixel group in an array substrate provided by an embodiment of the present disclosure;

FIG. 1D is a circuit layout including the sub-pixel group shown in FIG. 1C;

1E is a schematic diagram of the circuit layout matrix arrangement shown in FIG. 1D;

2A is a schematic diagram of a partial structure of an array substrate provided by another embodiment of the present disclosure;

2B is a schematic diagram of a partial structure of an array substrate provided by another embodiment of the present disclosure;

FIG. 2C is a schematic diagram of a pixel layout of a sub-pixel group in the array substrate shown in FIG. 2B; and

FIG. 3 is a schematic diagram of a pixel layout corresponding to the sub-pixel group shown in FIG. 2B.

Detailed ways

In order to make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be described clearly and completely in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only a part of the exemplary embodiments of the present invention, rather than all the embodiments. Based on the described exemplary embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the protection scope of the present invention.

Unless otherwise defined, the technical terms or scientific terms used herein shall be the ordinary meanings understood by those with ordinary skills in the field to which the present invention belongs. The "first", "second" and similar words used in the specification and claims of the patent application of the present invention do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "a", "one" or "the" do not mean quantity limitation, but mean that there is at least one. "Include" or "include" and other similar words mean that the element or item appearing before the word encompasses the element or item listed after the word and its equivalents, but does not exclude other elements or items. "Up", "Down", etc. are only used to indicate the relative position relationship. When the absolute position of the object being described changes, the relative position relationship may also change accordingly.

During the research, the inventor of the present application found that in the current display field, the number of display devices with a resolution of 8K is relatively small. Because the organic light emitting diode display device with a resolution of 8K is difficult to process, the pixel arrangement space is limited, and the manufacturing cost is too high, mass production has not yet been carried out.

At least one embodiment of the present disclosure provides an array substrate, a manufacturing method thereof, a display panel, and a display device.

At least one embodiment of the present disclosure provides an array substrate, including: a base substrate; a plurality of sub-pixel groups arranged in a row direction and a column direction on the base substrate; and a row direction on the base substrate The extended gate line. Each sub-pixel group includes a plurality of sub-pixels connected to a gate line; the gate line includes a first gate line group, and the first gate line group includes a first gate line and a second gate line on the same side of the sub-pixels connected to the first gate line group. Two gate lines. At least part of the plurality of sub-pixels includes a first thin film transistor and a second thin film transistor, connected to the sub-pixels of the first gate line group, the first thin film transistor is connected to the first gate line, and the second thin film transistor is connected to the second gate line And the channel region of the first thin film transistor and the channel region of the second thin film transistor are both located on the side of the first gate line group close to the sub-pixel connected to it. In the array substrate provided by this embodiment of the present disclosure, the channel region of the first thin film transistor and the channel region of the second thin film transistor are both arranged on the side of the first gate line group close to the sub-pixel connected to it, which can reduce The distance between the first gate line and the second gate line is to save wiring space. On the basis of ensuring the capacitance area, the line width of at least one of the first gate line and the second gate line can also be increased to reduce its resistance. The process difficulty is reduced, thereby saving the cost of the high-resolution display device including the array substrate.

At least one embodiment of the present disclosure further provides an array substrate including: a plurality of sub-pixel groups, at least one sub-pixel group in the plurality of sub-pixel groups includes two rows of sub-pixels, and the first row of sub-pixels is sequentially along a first direction It includes a first color subpixel, a second color subpixel, and a third color subpixel. The second row of subpixels includes the third color subpixel, the first color subpixel, and the The second color sub-pixels, and along the first direction, the second row of sub-pixels and the first row of sub-pixels are staggered from each other; multiple data lines, and the at least one sub-pixel group corresponds to the multiple data Three data lines in the line, and each of the three data lines is connected to two adjacent sub-pixels of different colors in different rows of sub-pixels in the at least one sub-pixel group, the plurality of data lines The extension direction intersects the first direction; a plurality of gate lines, the plurality of gate lines include a first gate line group and a second gate line group respectively located on both sides of the sub-pixel group in each row, the first Both a gate line group and the second gate line group include at least one gate line, and the plurality of gate lines extend along the first direction. At least some of the sub-pixels include a first thin film transistor and a second thin film transistor, and the first thin film transistor and the second thin film transistor of a row of sub pixels adjacent to the first gate line group are both connected to the first gate line group, Both the first thin film transistor and the second thin film transistor of a row of sub-pixels adjacent to the second gate line group are connected to the second gate line group. The array substrate provided by this embodiment of the present disclosure can save the number of data lines and effectively utilize the wiring space, so as to reduce the cost of a high-resolution display device including the array substrate.

The array substrate, its manufacturing method, display panel, and display device provided by the embodiments of the present disclosure will be described in more detail below in conjunction with the accompanying drawings.

At least one embodiment of the present disclosure provides an array substrate. FIG. 1A is a schematic diagram of a partial structure of an array substrate provided by an embodiment of the disclosure. As shown in FIG. 1A, the array substrate includes a base substrate 1010, and a plurality of sub-pixel groups 1000 arranged in an array along the row direction (ie X direction) and column direction (ie Y direction) on the base substrate 1010. The pixel group 1000 includes two rows of sub-pixels, and the number of sub-pixels in each row is, for example, three. The first row of sub-pixels includes the first color sub-pixel 1100, the second color sub-pixel 1200, and the third color sub-pixel 1300 in the first direction (the direction pointed by the arrow in the X direction); The direction includes the third color sub-pixel 1300, the first color sub-pixel 1100, and the second color sub-pixel 1200 in sequence. The distance between the centers of two adjacent sub-pixels in the first row of sub-pixels is equal to the distance between the centers of two adjacent sub-pixels in the second row of sub-pixels. The "center" in the embodiments of the present disclosure refers to the geometric center of the sub-pixel. Along the first direction, the distance D between the second row of sub-pixels and the first row of sub-pixels is less than the pitch of one sub-pixel, that is, the first row of sub-pixels and the second row of sub-pixels have a certain offset along the row direction, The two rows of sub-pixels are not aligned along the column direction. For example, the third color sub-pixel 1300 in the second row and the first color sub-pixel 1100 in the first row are offset from each other by less than one sub-pixel in the first direction, and the first color sub-pixel 1100 in the second row is offset from the first color sub-pixel 1100 in the second row. The second-color sub-pixels 1200 in the second row are offset from each other by less than one sub-pixel in the first direction, and the second-color sub-pixels 1200 in the second row and the third-color sub-pixels 1300 in the first row are offset from each other by less than The pitch of one sub-pixel.

As shown in FIG. 1A, the third color sub-pixel 1300 in the first row of sub-pixels and the first color sub-pixel 1100 and the second color sub-pixel 1200 in the second row of sub-pixels are arranged in a triangular pixel arrangement (for example, positive The triangular pixel arrangement). Similarly, the remaining three different-color sub-pixels in the sub-pixel group 1000 (ie, the first-color sub-pixel 1100 and the second-color sub-pixel 1200 in the first row of sub-pixels and the third-color sub-pixel in the second row of sub-pixels The arrangement of the sub-pixels 1300) is also a triangular pixel arrangement (for example, an inverted triangular pixel arrangement).

For example, as shown in FIG. 1A, each row of sub-pixels in each pixel group 1000 includes a first-color sub-pixel 1100, a second-color sub-pixel 1200, and a third-color sub-pixel 1300; each sub-pixel and adjacent sub-pixels (Here the adjacent sub-pixels refer to two adjacent sub-pixels in the same row or in different rows); and the center of the third-color sub-pixel 1300 in the first row of sub-pixels is away from the other two sub-pixels in the second row The distance between the centers of the two color sub-pixels is approximately the same, and the distance between the center of the third color sub-pixel 1300 in the second row of sub-pixels and the centers of the other two color sub-pixels in the first row is approximately the same. That is, the distance between the center of the third color sub-pixel 1300 in one row and the center of the first color sub-pixel 1100 and the center of the second color sub-pixel 1200 in another row is approximately the same.

For example, as shown in FIG. 1A, the first color sub pixel 1100, the second color sub pixel 1200, and the third color sub pixel 1300 are respectively a red sub pixel, a green sub pixel and a blue sub pixel.

For example, when the array substrate provided by at least one embodiment of the present disclosure is applied to a display device with a resolution of 8k, due to the large number of pixels, the display is sufficiently delicate and the graininess is reduced. Therefore, even if each sub-pixel group shown in FIG. 1A is The sub-pixels of the same color are not located on the same straight line extending along the Y direction, and will not affect the display.

As shown in FIG. 1A, the array substrate provided by the embodiment of the present disclosure further includes a plurality of data lines 2000 extending along the column direction on the base substrate 101, and at least one column of sub-pixel groups 1000 corresponds to three data lines 2000. For example, each column of sub-pixel group 1000 corresponds to three data lines 2000, and each data line is connected to two adjacent sub-pixels of different colors in different rows of sub-pixels in each sub-pixel group 1000.

For example, the array substrate further includes a plurality of gate lines 3000 extending in the row direction on the base substrate 1010, and the plurality of gate lines 3000 include first gate line groups located on both sides of each row of sub-pixel groups 1000 in the column direction. 3100 and the second gate line group 3200, two adjacent rows of sub-pixel groups 1000 include the first gate line group 3100 and the second gate line group 3200. In the embodiment of the present disclosure, the first gate line group 3100 includes at least one gate line, and the second gate line group 3200 includes at least one gate line. Therefore, the embodiment of the present disclosure adopts a dual gate technology, which reduces the number of data lines 2000 by half and doubles the number of gate lines 3000 to save costs.

For example, as shown in FIG. 1A, the six sub-pixels included in each column of the sub-pixel group 1000 are located in six sub-pixel columns. The six sub-pixel columns include two columns of first-color sub-pixels 1100, two columns of second-color sub-pixels 1200, and two columns. The third color sub-pixel 1300. Since each data line 2000 is connected to two adjacent sub-pixels of different colors in different rows of sub-pixels in each sub-pixel group 1000, every two sub-pixel columns share the same data line, that is, each data line is connected to The two columns of sub-pixel columns are connected, so that the number of data lines 2000 can be saved, and the number of integrated circuits (ICs) connected to the data lines 2000 can be halved, thereby greatly reducing costs.

For example, as shown in FIG. 1A, the data line 2000 includes a first data line 2100, a second data line 2200, and a third data line 2300. Since each data line is connected to two columns of sub-pixels, and the sub-pixels on the array substrate are arranged in a triangle, the shape of the data line is bent.

For example, as shown in FIG. 1A, the first data line 2100 is located between the first color sub-pixel 1100 in the first row and the second color sub-pixel 1200 in the first row, and is located in the third color sub-pixel 1300 in the second row. A side away from the first color sub-pixel 1100 in the second row; the first data line 2100 is connected to the first color sub-pixel 1100 in the first row and the third color sub-pixel 1300 in the second row. That is, the first data line 2100 passes through the first-color sub-pixel 1100 in the first row and the second-color sub-pixel in the first row in the Nth (N is an integer greater than 0) sub-pixel group 1000 arranged in the Y direction. 1200, and bypass the side of the third color sub-pixel 1300 in the second row (for example, the left side shown in FIG. 1A), and then continue to pass through the N+1th sub-pixel group 1000 arranged in the Y direction The gap between the first color sub-pixel 1100 in the first row and the second color sub-pixel 1200 in the first row, and so on. Thus, the sub-pixel column where the first color sub-pixel 1100 in the first row of the sub-pixel group 1000 is located and the sub-pixel column where the third color sub-pixel 1300 in the second row of the sub-pixel group 1000 is located share the first data line 2100 and Connect with it.

For example, as shown in FIG. 1A, the second data line 2200 is located between the second color sub-pixel 1200 in the first row and the third color sub-pixel 1300 in the first row, and is located in the third color sub-pixel 1300 in the second row. And the first color sub-pixel 1100 in the second row. The second data line 2200 is connected to the second color sub-pixel 1200 in the first row and the first color sub-pixel 1100 in the second row.

For example, the second data line 2200 may be a bent data line consistent with the bending direction of the first data line 2100. The sub-pixel column in which the second color sub-pixel 1200 in the first row in the sub-pixel group 1000 is located and the sub-pixel column in which the first color sub-pixel 1100 in the second row in the sub-pixel group 1000 is located are both connected to the second data line 2200.

For example, as shown in FIG. 1A, the third data line 2300 is located on the side of the third color sub-pixel 1300 in the first row away from the second color sub-pixel 1200 in the first row, and is located in the first color sub-pixel in the second row Between 1100 and the second color sub-pixel 1200 in the second row. The third data line 2300 is connected to the third color sub-pixel 1300 in the first row and the second color sub-pixel 1200 in the second row.

For example, the third data line 2300 may be a bent data line consistent with the bending direction of the first data line 2100. The sub-pixel column in which the third color sub-pixel 1300 in the first row in the sub-pixel group 1000 is located and the sub-pixel column in which the second color sub-pixel 1200 in the second row in the sub-pixel group 1000 is located are both connected to the third data line 2300.

FIG. 1B schematically shows a schematic diagram of a pixel circuit structure in one sub-pixel shown in FIG. 1A. The array substrate provided by the embodiments of the present disclosure may be applied to an organic light emitting diode (OLED) display device or a quantum dot light emitting diode (QLED) device. Pixel circuits in OLED display devices generally adopt a matrix driving method, and are divided into active matrix (Active Matrix) driving and passive matrix (Passive Matrix) driving according to whether switching elements are introduced in each pixel. The active matrix organic light-emitting diode (AMOLED) integrates a set of thin film transistors and storage capacitors in the pixel circuit of each pixel. Through the drive control of the thin film transistors and storage capacitors, the current flowing through the OLED is controlled, so that OLED emits light as needed.

FIG. 1B schematically shows a 3T1C pixel circuit that uses three thin-film transistors (TFT) and a storage capacitor Cst to realize the function of driving the OLED to emit light.

As shown in FIG. 1B, the 3T1C pixel circuit includes a first thin film transistor T1, a second thin film transistor T2, a driving transistor T3, a storage capacitor Cst, and a light emitting element EL. Of course, the pixel circuit of the sub-pixel may also be a 2T1C pixel circuit. For example, the above-mentioned first thin film transistor T1, driving transistor T3, and storage capacitor Cst constitute a 2T1C pixel circuit.

For example, the first thin film transistor T1, the second thin film transistor T2 and the driving transistor T3 may be top gate thin film transistors.

For example, the light emitting element EL may be an organic light emitting diode, such as a top light emitting diode, but the embodiment of the present disclosure is not limited thereto, for example, it may also be a quantum dot light emitting diode (QLED) or the like.

For example, the gate of the first thin film transistor T1 is connected to the gate line to receive the scan signal, the first electrode of the first thin film transistor T1 is connected to the data line to receive the data signal Vdata, and the second electrode of the first thin film transistor T1 is connected to the driving transistor The gate of T3; the first pole of the driving transistor T3 is connected to the power line (first voltage terminal) to receive the first voltage VDD (high voltage, such as a constant positive voltage), and the second pole of the driving transistor T3 is connected to the light-emitting element The positive terminal of EL; the first terminal of the storage capacitor Cst is connected to the second terminal of the first thin film transistor T1 and the gate of the driving transistor T3, and the second terminal of the storage capacitor Cst is connected to the second terminal of the driving transistor T3; The negative terminal of the EL is connected to the second voltage terminal to receive the second voltage VSS (low voltage, for example, ground voltage). When a scan signal is applied through the gate line to turn on the first thin film transistor T1, the data signal Vdata input by the data driving circuit through the data line can charge the storage capacitor Cst through the first thin film transistor T1, thereby storing the data signal Vdata in the storage In the capacitor Cst, the stored data signal Vdata can control the conduction degree of the driving transistor T3, thereby controlling the current flowing through the driving transistor T3 to drive the light-emitting element EL to emit light, that is, this current determines the gray scale of the sub-pixel's light emission .

At present, large-size display panels usually compensate pixel circuits by combining electrical compensation and optical compensation. This method can integrate the advantages of electrical compensation and optical compensation and improve the uniformity of the display panel. Generally speaking, electrical compensation can determine compensation data according to the voltage or current of the pixel circuit acquired by the sensing line to compensate for the characteristics of the driving thin film transistor (for example, threshold voltage and mobility, etc.); optical compensation can compensate the display panel as a whole The uniformity.

For example, the pixel circuit shown in FIG. 1B is a pixel circuit that can detect the threshold voltage of a driving transistor. The second thin film transistor T2 in the pixel circuit is a sensing transistor, and the first electrode of the sensing transistor is connected to the sensing line through the sensing line. The circuit (not shown) is connected to receive the sensing signal VSEN, thereby realizing the compensation function. As shown in FIG. 1B, after the driving transistor T3 is turned on, the detection circuit can be charged via the second thin film transistor T2, so that the second electrode potential of the driving transistor T3 changes. When the voltage Vs of the second electrode of the driving transistor T3 is equal to the difference between the gate voltage Vg of the driving transistor T3 and the threshold voltage Vth of the driving transistor, the driving transistor T3 is turned off. At this time, after the driving transistor T3 is turned off, the sensing voltage (ie, the source voltage Vb of the driving transistor T3 after the driving transistor T3 is turned off) can be obtained from the second electrode of the driving transistor T3 through the turned-on second thin film transistor T2. After the source voltage Vb of the driving transistor T3 is turned off, the threshold voltage Vth=Vdata-Vb of the driving transistor T3 can be obtained, which can be used for each pixel circuit based on the threshold voltage of the driving transistor in each pixel circuit. The compensation data is established, and the threshold voltage compensation function of each sub-pixel on the array substrate can be realized.

For example, the second electrode of the second thin film transistor T2 can also input the sensed current of the positive terminal of the light-emitting element EL to the detection circuit via the sensing line to obtain the current for the light-emitting element EL to emit light, and then based on the light-emitting current The current establishes compensation data for each light-emitting element, thereby realizing the optical compensation of each sub-pixel light-emitting element, so as to compensate the uniformity of the display panel as a whole.

As shown in FIGS. 1A and 1B, the first thin film transistor T1 and the second thin film transistor T2 of a row of sub-pixels adjacent to the first gate line group 3100 are both connected to the first gate line group 3100 and connected to the second gate line group 3100. Both the first thin film transistor T1 and the second thin film transistor T2 of a row of sub-pixels adjacent to 3200 are connected to the second gate line group 3200.

For example, FIG. 1A schematically shows that both the first gate line group 3100 and the second gate line group 3200 include one gate line, but it is not limited thereto, and each gate line group may also include two gate lines. When the pixel circuit structure shown in FIG. 1B is the pixel circuit of the first row of sub-pixels in the sub-pixel group, the gates of the first thin film transistor T1 and the second thin film transistor T2 are both connected to the first gate line group 3100; FIG. 1B When the pixel circuit structure shown is the pixel circuit of the second row of sub-pixels in the sub-pixel group, the gates of the first thin film transistor T1 and the second thin film transistor T2 are both connected to the second gate line group 3200.

For example, FIG. 1C is a schematic diagram of a sub-pixel group and signal lines connected to the sub-pixel group according to an embodiment of the disclosure. As shown in FIGS. 1B and 1C, the first gate line group 3100 includes a first gate line 3110 and a second gate line 3120 that do not cross each other, for example, parallel to each other, and the second gate line group 3200 includes a first gate line 3110 and a second gate line 3120 that do not cross each other, such as parallel to each other. The third gate line 3210 and the fourth gate line 3220. In the example shown in FIG. 1C, each gate line group includes two gate lines as an example. The gate of the first thin film transistor T1 is connected to the first gate line 3110 or the third gate line 3210, and the gate of the second thin film transistor T2 is connected to the second gate line 3120 or the fourth gate line 3220.

For example, the second gate line 3120 is closer to the sub-pixel relative to the first gate line 3110, and the fourth gate line 3220 is closer to the sub-pixel relative to the third gate line 3210. That is, the second gate line 3120 is located on the side of the first gate line 3110 facing the first row of sub-pixels, and the fourth gate line 3220 is located on the side of the third gate line 3210 facing the second row of sub-pixels.

For example, a scan driving circuit is also provided on the array substrate, and the scan driving circuit outputs scan signals for writing data into the first thin film transistor T1 and the second thin film transistor T2. For example, the scan driving circuit may be connected to the gate of the first thin film transistor T1. The electrode and the gate of the second thin film transistor T2 are connected to provide a corresponding scan signal, thereby controlling the on and off of the first thin film transistor T1 and the second thin film transistor T2. An example of the embodiment of the present disclosure is described by taking the gate of the first thin film transistor and the gate of the second thin film transistor respectively connected to different gate lines as an example, so that the time-sharing control of the first thin film transistor and the second thin film transistor Turn on and off to achieve complex compensation waveforms. However, this embodiment is not limited to this, and the first thin film transistor and the second thin film transistor can also be turned on or off under the control of the same gate line.

For example, as shown in FIG. 1C, the array substrate further includes: a plurality of sensing lines 4000 on the base substrate 1010, at least one column of sub-pixel group 1000 corresponds to two sensing lines 4000, and each sensing line and each sub-pixel Three adjacent sub-pixels of different colors among the sub-pixels of different rows in the pixel group are connected. Thus, for each sub-pixel group, the ratio of the number of sensing lines to the number of sub-pixels is 1:3.

For example, as shown in FIG. 1C, the two sensing lines include a first sensing line 4100 and a second sensing line 4200. Since each sensing line is connected to three adjacent sub-pixels of different colors in different rows of sub-pixels in each sub-pixel group, and the sub-pixels on the array substrate are arranged in a triangle, the shape of the sensing line is Bent.

For example, as shown in FIG. 1C, the first sensing line 4100 is connected to the first color sub-pixel 1100 in the first row, the second color sub-pixel 1200 in the first row, and the third color sub-pixel 1300 in the second row. The first sensing line 4100 is located between the first color sub-pixel 1100 in the first row and the second color sub-pixel 1200 in the first row, and is located between the third color sub-pixel 1300 in the second row and the first color sub-pixel 1300 in the second row. Between color sub-pixels 1100. That is, the first sensing line 4100 passes through the first-color sub-pixel 1100 in the first row and the second-color sub-pixel 1200 in the first row in the Nth (N is an integer greater than 0) sub-pixel groups arranged in the Y direction. And bypass the other side of the third color sub-pixel 1300 in the second row (for example, the right side shown in FIG. 1A), and then continue to pass through the N+1th sub-pixel group arranged in the Y direction The gap between the first color sub-pixel 1100 in the first row and the second color sub-pixel 1200 in the first row. That is, a first data line 2100 and a first sensing line 4100 are provided between the first color sub-pixel 1100 in the first row and the second color sub-pixel 1200 in the first row in each sub-pixel group, and this The two signal lines are respectively arranged on both sides of the third color sub-pixel 1300 in the second row along the X direction. In the embodiment of the present disclosure, the positions of the first data line 2100 and the first sensing line 4100 can be interchanged, but the connection relationship with the sub-pixels remains unchanged.

For example, as shown in FIG. 1C, the second sensing line 4200 is located between the second color sub-pixel 1200 in the first row and the third color sub-pixel 1300 in the first row, and is located in the first color sub-pixel in the second row. Between 1100 and the second color sub-pixel 1200 in the second row. The second sensing line 4200 is connected to the second color sub-pixel 1200 in the first row, the third color sub-pixel 1300 in the first row, and the first color sub-pixel 1100 in the second row.

For example, the second sensing line 4200 may be a bending sensing line consistent with the bending direction of the first sensing line 4100.

For example, as shown in FIGS. 1B and 1C, the first electrode of the first thin film transistor T1 is connected to the data line 2000, and the first electrode of the second thin film transistor T2 is connected to the sensing line 4000.

For example, taking the pixel circuit shown in FIG. 1B as an example of the first color sub-pixel 1100 located in the first row of the sub-pixel group, the first electrode of the first thin film transistor T1 of the sub-pixel is connected to the first data line 2100, The gate of the first thin film transistor T1 is connected to the first gate line 3110 to receive the scan signal VG1, the first electrode of the second thin film transistor T2 is connected to the first sensing line 4100, and the gate of the second thin film transistor T2 is connected to the second The gate line 3120 is connected to receive the scan signal VG2. The second thin film transistor in the embodiment of the present disclosure is a sensing transistor, and the sensing transistor is connected to a detection circuit via a sensing line to realize the electrical and optical compensation functions of the display device including the array substrate, thereby improving the display including the array substrate. The display quality of the device.

For example, taking the pixel circuit shown in FIG. 1B as the third color sub-pixel 1300 located in the second row of the sub-pixel group, the first electrode of the first thin film transistor T1 of the sub-pixel is connected to the first data line 2100. The gate of the first thin film transistor T1 is connected to the third gate line 3210 to receive the scan signal VG1, the first electrode of the second thin film transistor T2 is connected to the first sensing line 4100, and the gate of the second thin film transistor T2 is connected to the fourth The gate line 3220 is connected to receive the scan signal VG2.

For example, as shown in FIG. 1C, the array substrate further includes a plurality of power lines 5000, at least one column of sub-pixel groups corresponds to two power lines 5000, and each power line is adjacent to a different row of sub-pixels in each sub-pixel group. The three sub-pixels of different colors are connected.

For example, as shown in FIG. 1C, one of the two power lines is connected to the first color sub-pixel 1100 in the first row, the second color sub-pixel 1200 in the first row, and the third color sub-pixel 1300 in the second row. The other of the two power lines is connected to the remaining three different color sub-pixels in the sub-pixel group (that is, the third color sub-pixel 1300 in the first row, the first color sub-pixel 1100 in the second row, and the second row The second color sub-pixel 1200).

For example, as shown in FIG. 1C, a power line 5000 is provided between two adjacent sub-pixel groups along the row direction. If the sub-pixel group shown in FIG. 1C is the M-th (M is an integer greater than 0) sub-pixel group arranged along the X direction, the power line 5000 located between the M-th sub-pixel group and the M+1-th sub-pixel group In addition to being connected to the third color sub-pixel 1300 in the first row, the first color sub-pixel 1100 in the second row, and the second color sub-pixel 1200 in the second row in the M-th sub-pixel group, it is also connected to the M+1-th sub-pixel group. The first color sub-pixel 1100 in the first row, the second color sub-pixel 1200 in the first row, and the third color sub-pixel 1300 in the second row in the sub-pixel groups are connected.

For example, as shown in FIGS. 1B and 1C, the first pole of the driving transistor T3 in each sub-pixel is connected to a power line 5000, and the power line 5000 is used to provide the driving transistor T3 with a high voltage VDD, such as a constant positive voltage.

FIG. 1D is a circuit layout including the sub-pixel group shown in FIG. 1C. As shown in FIG. 1D, the circuit layout shows two rows of sub-pixels included in the sub-pixel group and three data lines (for example, the first data line, the second data line, and the third data line) connected to the sub-pixel group, The first gate line group 3100 (including the first gate line 3110 and the second gate line 3120), the second gate line group 3200 (including the third gate line 3210 and the fourth gate line 3220), two sensing lines (e.g., the A sensing line and a second sensing line) and two power lines (for example, a first power line and a second power line). The circuit layout shown in FIG. 1D also shows the first thin film transistor T1, the second thin film transistor T2, the driving transistor T3 included in the sub-pixel, and the connection relationship between each thin film transistor and the signal line.

For example, as shown in FIG. 1D, taking the first row of sub-pixel groups as an example, the gate G10 of the first thin film transistor T1 may be a part of the first gate line 3110, and the gate G20 of the second thin film transistor T2 may be the second For a part of the gate line 3120, the channel region 1110 of the first thin film transistor T1 overlaps the first gate line 3110, and the channel region 1120 of the second thin film transistor T2 overlaps the second gate line 3120.

For example, as shown in FIG. 1D, the array substrate includes a source and drain metal layer 1020 and a semiconductor layer 1030. The data line for transmitting data signals is a part of the source and drain metal layer 1020, and the semiconductor layer 1030 is located on the side of the data line facing the base substrate.

As shown in FIG. 1D, taking the sub-pixels connected to the first gate line group 3100 as an example, the source-drain metal layer 1020 is connected to a conductive part of the semiconductor layer 1030 through the first connection hole 1040 to form the first thin film transistor T1 The second pole, and the first connection hole 1040 is located between the first gate line 3110 and the second gate line 3120. The source-drain metal layer 1020 is connected to another part of the semiconductor layer 1030 that is conductive through the second connection hole 1060 to form the first electrode of the second thin film transistor T2, and the second connection hole 1060 is located between the first gate line 3110 and the second gate line 3110. Between line 3120. Taking the sub-pixels connected to the second gate line group 3200 as an example, the first connection hole 1040 is located between the third gate line 3210 and the fourth gate line 3220, and the second connection hole 1060 is located between the third gate line 3210 and the fourth gate line 3210. Between lines 3220.

For example, as shown in FIG. 1D, the power supply line 5000 is connected to the first electrode of the driving transistor T3 through the conductive portion 1031 of the semiconductor layer 1030. The dashed line frame in FIG. 1D schematically shows that the connection part connecting the two parts of the power supply line 5000 extending in the Y direction may be the conductorized part 1031 of the semiconductor layer 1030, but is not limited to this, and the connection is along the Y direction The connecting part of the two parts of the extended power cord 5000 may also be a metal layer of the same layer as the two parts of the power cord 5000.

For example, as shown in FIG. 1D, the orthographic projection of the second electrode of the first thin film transistor T1 on the base substrate 1010 overlaps with the orthographic projection of the second gate line 3120 (or 3220) on the base substrate 1010.

For example, as shown in FIG. 1D, the array substrate further includes a light shielding layer 1050 on the side of the sensing line 4000 and the data line 2000 facing the base substrate 1010. The first sensing line 4100 is connected to the first color sub-pixels 1100 in the first row through the first sensing line connecting portion 4101. The orthographic projection of the first sensing line connecting portion 4101 on the base substrate 1010 is in line with the data line 2000 The orthographic projection on the base substrate 1010 overlaps, and part of the light shielding layer 1050 is multiplexed into the first sensing line connecting portion 4101; the second sensing line 4200 passes through the second sensing line connecting portion 4201 and the second row The second color sub-pixels 1200 are connected, the second sensing line connecting portion 4201 and the gate line are arranged in the same layer, and the orthographic projection of the second sensing line connecting portion 4201 on the base substrate 1010 and the data line 2000 on the base substrate 1010 The orthographic projection on has overlap.

For example, the second sensing line connecting portion 4201 and the gate line may be formed using the same conductive material and through the same patterning process.

In the pixel layout shown in FIG. 1D, a first connection hole and a second connection hole are provided between the first gate line (or third gate line) and the second gate line (or fourth gate line), whereby the two The distance between the grid lines needs to be set larger, for example, not less than 14 microns. In order to ensure the area of the storage capacitor, the line width of the gate line and the line width of the data line in the pixel layout are set to be small (for example, the line width of the gate line is generally set to 2.5 microns, and the line width of the data line is generally set to 3. Micrometers).

For example, as shown in FIG. 1D, the length of the gate line corresponding to the three sub-pixels in the first row of each sub-pixel group is 172.2 μm, and the line width of the gate line is 2.5 μm. Taking two adjacent pixels arranged in the row direction as shown in FIG. 1D as a unit, the cell resistance of the gate line r=0.05Ω, then the gate line resistance in each cell R0=(172.2/2.5)*0.05= 3.44Ω. Then, the array substrate applied to the display device with 8k resolution includes 7680*4320 pixels, and the resistance of one gate line of the array substrate is R=3.44*(7680/2)=13.2kΩ.

FIG. 1E is a schematic diagram of the circuit layout matrix arrangement shown in FIG. 1D. The circuit layout shown in FIG. 1E includes four sub-pixel groups arranged in a 2*2 array, and signal lines connected to the four sub-pixel groups. FIG. 1E schematically shows a schematic diagram of a 2*2 array of the circuit layout 10000 shown in FIG. 1D arranged along the X direction and the Y direction.

Another embodiment of the present disclosure provides a display panel, which includes the array substrate described in the foregoing embodiment. The display panel adopting the above-mentioned array substrate has a small number of data lines, which can achieve ultra-high resolution in a limited wiring space and reduce the cost of the display panel.

Another embodiment of the present disclosure provides a display device including the display panel described in the foregoing embodiment. The display device adopting the above-mentioned display panel has a small number of data lines, which can achieve ultra-high resolution in a limited wiring space and reduce the cost of the display device.

For example, the display device provided by the embodiment of the present disclosure is an organic light emitting diode display device, and the resolution of the display device is 8k.

For example, the 8k image displayed by the display device may include 7680*4320 pixels, that is, the number of pixels in a row arranged in the horizontal direction is about 7680, and the number of pixels in a column arranged in the vertical direction is about 4320.

FIG. 2A is a schematic diagram of a partial structure of an array substrate provided by another embodiment of the present disclosure. As shown in FIG. 2A, the array substrate includes a base substrate 101, a plurality of arrays arranged on the base substrate 101 in the row direction (that is, the direction parallel to the X direction) and the column direction (that is, the direction parallel to the Y direction). There are three sub-pixel groups 100 and gate lines 300 extending in the row direction on the base substrate 101. FIG. 2A schematically shows 4 sub-pixel groups 100 arranged in a 2*2 array, and the number and arrangement of sub-pixels 123 included in the sub-pixel group 100 are only schematic.

As shown in FIG. 2A, the gate line 300 includes a first gate line group, the first gate line group includes a first gate line 311 and a second gate line 312, and the first gate line 311 and the second gate line 312 are located in contact with the first gate line. The same side of the sub-pixel 123 connected by the gate line group. Each sub-pixel 123 includes a first thin film transistor T1 and a second thin film transistor T2. The first thin film transistor T1 is connected to the first gate line 311, the second thin film transistor T2 is connected to the second gate line 312, and the first thin film transistor T1 The channel region 111 and the channel region 112 of the second thin film transistor T2 are both located on the side of the first gate line 311 and the second gate line 312 close to the sub-pixel 123 connected to the first gate line group. In the array substrate provided by the embodiment of the present disclosure, the channel region of the first thin film transistor and the channel region of the second thin film transistor are both arranged on the first gate line and the second gate line close to the sub-pixels connected to the first gate line group The distance between the first gate line and the second gate line can be reduced to save wiring space.

For example, the channel region of the first thin film transistor T1 and the channel region of the second thin film transistor T2 in the embodiments of the present disclosure are located close to the first gate line 311 and the second gate line 312 and the first gate line 311 and the second gate line 312. One side of the sub-pixel 123 to which the gate lines 312 are all connected. The channel region of the first thin film transistor T1 and the channel region of the second thin film transistor T2 are set to be directly opposite to the gate line in the direction perpendicular to the base substrate (for example, in the direction perpendicular to the base substrate, Compared with the gate line), there is no need to provide source and drain regions on both sides of the gate line, that is, there is no need to provide source and drain regions between the first gate line and the second gate line. The distance between adjacent gate lines (the first gate line and the second gate line) is to save wiring space.

In addition, in the case where the channel region of the thin film transistor is arranged to face the gate line in a direction perpendicular to the base substrate, since the source and drain regions need to be provided on both sides of the gate line, the gate lines adjacent to each other ( The regions between the first gate line and the second gate line except for the source and drain regions are vacant, and no other structure is provided. In the embodiments of the present disclosure, since the source and drain regions are no longer located between the first gate line and the second gate line, the wiring space occupied by the empty area can be reduced by reducing the distance between the first gate line and the second gate line , And the space saved can be used to increase the area of the pixel capacitor, and also to increase the width of the gate line.

For example, as shown in FIG. 2A, the distance between the first gate line 311 and the second gate line 312 may be 3-12 microns. For example, the distance between the first gate line 311 and the second gate line 312 may be 4-10 microns or 5-8 microns. Compared with the case where the channel region of the thin film transistor is arranged to be directly opposite to the gate line in the direction perpendicular to the base substrate, the distance between the first gate line and the second gate line that are immediately adjacent in the embodiment of the present disclosure can be reduced Greater than 10 microns.

For example, the width of at least one gate line 300 is 3 to 3.5 microns. For example, the width of at least one of the first gate line 311 and the second gate line 312 may be 3 to 3.5 microns. Compared with a general gate line with a width of 2.5 μm, the width of the gate line in the embodiments of the present disclosure can be increased by 0.5-1 μm, which can reduce the resistance of the gate line and also reduce the process difficulty. In the embodiments of the present disclosure, the space saved between the first gate line and the second gate line is not only used to increase the width of the gate line, but also used to increase the size of the pixel capacitance along the column direction, so it is in line with the channel of the thin film transistor. Compared with the case where the area is set directly above the gate line, while ensuring the constant area of the pixel capacitor, the size of the pixel capacitor along the row direction can be reduced, thereby increasing the width of the data line to reduce the resistance and resistance of the data line. Reduce process difficulty.

In this embodiment, the distance between the first gate line and the second gate line is set to be small, so that wiring space can be saved, and the line width of the gate line can be increased on the basis of ensuring the capacitance area to reduce the resistance of the gate line. At the same time, the process difficulty is reduced, thereby saving the cost of the high-resolution display device including the array substrate.

For example, FIG. 2B is a partial structural diagram of an array substrate provided by an embodiment of the disclosure, FIG. 2B schematically shows that the sub-pixel group shown in FIG. 2A includes two rows of sub-pixels, and FIG. 2C is a sub-pixel shown in FIG. 2B. Schematic diagram of the pixel layout of the pixel group.

For example, as shown in FIG. 2B, each sub-pixel group 100 includes two rows of sub-pixels 123, and the number of sub-pixels 123 in each row is, for example, three. The two rows of sub-pixels 123 each include a first-color sub-pixel 110, a second-color sub-pixel 120, and a third-color sub-pixel 130. The color of each sub-pixel 123 is different from the color of the adjacent sub-pixel 123 and runs along the row direction. , The sub-pixels in the second row and the sub-pixels in the first row are offset from each other by less than one sub-pixel pitch. For example, the first row of sub-pixels includes the first color sub-pixel 110, the second color sub-pixel 120, and the third color sub-pixel 130 in the row direction (for example, the direction indicated by the arrow in the X direction). The row direction includes the third color sub-pixel 130, the first color sub-pixel 110, and the second color sub-pixel 120 in sequence. Along the row direction (such as the direction indicated by the X-direction arrow), the distance between the second row of sub-pixels and the first row of sub-pixels is less than the pitch of one sub-pixel 123, that is, the first row of sub-pixels and the second row of sub-pixels There is a certain offset along the row direction, and the two rows of sub-pixels are not aligned along the column direction.

For example, as shown in FIG. 2B, the arrangement of the third color subpixel 130 in the first row of subpixels and the first color subpixel 110 and the second color subpixel 120 in the second row of subpixels is a triangular pixel arrangement ( For example, the right triangle pixel arrangement). Similarly, the remaining three different-color sub-pixels 123 in the sub-pixel group 100 (that is, the first-color sub-pixel 110 and the second-color sub-pixel 120 in the first row of sub-pixels, and the third sub-pixel in the second row The arrangement of the color sub-pixels 130) is also a triangular pixel arrangement (for example, an inverted triangular pixel arrangement).

For example, as shown in FIG. 2B, each row of sub-pixels 123 in each pixel group 100 includes a first-color sub-pixel 110, a second-color sub-pixel 120, and a third-color sub-pixel 130, and each sub-pixel 123 is connected to adjacent sub-pixels. The colors of the pixels 123 are different (here, the adjacent sub-pixels refer to two adjacent sub-pixels in the same row or in different rows), and the center of the third-color sub-pixel 130 in the first row of sub-pixels is distanced from the center of the second row of sub-pixels. The distance between the center of the first color sub-pixel 110 and the center of the second color sub-pixel 120 is approximately the same. The center of the third color sub-pixel 130 in the second row of sub-pixels is away from the other two color sub-pixels in the first row of sub-pixels (ie The distance between the centers of the first color sub pixel 110 and the second color sub pixel 120 in the first row of sub pixels is approximately the same. That is, the distance between the center of the third color sub-pixel 130 in one row and the center of the first color sub-pixel 110 and the center of the second color sub-pixel 120 in another row is approximately the same.

For example, as shown in FIG. 2B, the first color sub pixel 110, the second color sub pixel 120, and the third color sub pixel 130 are respectively a red sub pixel, a green sub pixel and a blue sub pixel.

For example, when the array substrate provided by the embodiment of the present disclosure is applied to a display device with a resolution of 8k, due to the large number of pixels, the display is sufficiently delicate and the graininess is weakened, so even if the same color in each sub-pixel group 100 shown in FIG. 2B is The sub-pixels 123 are not located on the same straight line extending along the Y direction, and will not affect the display.

As shown in FIG. 2B, the gate line 300 further includes a second gate line group 320. The first gate line group 310 and the second gate line group 320 are respectively located on both sides of each row of the sub-pixel group 100 in the column direction, and adjacent The two rows of sub-pixel groups 100 include a first gate line group 310 and a second gate line group 320, and the second gate line group 320 includes a third gate line 321 and a fourth gate line 322.

For example, as shown in FIG. 2B, in the sub-pixels 123 connected to the second gate line group 320, the first thin film transistor is connected to the third gate line 321, the second thin film transistor is connected to the fourth gate line 322, and the first thin film transistor is connected to the fourth gate line 322. The channel region of the transistor and the channel region of the second thin film transistor are both located on the side of the third gate line 321 and the fourth gate line 322 close to the sub-pixel 123 connected to the second gate line group 320.

For example, the distance between the third gate line 321 and the fourth gate line 322 is 3-12 microns.

In the embodiments of the present disclosure, the distance between the third gate line and the fourth gate line is set to be small, so that wiring space can be saved, and the line width of the gate line can be increased on the basis of ensuring the capacitance area to reduce the resistance of the gate line At the same time, the process difficulty is reduced, thereby saving the cost of the high-resolution display device including the array substrate.

For example, as shown in FIG. 2B, the array substrate further includes: data lines 200 on the base substrate 101, each column of sub-pixel group 100 corresponds to three data lines 200, and each data line 200 corresponds to a different row in each sub-pixel group 100 Two adjacent sub-pixels of different colors in the sub-pixels are connected. Therefore, the embodiment of the present disclosure adopts a dual gate technology, which reduces the number of data lines 200 by half and doubles the number of gate lines 300 to save costs.

For example, as shown in FIG. 2B, the data line 200 includes a first data line 210, a second data line 220, and a third data line 230. Since each data line is connected to two columns of sub-pixels 123, and the sub-pixels 123 on the array substrate are arranged in a triangle, the shape of the data line 200 is bent.

For example, as shown in FIG. 2B, the six sub-pixels 123 included in each sub-pixel group 100 are respectively located in six sub-pixel columns, that is, each sub-pixel 123 in each sub-pixel group 100 is located in a different sub-pixel column. For each column of the sub-pixel group 100, the first data line 210 is located between the first-color sub-pixel 110 and the second-color sub-pixel 120 in the first row, and the third-color sub-pixel 130 in the second row is far away from the second row. One side of the first color sub-pixel 110; the first data line 210 is connected to the first color sub-pixel 110 in the first row and the third color sub-pixel 130 in the second row. Thus, the sub-pixel column where the first color sub-pixel 110 located in the first row of the sub-pixel group 100 is located and the sub-pixel column where the third color sub-pixel 130 located in the second row of the sub-pixel group 100 is located share the first data Line 210.

For example, as shown in FIG. 2B, for each column of the sub-pixel group 100, the second data line 220 is located between the second color sub-pixel 120 and the third color sub-pixel 130 in the first row, and is located in the third color in the second row. Between the sub-pixel 130 and the first color sub-pixel 110. The sub-pixel column where the second color sub-pixel 120 in the first row is located and the sub-pixel column where the first color sub-pixel 110 in the second row is located share the second data line 220.

For example, the second data line 220 may be a bent data line consistent with the bending direction of the first data line 210.

For example, as shown in FIG. 2B, for each column of the sub-pixel group 100, the third data line 230 is located on the side of the third-color sub-pixel 130 in the first row away from the second-color sub-pixel 120 in the first row, and is located in the second row. Between the first color sub-pixel 110 and the second color sub-pixel 120 of the row. The sub-pixel column where the third color sub-pixel 130 in the first row is located and the sub-pixel column where the second color sub-pixel 120 in the second row is located share the third data line 230.

For example, the third data line 230 may be a bent data line consistent with the bending direction of the first data line 210.

As shown in FIGS. 2B-2C, each sub-pixel 123 includes a first thin film transistor T1 and a second thin film transistor T2; among the sub-pixels connected to the first gate line group 310, the first thin film transistor T1 and the first gate line 311 Connected, the second thin film transistor T2 is connected to the second gate line 312; in the sub-pixels connected to the second gate line group 320, the first thin film transistor T1 is connected to the third gate line 321, and the second thin film transistor T2 is connected to the fourth gate line. Line 322 is connected. The embodiments of the present disclosure are described by taking as an example that the gate of the first thin film transistor and the gate of the second thin film transistor are respectively connected to different gate lines, so that the conduction and conduction of the first thin film transistor and the second thin film transistor can be controlled in a time-sharing manner. Cut off to achieve complex compensation waveforms.

As shown in FIG. 2C, in the sub-pixels 123 connected to the first gate line group 310, the channel region 111 of the first thin film transistor T1 and the channel region 112 of the second thin film transistor T2 are both located in the first gate line 311 and the first gate line 311. The second gate line 312 is close to one side of the sub-pixel 123 connected to the first gate line group 310. Similarly, in the sub-pixels 123 connected to the second gate line group 320, the first thin film transistor T1 is connected to the third gate line 321, the second thin film transistor T2 is connected to the fourth gate line 322, and the first thin film transistor T1 The channel region 111 and the channel region 112 of the second thin film transistor T2 are both located on the side of the third gate line 321 and the fourth gate line 322 close to the sub-pixel 123 connected to the second gate line group 320.

For example, as shown in FIGS. 2B-2C, the gate G1 of the first thin film transistor T1 is connected to the first gate line 311, the first electrode D1 of the first thin film transistor T1 is connected to the data line 200, and the second thin film transistor T2 The gate G2 is connected to the second gate line 312.

For example, as shown in FIGS. 2B-2C, the array substrate further includes a sensing line 400. Each column of the sub-pixel group 100 corresponds to two sensing lines 410 and 420, and each sensing line 400 is connected to three adjacent sub-pixels 123 of different colors among the sub-pixels 123 in different rows in each sub-pixel group 100. In addition, the first electrode D2 of the second thin film transistor T2 of each sub-pixel 123 is connected to the sensing line 400. Thus, for each sub-pixel group, the ratio of the number of sensing lines to the number of sub-pixels is 1:3. Since the first gate line group and the second gate line group included in the gate lines are respectively located on both sides of each row of sub-pixel groups in the column direction, the sensing lines can be better distributed to reduce the number of sensing lines.

For example, as shown in FIGS. 2B-2C, since each sensing line 400 is connected to three adjacent sub-pixels 123 of different colors in different rows of sub-pixels 123 in each sub-pixel group 100, and the array substrate The upper sub-pixels 123 are arranged in a triangle, and the shape of the sensing line 400 is bent.

For example, as shown in FIGS. 2B-2C, the array substrate further includes power lines 500, which extend in the column direction and are located between two adjacent sub-pixel groups 100, and the power lines 500 are connected to two adjacent sub-pixel groups 100. Each sub-pixel 123 in each sub-pixel group 100 is connected to provide a power supply voltage.

For example, the schematic diagram of the pixel circuit structure in one sub-pixel shown in FIG. 2B in the embodiment of the present disclosure is shown in FIG. 1B, which will not be repeated here.

For example, as shown in FIGS. 2B-2C and 1B, each sub-pixel further includes a light-emitting element EL, a driving transistor T3, and a storage capacitor Cst. The second electrode of the second thin film transistor T2 is connected to the light emitting element EL; the gate of the driving transistor T3 is connected to the second electrode of the first thin film transistor T1, the first electrode of the driving transistor T3 is connected to the power line 500, and the driving transistor T3 The second electrode is connected to the light emitting element EL; the first electrode of the storage capacitor Cst is connected to the gate of the driving transistor T3, and the second electrode of the storage capacitor Cst is connected to the second electrode of the driving transistor T3. The first thin film transistor T1 is a switching transistor, and the second thin film transistor T2 is a compensation transistor. In the above, the pixel circuit of each sub-pixel is schematically described as a 3T1C pixel circuit. Of course, the pixel circuit of each sub-pixel may also be a 2T1C pixel circuit. For example, the above-mentioned first thin film transistor T1, driving transistor T3, and storage capacitor C constitute a 2T1C pixel circuit.

For example, as shown in FIG. 2C, in the sub-pixels 123 connected to the first gate line group 310, the gate G1 of the first thin film transistor T1 and the gate G2 of the second thin film transistor T2 are located at the first gate line 311 and the second gate line 311. The gate line 312 faces one side of the sub-pixel 123 connected to the first gate line group 310; in the sub-pixel 123 connected to the second gate line group 320, the gate G1 of the first thin film transistor T1 and the gate G1 of the second thin film transistor T2 The gate G2 is located on the side of the third gate line 321 and the fourth gate line 322 facing the sub-pixel 123 connected to the second gate line group 320.

For example, as shown in FIGS. 2B and 2C, the array substrate further includes: a source and drain metal layer (SD layer) 102 and a semiconductor layer 103 on the base substrate 101. The source-drain metal layer 102 includes the data line 200, that is, the data line 200 is a part of the source-drain metal layer 102. The semiconductor layer 103 is located on the side of the data line 200 close to the base substrate 101. The source-drain metal layer 102 is connected to the conductive first portion of the semiconductor layer 103 through the first connection hole 104 to form the second electrode of the first thin film transistor T1, and the first connection hole 104 is located at the first gate line 311 and the second gate line 311. The line 312 faces the side of the sub-pixel 123 connected to the first gate line group 310 or is located on the side of the third gate line 321 and the fourth gate line 322 facing the sub-pixel 123 connected to the second gate line group 320.

For example, as shown in FIG. 2C, taking the sub-pixels connected to the first gate line group 310 as an example, the first connection hole 104 is located on the side of the first gate line 311 away from the second gate line 312. Taking the sub-pixels connected to the second gate line group 320 as an example, the first connection hole 104 is located on the side of the fourth gate line 322 away from the third gate line 321.

For example, as shown in FIG. 2C, the source-drain metal layer 102 is connected to the conductive second portion of the semiconductor layer 103 through the second connection hole 106 to form the first electrode D2 of the second thin film transistor T2, and the second connection hole 106 Located on the side of the first gate line 311 and the second gate line 312 facing the sub-pixels connected to both the first gate line 311 and the second gate line 312, or located at the third gate line 321 and the fourth gate line 322 facing the second gate line One side of the sub-pixel to which both the third gate line 321 and the fourth gate line 322 are connected.

For example, as shown in FIG. 2C, taking the sub-pixels connected to the first gate line group 310 as an example, the second connection hole 106 is located on the side of the first gate line 311 away from the second gate line 312. Taking the sub-pixels connected to the second gate line group 320 as an example, the second connection hole 106 is located on the side of the fourth gate line 322 away from the third gate line 321.

For example, as shown in FIG. 2C, the first electrode of the driving transistor T3 of at least one sub-pixel is connected to the power line 500 through the third portion of the semiconductor layer 103 that is conductive.

In the embodiment of the present disclosure, as shown in FIG. 2C, the first connection hole and the second connection hole are not provided between the first gate line and the second gate line, and/or, the first connection hole and the second connection hole It is not provided between the third grid line and the fourth grid line. According to an embodiment of the present disclosure, by arranging the first connection hole and the second connection hole on the side of the first gate line (or fourth gate line) away from the second gate line (or third gate line), it is possible to reduce The distance between the first gate line (or the fourth gate line) and the second gate line (or the third gate line) is reduced to, for example, 4-10 microns, thereby increasing the space of the pixel layout. Therefore, under the condition that the area of the storage capacitor remains unchanged, the width of the gate line can be increased to reduce the resistance of the gate line.

For example, in this embodiment, the width of the gate line is increased to 3 microns, then referring to the formula for calculating the resistance value in the embodiment shown in FIG. 1D, it can be obtained that the present embodiment is applied to the array of the 8k resolution display device The resistance value of a gate line on the substrate is 11kΩ. Compared with the pixel layout shown in FIG. 1D, the pixel layout provided by the embodiment of the present disclosure can reduce the resistance of the gate line by 2 kΩ, so as to effectively alleviate the RC delay phenomenon. Moreover, since the width of the gate line can be set wider, the process difficulty in the process of manufacturing the gate line can be reduced.

For example, in the embodiments of the present disclosure, since the distance between adjacent gate lines is reduced, while keeping the storage capacitor area unchanged, in addition to increasing the width of the gate line, the width of the data line can also be increased. For example, the width of each data line can be increased to 3.5-4 microns. Compared with the data line with a width of 3 microns in the pixel layout shown in FIG. 1D, in the embodiment of the present disclosure, by increasing the width of the data line, not only the resistance of the data line can be reduced, but also the process difficulty of manufacturing the data line can be reduced. .

For example, as shown in FIGS. 2B-2C, along the column direction (for example, the direction indicated by the arrow in the Y direction), the arrangement order of the first gate line 311 and the second gate line 312 is the same as that of the third gate line 321 and the fourth gate line. The arrangement order of the lines 322 is the same. In the embodiments of the present disclosure, the arrangement sequence of the gate lines connected to the first thin film transistor and the gate lines connected to the second thin film transistor included in each sub-pixel is set to be consistent, so that when each gate line extends to a fanout area , The first grid line and the second grid line can be more easily identified.

For example, as shown in FIG. 2C, in each sub-pixel, the gate of one of the first thin film transistor T1 and the second thin film transistor T2 is connected to the gate line through the source-drain metal layer 102.

For example, as shown in FIG. 2C, in the sub-pixels in the first row, the gate G2 of the second thin film transistor T2 is connected to the second gate line 312 through the source and drain metal layer 102; in the sub-pixels in the second row, the The gate of a thin film transistor T1 is connected to the third gate line 321 through the source and drain metal layer 102.

For example, FIG. 3 is a pixel layout corresponding to the sub-pixel group shown in FIG. 2B. As shown in FIG. 3, the pixel layout shows two rows of sub-pixels included in each sub-pixel group 100, three data lines 200 connected to each sub-pixel group 100, and two first gate line groups 310 (for example, the first The gate line 311 and the second gate line 312), two second gate line groups 320 (for example, the third gate line 321 and the fourth gate line 322), two sensing lines 400, and two power lines 500. The pixel layout shown in FIG. 3 also shows the first thin film transistor T1, the second thin film transistor T2, the driving thin film transistor T3 included in each sub-pixel, and the connection relationship between each thin film transistor and the signal line.

FIG. 3 is also a schematic diagram of the pixel layout matrix arrangement shown in FIG. 2C. The pixel layout shown in FIG. 3 includes four sub-pixel groups arranged in a 2*2 array, and signal lines connected to the four sub-pixel groups. FIG. 3 schematically shows a schematic diagram of a 2*2 array of the pixel layout shown in FIG. 2C arranged along the X direction and the Y direction.

For example, as shown in FIGS. 2C and 3, the array substrate further includes a light-shielding layer 105 on the side of the sensing line 400 facing the base substrate 101, and the light-shielding layer 105 is made of a conductive material. The first electrode of the second thin film transistor T2 in the first row of sub-pixels in each sub-pixel group 100 is electrically connected to the sensing line 400 through a part of the light-shielding layer 105, that is, a part of the light-shielding layer 105 can be used for transmitting and sensing signal. Since the light shielding layer 105 and the sensing line 400 are in different layers, the thin film transistor is connected to the sensing line 400 through a part of the light shielding layer 105 with conductive characteristics, which can effectively save wiring space.

For example, as shown in FIG. 3, each sensing line 400 includes a plurality of sub-sensing lines 401 and a connecting line 107 connecting two adjacent sub-sensing lines 401. Each sub-sensing line 401 extends substantially in the column direction, the connecting line 107 extends in the row direction, and each sub-sensing line 401 corresponds to a sub-pixel group 100. The connecting line 107 is located between two adjacent sub-pixel groups 100 arranged in the column direction, and the orthographic projection of the connecting line 107 on the base substrate 101 and the orthographic projection of the data line 200 on the base substrate 101 overlap. In the embodiment of the present disclosure, a part of the light shielding layer 105 can be reused as the connecting line 107, that is, adjacent sub-sensing lines 401 are electrically connected through the part of the light shielding layer 105 that is multiplexed as the connecting line 107 to form a complete sensing line. Survey line 400.

For example, as shown in FIG. 3, the orthographic projection of the part of the light shielding layer 105 that is multiplexed as the connecting line 107 on the base substrate is located on the adjacent first gate line group 310 and second gate line group 320 on the base substrate. Between the orthographic projections.

For example, as shown in FIG. 3, the sub-sensing line 401 included in the first sensing line 410 is connected to the first-color sub-pixels in the first row and the second-color sub-pixels in the first row through the connecting lines 107; The sub-sensing line 401 included in the measuring line 420 is connected to the first color sub-pixels in the second row and the second color sub-pixels in the second row through the connecting line 107.

In the embodiment of the present disclosure, the connection line and the sub-sensing line are located on different layers, and the connection is realized through via holes, so that the distance between the sub-pixel groups of adjacent rows can be reduced to further save space.

Another embodiment of the present disclosure provides a display panel, which includes the array substrate described in the foregoing embodiment. In the display panel provided by the embodiment of the present disclosure, the channel region of the first thin film transistor and the channel region of the second thin film transistor are both arranged on the side of the first gate line and the second gate line close to the sub-pixels connected to them. The distance between the first gate line and the second gate line can be reduced to save wiring space, and the line width of the gate line can be increased on the basis of ensuring the capacitance area to reduce the resistance of the gate line, and at the same time reduce the process difficulty, thereby saving The cost of the high-resolution display device including the display panel.

Another embodiment of the present disclosure provides a display device including the display panel described in the foregoing embodiment.

For example, the display device provided by the embodiment of the present disclosure may be an organic light emitting diode display device, and the resolution of the display device is 8k. The display device adopting the above display panel reduces the distance between the first gate line and the second gate line to save wiring space, increases the line width of the gate line to reduce the resistance of the gate line, and reduces the process difficulty, thereby saving This reduces the cost of a high-resolution display device.

For example, the 8k image displayed by the display device provided by the embodiment of the present disclosure may include 7680*4320 pixels, that is, the number of pixels arranged in a row in the horizontal direction is about 7680, and the number of pixels in a column arranged in the vertical direction is about 4320. .

Another embodiment of the present disclosure provides a method for manufacturing the array substrate in the embodiment shown in FIGS. 2A-3, which includes forming a plurality of sub-pixel groups arrayed in a row direction and a column direction on a base substrate, And forming gate lines extending in the row direction on the base substrate. Forming each sub-pixel group includes forming a plurality of sub-pixels. Forming the gate line includes forming a first gate line group, and forming the first gate line group includes forming a first gate line and a second gate line located on the same side of the sub-pixel connected to the first gate line group. Forming at least one sub-pixel of the plurality of sub-pixels includes forming a first thin film transistor and a second thin film transistor, which are connected to the sub-pixels of the first gate line group, the first thin film transistor is connected to the first gate line, and the second thin film transistor is connected to the first gate line. The two gate lines are connected, and the channel region of the first thin film transistor and the channel region of the second thin film transistor are both formed on the side of the first gate line group close to the sub-pixel connected to it. The manufacturing method of the array substrate provided by the embodiment of the present disclosure is that the channel region of the first thin film transistor and the channel region of the second thin film transistor are both formed on the side of the first gate line group close to the sub-pixels connected to it. Reduce the distance between the first gate line and the second gate line to save wiring space. It is also possible to increase the line width of at least one of the first gate line and the second gate line on the basis of ensuring the capacitance area to reduce its resistance. At the same time, the process difficulty is reduced, thereby saving the cost of the high-resolution display device including the array substrate. The sub-pixel group and the first gate line group in this embodiment have all the features in the embodiment shown in FIGS. 2A-3, and will not be repeated here.

For example, in the manufacturing method provided by the embodiment of the present disclosure, forming the gate line further includes forming a second gate line group, and forming the second gate line group includes forming a third gate line and a fourth gate line. The first gate line group and the second gate line group are respectively formed on both sides of each row of sub-pixel groups in the column direction; among the sub-pixels connected to the second gate line group, the first thin film transistor is connected to the third gate line, The second thin film transistor is connected to the fourth gate line, and the channel region of the first thin film transistor and the channel region of the second thin film transistor are both formed on the side of the second gate line group close to the sub-pixel connected to it. In the embodiments of the present disclosure, the distance between the third gate line and the fourth gate line is set to be small, so that wiring space can be saved, and the line width of the gate line can be increased on the basis of ensuring the capacitance area to reduce the resistance of the gate line. At the same time, the process difficulty is reduced, thereby saving the cost of the high-resolution display device including the array substrate. The second gate line group in this embodiment has all the features in the embodiment shown in FIGS. 2A-2C, and will not be repeated here.

For example, the manufacturing method provided by the embodiment of the present disclosure further includes: forming a data line on the base substrate. For example, forming the first thin film transistor, the second thin film transistor, and the data line includes: forming a semiconductor layer on a base substrate; conducting a conductive process on the first part and the second part of the semiconductor layer to form the first conductive region and the second conductive region. Conduction area; an insulating layer is formed on the side of the semiconductor layer away from the base substrate, and the insulating layer includes a first connection hole and a second connection hole; a source and drain metal layer is formed on the side of the insulating layer away from the semiconductor layer; The layer is patterned to form data lines.

For example, the source and drain metal layers are connected to the first conductive area through the first connection hole to form the second electrode of the first thin film transistor, and the first connection hole is located on the side of the first gate line group close to the sub-pixel connected to it. Or located on the side of the second gate line group close to the sub-pixels connected to it; the source and drain metal layers are connected to the second conductive region through the second connection hole to form the first electrode of the second thin film transistor, and the second connection hole is located The first gate line group is close to the side of the sub-pixel connected to it, or the second gate line group is close to the side of the sub-pixel connected to it. The first connection hole and the second connection hole are not provided between the first gate line and the second gate line, and/or, the first connection hole and the second connection hole are not provided between the third gate line and the fourth gate line between. In this embodiment, for example, by arranging the first connection hole and the second connection hole on the side of the first grid line (or fourth grid line) away from the second grid line (or third grid line), The distance between the first gate line (or fourth gate line) and the second gate line (or third gate line) can be reduced, for example, to 4-10 microns, thereby increasing the pixel layout space. Therefore, under the condition that the area of the storage capacitor remains unchanged, the width of the gate line can be increased to reduce the resistance of the gate line.

For example, the manufacturing method provided by the embodiment of the present disclosure further includes forming a sensing line. Each formed sensing line is connected to three adjacent sub-pixels of different colors in the sub-pixels of different rows in each sub-pixel group, and the first electrode of the second thin film transistor of each sub-pixel is connected to the sensing line Connected, each column of sub-pixel groups corresponds to two sensing lines. Thus, for each sub-pixel group, the ratio of the number of formed sensing lines to the number of sub-pixels is 1:3. Since the first gate line group and the second gate line group included in the gate lines are respectively located on both sides of each row of sub-pixel groups in the column direction, the sensing lines can be better distributed to reduce the number of sensing lines.

For example, the manufacturing method provided by the embodiment of the present disclosure further includes: forming a light shielding layer on the base substrate before forming the sensing line. The shading layer is made of conductive material. The first electrode of the second thin film transistor located in the first row of sub-pixels in each sub-pixel group is electrically connected to a subsequently formed sensing line through a part of the light-shielding layer, that is, a part of the light-shielding layer can be used to transmit a sensing signal. Since the light shielding layer and the sensing line are in different layers, the thin film transistor is connected to the sensing line through a part of the light shielding layer with conductive characteristics, which can effectively save wiring space.

The following points need to be explained:

(1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the usual design.

(2) In the case of no conflict, the features in the same embodiment and different embodiments of the present disclosure can be combined with each other.

The above are only specific implementations of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present disclosure. It should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

This application claims the priority of the Chinese patent application No. 201910356036.6 filed on April 29, 2019 and the Chinese patent application No. 201910550358.4 filed on June 24, 2019. The contents of the above two Chinese patent applications are quoted here in full. As part of this application.

Claims

An array substrate, including:

Base substrate

A plurality of sub-pixel groups arranged in an array along a row direction and a column direction on the base substrate, each of the sub-pixel groups including a plurality of sub-pixels; and

A gate line extending in the row direction on the base substrate, the gate line including a first gate line group, the first gate line group including sub-pixels connected to the first gate line group The first grid line and the second grid line on the same side,

Wherein, at least some of the sub-pixels in the plurality of sub-pixels include a first thin film transistor and a second thin film transistor, which are connected to the sub-pixels of the first gate line group, and the first thin film transistor and the first gate Line connection, the second thin film transistor is connected to the second gate line, and the channel region of the first thin film transistor and the channel region of the second thin film transistor are both located in the first gate line group Close to the side of the sub-pixel connected to the first gate line group.
The array substrate according to claim 1, wherein the distance between the first gate line and the second gate line is 3 micrometers to 12 micrometers.
3. The array substrate according to claim 2, wherein the width of at least one of the first gate line and the second gate line is 3 micrometers to 3.5 micrometers.
3. The array substrate according to any one of claims 1 to 3, wherein the gate line further comprises a second gate line group, the first gate line group and the second gate line group are respectively located in each row of the The sub-pixel groups are on both sides in the column direction, so that the first gate line group and the second gate line group are included between two adjacent rows of the sub-pixel groups, and the second gate line group The line group includes a third grid line and a fourth grid line;

In the sub-pixels connected to the second gate line group, the first thin film transistor is connected to the third gate line, the second thin film transistor is connected to the fourth gate line, and the first thin film transistor is connected to the fourth gate line. The channel region of a thin film transistor and the channel region of the second thin film transistor are both located on the side of the second gate line group close to the sub-pixel connected to the second gate line group.
The array substrate according to claim 4, wherein the distance between the third grid line and the fourth grid line is 3 micrometers to 12 micrometers.
4. The array substrate according to claim 4, wherein, along the column direction, the order of the first gate line and the second gate line is the same as that of the third gate line and the fourth gate line The order is the same.
7. The array substrate according to claim 6, wherein the sub-pixel group includes two rows of sub-pixels, and each of the two rows of sub-pixels includes a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel. The color of a sub-pixel is different from the color of the sub-pixels adjacent to it in the row direction or the column direction, and along the row direction, the second row of sub-pixels and the first row of sub-pixels are offset from each other by less than one sub-pixel pitch ；

The array substrate further includes:

For the data lines located on the base substrate, each column of the sub-pixel group corresponds to three data lines, and each of the three data lines corresponds to the sub-pixels in different rows in each of the sub-pixel groups Two adjacent sub-pixels of different colors are connected to each other, and the first electrode of the first thin film transistor of the sub-pixel is connected to the data line.
8. The array substrate of claim 7, wherein the width of each of the data lines is 3.5 micrometers to 4 micrometers.
8. The array substrate according to claim 7, further comprising:

A source-drain metal layer located on the base substrate, the source-drain metal layer including the data line; and

The semiconductor layer is located on the side of the data line close to the base substrate, and includes a conductive first part,

Wherein, the source and drain metal layers are connected to the first part of the semiconductor layer through a first connection hole to form a second electrode of the first thin film transistor, and

The first connection hole is located on a side of the first gate line group close to the sub-pixel connected to the first gate line group, or located close to the second gate line group and the second gate line group. One side of the sub-pixel connected by the gate line group.
9. The array substrate according to claim 9, wherein the gate of one of the first thin film transistor and the second thin film transistor in the sub-pixel is connected to the gate line through the source and drain metal layer.
The array substrate according to claim 9, further comprising:

A sensing line, wherein each column of the sub-pixel group corresponds to two sensing lines, and each of the sensing lines is different from three adjacent ones of the sub-pixels in different rows in each sub-pixel group The color sub-pixels are connected, and the first electrode of the second thin film transistor of the sub-pixel is connected to the sensing line.
The array substrate according to claim 11, wherein the semiconductor layer further comprises a second portion that is conductive, and the source and drain metal layers are connected to the second portion of the semiconductor layer through a second connection hole To form the first pole of the second thin film transistor, and

The second connection hole is located on a side of the first gate line group close to the sub-pixel connected to the first gate line group, or located close to the second gate line group and the second gate line group. One side of the sub-pixel connected by the gate line group.
The array substrate according to claim 11, further comprising:

The light shielding layer is located on the side of the sensing line facing the base substrate,

Wherein, each of the sensing lines includes a plurality of sub-sensing lines and a connecting line connecting two adjacent sub-sensing lines, each of the sub-sensing lines corresponds to one of the sub-pixel groups, and The connecting line is located between two adjacent sub-pixel groups arranged along the column direction, and the orthographic projection of the connecting line on the base substrate is opposite to the orthographic projection of the data line on the base substrate. The projection is overlapped, and part of the light shielding layer is multiplexed as the connecting line.
11. The array substrate according to claim 11, further comprising a power supply line, wherein the sub-pixel further includes a light-emitting element, a driving transistor, and a storage capacitor, and the semiconductor layer further includes a third portion that is conductive;

The second electrode of the second thin film transistor is connected to the light emitting element;

The gate of the driving transistor is connected to the second electrode of the first thin film transistor, the first electrode of the driving transistor is connected to the power line, and the second electrode of the driving transistor is connected to the light emitting element, Wherein, the first pole of the driving transistor of at least one of the sub-pixels is connected to the power line through the third part of the semiconductor layer;

The first electrode of the storage capacitor is connected to the gate of the driving transistor, and the second electrode of the storage capacitor is connected to the second electrode of the driving transistor.
11. The array substrate of claim 11, wherein the two sensing lines include a first sensing line and a second sensing line,

The first sensing line is located between the first color subpixel in the first row and the second color subpixel in the first row, and is located between the third color subpixel and the second color subpixel in the second row. Between the first color sub-pixels in the first row, the first sensing line and the first color sub-pixels in the first row, the second color sub-pixels in the first row, and the second row The third color sub-pixel connection;

The second sensing line is located between the second color subpixel in the first row and the third color subpixel in the first row, and is located between the first color subpixel and the second color subpixel in the second row. Between the second color sub-pixels of the row, the second sensing line is connected to the second color sub-pixels of the first row, the third color sub-pixels of the first row, and the second row of the The first color sub-pixels are connected.
15. The array substrate of claim 15, wherein each of the first sensing line and the second sensing line includes a plurality of sub-sensing lines and connecting two adjacent sub-sensing lines Connection line,

The sub-sensing lines included in the first sensing line are connected to the first-color sub-pixels in the first row and the second-color sub-pixels in the first row through the connecting lines; the second The sub-sensing lines included in the sensing line are connected to the first color sub-pixels in the second row and the second color sub-pixels in the second row through the connecting lines.
A display panel, comprising the array substrate according to any one of claims 1-16.
A display device, comprising the display panel of claim 17.
18. The display device of claim 18, wherein the display device is an organic light emitting diode display device, and the resolution of the display device is 8k.
A manufacturing method of an array substrate includes:

Forming a plurality of sub-pixel groups arranged in an array along a row direction and a column direction on the base substrate, each of the sub-pixel groups including a plurality of sub-pixels;

A gate line extending in the row direction is formed on the base substrate, and forming the gate line includes forming a first gate line group, and the first gate line group includes a gate line connected to the first gate line group. The first gate line and the second gate line on the same side of the sub-pixel,

Wherein, forming at least one sub-pixel of the plurality of sub-pixels includes forming a first thin film transistor and a second thin film transistor, which are connected to the sub-pixels of the first gate line group, the first thin film transistor and the second thin film transistor. The first gate line is connected, the second thin film transistor is connected to the second gate line, and the channel region of the first thin film transistor and the channel region of the second thin film transistor are both formed in the first A side of a gate line group close to the sub-pixel connected to the first gate line group.
The manufacturing method according to claim 20, wherein forming the gate line further comprises: forming a second gate line group, the first gate line group and the second gate line group are respectively formed in each row of the sub Pixel groups are on both sides in the column direction, and forming the second gate line group includes forming a third gate line and a fourth gate line,

Wherein, in the sub-pixels connected to the second gate line group, the first thin film transistor is connected to the third gate line, the second thin film transistor is connected to the fourth gate line, and The channel region of the first thin film transistor and the channel region of the second thin film transistor are both formed on a side of the second gate line group close to the sub-pixel connected to the second gate line group.
The manufacturing method according to claim 21, further comprising: forming a data line on the base substrate, wherein forming the first thin film transistor, the second thin film transistor and the data line comprises:

Forming a semiconductor layer on the base substrate;

Conducting a conductive process on the first part and the second part of the semiconductor layer to form a first conductive region and a second conductive region;

Forming an insulating layer on the side of the semiconductor layer away from the base substrate, the insulating layer including a first connection hole and a second connection hole;

A source-drain metal layer is formed on the side of the insulating layer away from the semiconductor layer, wherein the source-drain metal layer is connected to the first conductive region through the first connection hole to form the first thin film The second electrode of the transistor, and the first connection hole is located on the side of the first gate line group close to the sub-pixel connected to the first gate line group, or located at the second gate line group The side close to the sub-pixel connected to the second gate line group; the source-drain metal layer is connected to the second conductive region through the second connection hole to form the second thin film transistor And the second connection hole is located on the side of the first gate line group close to the sub-pixels connected to the first gate line group, or located at the side of the second gate line group A side close to the sub-pixel connected to the second gate line group; and

The source and drain metal layers are patterned to form the data line.
An array substrate, including:

Base substrate

A plurality of sub-pixel groups located on the base substrate, at least one sub-pixel group in the plurality of sub-pixel groups includes two rows of sub-pixels, and the first row of sub-pixels includes first-color sub-pixels, first-color sub-pixels, and Two-color sub-pixels and third-color sub-pixels. The second row of sub-pixels includes the third-color sub-pixels, the first-color sub-pixels, and the second-color sub-pixels in sequence along the first direction, and In the first direction, the second row of sub-pixels and the first row of sub-pixels are staggered from each other;

A plurality of data lines located on the base substrate, the at least one sub-pixel group corresponds to three data lines in the plurality of data lines, and each of the three data lines is connected to the at least one Two adjacent sub-pixels of different colors in the sub-pixels of different rows in the sub-pixel group are connected; the extension direction of the plurality of data lines intersects the first direction; and

A plurality of gate lines located on the base substrate, the plurality of gate lines including a first gate line group and a second gate line group respectively located on both sides of the sub-pixel group in a direction intersecting the first direction Line group, each of the first gate line group and the second gate line group includes at least one gate line; the plurality of gate lines extend along the first direction,

Wherein, at least some of the sub-pixels include a first thin film transistor and a second thin film transistor, and the first thin film transistor and the second thin film transistor of a row of sub pixels adjacent to the first gate line group are both connected to the first gate line group. Connected, the first thin film transistor and the second thin film transistor of a row of sub-pixels adjacent to the second gate line group are both connected to the second gate line group.
23. The array substrate according to claim 23, wherein the first gate line group includes a first gate line and a second gate line that do not cross each other, and the second gate line group includes a third gate line that does not cross each other And the fourth gate line, and the first thin film transistor and the second thin film transistor in the same sub-pixel are connected to different gate lines in the same gate line group.
The array substrate according to claim 23, further comprising:

A plurality of sensing lines located on the base substrate, wherein the at least one sub-pixel group corresponds to two sensing lines, and each sensing line of the two sensing lines is connected to the at least one Three adjacent sub-pixels of different colors among the sub-pixels of different rows in the sub-pixel group are connected.
25. The array substrate of claim 25, wherein the first electrode of the first thin film transistor is connected to one of the three data lines, and the first electrode of the second thin film transistor is connected to the two data lines. One of the sensing lines is connected.
The array substrate of claim 25, wherein the two sensing lines include a first sensing line and a second sensing line,

The first sensing line is located between the first color sub-pixel in the first row and the second color sub-pixel in the first row in the at least one sub-pixel group, and is located in the second row Between the third color sub-pixel and the first color sub-pixel in the second row, and the first sensing line is between the first color sub-pixel in the first row, and the second color in the first row The sub-pixels are connected to the third color sub-pixels in the second row;

The second sensing line is located between the second color sub-pixel in the first row and the third color sub-pixel in the first row in the at least one sub-pixel group, and is located in the second row Between the first color sub-pixel and the second color sub-pixel in the second row, and the second sensing line is between the third color sub-pixel in the first row, and the first color in the second row The sub-pixels are connected to the second color sub-pixels in the second row.
The array substrate of claim 27, further comprising:

The light shielding layer is located on the side of the sensing line and the data line facing the base substrate, wherein the first sensing line is connected to the first line of the first line through the first sensing line connecting portion The color sub-pixels are connected, the orthographic projection of the first sensing line connection portion on the base substrate overlaps with the orthographic projection of the data line on the base substrate, and a portion of the light shielding layer Multiplexed as the first sensing line connection part;

The second sensing line is connected to the second color sub-pixels in the second row through a second sensing line connecting part, the second sensing line connecting part and the gate line are arranged in the same layer, and the The orthographic projection of the second sensing line connection portion on the base substrate overlaps the orthographic projection of the data line on the base substrate.
The array substrate according to any one of claims 23-28, wherein the three data lines corresponding to the at least one sub-pixel group include a first data line, a second data line, and a third data line,

The first data line is located between the first color sub-pixel in the first row and the second color sub-pixel in the first row in the at least one sub-pixel group, and is located in the second color sub-pixel in the second row. The three-color sub-pixels are away from the side of the first color sub-pixels in the second row

The second data line is located between the second color sub-pixel in the first row and the third color sub-pixel in the first row in the at least one sub-pixel group, and is located in the second color sub-pixel in the second row. Between the three-color sub-pixels and the first-color sub-pixels in the second row,

The third data line is located on the side of the third color sub-pixel in the first row of the at least one sub-pixel group away from the second color sub-pixel in the first row, and is located in the second row of the Between the first color sub-pixel and the second color sub-pixel in the second row.
28. The array substrate of claim 29, wherein the first data line is connected to the first color sub-pixels in a first row and the third color sub-pixels in a second row; the second data line Connected to the second color sub-pixels in the first row and the first color sub-pixels in the second row; the third data line is connected to the third color sub-pixels in the first row and all of the second row The second color sub-pixels are connected.
The array substrate according to claim 29, wherein the orthographic projection of the second electrode of the first thin film transistor on the base substrate and the orthographic projection of the second gate line on the base substrate are overlap.
The array substrate according to claim 26, further comprising:

A plurality of power lines located on the base substrate, wherein the at least one sub-pixel group corresponds to two power lines of the plurality of power lines, and each of the two power lines is connected to Three adjacent sub-pixels of different colors among the sub-pixels of different rows in the at least one sub-pixel group are connected.
The array substrate according to claim 32, wherein the at least part of the sub-pixels further comprises a light-emitting element, and the second electrode of the second thin film transistor is connected to the light-emitting element.
The array substrate according to claim 33, wherein the at least part of the sub-pixels further comprises a driving transistor and a storage capacitor,

The gate of the driving transistor is connected to the second electrode of the first thin film transistor, the first electrode of the driving transistor is connected to one of the two power lines, and the second electrode of the driving transistor is connected to the Light-emitting element connection;

The first electrode of the storage capacitor is connected to the gate of the driving transistor, and the second electrode of the storage capacitor is connected to the second electrode of the driving transistor.
The array substrate of claim 34, further comprising:

The semiconductor layer is located on the side of the data line close to the base substrate and includes a conductive part,

Wherein, the power supply line is connected to the first electrode of the driving transistor through the conductorized portion in the semiconductor layer.
The array substrate according to any one of claims 23-28, wherein in the at least one sub-pixel group, along the first direction, the second row of sub-pixels and the first row of sub-pixels are mutually The pitch is less than one sub-pixel, and the distance between the centers of two adjacent sub-pixels in the first row of sub-pixels is equal to the distance between the centers of two adjacent sub-pixels in the second row of sub-pixels .
28. The array substrate according to any one of claims 23-28, wherein, in the at least one sub-pixel group, the center of the third color sub-pixel in one row is away from the first color sub-pixel in another row The distance between the center and the center of the second color sub-pixel is equal.
The array substrate according to any one of claims 23-28, wherein the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel include a red sub-pixel, a green sub-pixel, and Blue sub pixel.
A display panel, comprising the array substrate according to any one of claims 23-38.
A display device, comprising the display panel of claim 39.
The display device of claim 40, wherein the display device is an organic light emitting diode display device, and the resolution of the display device is 8k.