WO2020211159A1 - 半导体基板结构及其制作方法 - Google Patents

半导体基板结构及其制作方法 Download PDF

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Publication number
WO2020211159A1
WO2020211159A1 PCT/CN2019/088314 CN2019088314W WO2020211159A1 WO 2020211159 A1 WO2020211159 A1 WO 2020211159A1 CN 2019088314 W CN2019088314 W CN 2019088314W WO 2020211159 A1 WO2020211159 A1 WO 2020211159A1
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Prior art keywords
layer
thin film
metal oxide
oxide thin
film transistor
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PCT/CN2019/088314
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English (en)
French (fr)
Inventor
卢马才
刘念
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H10F39/014—Manufacture or treatment of image sensors covered by group H10F39/12 of CMOS image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/803—Pixels having integrated switching, control, storage or amplification elements
    • H10F39/8037—Pixels having integrated switching, control, storage or amplification elements the integrated elements comprising a transistor

Definitions

  • the present disclosure relates to the field of display technology, in particular to a semiconductor substrate structure and a manufacturing method thereof.
  • the semiconductor substrate structure of existing displays does not have sensors.
  • the sensor is independently arranged at a position other than the semiconductor substrate structure, and therefore cannot be fixed-point sensed on the semiconductor substrate structure, resulting in poor performance of mobile phone fingerprint recognition and/or ambient light monitoring and TV remote control.
  • the semiconductor substrate structure of existing displays does not have sensors.
  • the sensor is independently arranged at a position other than the semiconductor substrate structure, and therefore cannot be fixed-point sensed on the semiconductor substrate structure, resulting in poor performance of mobile phone fingerprint recognition and/or ambient light monitoring and TV remote control.
  • an objective of the present disclosure is to provide a semiconductor substrate structure and a manufacturing method thereof, the semiconductor substrate structure having optical detection performance.
  • the present disclosure provides a semiconductor substrate structure.
  • the semiconductor substrate structure includes a substrate, a metal oxide thin film transistor, and a tunnel diode.
  • the metal oxide thin film transistor is disposed on the substrate.
  • the tunnel diode is arranged on the substrate and beside the metal oxide thin film transistor.
  • the gate electrode of the metal oxide thin film transistor and the anode of the tunnel diode are made of the same material, and the gate electrode of the metal oxide thin film transistor and the anode of the tunnel diode are both molybdenum/copper Laminate or molybdenum/aluminum laminate.
  • the gate of the metal oxide thin film transistor and the anode of the tunnel diode are disposed on the same layer on the substrate.
  • the semiconductor substrate structure further includes a gate insulating layer disposed on the substrate, the gate of the metal oxide thin film transistor, and the Tunnel on the anode of the diode.
  • the gate insulating layer is a SiOx layer, a SiOx/SiNx stack, a SiNx/SiOx stack, SiOx, SiNx and SiNO stacks, SiOx, SiNx and Al2O3 stacks, or AlN Floor.
  • the metal oxide thin film transistor further includes a stacked active layer channel, a first barrier layer, and source and drain electrodes
  • the tunnel diode further includes a stacked semiconductor layer, A second barrier layer and a cathode
  • the gate insulating layer includes an opening
  • the semiconductor layer and the second barrier layer of the tunnel diode are disposed in the opening of the gate insulating layer.
  • the semiconductor substrate structure further includes a stacked passivation layer and a pixel electrode layer, the passivation layer is disposed on the source and drain electrodes and the cathode, and the passivation The layer includes an opening, and the pixel electrode layer contacts the source and drain electrodes through the opening of the passivation layer.
  • the present disclosure also provides a semiconductor substrate structure.
  • the semiconductor substrate structure includes a substrate, a metal oxide thin film transistor, and a tunnel diode.
  • the metal oxide thin film transistor is disposed on the substrate.
  • the tunnel diode is arranged on the substrate and beside the metal oxide thin film transistor.
  • the gate of the metal oxide thin film transistor and the anode of the tunnel diode are arranged on the same layer on the substrate.
  • the gate electrode of the metal oxide thin film transistor and the anode of the tunnel diode are made of the same material, and the gate electrode of the metal oxide thin film transistor and The anode of the tunnel diode is either a molybdenum/copper laminate or a molybdenum/aluminum laminate.
  • the semiconductor substrate structure further includes a gate insulating layer disposed on the substrate, the gate of the metal oxide thin film transistor, and the Tunnel on the anode of the diode.
  • the gate insulating layer is a SiOx layer, a SiOx/SiNx stack, a SiNx/SiOx stack, a SiOx, SiNx and SiNO stack, SiOx, SiNx and Al2O3 stack or AlN Floor.
  • the metal oxide thin film transistor further includes a stacked active layer channel, a first barrier layer, and source and drain electrodes
  • the tunnel diode further includes a stacked semiconductor layer, A second barrier layer and a cathode
  • the gate insulating layer includes an opening
  • the semiconductor layer and the second barrier layer of the tunnel diode are disposed in the opening of the gate insulating layer.
  • the semiconductor substrate structure further includes a stacked passivation layer and a pixel electrode layer, the passivation layer is disposed on the source and drain electrodes and the cathode, and the passivation The layer includes an opening, and the pixel electrode layer contacts the source and drain electrodes through the opening of the passivation layer.
  • the disclosure also provides a manufacturing method of the semiconductor substrate structure.
  • the manufacturing method of the semiconductor substrate structure includes providing a substrate, forming a metal oxide thin film transistor on the substrate, and forming a tunnel diode on the substrate and beside the metal oxide thin film transistor.
  • the gate of the metal oxide thin film transistor and the anode of the tunnel diode are formed on the same layer on the substrate.
  • a gate insulating layer is formed on the substrate, the gate of the metal oxide thin film transistor, and the anode of the tunnel diode, and the gate is insulated
  • the active layer channel, the first barrier layer and the source and drain electrodes of the metal oxide thin film transistor are laminated on the layer, and the semiconductor layer of the tunnel diode is laminated on the gate insulating layer,
  • a second barrier layer and a cathode, the gate insulating layer includes an opening, and the semiconductor layer and the second barrier layer of the tunnel diode are disposed in the opening of the gate insulating layer.
  • the semiconductor substrate structure includes a substrate, a metal oxide thin film transistor, and a tunnel diode.
  • the metal oxide thin film transistor is disposed on the substrate.
  • the tunnel diode is arranged on the substrate and beside the metal oxide thin film transistor, so the semiconductor substrate structure has optical detection performance.
  • FIG. 1 shows a schematic structural diagram of a semiconductor substrate structure according to an embodiment of the present disclosure
  • FIG. 2 shows a schematic diagram of a circuit structure of a semiconductor substrate structure according to an embodiment of the present disclosure
  • FIG. 3 shows a flowchart of a manufacturing method of a semiconductor substrate structure according to an embodiment of the present disclosure
  • FIG. 4 shows a schematic diagram of a manufacturing method of a semiconductor substrate structure according to an embodiment of the present disclosure
  • FIG. 5 shows a schematic diagram of a manufacturing method of a semiconductor substrate structure according to an embodiment of the present disclosure
  • FIG. 6 shows a schematic diagram of a manufacturing method of a semiconductor substrate structure according to an embodiment of the present disclosure
  • FIG. 7 shows a schematic diagram of a manufacturing method of a semiconductor substrate structure according to an embodiment of the present disclosure
  • FIG. 8 shows a schematic diagram of a manufacturing method of a semiconductor substrate structure according to an embodiment of the present disclosure
  • FIG. 9 shows a schematic diagram of a manufacturing method of a semiconductor substrate structure according to an embodiment of the present disclosure.
  • FIG. 10 shows a schematic diagram of a manufacturing method of a semiconductor substrate structure according to an embodiment of the present disclosure.
  • FIG. 11 shows a schematic diagram of a manufacturing method of a semiconductor substrate structure according to an embodiment of the present disclosure.
  • an embodiment of the present disclosure provides a semiconductor substrate structure 100.
  • the semiconductor substrate structure 100 includes a substrate 110, a metal oxide thin film transistor 120, and a tunnel diode (tunnel diode) 130.
  • the metal oxide thin film transistor 120 is disposed on the substrate 110.
  • the tunnel diode 130 is disposed on the substrate 110 and beside the metal oxide thin film transistor 120.
  • the gate 122 of the metal oxide thin film transistor 120 and the anode 132 of the tunnel diode 130 are disposed on the same layer on the substrate 110.
  • the gate 122 of the metal oxide thin film transistor 120 and the anode 132 of the tunnel diode 130 are made of the same material, and the gate 122 of the metal oxide thin film transistor 120 and all of the tunnel diode 130 are made of the same material.
  • the anode 132 is either a molybdenum/copper laminate or a molybdenum/aluminum laminate.
  • the semiconductor substrate structure 100 further includes a gate insulating layer 140, and the gate insulating layer 140 is disposed on the substrate 110 and the metal oxide thin film transistor 120.
  • the gate insulating layer 140 is a SiOx layer, a SiOx/SiNx stack, a SiNx/SiOx stack, SiOx, SiNx and SiNO stacks, SiOx, SiNx and Al2O3 stacks, or AlN layers.
  • the metal oxide thin film transistor 120 further includes a stacked active layer channel 124, a first barrier layer 126, and source and drain electrodes 128.
  • the tunnel diode 130 further includes a stacked semiconductor layer 134, a second barrier layer 136, and a cathode 138.
  • the gate insulating layer 140 includes an opening 142, and the semiconductor layer 134 and the second barrier layer 136 of the tunnel diode 130 are disposed in the opening 142 of the gate insulating layer 140.
  • the height of the opening 142 ranges between 5 nm and 50 nm.
  • the active layer channel 124 of the metal oxide thin film transistor 120 and the semiconductor layer 134 of the tunnel diode 130 are made of the same material, and the metal oxide thin film transistor 120 has the same material.
  • the materials of the source channel 124 and the semiconductor layer 134 of the tunnel diode 130 include IGZO or IZO.
  • the semiconductor substrate structure 100 further includes a stacked passivation layer 150 and a pixel electrode layer 160.
  • the passivation layer 150 is disposed on the source and drain electrodes 128 and the cathode 138.
  • the passivation layer 150 includes an opening 152, and the pixel electrode layer 160 contacts the source and drain electrodes 128 through the opening 152 of the passivation layer 150.
  • the material of the passivation layer 150 includes SiNx, SiOx or SiNO.
  • the metal oxide thin film transistor 120 is connected to the tunnel diode 130, and the metal oxide thin film transistor 120 and the tunnel diode 130 form a logic circuit, for example, In-cell touch panel fingerprint recognition, display brightness adjustment of ambient light or detection of optical changes.
  • one end of the metal oxide thin film transistor 120 is used to receive a low potential VDD
  • one end of the tunnel diode 130 is used to receive a low potential Vss
  • the gate 122 of the metal oxide thin film transistor 120 is used To receive the input potential Vi
  • one end of the metal oxide thin film transistor 120 and the tunnel diode 130 connected to each other is used to output the potential Vo.
  • the semiconductor substrate structure 100 integrates the metal oxide thin film transistor 120 and the tunnel diode 130, and the tunnel diode 130 is compatible with the metal oxide thin film transistor 120.
  • the manufacturing process and the metal oxide thin film transistor 120 are fabricated on the substrate 110 together.
  • the tunnel diode 130 is used for optical detection or combined with the metal oxide thin film transistor 120 to form a logic circuit, for example, it can be used for fingerprint recognition of an in-cell touch panel, and display brightness adjustment of ambient light Or the detection of optical changes.
  • the tunneling diode 130 can be applied to the in-plane sensor (in Cell sensor) and fingerprint recognition, or can be applied to large display panels, such as TV monitors changes in ambient light and automatically adjusts the display brightness of different areas.
  • the manufacturing process of the tunnel diode 130 is compatible with the manufacturing process of the metal oxide thin film transistor 120, and no additional process is required.
  • an embodiment of the present disclosure provides a manufacturing method 300 of a semiconductor substrate structure, including the following steps.
  • Step 310 providing a substrate 110, step 320, forming a metal oxide thin film transistor 120 on the substrate 110, and step 330, forming a tunnel diode 130 on the substrate 110 and beside the metal oxide thin film transistor 120.
  • the gate 122 of the metal oxide thin film transistor 120 and the anode 132 of the tunnel diode 130 are formed on the same layer on the substrate 110.
  • the gate 122 of the metal oxide thin film transistor 120 and the anode 132 of the tunnel diode 130 are made of the same material, and the gate 122 of the metal oxide thin film transistor 120 and all of the tunnel diode 130 are made of the same material.
  • the anode 132 is either a molybdenum/copper laminate or a molybdenum/aluminum laminate.
  • a gate is formed on the substrate 110, the gate 122 of the metal oxide thin film transistor 120, and the anode 132 of the tunnel diode 130 Insulation layer 140.
  • the gate insulating layer 140 is a SiOx layer, a SiOx/SiNx stack, a SiNx/SiOx stack, SiOx, SiNx and SiNO stacks, SiOx, SiNx and Al2O3 stacks, or AlN layers.
  • the gate insulating layer 140 above the anode 132 corresponding to the tunneling diode 130 is partially etched to form an opening 142.
  • the thickness of the lower gate insulating layer 140 ranges between 5 nm and 50 nm. That is, the height range of the opening 142 is between 5 nm and 50 nm.
  • the active layer channel 124 and the first barrier layer of the metal oxide thin film transistor 120 are laminated on the gate insulating layer 140 126 and the source and drain electrodes 128, the semiconductor layer 134, the second barrier layer 136 and the cathode 138 of the tunnel diode 130 are laminated on the gate insulating layer 140, and the semiconductor layer of the tunnel diode 130 The layer 134 and the second barrier layer 136 are disposed in the opening 142 of the gate insulating layer 140.
  • a semiconductor metal oxide such as IGZO or IZO is deposited on the gate insulating layer 140, and the semiconductor metal oxide is etched to form the active material of the metal oxide thin film transistor 120.
  • the active layer channel 124 of the metal oxide thin film transistor 120 and the semiconductor layer 134 of the tunnel diode 130 are made of the same material, and the active layer channel of the metal oxide thin film transistor 120
  • the material of the channel 124 and the semiconductor layer 134 of the tunnel diode 130 includes IGZO or IZO.
  • a metal layer 180 and a barrier layer 190 are deposited on the active layer channel 124 of the metal oxide thin film transistor 120 and the semiconductor layer 134 of the tunnel diode 130.
  • the metal layer 180 and the barrier layer 190 may constitute an electrode layer.
  • the material of the metal layer 180 may include copper, aluminum or cobalt, and the barrier layer 190 may be a MoTi metal film layer, a Ti metal film layer or an oxide film layer.
  • the thickness of the MoTi metal film layer or the Ti metal film layer ranges between 10 nm and 30 nm.
  • the thickness of the oxide film layer is greater than the MoTi metal film layer or the Ti metal film layer.
  • the metal layer 180 and the barrier layer 190 are patterned by a yellow light process of a multi-gray-scale mask and two etchings to form the laminated metal oxide thin film transistor 120.
  • a stacked passivation layer 150 and a pixel electrode layer 160 are formed on the source and drain electrodes 128 and the cathode 138.
  • the passivation layer 150 includes an opening 152, and the pixel electrode layer 160 contacts the source and drain electrodes 128 through the opening 152 of the passivation layer 150.
  • the passivation layer 150 is deposited on the source and drain electrodes 128 and the cathode 138.
  • the material of the passivation layer 150 includes SiNx, SiOx or SiNO.
  • the opening 152 is formed on the passivation layer 150.
  • the pixel electrode layer 160 is deposited on the passivation layer 150 and the pixel electrode layer 160 is patterned.
  • the semiconductor substrate structure 100 integrates the metal oxide thin film transistor 120 and the tunnel diode 130, and the tunnel diode 130 is compatible with the metal oxide thin film transistor 120.
  • the manufacturing process and the metal oxide thin film transistor 120 are fabricated on the substrate 110 together.
  • the tunnel diode 130 is used for optical detection or combined with the metal oxide thin film transistor 120 to form a logic circuit, for example, it can be used for fingerprint recognition of an in-cell touch panel, and display brightness adjustment of ambient light Or the detection of optical changes.
  • the tunneling diode 130 can be applied to the in-plane sensor (in Cell sensor) and fingerprint recognition, or can be applied to large display panels, such as TV monitors changes in ambient light and automatically adjusts the display brightness of different areas.
  • the manufacturing process of the tunnel diode 130 is compatible with the manufacturing process of the metal oxide thin film transistor 120, and no additional process is required.
  • the semiconductor substrate structure includes a substrate, a metal oxide thin film transistor, and a tunnel diode.
  • the metal oxide thin film transistor is disposed on the substrate.
  • the tunnel diode is arranged on the substrate and beside the metal oxide thin film transistor, so the semiconductor substrate structure has optical detection performance.
  • the semiconductor substrate structure in the embodiment of the present disclosure has a sensor (ie, tunnel diode), so it can be fixed-point sensing on the semiconductor substrate structure, so it can be applied to displays (such as mobile phones and TVs) and to improve fingerprint recognition and/ Or the performance of ambient light monitoring and TV remote control.
  • a sensor ie, tunnel diode

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Abstract

半导体基板结构（100）及其制作方法。所述半导体基板结构（100）包括基板（110）、金属氧化物薄膜晶体管（120）以及遂穿二极管（130）。所述金属氧化物薄膜晶体管（120）设置在所述基板（110）上。所述遂穿二极管（130）设置在所述基板（110）上和所述金属氧化物薄膜晶体管（120）旁。该半导体基板结构（100）具有光学侦测性能。

Description

半导体基板结构及其制作方法 技术领域
本揭示涉及显示技术领域，特别涉及一种半导体基板结构及其制作方法。
 背景技术
现有显示器(例如手机和电视)的半导体基板结构不具有感应器。感应器独立设置在所述半导体基板结构以外的位置，因而无法在所述半导体基板结构上定点感应，因此造成手机指纹识别及/或环境光监测和电视的遥控的性能不佳。
故，有需要提供一种半导体基板结构及其制作方法，以解决现有技术存在的问题。
 技术问题
现有显示器(例如手机和电视)的半导体基板结构不具有感应器。感应器独立设置在所述半导体基板结构以外的位置，因而无法在所述半导体基板结构上定点感应，因此造成手机指纹识别及/或环境光监测和电视的遥控的性能不佳。
 技术解决方案
为解决上述技术问题，本揭示的一目的在于提供半导体基板结构及其制作方法，所述半导体基板结构具有光学侦测性能。
为达成上述目的，本揭示提供一半导体基板结构。所述半导体基板结构包括基板、金属氧化物薄膜晶体管以及遂穿二极管。所述金属氧化物薄膜晶体管设置在所述基板上。所述遂穿二极管设置在所述基板上和所述金属氧化物薄膜晶体管旁。所述金属氧化物薄膜晶体管的栅极和所述遂穿二极管的阳极的材料相同，且所述金属氧化物薄膜晶体管的所述栅极和所述遂穿二极管的所述阳极均为钼/铜叠层或钼/铝叠层。
于本揭示其中的一实施例中，所述金属氧化物薄膜晶体管的所述栅极和所述遂穿二极管的所述阳极设置在所述基板上的相同层上。
于本揭示其中的一实施例中，所述的半导体基板结构还包括栅极绝缘层，所述栅极绝缘层设置在所述基板、所述金属氧化物薄膜晶体管的所述栅极和所述遂穿二极管的所述阳极上。
于本揭示其中的一实施例中，所述栅极绝缘层为SiOx层、SiOx/SiNx叠层、SiNx/SiOx叠层、SiOx、SiNx与SiNO相互叠层、SiOx、SiNx与Al2O3叠层或AlN层。
于本揭示其中的一实施例中，所述金属氧化物薄膜晶体管还包括层迭的有源层沟道、第一阻挡层和源漏电极，所述遂穿二极管还包括层迭的半导体层、第二阻挡层和阴极，所述栅极绝缘层包括开口，所述遂穿二极管的所述半导体层和所述第二阻挡层设置于所述栅极绝缘层的所述开口内。
于本揭示其中的一实施例中，所述半导体基板结构还包括层迭的钝化层和像素电极层，所述钝化层设置于所述源漏电极和所述阴极上，所述钝化层包括开孔，所述像素电极层通过所述钝化层的所述开孔接触所述源漏电极。
本揭示还提供一半导体基板结构。所述半导体基板结构包括基板、金属氧化物薄膜晶体管以及遂穿二极管。所述金属氧化物薄膜晶体管设置在所述基板上。所述遂穿二极管设置在所述基板上和所述金属氧化物薄膜晶体管旁。
于本揭示其中的一实施例中，所述金属氧化物薄膜晶体管的栅极和所述遂穿二极管的阳极设置在所述基板上的相同层上。
于本揭示其中的一实施例中，所述金属氧化物薄膜晶体管的所述栅极和所述遂穿二极管的所述阳极的材料相同，且所述金属氧化物薄膜晶体管的所述栅极和所述遂穿二极管的所述阳极均为钼/铜叠层或钼/铝叠层。
于本揭示其中的一实施例中，所述的半导体基板结构还包括栅极绝缘层，所述栅极绝缘层设置在所述基板、所述金属氧化物薄膜晶体管的所述栅极和所述遂穿二极管的所述阳极上。
于本揭示其中的一实施例中，所述栅极绝缘层为SiOx层、SiOx/SiNx叠层、SiNx/SiOx叠层、SiOx、SiNx与SiNO相互叠层、SiOx、SiNx与Al2O3叠层或AlN层。
于本揭示其中的一实施例中，所述金属氧化物薄膜晶体管还包括层迭的有源层沟道、第一阻挡层和源漏电极，所述遂穿二极管还包括层迭的半导体层、第二阻挡层和阴极，所述栅极绝缘层包括开口，所述遂穿二极管的所述半导体层和所述第二阻挡层设置于所述栅极绝缘层的所述开口内。
于本揭示其中的一实施例中，所述半导体基板结构还包括层迭的钝化层和像素电极层，所述钝化层设置于所述源漏电极和所述阴极上，所述钝化层包括开孔，所述像素电极层通过所述钝化层的所述开孔接触所述源漏电极。
本揭示还提供一半导体基板结构的制作方法。所述半导体基板结构的制作方法包括提供基板，在所述基板上形成金属氧化物薄膜晶体管，以及在所述基板上和所述金属氧化物薄膜晶体管旁形成遂穿二极管。
于本揭示其中的一实施例中，在所述基板上的相同层上形成所述金属氧化物薄膜晶体管的栅极和所述遂穿二极管的阳极。
于本揭示其中的一实施例中，在所述基板、所述金属氧化物薄膜晶体管的所述栅极和所述遂穿二极管的所述阳极上形成栅极绝缘层，在所述栅极绝缘层上形成层迭的所述金属氧化物薄膜晶体管的有源层沟道、第一阻挡层和源漏电极，在所述栅极绝缘层上形成层迭的所述遂穿二极管的半导体层、第二阻挡层和阴极，所述栅极绝缘层包括开口，所述遂穿二极管的所述半导体层和所述第二阻挡层设置于所述栅极绝缘层的所述开口内。
 有益效果
相较于现有技术，为解决上述技术问题，由于本揭示的实施例中的半导体基板结构及其制作方法中，所述半导体基板结构包括基板、金属氧化物薄膜晶体管以及遂穿二极管。所述金属氧化物薄膜晶体管设置在所述基板上。所述遂穿二极管设置在所述基板上和所述金属氧化物薄膜晶体管旁，因此所述半导体基板结构具有光学侦测性能。
 附图说明
图1显示根据本揭示的一实施例的半导体基板结构的结构示意图；
图2显示根据本揭示的一实施例的半导体基板结构的电路结构示意图；
图3显示根据本揭示的一实施例的半导体基板结构的制作方法的流程图；
图4显示根据本揭示的一实施例的半导体基板结构的制作方法的示意图；
图5显示根据本揭示的一实施例的半导体基板结构的制作方法的示意图；
图6显示根据本揭示的一实施例的半导体基板结构的制作方法的示意图；
图7显示根据本揭示的一实施例的半导体基板结构的制作方法的示意图；
图8显示根据本揭示的一实施例的半导体基板结构的制作方法的示意图；
图9显示根据本揭示的一实施例的半导体基板结构的制作方法的示意图；
图10显示根据本揭示的一实施例的半导体基板结构的制作方法的示意图；以及
图11显示根据本揭示的一实施例的半导体基板结构的制作方法的示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本揭示可用以实施的特定实施例。
为了让本揭示的上述及其他目的、特征、优点能更明显易懂，下文将特举本揭示优选实施例，并配合所附图式，作详细说明如下。再者，本揭示所提到的方向用语，例如上、下、顶、底、前、后、左、右、内、外、侧层、周围、中央、水平、横向、垂直、纵向、轴向、径向、最上层或最下层等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本揭示，而非用以限制本揭示。
在图中，结构相似的单元是以相同标号表示。
参照图1和图2，本揭示的一实施例提供半导体基板结构100。所述半导体基板结构100包括基板110、金属氧化物薄膜晶体管120以及遂穿二极管(tunnel diode)130。所述金属氧化物薄膜晶体管120设置在所述基板110上。所述遂穿二极管130设置在所述基板110上和所述金属氧化物薄膜晶体管120旁。
于本揭示其中的一实施例中，所述金属氧化物薄膜晶体管120的栅极122和所述遂穿二极管130的阳极132设置在所述基板110上的相同层上。所述金属氧化物薄膜晶体管120的栅极122和所述遂穿二极管130的阳极132的材料相同，且所述金属氧化物薄膜晶体管120的所述栅极122和所述遂穿二极管130的所述阳极132均为钼/铜叠层或钼/铝叠层。
于本揭示其中的一实施例中，所述的半导体基板结构100还包括栅极绝缘层140，所述栅极绝缘层140设置在所述基板110、所述金属氧化物薄膜晶体管120的所述栅极122和所述遂穿二极管130的所述阳极132上。所述栅极绝缘层140为SiOx层、SiOx/SiNx叠层、SiNx/SiOx叠层、SiOx、SiNx与SiNO相互叠层、SiOx、SiNx与Al2O3叠层或AlN层。
于本揭示其中的一实施例中，所述金属氧化物薄膜晶体管120还包括层迭的有源层沟道124、第一阻挡层126和源漏电极128。所述遂穿二极管130还包括层迭的半导体层134、第二阻挡层136和阴极138。所述栅极绝缘层140包括开口142，所述遂穿二极管130的所述半导体层134和所述第二阻挡层136设置于所述栅极绝缘层140的所述开口142内。所述开口142的高度范围介于5nm以及50nm之间。
具体地，所述金属氧化物薄膜晶体管120的所述有源层沟道124和所述遂穿二极管130的所述半导体层134的材料相同，且所述金属氧化物薄膜晶体管120的所述有源层沟道124和所述遂穿二极管130的所述半导体层134的所述材料包括IGZO或IZO。
于本揭示其中的一实施例中，所述半导体基板结构100还包括层迭的钝化层150和像素电极层160。所述钝化层150设置于所述源漏电极128和所述阴极138上。所述钝化层150包括开孔152，所述像素电极层160通过所述钝化层150的所述开孔152接触所述源漏电极128。所述钝化层150的材料包括SiNx、SiOx或SiNO。
参照图2，本揭示的一实施例中，所述金属氧化物薄膜晶体管120连接所述遂穿二极管130，所述金属氧化物薄膜晶体管120和所述遂穿二极管130形成逻辑电路，例如可用于内嵌式(in-cell)触控面板的指纹识别、对环境光进行显示亮度调整或对光学变化的侦测。
具体地，所述金属氧化物薄膜晶体管120的一端用于接收低电位VDD，所述遂穿二极管130的一端用于接收低电位Vss，所述金属氧化物薄膜晶体管120的所述栅极122用于接收输入电位Vi，所述金属氧化物薄膜晶体管120和所述遂穿二极管130互相连接的一端用于输出电位Vo。
本揭示的一实施例中，所述半导体基板结构100集成有所述金属氧化物薄膜晶体管120和所述遂穿二极管130，所述遂穿二极管130通过与所述金属氧化物薄膜晶体管120兼容的制程与所述金属氧化物薄膜晶体管120一起制作到所述基板110上。所述遂穿二极管130用于光学检测或和所述金属氧化物薄膜晶体管120组合形成逻辑电路，例如可用于内嵌式(in-cell)触控面板的指纹识别、对环境光进行显示亮度调整或对光学变化的侦测。
所述遂穿二极管130在光学侦测上可应用于移动显示设备的显示面内感应器(in cell sensor)及指纹识别，或可应用于大显示面板，例如电视监控环境光变化及自动调整不同区域的显示亮度。所述遂穿二极管130的制程和所述金属氧化物薄膜晶体管120制程兼容，不需额外的制程。
参照图3，本揭示的一实施例提供半导体基板结构的制作方法300，包括如下步骤。
步骤310、提供基板110，步骤320、在所述基板110上形成金属氧化物薄膜晶体管120，以及步骤330、在所述基板110上和所述金属氧化物薄膜晶体管120旁形成遂穿二极管130。
参照图4，于本揭示其中的一实施例中，在所述基板110上的相同层上形成所述金属氧化物薄膜晶体管120的栅极122和所述遂穿二极管130的阳极132。所述金属氧化物薄膜晶体管120的栅极122和所述遂穿二极管130的阳极132的材料相同，且所述金属氧化物薄膜晶体管120的所述栅极122和所述遂穿二极管130的所述阳极132均为钼/铜叠层或钼/铝叠层。
参照图5，于本揭示其中的一实施例中，在所述基板110、所述金属氧化物薄膜晶体管120的所述栅极122和所述遂穿二极管130的所述阳极132上形成栅极绝缘层140。所述栅极绝缘层140为SiOx层、SiOx/SiNx叠层、SiNx/SiOx叠层、SiOx、SiNx与SiNO相互叠层、SiOx、SiNx与Al2O3叠层或AlN层。
参照图6，于本揭示其中的一实施例中，对对应于所述遂穿二极管130的所述阳极132上方的所述栅极绝缘层140进行部分刻蚀以形成开口142，刻蚀后剩下的所述栅极绝缘层140的厚度范围介于5nm以及50nm之间。也就是所述开口142的高度范围介于5nm以及50nm之间。
参照图7至图9，于本揭示其中的一实施例中，在所述栅极绝缘层140上形成层迭的所述金属氧化物薄膜晶体管120的有源层沟道124、第一阻挡层126和源漏电极128，在所述栅极绝缘层140上形成层迭的所述遂穿二极管130的半导体层134、第二阻挡层136和阴极138，所述遂穿二极管130的所述半导体层134和所述第二阻挡层136设置于所述栅极绝缘层140的所述开口142内。
具体地，参照图7，沉积IGZO或IZO等半导体金属氧化物在所述栅极绝缘层140上，并刻蚀所述半导体金属氧化物以形成所述金属氧化物薄膜晶体管120的所述有源层沟道124以及所述遂穿二极管130的所述半导体层134。所述金属氧化物薄膜晶体管120的所述有源层沟道124和所述遂穿二极管130的所述半导体层134的材料相同，且所述金属氧化物薄膜晶体管120的所述有源层沟道124和所述遂穿二极管130的所述半导体层134的所述材料包括IGZO或IZO。
具体地，参照图8，沉积金属层180及阻挡层190在所述金属氧化物薄膜晶体管120的所述有源层沟道124和所述遂穿二极管130的所述半导体层134上。所述金属层180及所述阻挡层190可构成电极层。所述金属层180的材料可包括为铜、铝或钴，所述阻挡层190可为MoTi金属膜层、Ti金属膜层或氧化物膜层。MoTi金属膜层或Ti金属膜层的厚度范围介于10nm以及30nm之间。氧化物膜层的厚度大于MoTi金属膜层或Ti金属膜层。
具体地，参照图8和图9，以多灰阶掩膜板的黄光制程及两次刻蚀对金属层180及阻挡层190图案化以形成层迭的所述金属氧化物薄膜晶体管120的所述第一阻挡层126和所述源漏电极128以及所述遂穿二极管130的所述第二阻挡层136和所述阴极138。
参照图10和图11，于本揭示其中的一实施例中，在所述源漏电极128和所述阴极138上形成层迭的钝化层150和像素电极层160。所述钝化层150包括开孔152，所述像素电极层160通过所述钝化层150的所述开孔152接触所述源漏电极128。
具体地，参照图10，在所述源漏电极128和所述阴极138上沉积所述钝化层150。所述钝化层150的材料包括SiNx、SiOx或SiNO。在所述钝化层150上形成所述开孔152。
具体地，参照图11，在所述钝化层150上沉积所述像素电极层160并图案化所述像素电极层160。
本揭示的一实施例中，所述半导体基板结构100集成有所述金属氧化物薄膜晶体管120和所述遂穿二极管130，所述遂穿二极管130通过与所述金属氧化物薄膜晶体管120兼容的制程与所述金属氧化物薄膜晶体管120一起制作到所述基板110上。所述遂穿二极管130用于光学检测或和所述金属氧化物薄膜晶体管120组合形成逻辑电路，例如可用于内嵌式(in-cell)触控面板的指纹识别、对环境光进行显示亮度调整或对光学变化的侦测。
所述遂穿二极管130在光学侦测上可应用于移动显示设备的显示面内感应器(in cell sensor)及指纹识别，或可应用于大显示面板，例如电视监控环境光变化及自动调整不同区域的显示亮度。所述遂穿二极管130的制程和所述金属氧化物薄膜晶体管120制程兼容，不需额外的制程。
由于本揭示的实施例中的半导体基板结构及其制作方法中，所述半导体基板结构包括基板、金属氧化物薄膜晶体管以及遂穿二极管。所述金属氧化物薄膜晶体管设置在所述基板上。所述遂穿二极管设置在所述基板上和所述金属氧化物薄膜晶体管旁，因此所述半导体基板结构具有光学侦测性能。
本揭示的实施例中的半导体基板结构具有感应器(即遂穿二极管)，因而可以在所述半导体基板结构上定点感应，因此可应用于显示器(例如手机和电视)以及提升手机指纹识别及/或环境光监测和电视的遥控的性能。
尽管已经相对于一个或多个实现方式示出并描述了本揭示，但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本揭示包括所有这样的修改和变型，并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能，用于描述这样的组件的术语旨在对应于执行所述组件的指定功能（例如其在功能上是等价的）的任意组件（除非另外指示），即使在结构上与执行本文所示的本说明书的示范性实现方式中的功能的公开结构不等同。此外，尽管本说明书的特定特征已经相对于若干实现方式中的仅一个被公开，但是这种特征可以与如可以对给定或特定应用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且，就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利要求中而言，这样的术语旨在以与术语“包含”相似的方式包括。
以上仅是本揭示的优选实施方式，应当指出，对于本领域普通技术人员，在不脱离本揭示原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本揭示的保护范围。

Claims (16)

  1. 一种半导体基板结构，包括:
    基板；
    金属氧化物薄膜晶体管，设置在所述基板上；以及
    遂穿二极管，设置在所述基板上和所述金属氧化物薄膜晶体管旁；
    其中所述金属氧化物薄膜晶体管的栅极和所述遂穿二极管的阳极的材料相同，且所述金属氧化物薄膜晶体管的所述栅极和所述遂穿二极管的所述阳极均为钼/铜叠层或钼/铝叠层。
  2. 如权利要求1所述的半导体基板结构，其中所述金属氧化物薄膜晶体管的所述栅极和所述遂穿二极管的所述阳极设置在所述基板上的相同层上。
  3. 如权利要求2所述的半导体基板结构，还包括栅极绝缘层，所述栅极绝缘层设置在所述基板、所述金属氧化物薄膜晶体管的所述栅极和所述遂穿二极管的所述阳极上。
  4. 如权利要求3所述的半导体基板结构，其中所述栅极绝缘层为SiOx层、SiOx/SiNx叠层、SiNx/SiOx叠层、SiOx、SiNx与SiNO相互叠层、SiOx、SiNx与Al2O3叠层或AlN层。
  5. 如权利要求2所述的半导体基板结构，其中所述金属氧化物薄膜晶体管还包括层迭的有源层沟道、第一阻挡层和源漏电极，所述遂穿二极管还包括层迭的半导体层、第二阻挡层和阴极，所述栅极绝缘层包括开口，所述遂穿二极管的所述半导体层和所述第二阻挡层设置于所述栅极绝缘层的所述开口内。
  6. 如权利要求5所述的半导体基板结构，其中所述半导体基板结构还包括层迭的钝化层和像素电极层，所述钝化层设置于所述源漏电极和所述阴极上，所述钝化层包括开孔，所述像素电极层通过所述钝化层的所述开孔接触所述源漏电极。
  7. 一种半导体基板结构，包括:
    基板；
    金属氧化物薄膜晶体管，设置在所述基板上；以及
    遂穿二极管，设置在所述基板上和所述金属氧化物薄膜晶体管旁。
  8. 如权利要求7所述的半导体基板结构，其中所述金属氧化物薄膜晶体管的栅极和所述遂穿二极管的阳极设置在所述基板上的相同层上。
  9. 如权利要求8所述的半导体基板结构，其中所述金属氧化物薄膜晶体管的所述栅极和所述遂穿二极管的所述阳极的材料相同，且所述金属氧化物薄膜晶体管的所述栅极和所述遂穿二极管的所述阳极均为钼/铜叠层或钼/铝叠层。
  10.     如权利要求8所述的半导体基板结构，还包括栅极绝缘层，所述栅极绝缘层设置在所述基板、所述金属氧化物薄膜晶体管的所述栅极和所述遂穿二极管的所述阳极上。
  11.      如权利要求10所述的半导体基板结构，其中所述栅极绝缘层为SiOx层、SiOx/SiNx叠层、SiNx/SiOx叠层、SiOx、SiNx与SiNO相互叠层、SiOx、SiNx与Al2O3叠层或AlN层。
  12.     如权利要求8所述的半导体基板结构，其中所述金属氧化物薄膜晶体管还包括层迭的有源层沟道、第一阻挡层和源漏电极，所述遂穿二极管还包括层迭的半导体层、第二阻挡层和阴极，所述栅极绝缘层包括开口，所述遂穿二极管的所述半导体层和所述第二阻挡层设置于所述栅极绝缘层的所述开口内。
  13.     如权利要求12所述的半导体基板结构，其中所述半导体基板结构还包括层迭的钝化层和像素电极层，所述钝化层设置于所述源漏电极和所述阴极上，所述钝化层包括开孔，所述像素电极层通过所述钝化层的所述开孔接触所述源漏电极。
  14.     一种半导体基板结构的制作方法，包括:
    提供基板；
    在所述基板上形成金属氧化物薄膜晶体管；以及
    在所述基板上和所述金属氧化物薄膜晶体管旁形成遂穿二极管。
  15.     如权利要求14所述的半导体基板结构的制作方法，其中在所述基板上的相同层上形成所述金属氧化物薄膜晶体管的栅极和所述遂穿二极管的阳极。
  16. 如权利要求15所述的半导体基板结构的制作方法，其中在所述基板、所述金属氧化物薄膜晶体管的所述栅极和所述遂穿二极管的所述阳极上形成栅极绝缘层，在所述栅极绝缘层上形成层迭的所述金属氧化物薄膜晶体管的有源层沟道、第一阻挡层和源漏电极，在所述栅极绝缘层上形成层迭的所述遂穿二极管的半导体层、第二阻挡层和阴极，所述栅极绝缘层包括开口，所述遂穿二极管的所述半导体层和所述第二阻挡层设置于所述栅极绝缘层的所述开口内。
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