WO2020199658A1 - Intelligent controller for permanent magnet maglev turnout - Google Patents

Intelligent controller for permanent magnet maglev turnout Download PDF

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Publication number
WO2020199658A1
WO2020199658A1 PCT/CN2019/126263 CN2019126263W WO2020199658A1 WO 2020199658 A1 WO2020199658 A1 WO 2020199658A1 CN 2019126263 W CN2019126263 W CN 2019126263W WO 2020199658 A1 WO2020199658 A1 WO 2020199658A1
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module
switch
controller
circuit
sub
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PCT/CN2019/126263
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French (fr)
Chinese (zh)
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樊宽刚
杨杰
邓永芳
唐宏
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赣州德业电子科技有限公司
江西理工大学
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Publication of WO2020199658A1 publication Critical patent/WO2020199658A1/en

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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B61RAILWAYS
    • B61LGUIDING RAILWAY TRAFFIC; ENSURING THE SAFETY OF RAILWAY TRAFFIC
    • B61L5/00Local operating mechanisms for points or track-mounted scotch-blocks; Visible or audible signals; Local operating mechanisms for visible or audible signals
    • B61L5/06Electric devices for operating points or scotch-blocks, e.g. using electromotive driving means
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00Programme-control systems
    • G05B19/02Programme-control systems electric
    • G05B19/04Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors

Definitions

  • the invention relates to track control technology, in particular to an intelligent controller of a permanent magnet maglev switch.
  • the switch control of maglev trains still mainly adopts centralized control, which can also be controlled on site and manually under authorization.
  • the executive layer of the maglev train switch control system is still composed of relay equipment and PLC controllers.
  • the PLC controller is responsible for fault detection and the driving part is completed by the relay equipment. This inevitably leads to high equipment failure rates and difficult maintenance.
  • the relay equipment occupies a large space, and there are many maglev train track equipment, lack of unified control of the equipment, and easy electromagnetic interference.
  • the existing technical solutions for intelligent turnout systems are usually for wheel-rail trains.
  • the turnouts of maglev trains are different from wheel-rail trains in that the turnouts of maglev trains are driven by electromechanical steel beams to switch as a whole, and sometimes Multiple turnouts are required to switch at the same time to form the route of the maglev train. Therefore, the implementation efficiency, safety and anti-electromagnetic interference of the turnout control system are higher.
  • the present invention aims to provide an intelligent controller for permanent magnet maglev switch, which adopts the combination of main controller and sub-controller to realize the intelligent control of maglev switch, and has high integration and small size. specialty.
  • An intelligent controller for a permanent magnet maglev switch which includes a main controller and several sub-controllers; both the main controller and the sub-controllers include a logic processing unit, a strong current unit, a power supply unit and a UWB communication unit. , The power supply unit and the UWB communication unit are both connected to the logic processing unit; the main controller and the sub-controller communicate through their own UWB communication unit;
  • the logic processing unit of the main controller adopts an FPGA+DSP structure, which specifically includes FPGA1 module, FPGA2 module, FPGA3 module, DSP1 module, and DSP2 module.
  • FPGA1 module, FPGA2 module and FPGA3 module separately receive computer connection through three control buses.
  • the upper-level control instructions of the lock system, and the FPGA1 module, FPGA2 module, and FPGA3 module communicate between each other for real-time comparison of whether the upper-level control instructions received by each are consistent.
  • the FPGA1, FPGA2, and FPGA3 modules make a three-out-of-two decision and issue a warning to the computer interlocking system;
  • FPGA2 and FPGA3 modules separately analyze and compare the upper-level control instructions that are consistent or three out of two, and pass the main controller
  • the UWB communication unit forwards the upper-level control command to the corresponding sub-controller;
  • the FPGA1 module communicates with the DSP1 module and the DSP2 module.
  • the DSP1 module and the DSP2 module are respectively connected to the high-current unit of the main controller through optocouplers, and are used to package and package the current fluctuation data collected by the high-current unit of the main controller Sent to the FPGA1 module;
  • the FPGA2 module and FPGA3 module are respectively connected to the strong current unit of the main controller through optocouplers, and the switch position information collected by the strong current unit of the main controller is transmitted to the FPGA2 module and the FPGA3 module, and the FPGA2 module And FPGA3 module is transmitted to FPGA1 module;
  • FPGA1 module also receives the current fluctuation data and switch position information collected by the strong current unit of the sub-controller through the UWB communication unit of the main controller in real time;
  • FPGA1 module controls all the received current fluctuation data Perform analysis and detection, compare the current fluctuation data of the working motor group in real time, and report the analysis and detection results and the received
  • the strong current unit of the main controller is used to collect the current fluctuation data and the position information of the switch of the switch controlled by the main controller, and drive the switch controlled by the main controller to execute the corresponding action;
  • the logic processing unit of the sub-controller also adopts an FPGA+DSP structure, which specifically includes an FPGA module, a DSP module, and a DSP module; the DSP module and the DSP module are respectively connected to the FPGA module in communication, and respectively It is connected to the strong current unit of the sub-controller through the optocoupler, and is used to send the motor group current fluctuation data collected by the strong current unit of the sub-controller to the FPGA module; the FPGA module is connected to the strong current unit of the sub-controller through the optocoupler , Used to receive the switch position information collected by the strong current unit of the sub-controller; the FPGA module independently analyzes after receiving the upper-level control instruction of the computer interlocking system forwarded by the autonomous controller, and compares the analysis result with the main control The upper-level control instructions of the device are compared to form a two-out-two redundant structure;
  • the strong current unit of the sub-controller is used to collect the current fluctuation data and the position information of the switch of the switch controlled by the sub-controller, and drive the sub-controller to execute the corresponding switch according to the control instruction of the sub-controller.
  • the FPGA module of the sub-controller sends the switch position information collected by the strong current unit and the current fluctuation data of each motor in the motor group in real time to the FPGA1 module of the main controller through the UWB communication unit of the sub-controller.
  • the FPGA1 module, FPGA2 module, and FPGA3 module use SPI high-speed interface for communication between each other.
  • the FPGA1 module communicates with the DSP1 module and the DSP2 module using SPI interfaces respectively.
  • the power supply units of the main controller and the sub-controller both adopt a redundant safe power supply mode, including power supply A and power supply B.
  • Power supply A is the default power supply.
  • the power switching circuit will automatically drop Power B is upgraded to power supply.
  • the high-current units of the main controller and the sub-controller both include a pulse drive circuit, a display acquisition circuit, a current acquisition circuit, and a signal conditioning circuit;
  • the display acquisition circuit is used for collecting switch position information, and the current acquisition circuit is used for Collect current fluctuation data of each motor in the motor group of the turnout, the pulse drive circuit is used to drive the turnout to turn or reverse;
  • the current acquisition circuit is connected to the signal conditioning circuit, and the pulse drive circuit is connected to the safety AND gate;
  • the DSP1 module and the DSP2 module of the logic processing unit are respectively connected to the signal conditioning circuit through optocouplers.
  • the security AND gate is connected to the FPGA2 module and FPGA3 module through optocouplers
  • the display acquisition circuit is connected to the FPGA2 module and FPGA3 module through optocouplers. Connect with FPGA2 module and FPGA3 module;
  • the first DSP module and the second DSP module of the logic processing unit are respectively connected to the signal conditioning circuit through optocouplers, and the security AND gate and the representation acquisition circuit are respectively connected to the FPGA module through optocouplers.
  • the pulse drive circuits of the main controller and the sub-controller both include a pulse processing circuit, a dynamic/static conversion circuit, a drive circuit and a high-power electronic switch;
  • the pulse processing circuit is used to process the pulse control instructions issued by the logic processing unit;
  • the dynamic and static conversion circuits are respectively connected to the pulse processing circuit and the driving circuit, and are used to convert dynamic pulses processed by the pulse processing circuit into dynamic and static conversions, and transmit them to the driving circuit;
  • the high-power electronic switch includes a switch DZ, a switch DK, a switch FK, a switch KH, and a switch DF.
  • the switch DF and the switch KH are connected in series, and the switch DK and the switch FK are respectively connected in parallel with the switch KH and the switch DZ;
  • the switch KH and the switch DF are arranged on the control loop X3 of the switch, and the switch DK and the switch FK are respectively arranged on the positioning control line X1 and the reverse control line X2 of the switch;
  • the driving circuit includes driving circuit 1, driving circuit 2, driving circuit 3, driving circuit 4 and driving circuit 5, which are respectively the driving circuits of switch DZ, switch DK, switch FK, switch KH, and switch DF; when driving circuit 1, Two, four, and five control switches DZ, switch DK, switch KH, and switch DF at the same time, and the turnout is turned to position.
  • driving circuit 1 Two, four, and five control switches DZ, switch DK, switch KH, and switch DF at the same time, and the turnout is turned to position.
  • driving circuit one, three, four, and five control switch DZ, switch FK, switch KH, and switch DF are opened at the same time, The turnout turned in the opposite position.
  • the pulse driving circuits of the main controller and the sub-controller both include a driving monitoring circuit, the driving monitoring circuit is connected to the driving circuit, and the logic processing unit sends a fixed sequence of pulses to the driving monitoring circuit and returning to the driving monitoring circuit.
  • the corresponding level can be used to analyze and judge the quality of the dynamic and static conversion circuit to achieve closed-loop monitoring.
  • the present invention adopts the combination of the main controller and the sub-controller to realize the intelligent control of the maglev switch, and has the characteristics of high integration and small size.
  • Figure 1 is a schematic diagram of the overall structure of the present invention.
  • FIG. 2 is a schematic diagram of the structure of a main controller according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of the structure of the controller of the embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a pulse driving circuit according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram showing the acquisition circuit of the main controller of the embodiment of the invention.
  • FIG. 6 is a schematic diagram showing the acquisition circuit of the sub-controller of the embodiment of the invention.
  • Fig. 7 is a schematic diagram of a driving circuit according to an embodiment of the present invention.
  • this embodiment provides an intelligent controller for a permanent magnet maglev switch, which includes a main controller and several sub-controllers (the number of sub-controllers is not limited and can be configured according to actual needs);
  • the main controller and the sub-controller both include a logic processing unit, a strong current unit, a power supply unit, and a UWB communication unit.
  • the strong current unit, power supply unit, and UWB communication unit are all connected to the logic processing unit; the main controller and the sub-controller The controllers communicate through their own UWB communication unit;
  • the logic processing unit of the main controller adopts an FPGA+DSP structure, which specifically includes FPGA1 module, FPGA2 module, FPGA3 module, DSP1 module, and DSP2 module.
  • FPGA1 module, FPGA2 module and FPGA3 module separately receive computer connection through three control buses.
  • the upper-level control instructions of the lock system, and the FPGA1 module, FPGA2 module, and FPGA3 module communicate between each other for real-time comparison of whether the upper-level control instructions received by each are consistent.
  • the FPGA1, FPGA2, and FPGA3 modules make a three-out-of-two decision and issue a warning to the computer interlocking system;
  • FPGA2 and FPGA3 modules separately analyze and compare the upper-level control instructions that are consistent or three out of two, and pass the main controller
  • the UWB communication unit forwards the upper-level control command to the corresponding sub-controller;
  • the FPGA1 module communicates with the DSP1 module and the DSP2 module.
  • the DSP1 module and the DSP2 module are respectively connected to the high-current unit of the main controller through optocouplers, and are used to package and package the current fluctuation data collected by the high-current unit of the main controller Sent to the FPGA1 module;
  • the FPGA2 module and FPGA3 module are respectively connected to the strong current unit of the main controller through optocouplers, and the switch position information collected by the strong current unit of the main controller is transmitted to the FPGA2 module and the FPGA3 module, and the FPGA2 module And FPGA3 module is transmitted to FPGA1 module;
  • FPGA1 module also receives the current fluctuation data and switch position information collected by the strong current unit of the sub-controller through the UWB communication unit of the main controller in real time;
  • FPGA1 module controls all the received current fluctuation data Carry out analysis and detection, compare the current fluctuation data of the working motor group in real time whether the current fluctuation data is consistent (
  • the strong current unit of the main controller is used to collect the current fluctuation data and the position information of the switch of the switch controlled by the main controller, and drive the switch controlled by the main controller to execute the corresponding action;
  • the logic processing unit of the sub-controller also adopts an FPGA+DSP structure, which specifically includes an FPGA module, a DSP module, and a DSP module; the DSP module and the DSP module are respectively connected to the FPGA module in communication, and respectively It is connected to the strong current unit of the sub-controller through the optocoupler, and is used to send the motor group current fluctuation data collected by the strong current unit of the sub-controller to the FPGA module; the FPGA module is connected to the strong current unit of the sub-controller through the optocoupler , Used to receive the switch position information collected by the strong current unit of the sub-controller; the FPGA module independently analyzes after receiving the upper-level control instruction of the computer interlocking system forwarded by the autonomous controller, and compares the analysis result with the main control The upper-level control instructions of the device are compared to form a two-out-two redundant structure;
  • the strong current unit of the sub-controller is used to collect the current fluctuation data and the position information of the switch of the switch controlled by the sub-controller, and drive the sub-controller to execute the corresponding switch according to the control instruction of the sub-controller.
  • the FPGA module of the sub-controller sends the switch position information collected by the strong current unit and the current fluctuation data of each motor in the motor group in real time to the FPGA1 module of the main controller through the UWB communication unit of the sub-controller.
  • the FPGA1 module, FPGA2 module, and FPGA3 module use SPI high-speed interface for communication between each other.
  • the FPGA1 module communicates with the DSP1 module and the DSP2 module using SPI interfaces respectively.
  • the power supply units of the main controller and the sub-controller both adopt a redundant safe power supply mode, including power supply A and power supply B.
  • Power supply A is the default power supply.
  • the power switching circuit will automatically drop Power B is upgraded to power supply.
  • the high-current units of the main controller and the sub-controller both include a pulse drive circuit, a display acquisition circuit, a current acquisition circuit, and a signal conditioning circuit;
  • the display acquisition circuit is used for collecting switch position information, and the current acquisition circuit is used for Collect current fluctuation data of each motor in the motor group of the turnout, the pulse drive circuit is used to drive the turnout to turn or reverse;
  • the current acquisition circuit is connected to the signal conditioning circuit, and the pulse drive circuit is connected to the safety AND gate;
  • the DSP1 module and the DSP2 module of the logic processing unit are respectively connected to the signal conditioning circuit through optocouplers.
  • the security AND gate is connected to the FPGA2 module and FPGA3 module through optocouplers
  • the display acquisition circuit is connected to the FPGA2 module and FPGA3 module through optocouplers. Connect with FPGA2 module and FPGA3 module;
  • the first DSP module and the second DSP module of the logic processing unit are respectively connected to the signal conditioning circuit through optocouplers, and the security AND gate and the representation acquisition circuit are respectively connected to the FPGA module through optocouplers.
  • the pulse driving circuits of the main controller and the sub-controller both include a pulse processing circuit, a dynamic-static conversion circuit, a driving circuit, a driving monitoring circuit and a high-power electronic switch;
  • the pulse processing circuit is used to process pulse control instructions issued by the logic processing unit through the control bus;
  • the dynamic and static conversion circuit adopts a monostable circuit, which is respectively connected to the pulse processing circuit and the drive circuit, and is used to perform dynamic and static conversion of the dynamic pulse processed by the pulse processing circuit and transmit it to the drive circuit;
  • the high-power electronic switch adopts IGBT, and its model can be SKM100GB124D, including switch DZ, switch DK, switch FK, switch KH, switch DF.
  • the switch DF and switch KH are connected in series, and the switch DK and switch FK are connected to the switch respectively.
  • KH and switch DZ are connected in parallel;
  • the switch KH and switch DF are arranged on the control loop X3 of the switch, and the switch DK and switch FK are respectively arranged on the positioning control line X1 and the reverse control line X2 of the switch on;
  • the driving circuit includes driving circuit 1, driving circuit 2, driving circuit 3, driving circuit 4 and driving circuit 5, which are respectively the driving circuits of switch DZ, switch DK, switch FK, switch KH, and switch DF; when driving circuit 1, Two, four, and five control switches DZ, switch DK, switch KH, and switch DF at the same time, and the turnout is turned to position.
  • driving circuit 1 Two, four, and five control switches DZ, switch DK, switch KH, and switch DF at the same time, and the turnout is turned to position.
  • the drive circuit one, three, four, and five control switch DZ, switch FK, switch KH, and switch DF are opened at the same time, The turnout turns to the reverse position;
  • the driving monitoring circuit is a photoelectric converter circuit, which is connected to the driving circuit.
  • the logic processing unit sends a fixed sequence of pulses to the driving monitoring circuit through the IO port, and returns the corresponding level of the driving monitoring circuit to analyze and judge the quality of the dynamic/static conversion circuit , Realize closed-loop monitoring.
  • the display acquisition circuit includes a positioning display circuit and a reverse position display circuit.
  • Both the positioning display circuit and the reverse position display circuit include a current limiting resistor R1, a first acquisition current threshold control resistor R2, a second acquisition current threshold control resistor R3,
  • the optocoupler U1, the optocoupler U2, the optocoupler U3, and the optocoupler U4, the current limiting resistor R1, the first collection current threshold control resistor R2, and the second collection current threshold control resistor R3 are connected in series in sequence, the optocoupler U1 and the optocoupler U2
  • the input terminals of each are connected in parallel with the first acquisition threshold control resistor R2, and the input terminals of the optocoupler U3 and the optocoupler U4 are respectively connected in parallel with the second acquisition current threshold control resistor R3;
  • the output ends of the optocoupler U1 and the optocoupler U2 are respectively connected to the FPGA2 module of the main controller, and the output ends of the optocoupler U3 and the optocoupler U4 are respectively connected to the FPGA3 module of the main controller;
  • the output terminals of the optocoupler U1, the optocoupler U2, the optocoupler U3, and the optocoupler U4 are all connected to the FPGA module of the sub-controller;
  • the positioning indicates that the input of the current limiting resistor R1 of the circuit is the negative half-wave signal output by the rectifier diode inside the switch; the reverse bit indicates that the input of the current limiting resistor R1 of the circuit is the positive half of the output of the rectifier diode inside the switch Wave signal.

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Abstract

An intelligent controller for a permanent magnet maglev turnout, comprising a main controller and several sub-controllers. The main controller and the sub-controllers communicate by means of UWB communication units; the main controller and the sub-controllers each comprises a logic processing unit, a strong current unit, a power supply unit, and a UWB communication unit; the strong current unit, the power supply unit, and the UWB communication unit are all connected to the logic processing unit. The intelligent control of a maglev turnout is implemented by means of the combination of a main controller and sub-controllers, and the present invention has the characteristics of high integration and small size.

Description

一种永磁磁浮道岔的智能控制器Intelligent controller for permanent magnet maglev switch 技术领域Technical field
本发明涉及轨道控制技术,具体涉及一种永磁磁浮道岔的智能控制器。The invention relates to track control technology, in particular to an intelligent controller of a permanent magnet maglev switch.
背景技术Background technique
目前磁浮列车的道岔控制仍然主要采用集中控制,其中也可以在授权的情况下进行现地控制及人工控制。但是磁浮列车道岔控制系统的执行层仍然是采用继电设备和PLC控制器组成的,PLC控制器负责故障检测,驱动部分由继电设备完成,这就不可避免的出现设备故障率高且难以维修的问题,同时继电器设备占用空间较大,磁浮列车轨道设备较多,缺乏对设备统一的控制并且容易出现电磁干扰。At present, the switch control of maglev trains still mainly adopts centralized control, which can also be controlled on site and manually under authorization. However, the executive layer of the maglev train switch control system is still composed of relay equipment and PLC controllers. The PLC controller is responsible for fault detection and the driving part is completed by the relay equipment. This inevitably leads to high equipment failure rates and difficult maintenance. At the same time, the relay equipment occupies a large space, and there are many maglev train track equipment, lack of unified control of the equipment, and easy electromagnetic interference.
现有的智能道岔系统技术方案中,通常都是针对轮轨列车的技术方案,但是磁浮列车的道岔不同于轮轨列车的是,磁浮列车的道岔由电动机械驱动钢梁整体转辙,且有时需要多个道岔同时转辙从而构成磁浮列车的进路,因此对道岔控制系统的执行效率、安全性以及抗电磁干扰性要求更高。The existing technical solutions for intelligent turnout systems are usually for wheel-rail trains. However, the turnouts of maglev trains are different from wheel-rail trains in that the turnouts of maglev trains are driven by electromechanical steel beams to switch as a whole, and sometimes Multiple turnouts are required to switch at the same time to form the route of the maglev train. Therefore, the implementation efficiency, safety and anti-electromagnetic interference of the turnout control system are higher.
因此,针对现有方案的不足,有必要对其进行研究以提供一种可行的方案,解决上述问题。Therefore, in view of the shortcomings of the existing solutions, it is necessary to study them to provide a feasible solution to solve the above problems.
发明内容Summary of the invention
针对现有技术的不足,本发明旨在提供一种永磁磁浮道岔的智能控制器,采用主控制器与子控制器相结合的方式以实现磁浮道岔的智能控制,且具有高度集成和体积小的特点。In view of the shortcomings of the prior art, the present invention aims to provide an intelligent controller for permanent magnet maglev switch, which adopts the combination of main controller and sub-controller to realize the intelligent control of maglev switch, and has high integration and small size. specialty.
为了实现上述目的,本发明采用如下技术方案:In order to achieve the above objectives, the present invention adopts the following technical solutions:
一种永磁磁浮道岔的智能控制器,包括一个主控制器和若干子控制器;主控制器和子控制器均包括逻辑处理单元、强电单元、供电单元和UWB通信单元,所述强电单元、供电单元和UWB通信单元均连接于所述逻辑处理单元;所述主控制器和子控制器之间通过自身的UWB通信单元进行通信;An intelligent controller for a permanent magnet maglev switch, which includes a main controller and several sub-controllers; both the main controller and the sub-controllers include a logic processing unit, a strong current unit, a power supply unit and a UWB communication unit. , The power supply unit and the UWB communication unit are both connected to the logic processing unit; the main controller and the sub-controller communicate through their own UWB communication unit;
所述主控制器的逻辑处理单元采用FPGA+DSP结构,具体包括FPGA1模块、FPGA2模块、FPGA3模块、DSP1模块、DSP2模块,其中FPGA1模块、FPGA2模块、FPGA3模块分别通过三条控制总线单独接收计算机联锁系统的上层控制指令,且FPGA1模块、FPGA2模块、FPGA3模块两两之间进行通信,用于实时比对各自所接收的上层控制指令是否一致,一旦出现上层控制指令比对不一致的情况,则FPGA1模块、FPGA2模块、FPGA3模块进行三取二抉择并向计算机联锁系统发出警告;由FPGA2模块和FPGA3模块分别单独解析比对一致或三取二抉择得到的上层控制指令,并通过主控制器的UWB通信单元将上层控制指令转发给相应的子控制器;The logic processing unit of the main controller adopts an FPGA+DSP structure, which specifically includes FPGA1 module, FPGA2 module, FPGA3 module, DSP1 module, and DSP2 module. Among them, FPGA1 module, FPGA2 module and FPGA3 module separately receive computer connection through three control buses. The upper-level control instructions of the lock system, and the FPGA1 module, FPGA2 module, and FPGA3 module communicate between each other for real-time comparison of whether the upper-level control instructions received by each are consistent. Once the upper-level control instruction comparison is inconsistent, then The FPGA1, FPGA2, and FPGA3 modules make a three-out-of-two decision and issue a warning to the computer interlocking system; FPGA2 and FPGA3 modules separately analyze and compare the upper-level control instructions that are consistent or three out of two, and pass the main controller The UWB communication unit forwards the upper-level control command to the corresponding sub-controller;
FPGA1模块分别与DSP1模块和DSP2模块进行通信,DSP1模块、DSP2模块分别通过光耦与主控制器的强电单元相连,用于将主控制器的强电单元采集到的电流波动数据组包封装发送给FPGA1模 块;所述FPGA2模块和FPGA3模块分别通过光耦与主控制器的强电单元相连,主控制器的强电单元所采集的道岔位置信息分别传输至FPGA2模块和FPGA3模块,FPGA2模块和FPGA3模块传输至FPGA1模块;FPGA1模块还通过主控制器的UWB通信单元实时接收子控制器的强电单元所采集到的电流波动数据和道岔位置信息;FPGA1模块对所接收的所有电流波动数据进行分析检测,实时比对工作的电机组的电流波动数据是否一致,并通过控制总线将分析检测结果和所接收的道岔位置信息一并上报计算机联锁系统;FPGA1模块将子控制器传输而来的道岔位置信息与FPGA2模块、FPGA3模块共享;The FPGA1 module communicates with the DSP1 module and the DSP2 module. The DSP1 module and the DSP2 module are respectively connected to the high-current unit of the main controller through optocouplers, and are used to package and package the current fluctuation data collected by the high-current unit of the main controller Sent to the FPGA1 module; the FPGA2 module and FPGA3 module are respectively connected to the strong current unit of the main controller through optocouplers, and the switch position information collected by the strong current unit of the main controller is transmitted to the FPGA2 module and the FPGA3 module, and the FPGA2 module And FPGA3 module is transmitted to FPGA1 module; FPGA1 module also receives the current fluctuation data and switch position information collected by the strong current unit of the sub-controller through the UWB communication unit of the main controller in real time; FPGA1 module controls all the received current fluctuation data Perform analysis and detection, compare the current fluctuation data of the working motor group in real time, and report the analysis and detection results and the received switch position information to the computer interlocking system through the control bus; FPGA1 module transmits the sub-controller The position information of the turnout is shared with FPGA2 and FPGA3 modules;
所述主控制器的强电单元用于采集主控制器负责控制的道岔的电机组的电流波动数据和道岔位置信息,并根据主控制器的控制指令驱动主控制器负责控制的道岔执行相应的动作;The strong current unit of the main controller is used to collect the current fluctuation data and the position information of the switch of the switch controlled by the main controller, and drive the switch controlled by the main controller to execute the corresponding action;
所述子控制器的逻辑处理单元同样采用FPGA+DSP结构,具体包括一个FPGA模块和DSP一模块、DSP二模块;所述DSP一模块、DSP二模块分别与所述FPGA模块通信连接,并分别通过光耦与子控制器的强电单元连接,用于将子控制器的强电单元采集的电机组电流波动数据发送至FPGA模块;所述FPGA模块通过光耦连接子控制器的强电单元,用于接收子控制器的强电单元采集的道岔位置信息;所述FPGA模块在接收到来自主控制器转发的计算机联锁系统的上层控制指令后独自进行解析,并将解析结果与来自主控制器的上层控制指令进行比对,构成二取二冗余结构;The logic processing unit of the sub-controller also adopts an FPGA+DSP structure, which specifically includes an FPGA module, a DSP module, and a DSP module; the DSP module and the DSP module are respectively connected to the FPGA module in communication, and respectively It is connected to the strong current unit of the sub-controller through the optocoupler, and is used to send the motor group current fluctuation data collected by the strong current unit of the sub-controller to the FPGA module; the FPGA module is connected to the strong current unit of the sub-controller through the optocoupler , Used to receive the switch position information collected by the strong current unit of the sub-controller; the FPGA module independently analyzes after receiving the upper-level control instruction of the computer interlocking system forwarded by the autonomous controller, and compares the analysis result with the main control The upper-level control instructions of the device are compared to form a two-out-two redundant structure;
所述子控制器的强电单元用于采集该子控制器负责控制的道岔 的电机组的电流波动数据和道岔位置信息,并根据子控制器的控制指令驱动子控制器负责控制的道岔执行相应的动作;子控制器的FPGA模块实时将强电单元采集到的道岔位置信息和电机组中每个电机的电流波动数据通过子控制器自身的UWB通信单元发送给主控制器的FPGA1模块。The strong current unit of the sub-controller is used to collect the current fluctuation data and the position information of the switch of the switch controlled by the sub-controller, and drive the sub-controller to execute the corresponding switch according to the control instruction of the sub-controller. The FPGA module of the sub-controller sends the switch position information collected by the strong current unit and the current fluctuation data of each motor in the motor group in real time to the FPGA1 module of the main controller through the UWB communication unit of the sub-controller.
进一步地,所述FPGA1模块、FPGA2模块、FPGA3模块两两之间使用SPI高速接口进行通信。Further, the FPGA1 module, FPGA2 module, and FPGA3 module use SPI high-speed interface for communication between each other.
进一步地,所述FPGA1模块分别与DSP1模块和DSP2模块使用SPI接口进行通信。Further, the FPGA1 module communicates with the DSP1 module and the DSP2 module using SPI interfaces respectively.
进一步地,所述主控制器和子控制器的供电单元均采用冗余的安全供电方式,包括电源A和电源B,电源A作为默认供电电源,当电源A出现故障时,电源切换电路自动落下将电源B升为供电电源。Further, the power supply units of the main controller and the sub-controller both adopt a redundant safe power supply mode, including power supply A and power supply B. Power supply A is the default power supply. When power supply A fails, the power switching circuit will automatically drop Power B is upgraded to power supply.
进一步地,所述主控制器和子控制器的强电单元均包括脉冲驱动电路、表示采集电路、电流采集电路和信号调理电路;所述表示采集电路用于采集道岔位置信息,电流采集电路用于采集道岔的电机组中每个电机的电流波动数据,所述脉冲驱动电路用于驱动道岔转向定位或转向反位;电流采集电路连接于所述信号调理电路,脉冲驱动电路和安全与门相连;Further, the high-current units of the main controller and the sub-controller both include a pulse drive circuit, a display acquisition circuit, a current acquisition circuit, and a signal conditioning circuit; the display acquisition circuit is used for collecting switch position information, and the current acquisition circuit is used for Collect current fluctuation data of each motor in the motor group of the turnout, the pulse drive circuit is used to drive the turnout to turn or reverse; the current acquisition circuit is connected to the signal conditioning circuit, and the pulse drive circuit is connected to the safety AND gate;
在主控制器,逻辑处理单元的DSP1模块和DSP2模块分别通过光耦连接于信号调理电路,所述安全与门通过光耦分别与FPGA2模块、FPGA3模块相连,所述表示采集电路通过光耦分别与FPGA2模块、FPGA3模块相连接;In the main controller, the DSP1 module and the DSP2 module of the logic processing unit are respectively connected to the signal conditioning circuit through optocouplers. The security AND gate is connected to the FPGA2 module and FPGA3 module through optocouplers, and the display acquisition circuit is connected to the FPGA2 module and FPGA3 module through optocouplers. Connect with FPGA2 module and FPGA3 module;
在子控制器,逻辑处理单元的DSP一模块和DSP二模块分别通过光耦连接于信号调理电路,所述安全与门和表示采集电路均通过光耦分别与FPGA模块相连。In the sub-controller, the first DSP module and the second DSP module of the logic processing unit are respectively connected to the signal conditioning circuit through optocouplers, and the security AND gate and the representation acquisition circuit are respectively connected to the FPGA module through optocouplers.
更进一步地,所述主控制器和子控制器的脉冲驱动电路均包括脉冲处理电路、动静转换电路、驱动电路和大功率电子开关;Furthermore, the pulse drive circuits of the main controller and the sub-controller both include a pulse processing circuit, a dynamic/static conversion circuit, a drive circuit and a high-power electronic switch;
所述脉冲处理电路用于处理逻辑处理单元开出的脉冲控制指令;The pulse processing circuit is used to process the pulse control instructions issued by the logic processing unit;
动静转换电路分别连接于所述脉冲处理电路和驱动电路,用于将经脉冲处理电路处理后的动态脉冲进行动静转换,并传输至驱动电路;The dynamic and static conversion circuits are respectively connected to the pulse processing circuit and the driving circuit, and are used to convert dynamic pulses processed by the pulse processing circuit into dynamic and static conversions, and transmit them to the driving circuit;
所述大功率电子开关包括开关DZ、开关DK、开关FK、开关KH、开关DF,所述开关DF、开关KH串联,所述开关DK和开关FK分别与开关KH和开关DZ并联连接;所述开关KH和开关DF设于所述道岔的控制回线X3上,所述开关DK和开关FK分别设于所述道岔的定位控制线X1和反位控制线X2上;The high-power electronic switch includes a switch DZ, a switch DK, a switch FK, a switch KH, and a switch DF. The switch DF and the switch KH are connected in series, and the switch DK and the switch FK are respectively connected in parallel with the switch KH and the switch DZ; The switch KH and the switch DF are arranged on the control loop X3 of the switch, and the switch DK and the switch FK are respectively arranged on the positioning control line X1 and the reverse control line X2 of the switch;
所述驱动电路包括驱动电路一、驱动电路二、驱动电路三、驱动电路四和驱动电路五,分别为开关DZ、开关DK、开关FK、开关KH、开关DF的驱动电路;当驱动电路一、二、四、五同时控制开关DZ、开关DK、开关KH、开关DF打开,道岔转向定位,当驱动电路一、三、四、五控制开关DZ、开关FK、开关KH、开关DF同时打开时,道岔转向反位。The driving circuit includes driving circuit 1, driving circuit 2, driving circuit 3, driving circuit 4 and driving circuit 5, which are respectively the driving circuits of switch DZ, switch DK, switch FK, switch KH, and switch DF; when driving circuit 1, Two, four, and five control switches DZ, switch DK, switch KH, and switch DF at the same time, and the turnout is turned to position. When the drive circuit one, three, four, and five control switch DZ, switch FK, switch KH, and switch DF are opened at the same time, The turnout turned in the opposite position.
再进一步地,所述主控制器和子控制器的脉冲驱动电路均包括驱动监测电路,所述驱动监测电路与驱动电路连接,逻辑处理单元通过向驱动监测电路发送定序列脉冲,并回采驱动监测电路的相应电平以 分析判断动静转换电路的好坏,实现闭环监测。Still further, the pulse driving circuits of the main controller and the sub-controller both include a driving monitoring circuit, the driving monitoring circuit is connected to the driving circuit, and the logic processing unit sends a fixed sequence of pulses to the driving monitoring circuit and returning to the driving monitoring circuit. The corresponding level can be used to analyze and judge the quality of the dynamic and static conversion circuit to achieve closed-loop monitoring.
本发明的有益效果在于:本发明采用主控制器与子控制器相结合的方式以实现磁浮道岔的智能控制,且具有高度集成和体积小的特点。The beneficial effects of the present invention are: the present invention adopts the combination of the main controller and the sub-controller to realize the intelligent control of the maglev switch, and has the characteristics of high integration and small size.
附图说明Description of the drawings
图1为本发明的总体结构示意图;Figure 1 is a schematic diagram of the overall structure of the present invention;
图2为本发明实施例主控制器的结构示意图;2 is a schematic diagram of the structure of a main controller according to an embodiment of the present invention;
图3为本发明实施例子控制器的结构示意图;Figure 3 is a schematic diagram of the structure of the controller of the embodiment of the present invention;
图4为本发明实施例的脉冲驱动电路示意图;4 is a schematic diagram of a pulse driving circuit according to an embodiment of the present invention;
图5为发明实施例的主控制器表示采集电路示意图;FIG. 5 is a schematic diagram showing the acquisition circuit of the main controller of the embodiment of the invention;
图6为发明实施例的子控制器表示采集电路示意图;FIG. 6 is a schematic diagram showing the acquisition circuit of the sub-controller of the embodiment of the invention;
图7为本发明实施例的驱动电路示意图。Fig. 7 is a schematic diagram of a driving circuit according to an embodiment of the present invention.
具体实施方式detailed description
以下将结合附图对本发明作进一步的描述,需要说明的是,本实施例以本技术方案为前提,给出了详细的实施方式和具体的操作过程,但本发明的保护范围并不限于本实施例。The present invention will be further described below with reference to the accompanying drawings. It should be noted that this embodiment is based on the technical solution, and provides detailed implementation and specific operating procedures, but the scope of protection of the present invention is not limited to this Examples.
参阅图1-图7所示,本实施例提供一种永磁磁浮道岔的智能控制器,包括一个主控制器和若干子控制器(子控制器不限制数量,可根据实际需要进行配置);主控制器和子控制器均包括逻辑处理单元、强电单元、供电单元和UWB通信单元,所述强电单元、供电单元和UWB通信单元均连接于所述逻辑处理单元;所述主控制器和子控制 器之间通过自身的UWB通信单元进行通信;Referring to Figures 1 to 7, this embodiment provides an intelligent controller for a permanent magnet maglev switch, which includes a main controller and several sub-controllers (the number of sub-controllers is not limited and can be configured according to actual needs); The main controller and the sub-controller both include a logic processing unit, a strong current unit, a power supply unit, and a UWB communication unit. The strong current unit, power supply unit, and UWB communication unit are all connected to the logic processing unit; the main controller and the sub-controller The controllers communicate through their own UWB communication unit;
所述主控制器的逻辑处理单元采用FPGA+DSP结构,具体包括FPGA1模块、FPGA2模块、FPGA3模块、DSP1模块、DSP2模块,其中FPGA1模块、FPGA2模块、FPGA3模块分别通过三条控制总线单独接收计算机联锁系统的上层控制指令,且FPGA1模块、FPGA2模块、FPGA3模块两两之间进行通信,用于实时比对各自所接收的上层控制指令是否一致,一旦出现上层控制指令比对不一致的情况,则FPGA1模块、FPGA2模块、FPGA3模块进行三取二抉择并向计算机联锁系统发出警告;由FPGA2模块和FPGA3模块分别单独解析比对一致或三取二抉择得到的上层控制指令,并通过主控制器的UWB通信单元将上层控制指令转发给相应的子控制器;The logic processing unit of the main controller adopts an FPGA+DSP structure, which specifically includes FPGA1 module, FPGA2 module, FPGA3 module, DSP1 module, and DSP2 module. Among them, FPGA1 module, FPGA2 module and FPGA3 module separately receive computer connection through three control buses. The upper-level control instructions of the lock system, and the FPGA1 module, FPGA2 module, and FPGA3 module communicate between each other for real-time comparison of whether the upper-level control instructions received by each are consistent. Once the upper-level control instruction comparison is inconsistent, then The FPGA1, FPGA2, and FPGA3 modules make a three-out-of-two decision and issue a warning to the computer interlocking system; FPGA2 and FPGA3 modules separately analyze and compare the upper-level control instructions that are consistent or three out of two, and pass the main controller The UWB communication unit forwards the upper-level control command to the corresponding sub-controller;
FPGA1模块分别与DSP1模块和DSP2模块进行通信,DSP1模块、DSP2模块分别通过光耦与主控制器的强电单元相连,用于将主控制器的强电单元采集到的电流波动数据组包封装发送给FPGA1模块;所述FPGA2模块和FPGA3模块分别通过光耦与主控制器的强电单元相连,主控制器的强电单元所采集的道岔位置信息分别传输至FPGA2模块和FPGA3模块,FPGA2模块和FPGA3模块传输至FPGA1模块;FPGA1模块还通过主控制器的UWB通信单元实时接收子控制器的强电单元所采集到的电流波动数据和道岔位置信息;FPGA1模块对所接收的所有电流波动数据进行分析检测,实时比对工作的电机组的电流波动数据是否一致(若对比发现不一致,说明有个别电机的电流波动异常),并通过控制总线将分析检测结果和所接收的道岔位 置信息一并上报计算机联锁系统;FPGA1模块将子控制器传输而来的道岔位置信息与FPGA2模块、FPGA3模块共享;The FPGA1 module communicates with the DSP1 module and the DSP2 module. The DSP1 module and the DSP2 module are respectively connected to the high-current unit of the main controller through optocouplers, and are used to package and package the current fluctuation data collected by the high-current unit of the main controller Sent to the FPGA1 module; the FPGA2 module and FPGA3 module are respectively connected to the strong current unit of the main controller through optocouplers, and the switch position information collected by the strong current unit of the main controller is transmitted to the FPGA2 module and the FPGA3 module, and the FPGA2 module And FPGA3 module is transmitted to FPGA1 module; FPGA1 module also receives the current fluctuation data and switch position information collected by the strong current unit of the sub-controller through the UWB communication unit of the main controller in real time; FPGA1 module controls all the received current fluctuation data Carry out analysis and detection, compare the current fluctuation data of the working motor group in real time whether the current fluctuation data is consistent (if the comparison is found to be inconsistent, it means that there is an abnormal current fluctuation of the individual motor), and combine the analysis and detection results with the received switch position information through the control bus Report to the computer interlocking system; FPGA1 module shares the switch position information transmitted from the sub-controller with FPGA2 and FPGA3 modules;
所述主控制器的强电单元用于采集主控制器负责控制的道岔的电机组的电流波动数据和道岔位置信息,并根据主控制器的控制指令驱动主控制器负责控制的道岔执行相应的动作;The strong current unit of the main controller is used to collect the current fluctuation data and the position information of the switch of the switch controlled by the main controller, and drive the switch controlled by the main controller to execute the corresponding action;
所述子控制器的逻辑处理单元同样采用FPGA+DSP结构,具体包括一个FPGA模块和DSP一模块、DSP二模块;所述DSP一模块、DSP二模块分别与所述FPGA模块通信连接,并分别通过光耦与子控制器的强电单元连接,用于将子控制器的强电单元采集的电机组电流波动数据发送至FPGA模块;所述FPGA模块通过光耦连接子控制器的强电单元,用于接收子控制器的强电单元采集的道岔位置信息;所述FPGA模块在接收到来自主控制器转发的计算机联锁系统的上层控制指令后独自进行解析,并将解析结果与来自主控制器的上层控制指令进行比对,构成二取二冗余结构;The logic processing unit of the sub-controller also adopts an FPGA+DSP structure, which specifically includes an FPGA module, a DSP module, and a DSP module; the DSP module and the DSP module are respectively connected to the FPGA module in communication, and respectively It is connected to the strong current unit of the sub-controller through the optocoupler, and is used to send the motor group current fluctuation data collected by the strong current unit of the sub-controller to the FPGA module; the FPGA module is connected to the strong current unit of the sub-controller through the optocoupler , Used to receive the switch position information collected by the strong current unit of the sub-controller; the FPGA module independently analyzes after receiving the upper-level control instruction of the computer interlocking system forwarded by the autonomous controller, and compares the analysis result with the main control The upper-level control instructions of the device are compared to form a two-out-two redundant structure;
所述子控制器的强电单元用于采集该子控制器负责控制的道岔的电机组的电流波动数据和道岔位置信息,并根据子控制器的控制指令驱动子控制器负责控制的道岔执行相应的动作;子控制器的FPGA模块实时将强电单元采集到的道岔位置信息和电机组中每个电机的电流波动数据通过子控制器自身的UWB通信单元发送给主控制器的FPGA1模块。The strong current unit of the sub-controller is used to collect the current fluctuation data and the position information of the switch of the switch controlled by the sub-controller, and drive the sub-controller to execute the corresponding switch according to the control instruction of the sub-controller. The FPGA module of the sub-controller sends the switch position information collected by the strong current unit and the current fluctuation data of each motor in the motor group in real time to the FPGA1 module of the main controller through the UWB communication unit of the sub-controller.
进一步地,所述FPGA1模块、FPGA2模块、FPGA3模块两两之间使用SPI高速接口进行通信。Further, the FPGA1 module, FPGA2 module, and FPGA3 module use SPI high-speed interface for communication between each other.
进一步地,所述FPGA1模块分别与DSP1模块和DSP2模块使用SPI接口进行通信。Further, the FPGA1 module communicates with the DSP1 module and the DSP2 module using SPI interfaces respectively.
进一步地,所述主控制器和子控制器的供电单元均采用冗余的安全供电方式,包括电源A和电源B,电源A作为默认供电电源,当电源A出现故障时,电源切换电路自动落下将电源B升为供电电源。Further, the power supply units of the main controller and the sub-controller both adopt a redundant safe power supply mode, including power supply A and power supply B. Power supply A is the default power supply. When power supply A fails, the power switching circuit will automatically drop Power B is upgraded to power supply.
进一步地,所述主控制器和子控制器的强电单元均包括脉冲驱动电路、表示采集电路、电流采集电路和信号调理电路;所述表示采集电路用于采集道岔位置信息,电流采集电路用于采集道岔的电机组中每个电机的电流波动数据,所述脉冲驱动电路用于驱动道岔转向定位或转向反位;电流采集电路连接于所述信号调理电路,脉冲驱动电路和安全与门相连;Further, the high-current units of the main controller and the sub-controller both include a pulse drive circuit, a display acquisition circuit, a current acquisition circuit, and a signal conditioning circuit; the display acquisition circuit is used for collecting switch position information, and the current acquisition circuit is used for Collect current fluctuation data of each motor in the motor group of the turnout, the pulse drive circuit is used to drive the turnout to turn or reverse; the current acquisition circuit is connected to the signal conditioning circuit, and the pulse drive circuit is connected to the safety AND gate;
在主控制器,逻辑处理单元的DSP1模块和DSP2模块分别通过光耦连接于信号调理电路,所述安全与门通过光耦分别与FPGA2模块、FPGA3模块相连,所述表示采集电路通过光耦分别与FPGA2模块、FPGA3模块相连接;In the main controller, the DSP1 module and the DSP2 module of the logic processing unit are respectively connected to the signal conditioning circuit through optocouplers. The security AND gate is connected to the FPGA2 module and FPGA3 module through optocouplers, and the display acquisition circuit is connected to the FPGA2 module and FPGA3 module through optocouplers. Connect with FPGA2 module and FPGA3 module;
在子控制器,逻辑处理单元的DSP一模块和DSP二模块分别通过光耦连接于信号调理电路,所述安全与门和表示采集电路均通过光耦分别与FPGA模块相连。In the sub-controller, the first DSP module and the second DSP module of the logic processing unit are respectively connected to the signal conditioning circuit through optocouplers, and the security AND gate and the representation acquisition circuit are respectively connected to the FPGA module through optocouplers.
更进一步地,所述主控制器和子控制器的脉冲驱动电路均包括脉冲处理电路、动静转换电路、驱动电路、驱动监测电路和大功率电子开关;Furthermore, the pulse driving circuits of the main controller and the sub-controller both include a pulse processing circuit, a dynamic-static conversion circuit, a driving circuit, a driving monitoring circuit and a high-power electronic switch;
所述脉冲处理电路用于处理逻辑处理单元通过控制总线开出的 脉冲控制指令;The pulse processing circuit is used to process pulse control instructions issued by the logic processing unit through the control bus;
动静转换电路采用单稳态电路,其分别连接于所述脉冲处理电路和驱动电路,用于将经脉冲处理电路处理后的动态脉冲进行动静转换,并传输至驱动电路;The dynamic and static conversion circuit adopts a monostable circuit, which is respectively connected to the pulse processing circuit and the drive circuit, and is used to perform dynamic and static conversion of the dynamic pulse processed by the pulse processing circuit and transmit it to the drive circuit;
所述大功率电子开关采用IGBT,其型号可选SKM100GB124D,包括开关DZ、开关DK、开关FK、开关KH、开关DF,所述开关DF、开关KH串联,所述开关DK和开关FK分别与开关KH和开关DZ并联连接;所述开关KH和开关DF设于所述道岔的控制回线X3上,所述开关DK和开关FK分别设于所述道岔的定位控制线X1和反位控制线X2上;The high-power electronic switch adopts IGBT, and its model can be SKM100GB124D, including switch DZ, switch DK, switch FK, switch KH, switch DF. The switch DF and switch KH are connected in series, and the switch DK and switch FK are connected to the switch respectively. KH and switch DZ are connected in parallel; the switch KH and switch DF are arranged on the control loop X3 of the switch, and the switch DK and switch FK are respectively arranged on the positioning control line X1 and the reverse control line X2 of the switch on;
所述驱动电路包括驱动电路一、驱动电路二、驱动电路三、驱动电路四和驱动电路五,分别为开关DZ、开关DK、开关FK、开关KH、开关DF的驱动电路;当驱动电路一、二、四、五同时控制开关DZ、开关DK、开关KH、开关DF打开,道岔转向定位,当驱动电路一、三、四、五控制开关DZ、开关FK、开关KH、开关DF同时打开时,道岔转向反位;The driving circuit includes driving circuit 1, driving circuit 2, driving circuit 3, driving circuit 4 and driving circuit 5, which are respectively the driving circuits of switch DZ, switch DK, switch FK, switch KH, and switch DF; when driving circuit 1, Two, four, and five control switches DZ, switch DK, switch KH, and switch DF at the same time, and the turnout is turned to position. When the drive circuit one, three, four, and five control switch DZ, switch FK, switch KH, and switch DF are opened at the same time, The turnout turns to the reverse position;
所述驱动监测电路为光电转换器电路,其与驱动电路连接,逻辑处理单元通过IO口向驱动监测电路发送定序列脉冲,并回采驱动监测电路的相应电平以分析判断动静转换电路的好坏,实现闭环监测。The driving monitoring circuit is a photoelectric converter circuit, which is connected to the driving circuit. The logic processing unit sends a fixed sequence of pulses to the driving monitoring circuit through the IO port, and returns the corresponding level of the driving monitoring circuit to analyze and judge the quality of the dynamic/static conversion circuit , Realize closed-loop monitoring.
更进一步地,表示采集电路包括定位表示电路和反位表示电路,定位表示电路和反位表示电路均包括限流电阻R1、第一采集电流门限控制电阻R2、第二采集电流门限控制电阻R3、光耦U1、光耦U2、 光耦U3和光耦U4,所述限流电阻R1、第一采集电流门限控制电阻R2、第二采集电流门限控制电阻R3依次串联,所述光耦U1和光耦U2的输入端分别与所述第一采集门限控制电阻R2并联,所述光耦U3和光耦U4的输入端分别与所述第二采集电流门限控制电阻R3的并联;Furthermore, the display acquisition circuit includes a positioning display circuit and a reverse position display circuit. Both the positioning display circuit and the reverse position display circuit include a current limiting resistor R1, a first acquisition current threshold control resistor R2, a second acquisition current threshold control resistor R3, The optocoupler U1, the optocoupler U2, the optocoupler U3, and the optocoupler U4, the current limiting resistor R1, the first collection current threshold control resistor R2, and the second collection current threshold control resistor R3 are connected in series in sequence, the optocoupler U1 and the optocoupler U2 The input terminals of each are connected in parallel with the first acquisition threshold control resistor R2, and the input terminals of the optocoupler U3 and the optocoupler U4 are respectively connected in parallel with the second acquisition current threshold control resistor R3;
在主控制器中,所述光耦U1和光耦U2的输出端分别连接于主控制器的FPGA2模块,所述光耦U3和光耦U4的输出端分别连接于主控器的FPGA3模块;In the main controller, the output ends of the optocoupler U1 and the optocoupler U2 are respectively connected to the FPGA2 module of the main controller, and the output ends of the optocoupler U3 and the optocoupler U4 are respectively connected to the FPGA3 module of the main controller;
在子控制器中,所述光耦U1、光耦U2、光耦U3和光耦U4的输出端均连接于子控制器的FPGA模块;In the sub-controller, the output terminals of the optocoupler U1, the optocoupler U2, the optocoupler U3, and the optocoupler U4 are all connected to the FPGA module of the sub-controller;
所述定位表示电路的限流电阻R1的输入为道岔内部的整流二极管输出的负半波信号;所述反位表示电路的限流电阻R1的输入为所述道岔内部的整流二极管输出的正半波信号。The positioning indicates that the input of the current limiting resistor R1 of the circuit is the negative half-wave signal output by the rectifier diode inside the switch; the reverse bit indicates that the input of the current limiting resistor R1 of the circuit is the positive half of the output of the rectifier diode inside the switch Wave signal.
对于本领域的技术人员来说,可以根据以上的技术方案和构思,给出各种相应的改变和变形,而所有的这些改变和变形,都应该包括在本发明权利要求的保护范围之内。For those skilled in the art, various corresponding changes and modifications can be given based on the above technical solutions and ideas, and all these changes and modifications should be included in the protection scope of the claims of the present invention.

Claims (7)

  1. 一种永磁磁浮道岔的智能控制器,其特征在于,包括一个主控制器和若干子控制器;主控制器和子控制器均包括逻辑处理单元、强电单元、供电单元和UWB通信单元,所述强电单元、供电单元和UWB通信单元均连接于所述逻辑处理单元;所述主控制器和子控制器之间通过自身的UWB通信单元进行通信;An intelligent controller for a permanent magnet maglev switch, which is characterized in that it includes a main controller and several sub-controllers; both the main controller and the sub-controllers include a logic processing unit, a strong current unit, a power supply unit and a UWB communication unit. The strong current unit, the power supply unit and the UWB communication unit are all connected to the logic processing unit; the main controller and the sub-controller communicate through their own UWB communication unit;
    所述主控制器的逻辑处理单元采用FPGA+DSP结构,具体包括FPGA1模块、FPGA2模块、FPGA3模块、DSP1模块、DSP2模块,其中FPGA1模块、FPGA2模块、FPGA3模块分别通过三条控制总线单独接收计算机联锁系统的上层控制指令,且FPGA1模块、FPGA2模块、FPGA3模块两两之间进行通信,用于实时比对各自所接收的上层控制指令是否一致,一旦出现上层控制指令比对不一致的情况,则FPGA1模块、FPGA2模块、FPGA3模块进行三取二抉择并向计算机联锁系统发出警告;由FPGA2模块和FPGA3模块分别单独解析比对一致或三取二抉择得到的上层控制指令,并通过主控制器的UWB通信单元将上层控制指令转发给相应的子控制器;The logic processing unit of the main controller adopts an FPGA+DSP structure, which specifically includes FPGA1 module, FPGA2 module, FPGA3 module, DSP1 module, and DSP2 module. Among them, FPGA1 module, FPGA2 module and FPGA3 module separately receive computer connection through three control buses. The upper-level control instructions of the lock system, and the FPGA1 module, FPGA2 module, and FPGA3 module communicate between each other for real-time comparison of whether the upper-level control instructions received by each are consistent. Once the upper-level control instruction comparison is inconsistent, then The FPGA1, FPGA2, and FPGA3 modules make a three-out-of-two decision and issue a warning to the computer interlocking system; FPGA2 and FPGA3 modules separately analyze and compare the upper-level control instructions that are consistent or three out of two, and pass the main controller The UWB communication unit forwards the upper-level control command to the corresponding sub-controller;
    FPGA1模块分别与DSP1模块和DSP2模块进行通信,DSP1模块、DSP2模块分别通过光耦与主控制器的强电单元相连,用于将主控制器的强电单元采集到的电流波动数据组包封装发送给FPGA1模块;所述FPGA2模块和FPGA3模块分别通过光耦与主控制器的强电单元相连,主控制器的强电单元所采集的道岔位置信息分别传输至FPGA2模块和FPGA3模块,FPGA2模块和FPGA3模块传输至FPGA1 模块;FPGA1模块还通过主控制器的UWB通信单元实时接收子控制器的强电单元所采集到的电流波动数据和道岔位置信息;FPGA1模块对所接收的所有电流波动数据进行分析检测,实时比对工作的电机组的电流波动数据是否一致,并通过控制总线将分析检测结果和所接收的道岔位置信息一并上报计算机联锁系统;FPGA1模块将子控制器传输而来的道岔位置信息与FPGA2模块、FPGA3模块共享;The FPGA1 module communicates with the DSP1 module and the DSP2 module. The DSP1 module and the DSP2 module are respectively connected to the high-current unit of the main controller through optocouplers, and are used to package and package the current fluctuation data collected by the high-current unit of the main controller Sent to the FPGA1 module; the FPGA2 module and FPGA3 module are respectively connected to the strong current unit of the main controller through optocouplers, and the switch position information collected by the strong current unit of the main controller is transmitted to the FPGA2 module and the FPGA3 module, and the FPGA2 module And FPGA3 module is transmitted to FPGA1 module; FPGA1 module also receives the current fluctuation data and switch position information collected by the strong current unit of the sub-controller through the UWB communication unit of the main controller in real time; FPGA1 module controls all the received current fluctuation data Perform analysis and detection, compare the current fluctuation data of the working motor group in real time, and report the analysis and detection results and the received switch position information to the computer interlocking system through the control bus; FPGA1 module transmits the sub-controller The position information of the turnout is shared with FPGA2 and FPGA3 modules;
    所述主控制器的强电单元用于采集主控制器负责控制的道岔的电机组的电流波动数据和道岔位置信息,并根据主控制器的控制指令驱动主控制器负责控制的道岔执行相应的动作;The strong current unit of the main controller is used to collect the current fluctuation data and the position information of the switch of the switch controlled by the main controller, and drive the switch controlled by the main controller to execute the corresponding action;
    所述子控制器的逻辑处理单元同样采用FPGA+DSP结构,具体包括一个FPGA模块和DSP一模块、DSP二模块;所述DSP一模块、DSP二模块分别与所述FPGA模块通信连接,并分别通过光耦与子控制器的强电单元连接,用于将子控制器的强电单元采集的电机组电流波动数据发送至FPGA模块;所述FPGA模块通过光耦连接子控制器的强电单元,用于接收子控制器的强电单元采集的道岔位置信息;所述FPGA模块在接收到来自主控制器转发的计算机联锁系统的上层控制指令后独自进行解析,并将解析结果与来自主控制器的上层控制指令进行比对,构成二取二冗余结构;The logic processing unit of the sub-controller also adopts an FPGA+DSP structure, which specifically includes an FPGA module, a DSP module, and a DSP module; the DSP module and the DSP module are respectively connected to the FPGA module in communication, and respectively It is connected to the strong current unit of the sub-controller through the optocoupler, and is used to send the motor group current fluctuation data collected by the strong current unit of the sub-controller to the FPGA module; the FPGA module is connected to the strong current unit of the sub-controller through the optocoupler , Used to receive the switch position information collected by the strong current unit of the sub-controller; the FPGA module independently analyzes after receiving the upper-level control instruction of the computer interlocking system forwarded by the autonomous controller, and compares the analysis result with the main control The upper-level control instructions of the device are compared to form a two-out-two redundant structure;
    所述子控制器的强电单元用于采集该子控制器负责控制的道岔的电机组的电流波动数据和道岔位置信息,并根据子控制器的控制指令驱动子控制器负责控制的道岔执行相应的动作;子控制器的FPGA模块实时将强电单元采集到的道岔位置信息和电机组中每个电机的 电流波动数据通过子控制器自身的UWB通信单元发送给主控制器的FPGA1模块。The strong current unit of the sub-controller is used to collect the current fluctuation data and the position information of the switch of the switch controlled by the sub-controller, and drive the sub-controller to execute the corresponding switch according to the control instruction of the sub-controller. The FPGA module of the sub-controller sends the switch position information collected by the strong current unit and the current fluctuation data of each motor in the motor group in real time to the FPGA1 module of the main controller through the UWB communication unit of the sub-controller.
  2. 根据权利要求1所述的永磁磁浮道岔的智能控制器,其特征在于,所述FPGA1模块、FPGA2模块、FPGA3模块两两之间使用SPI高速接口进行通信。The intelligent controller of a permanent magnet maglev switch according to claim 1, wherein the FPGA1 module, FPGA2 module, and FPGA3 module use SPI high-speed interface for communication between each other.
  3. 根据权利要求1所述的永磁磁浮道岔的智能控制器,其特征在于,所述FPGA1模块分别与DSP1模块和DSP2模块使用SPI接口进行通信。The intelligent controller of a permanent magnet maglev switch according to claim 1, wherein the FPGA1 module communicates with the DSP1 module and the DSP2 module using SPI interfaces respectively.
  4. 根据权利要求1所述的永磁磁浮道岔的智能控制器,其特征在于,所述主控制器和子控制器的供电单元均采用冗余的安全供电方式,包括电源A和电源B,电源A作为默认供电电源,当电源A出现故障时,电源切换电路自动落下将电源B升为供电电源。The intelligent controller for a permanent magnet maglev switch according to claim 1, wherein the power supply units of the main controller and the sub-controller both adopt a redundant safe power supply mode, including power supply A and power supply B, and power supply A is used as The default power supply, when the power supply A fails, the power switching circuit automatically drops to upgrade the power supply B to the power supply.
  5. 根据权利要求1所述的永磁磁浮道岔的智能控制器,其特征在于,所述主控制器和子控制器的强电单元均包括脉冲驱动电路、表示采集电路、电流采集电路和信号调理电路;所述表示采集电路用于采集道岔位置信息,电流采集电路用于采集道岔的电机组中每个电机的电流波动数据,所述脉冲驱动电路用于驱动道岔转向定位或转向反位;电流采集电路连接于所述信号调理电路,脉冲驱动电路和安全与门相连;The intelligent controller for a permanent magnet maglev switch according to claim 1, wherein the strong current units of the main controller and the sub-controller both include a pulse drive circuit, a display acquisition circuit, a current acquisition circuit and a signal conditioning circuit; The display collection circuit is used to collect the position information of the turnout, the current collection circuit is used to collect the current fluctuation data of each motor in the motor group of the turnout, and the pulse drive circuit is used to drive the turnout to turn to position or turn to reverse; current collection circuit Connected to the signal conditioning circuit, the pulse drive circuit is connected to the safety AND gate;
    在主控制器,逻辑处理单元的DSP1模块和DSP2模块分别通过光耦连接于信号调理电路,所述安全与门通过光耦分别与FPGA2模块、FPGA3模块相连,所述表示采集电路通过光耦分别与FPGA2模 块、FPGA3模块相连接;In the main controller, the DSP1 module and the DSP2 module of the logic processing unit are respectively connected to the signal conditioning circuit through optocouplers. The security AND gate is connected to the FPGA2 module and FPGA3 module through optocouplers, and the display acquisition circuit is connected to the FPGA2 module and FPGA3 module through optocouplers. Connect with FPGA2 module and FPGA3 module;
    在子控制器,逻辑处理单元的DSP一模块和DSP二模块分别通过光耦连接于信号调理电路,所述安全与门和表示采集电路均通过光耦分别与FPGA模块相连。In the sub-controller, the first DSP module and the second DSP module of the logic processing unit are respectively connected to the signal conditioning circuit through optocouplers, and the security AND gate and the representation acquisition circuit are respectively connected to the FPGA module through optocouplers.
  6. 根据权利要求5所述的永磁磁浮道岔的智能控制器,其特征在于,所述主控制器和子控制器的脉冲驱动电路均包括脉冲处理电路、动静转换电路、驱动电路和大功率电子开关;The intelligent controller for a permanent magnet maglev switch according to claim 5, wherein the pulse drive circuits of the main controller and the sub-controller both include a pulse processing circuit, a dynamic and static conversion circuit, a drive circuit and a high-power electronic switch;
    所述脉冲处理电路用于处理逻辑处理单元开出的脉冲控制指令;The pulse processing circuit is used to process the pulse control instructions issued by the logic processing unit;
    动静转换电路分别连接于所述脉冲处理电路和驱动电路,用于将经脉冲处理电路处理后的动态脉冲进行动静转换,并传输至驱动电路;The dynamic and static conversion circuits are respectively connected to the pulse processing circuit and the driving circuit, and are used to convert dynamic pulses processed by the pulse processing circuit into dynamic and static conversions, and transmit them to the driving circuit;
    所述大功率电子开关包括开关DZ、开关DK、开关FK、开关KH、开关DF,所述开关DF、开关KH串联,所述开关DK和开关FK分别与开关KH和开关DZ并联连接;所述开关KH和开关DF设于所述道岔的控制回线X3上,所述开关DK和开关FK分别设于所述道岔的定位控制线X1和反位控制线X2上;The high-power electronic switch includes a switch DZ, a switch DK, a switch FK, a switch KH, and a switch DF. The switch DF and the switch KH are connected in series, and the switch DK and the switch FK are respectively connected in parallel with the switch KH and the switch DZ; The switch KH and the switch DF are arranged on the control loop X3 of the switch, and the switch DK and the switch FK are respectively arranged on the positioning control line X1 and the reverse control line X2 of the switch;
    所述驱动电路包括驱动电路一、驱动电路二、驱动电路三、驱动电路四和驱动电路五,分别为开关DZ、开关DK、开关FK、开关KH、开关DF的驱动电路;当驱动电路一、二、四、五同时控制开关DZ、开关DK、开关KH、开关DF打开,道岔转向定位,当驱动电路一、三、四、五控制开关DZ、开关FK、开关KH、开关DF同时打开时,道岔转向反位。The driving circuit includes driving circuit 1, driving circuit 2, driving circuit 3, driving circuit 4 and driving circuit 5, which are respectively the driving circuits of switch DZ, switch DK, switch FK, switch KH, and switch DF; when driving circuit 1, Two, four, and five control switches DZ, switch DK, switch KH, and switch DF at the same time, and the turnout is turned to position. When the drive circuit one, three, four, and five control switch DZ, switch FK, switch KH, and switch DF are opened at the same time, The turnout turned in the opposite position.
  7. 根据权利要求6所述的永磁磁浮道岔的智能控制器,其特征 在于,所述主控制器和子控制器的脉冲驱动电路均包括驱动监测电路,所述驱动监测电路与驱动电路连接,逻辑处理单元通过向驱动监测电路发送定序列脉冲,并回采驱动监测电路的相应电平以分析判断动静转换电路的好坏,实现闭环监测。The intelligent controller for a permanent magnet maglev switch according to claim 6, wherein the pulse drive circuits of the main controller and the sub-controller both include a drive monitoring circuit, the drive monitoring circuit is connected to the drive circuit, and the logic processing The unit sends a fixed sequence of pulses to the drive monitoring circuit, and retrieves the corresponding level of the drive monitoring circuit to analyze and judge the quality of the dynamic/static conversion circuit, and realize closed-loop monitoring.
PCT/CN2019/126263 2019-04-04 2019-12-18 Intelligent controller for permanent magnet maglev turnout WO2020199658A1 (en)

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