WO2020199489A1 - 一种适用于NVMe命名空间配置的双接口架构 - Google Patents

一种适用于NVMe命名空间配置的双接口架构 Download PDF

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WO2020199489A1
WO2020199489A1 PCT/CN2019/103914 CN2019103914W WO2020199489A1 WO 2020199489 A1 WO2020199489 A1 WO 2020199489A1 CN 2019103914 W CN2019103914 W CN 2019103914W WO 2020199489 A1 WO2020199489 A1 WO 2020199489A1
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namespace
interface
dual
decryption
interface module
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PCT/CN2019/103914
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English (en)
French (fr)
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郭书玮
李庭育
洪振洲
陈育鸣
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江苏华存电子科技有限公司
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Publication of WO2020199489A1 publication Critical patent/WO2020199489A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

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  • the invention relates to the field of storage technology, in particular to a dual-interface architecture suitable for NVMe namespace configuration.
  • NVMe Non-Volatile Memory Host Controller Interface Specification
  • the user space of the flash memory can be divided into several independent logical spaces.
  • Each logical space can be defined as a namespace.
  • a number of namespaces can be defined in the non-volatile memory host controller interface specification, each named The space has independent instruction read and write operations.
  • multi-core processor operation instructions can be processed in parallel, thereby reducing the delay time between instructions.
  • the demand for the number of namespaces is getting higher and higher.
  • each command needs to query each space feature value through the namespace definition and confirm whether the namespace is valid.
  • the namespace definition is also used to support the protection of encryption and decryption behaviors, and is used to read the encryption and decryption feature values of the corresponding logical interval.
  • the purpose of the present invention is to overcome the defects of the prior art, provide a dual interface architecture suitable for NVMe namespace configuration, configure dual interfaces to synchronize the query and read of namespace feature values and area encryption and decryption feature values, and reduce delay time.
  • a dual interface architecture suitable for NVMe namespace configuration including an NVMe solid state drive, which is divided into multiple namespaces, and each namespace is provided with dual interfaces Module, one interface module is the namespace configuration interface module, which queries and reads the feature value of the namespace, the other interface is the area write encryption and decryption interface module, which queries and reads the area encryption and decryption feature value, the namespace configuration interface module Group and area write encryption and decryption interface modules share integrated memory space.
  • the area write encryption/decryption interface module includes an integrated output module and a plurality of comparators.
  • the input end of the comparator is connected to the integrated memory space, and simultaneously receives written data and memory index data, and outputs the comparison result and Write data to the integrated output module.
  • the integrated memory space integrates namespace feature values, regional encryption and decryption feature values, and logical block addresses.
  • the output ends of the namespace configuration interface module and the area write encryption/decryption interface module are both connected to a cache memory, and the last data is stored, so as to quickly read the corresponding characteristic value without performing a query step .
  • the dual-interface architecture suitable for NVMe namespace configuration disclosed in the present invention has the following beneficial effects: the dual-interface architecture can simultaneously query and read namespace feature values and encryption and decryption feature values, which is effective Reduce the delay time of switching between command operations;
  • Cache memory is provided at the output. To store the last data, as long as the command remains unchanged, the required feature values can be quickly read from the cache memory without the need to perform query steps. According to such hardware acceleration Architecture, which greatly reduces the delay time caused by the old microprocessor inspection process
  • Figure 1 is a schematic diagram of the framework of the first embodiment of the present invention.
  • FIG. 2 is a framework diagram of the area write encryption and decryption interface module in the first embodiment of the present invention
  • Figure 3 is a schematic diagram of the integration of the integrated memory space in the present invention.
  • Fig. 4 is a schematic diagram of the framework of the second embodiment of the present invention.
  • the present invention discloses a dual-interface architecture suitable for NVMe namespace configuration, including an NVMe solid state drive, which is divided into multiple namespaces, and each namespace is provided with a dual-interface module.
  • One of the interface modules is the namespace configuration interface module, which is used to query and read the feature value of the namespace. This interface is consistent with the interface in the existing namespace, and the other interface is the area write encryption and decryption interface module, query and read Take the area encryption and decryption feature value.
  • the area write encryption and decryption interface module includes an integrated output module and a plurality of comparators.
  • the input of the comparator is connected to the integrated memory space, and simultaneously receives written data and memory index data, and outputs Compare the result and write the data to the integrated output module (here is what data is compared with what data, and what is the function of the output result).
  • the namespace configuration interface module and the area write encryption and decryption interface module share the integrated memory space. Specifically, it integrates namespace feature values, regional encryption and decryption feature values, and logical block addresses.
  • Figure 4 shows the second embodiment of the present invention.
  • the difference from the first embodiment is that the output terminals of the namespace configuration interface module and the area write encryption/decryption interface module are both connected to the cache
  • the memory stores the last data.
  • the namespace definition of the address corresponding to the command is unchanged, the content of the cache memory is directly read, which can save query time and further reduce the delay time spent.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Storage Device Security (AREA)

Abstract

一种适用于NVMe命名空间配置的双接口架构，包括一NVMe固态硬盘，其内部被划分为多个命名空间，每个命名空间均设置有双接口模块，一个接口模块为命名空间配置接口模组，查询读取命名空间特征值，另一接口为区域写入加解密接口模组，查询读取区域加解密特征值，所述命名空间配置接口模组与区域写入加解密接口模组共用整合记忆空间。所述双接口架构可配置双接口同步实现命名空间特征值和区域加解密特征值的查询读取，减少延迟时间。

Description

一种适用于NVMe命名空间配置的双接口架构 技术领域
本发明涉及存储技术领域，尤其涉及一种适用于NVMe命名空间配置的双接口架构。
背景技术
非易失性内存主机控制器接口规范(NVMe)是一个逻辑设备接口规范，此规范于充分利用快捷外设互联标准信道的低延时以及多线平行高速传输，还有现行通用处理器应用的操作并行性，摆脱过往控制器接口的速度限制，大幅度提升固态硬盘的读写传输速度。
将闪存用户空间进行划分，可以分成数个独立的逻辑空间，每个逻辑空间就可以被定义为命名空间，由非易失性内存主机控制器接口规范中可以定义多数个命名空间，每个命名空间拥有独立的指令读写操作，藉由每个独立的命名空间，可以平行处理多核心处理器操作指令，进而减少指令之间的延迟时间。在存储容量要求日渐提高的情况下，加上不同的管理需求,对于命名空间的数量需求越来越高。而根据NVMe标准下，每笔指令都需要藉由命名空间定义来查询各空间特征值，并确认其命名空间是否有效 空间。此外命名空间定义也用来支持保护加解密行为，用来读取对应逻辑区间加解密特征值，其加解密特征值与空间特征值并非同值。
发明内容
本发明的目的在于克服现有技术的缺陷，提供一种适用于NVMe命名空间配置的双接口架构，配置双接口同步实现命名空间特征值和区域加解密特征值的查询读取，减少延迟时间。
为实现上述目的，本发明提出如下技术方案：一种适用于NVMe命名空间配置的双接口架构，包括一NVMe固态硬盘，其内部被划分为多个命名空间，每个命名空间均设置有双接口模块，一个接口模块为命名空间配置接口模组，查询读取命名空间特征值，另一接口为区域写入加解密接口模组，查询读取区域加解密特征值，所述命名空间配置接口模组与区域写入加解密接口模组共用整合记忆空间。
优选的，所述区域写入加解密接口模组包括整合输出模组以及多个比较器，比较器的输入端连接整合记忆空间，同时接收写入资料和记忆体索引资料，并输出比较结果和写入资料给整合输出模组。
优选的，所述整合记忆空间对命名空间特征值、区域加解密特征值及逻辑区块位址进行整合。
优选的，所述命名空间配置接口模组和区域写入加解密接口模组的输出端均连接有快取记忆体，存储有上一笔资料，以快速读取相应特征值而无需执行查询步骤。
与现有技术相比，本发明所揭示的一种适用于NVMe命名空间配置的双接口架构，具有如下有益效果：采用双接口架构可以同时查询读取命名空间特征值和加解密特征值，有效降低指令操作之间转换的延迟时间；
外对空间特征值与区域加解密特征值的记忆空间进行整合,减少双接口所使用记忆体空间；
在输出端提供快取记忆体.存储上一笔的资料,只要指令不变,便能快速从快取记忆体读取所需之特征值而不需要再执行查询步骤.根据这样的硬体加速架构,大量地缩减旧有微处理器检查流程带来的延迟时间
附图说明
图1是本发明第一实施例中架构的框架示意图；
图2是本发明第一实施例中区域写入加解密接口模组框架图；
图3是本发明中整合记忆空间的整合示意图；
图4是本发明第二实施例中架构的框架示意图。
具体实施方式
下面将结合本发明的附图，对本发明实施例的技术方案进行清楚、完整的描述。
如图1所示，本发明所揭示的一种适用于NVMe命名空间配置的双接口架构，包括NVMe固态硬盘，其内部被划分为多个命名空间，每个命名空间均设置有双接口模块，其中一个接口模块为命名空间配置接口模组，用来查询读取命名空间特征值，这个接口和现有命名空间中的接口一致，而另一个接口为区域写入加解密接口模组，查询读取区域加解密特征值。
如图2所示，所述区域写入加解密接口模组包括整合输出模组以及多个比较器，比较器的输入端连接整合记忆空间，同时接收写入资料和记忆体索引资料，并输出比较结果和写入资料给整合输出模组(这边是将什么资料和什么资料进行比较，输出的结果作用是什么)。
如图3所示，为了减少双接口配置对记忆体空间的实用，将命名空间配置接口模组与区域写入加解密接口模组共用整合记忆空间。具体的是将命名空间特征值、区域加解密特征值及逻辑区块位址进行整合。
如图4所示为本发明的第二实施例，其相比第一实施例的区别是，所述命名空间配置接口模组和区域写入加解密接口模组的输出端均连接有快取记忆体，存储有上一笔资料，当指令所对应位址之命名空间定义不变,便直接读取快取记忆体内容,可省去查询的时间,进而更加减少所花费的延迟时间。
本发明的技术内容及技术特征已揭示如上，然而熟悉本领域的技术人员仍可能基于本发明的教示及揭示而作种种不背离本发明精神的替换及修饰，因此，本发明保护范围应不限于实施例所揭示的内容，而应包括各种不背离本发明的替换及修饰，并为本专利申请权利要求所涵盖。

Claims (4)

  1. 一种适用于NVMe命名空间配置的双接口架构，其特征在于：包括一NVMe固态硬盘，其内部被划分为多个命名空间，每个命名空间均设置有双接口模块，一个接口模块为命名空间配置接口模组，查询读取命名空间特征值，另一接口为区域写入加解密接口模组，查询读取区域加解密特征值，所述命名空间配置接口模组与区域写入加解密接口模组共用整合记忆空间。
  2. 根据权利要求1所述的适用于NVMe命名空间配置的双接口架构，其特征在于：所述区域写入加解密接口模组包括整合输出模组以及多个比较器，比较器的输入端连接整合记忆空间，同时接收写入资料和记忆体索引资料，并输出比较结果和写入资料给整合输出模组。
  3. 根据权利要求1所述的适用于NVMe命名空间配置的双接口架构，其特征在于：所述整合记忆空间对命名空间特征值、区域加解密特征值及逻辑区块位址进行整合。
  4. 根据权利要求1所述的适用于NVMe命名空间配置的双接口架构，其特征在于：所述命名空间配置接口模组和区域写入加解密接口模组的输出端均连接有快取记忆体，存储有上一笔资料，以快速读取相应特征值而无需执行查询步骤。
PCT/CN2019/103914 2019-04-01 2019-09-02 一种适用于NVMe命名空间配置的双接口架构 WO2020199489A1 (zh)

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CN109918324A (zh) * 2019-04-01 2019-06-21 江苏华存电子科技有限公司 一种适用于NVMe命名空间配置的双接口架构
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